4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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18 * contributors may be used to endorse or promote products derived
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
65 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
66 #define IGB_DEFAULT_RX_HTHRESH 8
67 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
70 #define IGB_DEFAULT_TX_HTHRESH 1
71 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73 #define IGB_HKEY_MAX_INDEX 10
75 /* Bit shift and mask */
76 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
77 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
78 #define IGB_8_BIT_WIDTH CHAR_BIT
79 #define IGB_8_BIT_MASK UINT8_MAX
81 /* Additional timesync values. */
82 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
83 #define E1000_ETQF_FILTER_1588 3
84 #define IGB_82576_TSYNC_SHIFT 16
85 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
86 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89 #define E1000_VTIVAR_MISC 0x01740
90 #define E1000_VTIVAR_MISC_MASK 0xFF
91 #define E1000_VTIVAR_VALID 0x80
92 #define E1000_VTIVAR_MISC_MAILBOX 0
93 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
95 /* External VLAN Enable bit mask */
96 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
98 /* External VLAN Ether Type bit mask and shift */
99 #define E1000_VET_VET_EXT 0xFFFF0000
100 #define E1000_VET_VET_EXT_SHIFT 16
102 static int eth_igb_configure(struct rte_eth_dev *dev);
103 static int eth_igb_start(struct rte_eth_dev *dev);
104 static void eth_igb_stop(struct rte_eth_dev *dev);
105 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
107 static void eth_igb_close(struct rte_eth_dev *dev);
108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
112 static int eth_igb_link_update(struct rte_eth_dev *dev,
113 int wait_to_complete);
114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
115 struct rte_eth_stats *rte_stats);
116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
117 struct rte_eth_xstat *xstats, unsigned n);
118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
119 struct rte_eth_xstat_name *xstats_names,
121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
124 struct rte_eth_dev_info *dev_info);
125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
127 struct rte_eth_dev_info *dev_info);
128 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
129 struct rte_eth_fc_conf *fc_conf);
130 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
138 static int igb_hardware_init(struct e1000_hw *hw);
139 static void igb_hw_control_acquire(struct e1000_hw *hw);
140 static void igb_hw_control_release(struct e1000_hw *hw);
141 static void igb_init_manageability(struct e1000_hw *hw);
142 static void igb_release_manageability(struct e1000_hw *hw);
144 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
147 uint16_t vlan_id, int on);
148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
149 enum rte_vlan_type vlan_type,
151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int eth_igb_led_on(struct rte_eth_dev *dev);
161 static int eth_igb_led_off(struct rte_eth_dev *dev);
163 static void igb_intr_disable(struct e1000_hw *hw);
164 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
166 struct ether_addr *mac_addr,
167 uint32_t index, uint32_t pool);
168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
170 struct ether_addr *addr);
172 static void igbvf_intr_disable(struct e1000_hw *hw);
173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
174 static int igbvf_dev_start(struct rte_eth_dev *dev);
175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
176 static void igbvf_dev_close(struct rte_eth_dev *dev);
177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
181 static int eth_igbvf_link_update(struct e1000_hw *hw);
182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
183 struct rte_eth_stats *rte_stats);
184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
187 struct rte_eth_xstat_name *xstats_names,
189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
191 uint16_t vlan_id, int on);
192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
195 struct ether_addr *addr);
196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
197 static int igbvf_get_regs(struct rte_eth_dev *dev,
198 struct rte_dev_reg_info *regs);
200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
201 struct rte_eth_rss_reta_entry64 *reta_conf,
203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
204 struct rte_eth_rss_reta_entry64 *reta_conf,
207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
208 struct rte_eth_syn_filter *filter,
210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
211 struct rte_eth_syn_filter *filter);
212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ntuple_filter *ntuple_filter);
217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
218 struct rte_eth_ntuple_filter *ntuple_filter);
219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
220 struct rte_eth_flex_filter *filter,
222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
223 struct rte_eth_flex_filter *filter);
224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
225 enum rte_filter_op filter_op,
227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
228 struct rte_eth_ntuple_filter *ntuple_filter);
229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
230 struct rte_eth_ntuple_filter *ntuple_filter);
231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
232 struct rte_eth_ntuple_filter *filter,
234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter);
236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
237 enum rte_filter_op filter_op,
239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
240 struct rte_eth_ethertype_filter *filter,
242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
243 enum rte_filter_op filter_op,
245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
246 struct rte_eth_ethertype_filter *filter);
247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
248 enum rte_filter_type filter_type,
249 enum rte_filter_op filter_op,
251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
253 struct rte_dev_reg_info *regs);
254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
256 struct rte_dev_eeprom_info *eeprom);
257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
258 struct rte_dev_eeprom_info *eeprom);
259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
260 struct ether_addr *mc_addr_set,
261 uint32_t nb_mc_addr);
262 static int igb_timesync_enable(struct rte_eth_dev *dev);
263 static int igb_timesync_disable(struct rte_eth_dev *dev);
264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
265 struct timespec *timestamp,
267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
268 struct timespec *timestamp);
269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
271 struct timespec *timestamp);
272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
273 const struct timespec *timestamp);
274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
279 uint8_t queue, uint8_t msix_vector);
280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
281 uint8_t index, uint8_t offset);
282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
288 * Define VF Stats MACRO for Non "cleared on read" register
290 #define UPDATE_VF_STAT(reg, last, cur) \
292 u32 latest = E1000_READ_REG(hw, reg); \
293 cur += (latest - last) & UINT_MAX; \
297 #define IGB_FC_PAUSE_TIME 0x0680
298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
301 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
306 * The set of PCI devices this driver supports
308 static const struct rte_pci_id pci_id_igb_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
348 { .vendor_id = 0, /* sentinel */ },
352 * The set of PCI devices this driver supports (for 82576&I350 VF)
354 static const struct rte_pci_id pci_id_igbvf_map[] = {
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
356 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
357 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
358 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
359 { .vendor_id = 0, /* sentinel */ },
362 static const struct rte_eth_desc_lim rx_desc_lim = {
363 .nb_max = E1000_MAX_RING_DESC,
364 .nb_min = E1000_MIN_RING_DESC,
365 .nb_align = IGB_RXD_ALIGN,
368 static const struct rte_eth_desc_lim tx_desc_lim = {
369 .nb_max = E1000_MAX_RING_DESC,
370 .nb_min = E1000_MIN_RING_DESC,
371 .nb_align = IGB_RXD_ALIGN,
374 static const struct eth_dev_ops eth_igb_ops = {
375 .dev_configure = eth_igb_configure,
376 .dev_start = eth_igb_start,
377 .dev_stop = eth_igb_stop,
378 .dev_set_link_up = eth_igb_dev_set_link_up,
379 .dev_set_link_down = eth_igb_dev_set_link_down,
380 .dev_close = eth_igb_close,
381 .promiscuous_enable = eth_igb_promiscuous_enable,
382 .promiscuous_disable = eth_igb_promiscuous_disable,
383 .allmulticast_enable = eth_igb_allmulticast_enable,
384 .allmulticast_disable = eth_igb_allmulticast_disable,
385 .link_update = eth_igb_link_update,
386 .stats_get = eth_igb_stats_get,
387 .xstats_get = eth_igb_xstats_get,
388 .xstats_get_names = eth_igb_xstats_get_names,
389 .stats_reset = eth_igb_stats_reset,
390 .xstats_reset = eth_igb_xstats_reset,
391 .dev_infos_get = eth_igb_infos_get,
392 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
393 .mtu_set = eth_igb_mtu_set,
394 .vlan_filter_set = eth_igb_vlan_filter_set,
395 .vlan_tpid_set = eth_igb_vlan_tpid_set,
396 .vlan_offload_set = eth_igb_vlan_offload_set,
397 .rx_queue_setup = eth_igb_rx_queue_setup,
398 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
399 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
400 .rx_queue_release = eth_igb_rx_queue_release,
401 .rx_queue_count = eth_igb_rx_queue_count,
402 .rx_descriptor_done = eth_igb_rx_descriptor_done,
403 .tx_queue_setup = eth_igb_tx_queue_setup,
404 .tx_queue_release = eth_igb_tx_queue_release,
405 .dev_led_on = eth_igb_led_on,
406 .dev_led_off = eth_igb_led_off,
407 .flow_ctrl_get = eth_igb_flow_ctrl_get,
408 .flow_ctrl_set = eth_igb_flow_ctrl_set,
409 .mac_addr_add = eth_igb_rar_set,
410 .mac_addr_remove = eth_igb_rar_clear,
411 .mac_addr_set = eth_igb_default_mac_addr_set,
412 .reta_update = eth_igb_rss_reta_update,
413 .reta_query = eth_igb_rss_reta_query,
414 .rss_hash_update = eth_igb_rss_hash_update,
415 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
416 .filter_ctrl = eth_igb_filter_ctrl,
417 .set_mc_addr_list = eth_igb_set_mc_addr_list,
418 .rxq_info_get = igb_rxq_info_get,
419 .txq_info_get = igb_txq_info_get,
420 .timesync_enable = igb_timesync_enable,
421 .timesync_disable = igb_timesync_disable,
422 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
423 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
424 .get_reg = eth_igb_get_regs,
425 .get_eeprom_length = eth_igb_get_eeprom_length,
426 .get_eeprom = eth_igb_get_eeprom,
427 .set_eeprom = eth_igb_set_eeprom,
428 .timesync_adjust_time = igb_timesync_adjust_time,
429 .timesync_read_time = igb_timesync_read_time,
430 .timesync_write_time = igb_timesync_write_time,
434 * dev_ops for virtual function, bare necessities for basic vf
435 * operation have been implemented
437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
438 .dev_configure = igbvf_dev_configure,
439 .dev_start = igbvf_dev_start,
440 .dev_stop = igbvf_dev_stop,
441 .dev_close = igbvf_dev_close,
442 .promiscuous_enable = igbvf_promiscuous_enable,
443 .promiscuous_disable = igbvf_promiscuous_disable,
444 .allmulticast_enable = igbvf_allmulticast_enable,
445 .allmulticast_disable = igbvf_allmulticast_disable,
446 .link_update = eth_igb_link_update,
447 .stats_get = eth_igbvf_stats_get,
448 .xstats_get = eth_igbvf_xstats_get,
449 .xstats_get_names = eth_igbvf_xstats_get_names,
450 .stats_reset = eth_igbvf_stats_reset,
451 .xstats_reset = eth_igbvf_stats_reset,
452 .vlan_filter_set = igbvf_vlan_filter_set,
453 .dev_infos_get = eth_igbvf_infos_get,
454 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
455 .rx_queue_setup = eth_igb_rx_queue_setup,
456 .rx_queue_release = eth_igb_rx_queue_release,
457 .tx_queue_setup = eth_igb_tx_queue_setup,
458 .tx_queue_release = eth_igb_tx_queue_release,
459 .set_mc_addr_list = eth_igb_set_mc_addr_list,
460 .rxq_info_get = igb_rxq_info_get,
461 .txq_info_get = igb_txq_info_get,
462 .mac_addr_set = igbvf_default_mac_addr_set,
463 .get_reg = igbvf_get_regs,
466 /* store statistics names and its offset in stats structure */
467 struct rte_igb_xstats_name_off {
468 char name[RTE_ETH_XSTATS_NAME_SIZE];
472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
473 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
474 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
475 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
476 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
477 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
478 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
479 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
481 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
482 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
483 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
484 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
485 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
486 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
487 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
488 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
489 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
490 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
491 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
493 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
494 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
495 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
496 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
497 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
499 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
501 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
502 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
503 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
504 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
505 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
506 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
507 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
508 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
509 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
510 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
511 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
512 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
513 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
514 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
515 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
516 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
517 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
518 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
520 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
522 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
523 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
524 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
525 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
526 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
527 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
528 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
530 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
534 sizeof(rte_igb_stats_strings[0]))
536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
537 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
538 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
539 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
540 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
541 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
545 sizeof(rte_igbvf_stats_strings[0]))
548 * Atomically reads the link status information from global
549 * structure rte_eth_dev.
552 * - Pointer to the structure rte_eth_dev to read from.
553 * - Pointer to the buffer to be saved with the link status.
556 * - On success, zero.
557 * - On failure, negative value.
560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
561 struct rte_eth_link *link)
563 struct rte_eth_link *dst = link;
564 struct rte_eth_link *src = &(dev->data->dev_link);
566 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
567 *(uint64_t *)src) == 0)
574 * Atomically writes the link status information into global
575 * structure rte_eth_dev.
578 * - Pointer to the structure rte_eth_dev to read from.
579 * - Pointer to the buffer to be saved with the link status.
582 * - On success, zero.
583 * - On failure, negative value.
586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
587 struct rte_eth_link *link)
589 struct rte_eth_link *dst = &(dev->data->dev_link);
590 struct rte_eth_link *src = link;
592 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
593 *(uint64_t *)src) == 0)
600 igb_intr_enable(struct rte_eth_dev *dev)
602 struct e1000_interrupt *intr =
603 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
604 struct e1000_hw *hw =
605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
607 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
608 E1000_WRITE_FLUSH(hw);
612 igb_intr_disable(struct e1000_hw *hw)
614 E1000_WRITE_REG(hw, E1000_IMC, ~0);
615 E1000_WRITE_FLUSH(hw);
619 igbvf_intr_enable(struct rte_eth_dev *dev)
621 struct e1000_hw *hw =
622 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
624 /* only for mailbox */
625 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
626 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
627 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
628 E1000_WRITE_FLUSH(hw);
631 /* only for mailbox now. If RX/TX needed, should extend this function. */
633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
638 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
639 tmp |= E1000_VTIVAR_VALID;
640 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
646 struct e1000_hw *hw =
647 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
649 /* Configure VF other cause ivar */
650 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
653 static inline int32_t
654 igb_pf_reset_hw(struct e1000_hw *hw)
659 status = e1000_reset_hw(hw);
661 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
662 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
663 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
664 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
665 E1000_WRITE_FLUSH(hw);
671 igb_identify_hardware(struct rte_eth_dev *dev)
673 struct e1000_hw *hw =
674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
676 hw->vendor_id = dev->pci_dev->id.vendor_id;
677 hw->device_id = dev->pci_dev->id.device_id;
678 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
679 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
681 e1000_set_mac_type(hw);
683 /* need to check if it is a vf device below */
687 igb_reset_swfw_lock(struct e1000_hw *hw)
692 * Do mac ops initialization manually here, since we will need
693 * some function pointers set by this call.
695 ret_val = e1000_init_mac_params(hw);
700 * SMBI lock should not fail in this early stage. If this is the case,
701 * it is due to an improper exit of the application.
702 * So force the release of the faulty lock.
704 if (e1000_get_hw_semaphore_generic(hw) < 0) {
705 PMD_DRV_LOG(DEBUG, "SMBI lock released");
707 e1000_put_hw_semaphore_generic(hw);
709 if (hw->mac.ops.acquire_swfw_sync != NULL) {
713 * Phy lock should not fail in this early stage. If this is the case,
714 * it is due to an improper exit of the application.
715 * So force the release of the faulty lock.
717 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
718 if (hw->bus.func > E1000_FUNC_1)
720 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
721 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
724 hw->mac.ops.release_swfw_sync(hw, mask);
727 * This one is more tricky since it is common to all ports; but
728 * swfw_sync retries last long enough (1s) to be almost sure that if
729 * lock can not be taken it is due to an improper lock of the
732 mask = E1000_SWFW_EEP_SM;
733 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
734 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
736 hw->mac.ops.release_swfw_sync(hw, mask);
739 return E1000_SUCCESS;
743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
746 struct rte_pci_device *pci_dev;
747 struct e1000_hw *hw =
748 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
749 struct e1000_vfta * shadow_vfta =
750 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
751 struct e1000_filter_info *filter_info =
752 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
753 struct e1000_adapter *adapter =
754 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
758 pci_dev = eth_dev->pci_dev;
760 eth_dev->dev_ops = ð_igb_ops;
761 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
762 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
764 /* for secondary processes, we don't initialise any further as primary
765 * has already done this work. Only check we don't need a different
767 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
768 if (eth_dev->data->scattered_rx)
769 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
773 rte_eth_copy_pci_info(eth_dev, pci_dev);
775 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
777 igb_identify_hardware(eth_dev);
778 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
783 e1000_get_bus_info(hw);
785 /* Reset any pending lock */
786 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
791 /* Finish initialization */
792 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
798 hw->phy.autoneg_wait_to_complete = 0;
799 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
802 if (hw->phy.media_type == e1000_media_type_copper) {
803 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
804 hw->phy.disable_polarity_correction = 0;
805 hw->phy.ms_type = e1000_ms_hw_default;
809 * Start from a known state, this is important in reading the nvm
814 /* Make sure we have a good EEPROM before we read from it */
815 if (e1000_validate_nvm_checksum(hw) < 0) {
817 * Some PCI-E parts fail the first check due to
818 * the link being in sleep state, call it again,
819 * if it fails a second time its a real issue.
821 if (e1000_validate_nvm_checksum(hw) < 0) {
822 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
828 /* Read the permanent MAC address out of the EEPROM */
829 if (e1000_read_mac_addr(hw) != 0) {
830 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
835 /* Allocate memory for storing MAC addresses */
836 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
837 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
838 if (eth_dev->data->mac_addrs == NULL) {
839 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
840 "store MAC addresses",
841 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
846 /* Copy the permanent MAC address */
847 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
849 /* initialize the vfta */
850 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
852 /* Now initialize the hardware */
853 if (igb_hardware_init(hw) != 0) {
854 PMD_INIT_LOG(ERR, "Hardware initialization failed");
855 rte_free(eth_dev->data->mac_addrs);
856 eth_dev->data->mac_addrs = NULL;
860 hw->mac.get_link_status = 1;
861 adapter->stopped = 0;
863 /* Indicate SOL/IDER usage */
864 if (e1000_check_reset_block(hw) < 0) {
865 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
869 /* initialize PF if max_vfs not zero */
870 igb_pf_host_init(eth_dev);
872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
873 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
874 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
876 E1000_WRITE_FLUSH(hw);
878 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
879 eth_dev->data->port_id, pci_dev->id.vendor_id,
880 pci_dev->id.device_id);
882 rte_intr_callback_register(&pci_dev->intr_handle,
883 eth_igb_interrupt_handler,
886 /* enable uio/vfio intr/eventfd mapping */
887 rte_intr_enable(&pci_dev->intr_handle);
889 /* enable support intr */
890 igb_intr_enable(eth_dev);
892 TAILQ_INIT(&filter_info->flex_list);
893 filter_info->flex_mask = 0;
894 TAILQ_INIT(&filter_info->twotuple_list);
895 filter_info->twotuple_mask = 0;
896 TAILQ_INIT(&filter_info->fivetuple_list);
897 filter_info->fivetuple_mask = 0;
902 igb_hw_control_release(hw);
908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
910 struct rte_pci_device *pci_dev;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
915 PMD_INIT_FUNC_TRACE();
917 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
920 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
921 pci_dev = eth_dev->pci_dev;
923 if (adapter->stopped == 0)
924 eth_igb_close(eth_dev);
926 eth_dev->dev_ops = NULL;
927 eth_dev->rx_pkt_burst = NULL;
928 eth_dev->tx_pkt_burst = NULL;
930 /* Reset any pending lock */
931 igb_reset_swfw_lock(hw);
933 rte_free(eth_dev->data->mac_addrs);
934 eth_dev->data->mac_addrs = NULL;
936 /* uninitialize PF if max_vfs not zero */
937 igb_pf_host_uninit(eth_dev);
939 /* disable uio intr before callback unregister */
940 rte_intr_disable(&(pci_dev->intr_handle));
941 rte_intr_callback_unregister(&(pci_dev->intr_handle),
942 eth_igb_interrupt_handler, (void *)eth_dev);
948 * Virtual Function device init
951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
953 struct rte_pci_device *pci_dev;
954 struct e1000_adapter *adapter =
955 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
956 struct e1000_hw *hw =
957 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
959 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
961 PMD_INIT_FUNC_TRACE();
963 eth_dev->dev_ops = &igbvf_eth_dev_ops;
964 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
965 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
967 /* for secondary processes, we don't initialise any further as primary
968 * has already done this work. Only check we don't need a different
970 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
971 if (eth_dev->data->scattered_rx)
972 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
976 pci_dev = eth_dev->pci_dev;
978 rte_eth_copy_pci_info(eth_dev, pci_dev);
980 hw->device_id = pci_dev->id.device_id;
981 hw->vendor_id = pci_dev->id.vendor_id;
982 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
983 adapter->stopped = 0;
985 /* Initialize the shared code (base driver) */
986 diag = e1000_setup_init_funcs(hw, TRUE);
988 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
993 /* init_mailbox_params */
994 hw->mbx.ops.init_params(hw);
996 /* Disable the interrupts for VF */
997 igbvf_intr_disable(hw);
999 diag = hw->mac.ops.reset_hw(hw);
1001 /* Allocate memory for storing MAC addresses */
1002 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003 hw->mac.rar_entry_count, 0);
1004 if (eth_dev->data->mac_addrs == NULL) {
1006 "Failed to allocate %d bytes needed to store MAC "
1008 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1012 /* Generate a random MAC address, if none was assigned by PF. */
1013 if (is_zero_ether_addr(perm_addr)) {
1014 eth_random_addr(perm_addr->addr_bytes);
1015 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1017 rte_free(eth_dev->data->mac_addrs);
1018 eth_dev->data->mac_addrs = NULL;
1021 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1022 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1023 "%02x:%02x:%02x:%02x:%02x:%02x",
1024 perm_addr->addr_bytes[0],
1025 perm_addr->addr_bytes[1],
1026 perm_addr->addr_bytes[2],
1027 perm_addr->addr_bytes[3],
1028 perm_addr->addr_bytes[4],
1029 perm_addr->addr_bytes[5]);
1032 /* Copy the permanent MAC address */
1033 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034 ð_dev->data->mac_addrs[0]);
1036 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1038 eth_dev->data->port_id, pci_dev->id.vendor_id,
1039 pci_dev->id.device_id, "igb_mac_82576_vf");
1041 rte_intr_callback_register(&pci_dev->intr_handle,
1042 eth_igbvf_interrupt_handler,
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1051 struct e1000_adapter *adapter =
1052 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1055 PMD_INIT_FUNC_TRACE();
1057 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1060 if (adapter->stopped == 0)
1061 igbvf_dev_close(eth_dev);
1063 eth_dev->dev_ops = NULL;
1064 eth_dev->rx_pkt_burst = NULL;
1065 eth_dev->tx_pkt_burst = NULL;
1067 rte_free(eth_dev->data->mac_addrs);
1068 eth_dev->data->mac_addrs = NULL;
1070 /* disable uio intr before callback unregister */
1071 rte_intr_disable(&pci_dev->intr_handle);
1072 rte_intr_callback_unregister(&pci_dev->intr_handle,
1073 eth_igbvf_interrupt_handler,
1079 static struct eth_driver rte_igb_pmd = {
1081 .name = "rte_igb_pmd",
1082 .id_table = pci_id_igb_map,
1083 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1084 RTE_PCI_DRV_DETACHABLE,
1086 .eth_dev_init = eth_igb_dev_init,
1087 .eth_dev_uninit = eth_igb_dev_uninit,
1088 .dev_private_size = sizeof(struct e1000_adapter),
1092 * virtual function driver struct
1094 static struct eth_driver rte_igbvf_pmd = {
1096 .name = "rte_igbvf_pmd",
1097 .id_table = pci_id_igbvf_map,
1098 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1100 .eth_dev_init = eth_igbvf_dev_init,
1101 .eth_dev_uninit = eth_igbvf_dev_uninit,
1102 .dev_private_size = sizeof(struct e1000_adapter),
1106 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1108 rte_eth_driver_register(&rte_igb_pmd);
1113 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1115 struct e1000_hw *hw =
1116 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1118 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1119 rctl |= E1000_RCTL_VFE;
1120 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1124 * VF Driver initialization routine.
1125 * Invoked one at EAL init time.
1126 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1129 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1131 PMD_INIT_FUNC_TRACE();
1133 rte_eth_driver_register(&rte_igbvf_pmd);
1138 igb_check_mq_mode(struct rte_eth_dev *dev)
1140 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1141 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1142 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1143 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1145 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1146 tx_mq_mode == ETH_MQ_TX_DCB ||
1147 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1148 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1151 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1152 /* Check multi-queue mode.
1153 * To no break software we accept ETH_MQ_RX_NONE as this might
1154 * be used to turn off VLAN filter.
1157 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1158 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1159 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1160 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1162 /* Only support one queue on VFs.
1163 * RSS together with SRIOV is not supported.
1165 PMD_INIT_LOG(ERR, "SRIOV is active,"
1166 " wrong mq_mode rx %d.",
1170 /* TX mode is not used here, so mode might be ignored.*/
1171 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1172 /* SRIOV only works in VMDq enable mode */
1173 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1174 " TX mode %d is not supported. "
1175 " Driver will behave as %d mode.",
1176 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1179 /* check valid queue number */
1180 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1181 PMD_INIT_LOG(ERR, "SRIOV is active,"
1182 " only support one queue on VFs.");
1186 /* To no break software that set invalid mode, only display
1187 * warning if invalid mode is used.
1189 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1190 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1191 rx_mq_mode != ETH_MQ_RX_RSS) {
1192 /* RSS together with VMDq not supported*/
1193 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1198 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1199 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1200 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1201 " Due to txmode is meaningless in this"
1202 " driver, just ignore.",
1210 eth_igb_configure(struct rte_eth_dev *dev)
1212 struct e1000_interrupt *intr =
1213 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1216 PMD_INIT_FUNC_TRACE();
1218 /* multipe queue mode checking */
1219 ret = igb_check_mq_mode(dev);
1221 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1226 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1227 PMD_INIT_FUNC_TRACE();
1233 eth_igb_start(struct rte_eth_dev *dev)
1235 struct e1000_hw *hw =
1236 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237 struct e1000_adapter *adapter =
1238 E1000_DEV_PRIVATE(dev->data->dev_private);
1239 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1241 uint32_t intr_vector = 0;
1247 PMD_INIT_FUNC_TRACE();
1249 /* disable uio/vfio intr/eventfd mapping */
1250 rte_intr_disable(intr_handle);
1252 /* Power up the phy. Needed to make the link go Up */
1253 eth_igb_dev_set_link_up(dev);
1256 * Packet Buffer Allocation (PBA)
1257 * Writing PBA sets the receive portion of the buffer
1258 * the remainder is used for the transmit buffer.
1260 if (hw->mac.type == e1000_82575) {
1263 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1264 E1000_WRITE_REG(hw, E1000_PBA, pba);
1267 /* Put the address into the Receive Address Array */
1268 e1000_rar_set(hw, hw->mac.addr, 0);
1270 /* Initialize the hardware */
1271 if (igb_hardware_init(hw)) {
1272 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1275 adapter->stopped = 0;
1277 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1279 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1280 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1281 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1282 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1283 E1000_WRITE_FLUSH(hw);
1285 /* configure PF module if SRIOV enabled */
1286 igb_pf_host_configure(dev);
1288 /* check and configure queue intr-vector mapping */
1289 if ((rte_intr_cap_multiple(intr_handle) ||
1290 !RTE_ETH_DEV_SRIOV(dev).active) &&
1291 dev->data->dev_conf.intr_conf.rxq != 0) {
1292 intr_vector = dev->data->nb_rx_queues;
1293 if (rte_intr_efd_enable(intr_handle, intr_vector))
1297 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1298 intr_handle->intr_vec =
1299 rte_zmalloc("intr_vec",
1300 dev->data->nb_rx_queues * sizeof(int), 0);
1301 if (intr_handle->intr_vec == NULL) {
1302 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1303 " intr_vec\n", dev->data->nb_rx_queues);
1308 /* confiugre msix for rx interrupt */
1309 eth_igb_configure_msix_intr(dev);
1311 /* Configure for OS presence */
1312 igb_init_manageability(hw);
1314 eth_igb_tx_init(dev);
1316 /* This can fail when allocating mbufs for descriptor rings */
1317 ret = eth_igb_rx_init(dev);
1319 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1320 igb_dev_clear_queues(dev);
1324 e1000_clear_hw_cntrs_base_generic(hw);
1327 * VLAN Offload Settings
1329 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1330 ETH_VLAN_EXTEND_MASK;
1331 eth_igb_vlan_offload_set(dev, mask);
1333 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1334 /* Enable VLAN filter since VMDq always use VLAN filter */
1335 igb_vmdq_vlan_hw_filter_enable(dev);
1338 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1339 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1340 (hw->mac.type == e1000_i211)) {
1341 /* Configure EITR with the maximum possible value (0xFFFF) */
1342 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1345 /* Setup link speed and duplex */
1346 speeds = &dev->data->dev_conf.link_speeds;
1347 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1348 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1351 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1354 hw->phy.autoneg_advertised = 0;
1356 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1357 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1358 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1360 goto error_invalid_config;
1362 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1363 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1366 if (*speeds & ETH_LINK_SPEED_10M) {
1367 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1370 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1371 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1374 if (*speeds & ETH_LINK_SPEED_100M) {
1375 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1378 if (*speeds & ETH_LINK_SPEED_1G) {
1379 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1382 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1383 goto error_invalid_config;
1386 e1000_setup_link(hw);
1388 if (rte_intr_allow_others(intr_handle)) {
1389 /* check if lsc interrupt is enabled */
1390 if (dev->data->dev_conf.intr_conf.lsc != 0)
1391 eth_igb_lsc_interrupt_setup(dev);
1393 rte_intr_callback_unregister(intr_handle,
1394 eth_igb_interrupt_handler,
1396 if (dev->data->dev_conf.intr_conf.lsc != 0)
1397 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1398 " no intr multiplex\n");
1401 /* check if rxq interrupt is enabled */
1402 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1403 rte_intr_dp_is_en(intr_handle))
1404 eth_igb_rxq_interrupt_setup(dev);
1406 /* enable uio/vfio intr/eventfd mapping */
1407 rte_intr_enable(intr_handle);
1409 /* resume enabled intr since hw reset */
1410 igb_intr_enable(dev);
1412 PMD_INIT_LOG(DEBUG, "<<");
1416 error_invalid_config:
1417 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1418 dev->data->dev_conf.link_speeds, dev->data->port_id);
1419 igb_dev_clear_queues(dev);
1423 /*********************************************************************
1425 * This routine disables all traffic on the adapter by issuing a
1426 * global reset on the MAC.
1428 **********************************************************************/
1430 eth_igb_stop(struct rte_eth_dev *dev)
1432 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433 struct e1000_filter_info *filter_info =
1434 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1435 struct rte_eth_link link;
1436 struct e1000_flex_filter *p_flex;
1437 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1438 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1439 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1441 igb_intr_disable(hw);
1443 /* disable intr eventfd mapping */
1444 rte_intr_disable(intr_handle);
1446 igb_pf_reset_hw(hw);
1447 E1000_WRITE_REG(hw, E1000_WUC, 0);
1449 /* Set bit for Go Link disconnect */
1450 if (hw->mac.type >= e1000_82580) {
1453 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1454 phpm_reg |= E1000_82580_PM_GO_LINKD;
1455 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1458 /* Power down the phy. Needed to make the link go Down */
1459 eth_igb_dev_set_link_down(dev);
1461 igb_dev_clear_queues(dev);
1463 /* clear the recorded link status */
1464 memset(&link, 0, sizeof(link));
1465 rte_igb_dev_atomic_write_link_status(dev, &link);
1467 /* Remove all flex filters of the device */
1468 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1469 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1472 filter_info->flex_mask = 0;
1474 /* Remove all ntuple filters of the device */
1475 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1476 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1477 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1478 TAILQ_REMOVE(&filter_info->fivetuple_list,
1482 filter_info->fivetuple_mask = 0;
1483 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1484 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1485 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1486 TAILQ_REMOVE(&filter_info->twotuple_list,
1490 filter_info->twotuple_mask = 0;
1492 if (!rte_intr_allow_others(intr_handle))
1493 /* resume to the default handler */
1494 rte_intr_callback_register(intr_handle,
1495 eth_igb_interrupt_handler,
1498 /* Clean datapath event and queue/vec mapping */
1499 rte_intr_efd_disable(intr_handle);
1500 if (intr_handle->intr_vec != NULL) {
1501 rte_free(intr_handle->intr_vec);
1502 intr_handle->intr_vec = NULL;
1507 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1509 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511 if (hw->phy.media_type == e1000_media_type_copper)
1512 e1000_power_up_phy(hw);
1514 e1000_power_up_fiber_serdes_link(hw);
1520 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1522 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 if (hw->phy.media_type == e1000_media_type_copper)
1525 e1000_power_down_phy(hw);
1527 e1000_shutdown_fiber_serdes_link(hw);
1533 eth_igb_close(struct rte_eth_dev *dev)
1535 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536 struct e1000_adapter *adapter =
1537 E1000_DEV_PRIVATE(dev->data->dev_private);
1538 struct rte_eth_link link;
1539 struct rte_pci_device *pci_dev;
1542 adapter->stopped = 1;
1544 e1000_phy_hw_reset(hw);
1545 igb_release_manageability(hw);
1546 igb_hw_control_release(hw);
1548 /* Clear bit for Go Link disconnect */
1549 if (hw->mac.type >= e1000_82580) {
1552 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1553 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1554 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1557 igb_dev_free_queues(dev);
1559 pci_dev = dev->pci_dev;
1560 if (pci_dev->intr_handle.intr_vec) {
1561 rte_free(pci_dev->intr_handle.intr_vec);
1562 pci_dev->intr_handle.intr_vec = NULL;
1565 memset(&link, 0, sizeof(link));
1566 rte_igb_dev_atomic_write_link_status(dev, &link);
1570 igb_get_rx_buffer_size(struct e1000_hw *hw)
1572 uint32_t rx_buf_size;
1573 if (hw->mac.type == e1000_82576) {
1574 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1575 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1576 /* PBS needs to be translated according to a lookup table */
1577 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1578 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1579 rx_buf_size = (rx_buf_size << 10);
1580 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1581 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1583 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1589 /*********************************************************************
1591 * Initialize the hardware
1593 **********************************************************************/
1595 igb_hardware_init(struct e1000_hw *hw)
1597 uint32_t rx_buf_size;
1600 /* Let the firmware know the OS is in control */
1601 igb_hw_control_acquire(hw);
1604 * These parameters control the automatic generation (Tx) and
1605 * response (Rx) to Ethernet PAUSE frames.
1606 * - High water mark should allow for at least two standard size (1518)
1607 * frames to be received after sending an XOFF.
1608 * - Low water mark works best when it is very near the high water mark.
1609 * This allows the receiver to restart by sending XON when it has
1610 * drained a bit. Here we use an arbitrary value of 1500 which will
1611 * restart after one full frame is pulled from the buffer. There
1612 * could be several smaller frames in the buffer and if so they will
1613 * not trigger the XON until their total number reduces the buffer
1615 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1617 rx_buf_size = igb_get_rx_buffer_size(hw);
1619 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1620 hw->fc.low_water = hw->fc.high_water - 1500;
1621 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1622 hw->fc.send_xon = 1;
1624 /* Set Flow control, use the tunable location if sane */
1625 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1626 hw->fc.requested_mode = igb_fc_setting;
1628 hw->fc.requested_mode = e1000_fc_none;
1630 /* Issue a global reset */
1631 igb_pf_reset_hw(hw);
1632 E1000_WRITE_REG(hw, E1000_WUC, 0);
1634 diag = e1000_init_hw(hw);
1638 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1639 e1000_get_phy_info(hw);
1640 e1000_check_for_link(hw);
1645 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1647 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1651 uint64_t old_gprc = stats->gprc;
1652 uint64_t old_gptc = stats->gptc;
1653 uint64_t old_tpr = stats->tpr;
1654 uint64_t old_tpt = stats->tpt;
1655 uint64_t old_rpthc = stats->rpthc;
1656 uint64_t old_hgptc = stats->hgptc;
1658 if(hw->phy.media_type == e1000_media_type_copper ||
1659 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1661 E1000_READ_REG(hw,E1000_SYMERRS);
1662 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1665 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1666 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1667 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1668 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1670 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1671 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1672 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1673 stats->dc += E1000_READ_REG(hw, E1000_DC);
1674 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1675 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1676 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1678 ** For watchdog management we need to know if we have been
1679 ** paused during the last interval, so capture that here.
1681 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1682 stats->xoffrxc += pause_frames;
1683 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1684 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1685 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1686 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1687 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1688 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1689 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1690 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1691 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1692 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1693 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1694 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1696 /* For the 64-bit byte counters the low dword must be read first. */
1697 /* Both registers clear on the read of the high dword */
1699 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1700 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1701 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1702 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1703 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1704 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1705 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1707 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1708 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1709 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1710 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1711 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1713 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1714 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1716 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1717 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1718 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1719 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1720 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1721 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1723 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1724 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1725 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1726 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1727 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1728 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1729 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1730 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1732 /* Interrupt Counts */
1734 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1735 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1736 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1737 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1738 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1739 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1740 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1741 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1742 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1744 /* Host to Card Statistics */
1746 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1747 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1748 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1749 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1750 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1751 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1752 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1753 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1754 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1755 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1756 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1757 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1758 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1759 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1760 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1761 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1763 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1764 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1765 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1766 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1767 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1768 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1772 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1774 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775 struct e1000_hw_stats *stats =
1776 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1778 igb_read_stats_registers(hw, stats);
1780 if (rte_stats == NULL)
1784 rte_stats->imissed = stats->mpc;
1785 rte_stats->ierrors = stats->crcerrs +
1786 stats->rlec + stats->ruc + stats->roc +
1787 stats->rxerrc + stats->algnerrc + stats->cexterr;
1790 rte_stats->oerrors = stats->ecol + stats->latecol;
1792 rte_stats->ipackets = stats->gprc;
1793 rte_stats->opackets = stats->gptc;
1794 rte_stats->ibytes = stats->gorc;
1795 rte_stats->obytes = stats->gotc;
1799 eth_igb_stats_reset(struct rte_eth_dev *dev)
1801 struct e1000_hw_stats *hw_stats =
1802 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1804 /* HW registers are cleared on read */
1805 eth_igb_stats_get(dev, NULL);
1807 /* Reset software totals */
1808 memset(hw_stats, 0, sizeof(*hw_stats));
1812 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1814 struct e1000_hw_stats *stats =
1815 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817 /* HW registers are cleared on read */
1818 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1820 /* Reset software totals */
1821 memset(stats, 0, sizeof(*stats));
1824 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1825 struct rte_eth_xstat_name *xstats_names,
1826 __rte_unused unsigned limit)
1830 if (xstats_names == NULL)
1831 return IGB_NB_XSTATS;
1833 /* Note: limit checked in rte_eth_xstats_names() */
1835 for (i = 0; i < IGB_NB_XSTATS; i++) {
1836 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1837 "%s", rte_igb_stats_strings[i].name);
1840 return IGB_NB_XSTATS;
1844 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1847 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848 struct e1000_hw_stats *hw_stats =
1849 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1852 if (n < IGB_NB_XSTATS)
1853 return IGB_NB_XSTATS;
1855 igb_read_stats_registers(hw, hw_stats);
1857 /* If this is a reset xstats is NULL, and we have cleared the
1858 * registers by reading them.
1863 /* Extended stats */
1864 for (i = 0; i < IGB_NB_XSTATS; i++) {
1866 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1867 rte_igb_stats_strings[i].offset);
1870 return IGB_NB_XSTATS;
1874 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1876 /* Good Rx packets, include VF loopback */
1877 UPDATE_VF_STAT(E1000_VFGPRC,
1878 hw_stats->last_gprc, hw_stats->gprc);
1880 /* Good Rx octets, include VF loopback */
1881 UPDATE_VF_STAT(E1000_VFGORC,
1882 hw_stats->last_gorc, hw_stats->gorc);
1884 /* Good Tx packets, include VF loopback */
1885 UPDATE_VF_STAT(E1000_VFGPTC,
1886 hw_stats->last_gptc, hw_stats->gptc);
1888 /* Good Tx octets, include VF loopback */
1889 UPDATE_VF_STAT(E1000_VFGOTC,
1890 hw_stats->last_gotc, hw_stats->gotc);
1892 /* Rx Multicst packets */
1893 UPDATE_VF_STAT(E1000_VFMPRC,
1894 hw_stats->last_mprc, hw_stats->mprc);
1896 /* Good Rx loopback packets */
1897 UPDATE_VF_STAT(E1000_VFGPRLBC,
1898 hw_stats->last_gprlbc, hw_stats->gprlbc);
1900 /* Good Rx loopback octets */
1901 UPDATE_VF_STAT(E1000_VFGORLBC,
1902 hw_stats->last_gorlbc, hw_stats->gorlbc);
1904 /* Good Tx loopback packets */
1905 UPDATE_VF_STAT(E1000_VFGPTLBC,
1906 hw_stats->last_gptlbc, hw_stats->gptlbc);
1908 /* Good Tx loopback octets */
1909 UPDATE_VF_STAT(E1000_VFGOTLBC,
1910 hw_stats->last_gotlbc, hw_stats->gotlbc);
1913 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1914 struct rte_eth_xstat_name *xstats_names,
1915 __rte_unused unsigned limit)
1919 if (xstats_names != NULL)
1920 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1921 snprintf(xstats_names[i].name,
1922 sizeof(xstats_names[i].name), "%s",
1923 rte_igbvf_stats_strings[i].name);
1925 return IGBVF_NB_XSTATS;
1929 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1932 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1934 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1937 if (n < IGBVF_NB_XSTATS)
1938 return IGBVF_NB_XSTATS;
1940 igbvf_read_stats_registers(hw, hw_stats);
1945 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1947 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1948 rte_igbvf_stats_strings[i].offset);
1951 return IGBVF_NB_XSTATS;
1955 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1957 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1959 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1961 igbvf_read_stats_registers(hw, hw_stats);
1963 if (rte_stats == NULL)
1966 rte_stats->ipackets = hw_stats->gprc;
1967 rte_stats->ibytes = hw_stats->gorc;
1968 rte_stats->opackets = hw_stats->gptc;
1969 rte_stats->obytes = hw_stats->gotc;
1973 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1975 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1976 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1978 /* Sync HW register to the last stats */
1979 eth_igbvf_stats_get(dev, NULL);
1981 /* reset HW current stats*/
1982 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1983 offsetof(struct e1000_vf_stats, gprc));
1987 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1989 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1992 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1993 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1994 dev_info->rx_offload_capa =
1995 DEV_RX_OFFLOAD_VLAN_STRIP |
1996 DEV_RX_OFFLOAD_IPV4_CKSUM |
1997 DEV_RX_OFFLOAD_UDP_CKSUM |
1998 DEV_RX_OFFLOAD_TCP_CKSUM;
1999 dev_info->tx_offload_capa =
2000 DEV_TX_OFFLOAD_VLAN_INSERT |
2001 DEV_TX_OFFLOAD_IPV4_CKSUM |
2002 DEV_TX_OFFLOAD_UDP_CKSUM |
2003 DEV_TX_OFFLOAD_TCP_CKSUM |
2004 DEV_TX_OFFLOAD_SCTP_CKSUM |
2005 DEV_TX_OFFLOAD_TCP_TSO;
2007 switch (hw->mac.type) {
2009 dev_info->max_rx_queues = 4;
2010 dev_info->max_tx_queues = 4;
2011 dev_info->max_vmdq_pools = 0;
2015 dev_info->max_rx_queues = 16;
2016 dev_info->max_tx_queues = 16;
2017 dev_info->max_vmdq_pools = ETH_8_POOLS;
2018 dev_info->vmdq_queue_num = 16;
2022 dev_info->max_rx_queues = 8;
2023 dev_info->max_tx_queues = 8;
2024 dev_info->max_vmdq_pools = ETH_8_POOLS;
2025 dev_info->vmdq_queue_num = 8;
2029 dev_info->max_rx_queues = 8;
2030 dev_info->max_tx_queues = 8;
2031 dev_info->max_vmdq_pools = ETH_8_POOLS;
2032 dev_info->vmdq_queue_num = 8;
2036 dev_info->max_rx_queues = 8;
2037 dev_info->max_tx_queues = 8;
2041 dev_info->max_rx_queues = 4;
2042 dev_info->max_tx_queues = 4;
2043 dev_info->max_vmdq_pools = 0;
2047 dev_info->max_rx_queues = 2;
2048 dev_info->max_tx_queues = 2;
2049 dev_info->max_vmdq_pools = 0;
2053 /* Should not happen */
2056 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2057 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2058 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2060 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2062 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2063 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2064 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2066 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2070 dev_info->default_txconf = (struct rte_eth_txconf) {
2072 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2073 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2074 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2079 dev_info->rx_desc_lim = rx_desc_lim;
2080 dev_info->tx_desc_lim = tx_desc_lim;
2082 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2083 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2087 static const uint32_t *
2088 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2090 static const uint32_t ptypes[] = {
2091 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2094 RTE_PTYPE_L3_IPV4_EXT,
2096 RTE_PTYPE_L3_IPV6_EXT,
2100 RTE_PTYPE_TUNNEL_IP,
2101 RTE_PTYPE_INNER_L3_IPV6,
2102 RTE_PTYPE_INNER_L3_IPV6_EXT,
2103 RTE_PTYPE_INNER_L4_TCP,
2104 RTE_PTYPE_INNER_L4_UDP,
2108 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2109 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2115 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2117 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2120 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2121 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2122 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2123 DEV_RX_OFFLOAD_IPV4_CKSUM |
2124 DEV_RX_OFFLOAD_UDP_CKSUM |
2125 DEV_RX_OFFLOAD_TCP_CKSUM;
2126 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2127 DEV_TX_OFFLOAD_IPV4_CKSUM |
2128 DEV_TX_OFFLOAD_UDP_CKSUM |
2129 DEV_TX_OFFLOAD_TCP_CKSUM |
2130 DEV_TX_OFFLOAD_SCTP_CKSUM |
2131 DEV_TX_OFFLOAD_TCP_TSO;
2132 switch (hw->mac.type) {
2134 dev_info->max_rx_queues = 2;
2135 dev_info->max_tx_queues = 2;
2137 case e1000_vfadapt_i350:
2138 dev_info->max_rx_queues = 1;
2139 dev_info->max_tx_queues = 1;
2142 /* Should not happen */
2146 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2148 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2149 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2150 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2152 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2156 dev_info->default_txconf = (struct rte_eth_txconf) {
2158 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2159 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2160 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2165 dev_info->rx_desc_lim = rx_desc_lim;
2166 dev_info->tx_desc_lim = tx_desc_lim;
2169 /* return 0 means link status changed, -1 means not changed */
2171 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2173 struct e1000_hw *hw =
2174 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175 struct rte_eth_link link, old;
2176 int link_check, count;
2179 hw->mac.get_link_status = 1;
2181 /* possible wait-to-complete in up to 9 seconds */
2182 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2183 /* Read the real link status */
2184 switch (hw->phy.media_type) {
2185 case e1000_media_type_copper:
2186 /* Do the work to read phy */
2187 e1000_check_for_link(hw);
2188 link_check = !hw->mac.get_link_status;
2191 case e1000_media_type_fiber:
2192 e1000_check_for_link(hw);
2193 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2197 case e1000_media_type_internal_serdes:
2198 e1000_check_for_link(hw);
2199 link_check = hw->mac.serdes_has_link;
2202 /* VF device is type_unknown */
2203 case e1000_media_type_unknown:
2204 eth_igbvf_link_update(hw);
2205 link_check = !hw->mac.get_link_status;
2211 if (link_check || wait_to_complete == 0)
2213 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2215 memset(&link, 0, sizeof(link));
2216 rte_igb_dev_atomic_read_link_status(dev, &link);
2219 /* Now we check if a transition has happened */
2221 uint16_t duplex, speed;
2222 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2223 link.link_duplex = (duplex == FULL_DUPLEX) ?
2224 ETH_LINK_FULL_DUPLEX :
2225 ETH_LINK_HALF_DUPLEX;
2226 link.link_speed = speed;
2227 link.link_status = ETH_LINK_UP;
2228 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2229 ETH_LINK_SPEED_FIXED);
2230 } else if (!link_check) {
2231 link.link_speed = 0;
2232 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2233 link.link_status = ETH_LINK_DOWN;
2234 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2236 rte_igb_dev_atomic_write_link_status(dev, &link);
2239 if (old.link_status == link.link_status)
2247 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2248 * For ASF and Pass Through versions of f/w this means
2249 * that the driver is loaded.
2252 igb_hw_control_acquire(struct e1000_hw *hw)
2256 /* Let firmware know the driver has taken over */
2257 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2258 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2262 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2263 * For ASF and Pass Through versions of f/w this means that the
2264 * driver is no longer loaded.
2267 igb_hw_control_release(struct e1000_hw *hw)
2271 /* Let firmware taken over control of h/w */
2272 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2273 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2274 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2278 * Bit of a misnomer, what this really means is
2279 * to enable OS management of the system... aka
2280 * to disable special hardware management features.
2283 igb_init_manageability(struct e1000_hw *hw)
2285 if (e1000_enable_mng_pass_thru(hw)) {
2286 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2287 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2289 /* disable hardware interception of ARP */
2290 manc &= ~(E1000_MANC_ARP_EN);
2292 /* enable receiving management packets to the host */
2293 manc |= E1000_MANC_EN_MNG2HOST;
2294 manc2h |= 1 << 5; /* Mng Port 623 */
2295 manc2h |= 1 << 6; /* Mng Port 664 */
2296 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2297 E1000_WRITE_REG(hw, E1000_MANC, manc);
2302 igb_release_manageability(struct e1000_hw *hw)
2304 if (e1000_enable_mng_pass_thru(hw)) {
2305 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2307 manc |= E1000_MANC_ARP_EN;
2308 manc &= ~E1000_MANC_EN_MNG2HOST;
2310 E1000_WRITE_REG(hw, E1000_MANC, manc);
2315 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2317 struct e1000_hw *hw =
2318 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321 rctl = E1000_READ_REG(hw, E1000_RCTL);
2322 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2327 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2329 struct e1000_hw *hw =
2330 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333 rctl = E1000_READ_REG(hw, E1000_RCTL);
2334 rctl &= (~E1000_RCTL_UPE);
2335 if (dev->data->all_multicast == 1)
2336 rctl |= E1000_RCTL_MPE;
2338 rctl &= (~E1000_RCTL_MPE);
2339 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2343 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2345 struct e1000_hw *hw =
2346 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349 rctl = E1000_READ_REG(hw, E1000_RCTL);
2350 rctl |= E1000_RCTL_MPE;
2351 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2355 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2357 struct e1000_hw *hw =
2358 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 if (dev->data->promiscuous == 1)
2362 return; /* must remain in all_multicast mode */
2363 rctl = E1000_READ_REG(hw, E1000_RCTL);
2364 rctl &= (~E1000_RCTL_MPE);
2365 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2369 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2371 struct e1000_hw *hw =
2372 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373 struct e1000_vfta * shadow_vfta =
2374 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2379 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2380 E1000_VFTA_ENTRY_MASK);
2381 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2382 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2387 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2389 /* update local VFTA copy */
2390 shadow_vfta->vfta[vid_idx] = vfta;
2396 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2397 enum rte_vlan_type vlan_type,
2400 struct e1000_hw *hw =
2401 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2405 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2407 /* only outer TPID of double VLAN can be configured*/
2408 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2409 reg = E1000_READ_REG(hw, E1000_VET);
2410 reg = (reg & (~E1000_VET_VET_EXT)) |
2411 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2412 E1000_WRITE_REG(hw, E1000_VET, reg);
2417 /* all other TPID values are read-only*/
2418 PMD_DRV_LOG(ERR, "Not supported");
2424 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2426 struct e1000_hw *hw =
2427 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 /* Filter Table Disable */
2431 reg = E1000_READ_REG(hw, E1000_RCTL);
2432 reg &= ~E1000_RCTL_CFIEN;
2433 reg &= ~E1000_RCTL_VFE;
2434 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2438 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2440 struct e1000_hw *hw =
2441 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442 struct e1000_vfta * shadow_vfta =
2443 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2447 /* Filter Table Enable, CFI not used for packet acceptance */
2448 reg = E1000_READ_REG(hw, E1000_RCTL);
2449 reg &= ~E1000_RCTL_CFIEN;
2450 reg |= E1000_RCTL_VFE;
2451 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2453 /* restore VFTA table */
2454 for (i = 0; i < IGB_VFTA_SIZE; i++)
2455 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2459 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2461 struct e1000_hw *hw =
2462 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 /* VLAN Mode Disable */
2466 reg = E1000_READ_REG(hw, E1000_CTRL);
2467 reg &= ~E1000_CTRL_VME;
2468 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2472 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2474 struct e1000_hw *hw =
2475 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478 /* VLAN Mode Enable */
2479 reg = E1000_READ_REG(hw, E1000_CTRL);
2480 reg |= E1000_CTRL_VME;
2481 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2485 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2487 struct e1000_hw *hw =
2488 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491 /* CTRL_EXT: Extended VLAN */
2492 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2493 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2494 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2496 /* Update maximum packet length */
2497 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2498 E1000_WRITE_REG(hw, E1000_RLPML,
2499 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2504 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2506 struct e1000_hw *hw =
2507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510 /* CTRL_EXT: Extended VLAN */
2511 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2512 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2513 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2515 /* Update maximum packet length */
2516 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2517 E1000_WRITE_REG(hw, E1000_RLPML,
2518 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2523 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2525 if(mask & ETH_VLAN_STRIP_MASK){
2526 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2527 igb_vlan_hw_strip_enable(dev);
2529 igb_vlan_hw_strip_disable(dev);
2532 if(mask & ETH_VLAN_FILTER_MASK){
2533 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2534 igb_vlan_hw_filter_enable(dev);
2536 igb_vlan_hw_filter_disable(dev);
2539 if(mask & ETH_VLAN_EXTEND_MASK){
2540 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2541 igb_vlan_hw_extend_enable(dev);
2543 igb_vlan_hw_extend_disable(dev);
2549 * It enables the interrupt mask and then enable the interrupt.
2552 * Pointer to struct rte_eth_dev.
2555 * - On success, zero.
2556 * - On failure, a negative value.
2559 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2561 struct e1000_interrupt *intr =
2562 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2564 intr->mask |= E1000_ICR_LSC;
2569 /* It clears the interrupt causes and enables the interrupt.
2570 * It will be called once only during nic initialized.
2573 * Pointer to struct rte_eth_dev.
2576 * - On success, zero.
2577 * - On failure, a negative value.
2579 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2581 uint32_t mask, regval;
2582 struct e1000_hw *hw =
2583 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 struct rte_eth_dev_info dev_info;
2586 memset(&dev_info, 0, sizeof(dev_info));
2587 eth_igb_infos_get(dev, &dev_info);
2589 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2590 regval = E1000_READ_REG(hw, E1000_EIMS);
2591 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2597 * It reads ICR and gets interrupt causes, check it and set a bit flag
2598 * to update link status.
2601 * Pointer to struct rte_eth_dev.
2604 * - On success, zero.
2605 * - On failure, a negative value.
2608 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2611 struct e1000_hw *hw =
2612 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613 struct e1000_interrupt *intr =
2614 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2616 igb_intr_disable(hw);
2618 /* read-on-clear nic registers here */
2619 icr = E1000_READ_REG(hw, E1000_ICR);
2622 if (icr & E1000_ICR_LSC) {
2623 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2626 if (icr & E1000_ICR_VMMB)
2627 intr->flags |= E1000_FLAG_MAILBOX;
2633 * It executes link_update after knowing an interrupt is prsent.
2636 * Pointer to struct rte_eth_dev.
2639 * - On success, zero.
2640 * - On failure, a negative value.
2643 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2645 struct e1000_hw *hw =
2646 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 struct e1000_interrupt *intr =
2648 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2649 uint32_t tctl, rctl;
2650 struct rte_eth_link link;
2653 if (intr->flags & E1000_FLAG_MAILBOX) {
2654 igb_pf_mbx_process(dev);
2655 intr->flags &= ~E1000_FLAG_MAILBOX;
2658 igb_intr_enable(dev);
2659 rte_intr_enable(&(dev->pci_dev->intr_handle));
2661 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2662 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2664 /* set get_link_status to check register later */
2665 hw->mac.get_link_status = 1;
2666 ret = eth_igb_link_update(dev, 0);
2668 /* check if link has changed */
2672 memset(&link, 0, sizeof(link));
2673 rte_igb_dev_atomic_read_link_status(dev, &link);
2674 if (link.link_status) {
2676 " Port %d: Link Up - speed %u Mbps - %s",
2678 (unsigned)link.link_speed,
2679 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2680 "full-duplex" : "half-duplex");
2682 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2683 dev->data->port_id);
2686 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2687 dev->pci_dev->addr.domain,
2688 dev->pci_dev->addr.bus,
2689 dev->pci_dev->addr.devid,
2690 dev->pci_dev->addr.function);
2691 tctl = E1000_READ_REG(hw, E1000_TCTL);
2692 rctl = E1000_READ_REG(hw, E1000_RCTL);
2693 if (link.link_status) {
2695 tctl |= E1000_TCTL_EN;
2696 rctl |= E1000_RCTL_EN;
2699 tctl &= ~E1000_TCTL_EN;
2700 rctl &= ~E1000_RCTL_EN;
2702 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2703 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2704 E1000_WRITE_FLUSH(hw);
2705 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2712 * Interrupt handler which shall be registered at first.
2715 * Pointer to interrupt handle.
2717 * The address of parameter (struct rte_eth_dev *) regsitered before.
2723 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2726 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2728 eth_igb_interrupt_get_status(dev);
2729 eth_igb_interrupt_action(dev);
2733 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2736 struct e1000_hw *hw =
2737 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738 struct e1000_interrupt *intr =
2739 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2741 igbvf_intr_disable(hw);
2743 /* read-on-clear nic registers here */
2744 eicr = E1000_READ_REG(hw, E1000_EICR);
2747 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2748 intr->flags |= E1000_FLAG_MAILBOX;
2753 void igbvf_mbx_process(struct rte_eth_dev *dev)
2755 struct e1000_hw *hw =
2756 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757 struct e1000_mbx_info *mbx = &hw->mbx;
2760 if (mbx->ops.read(hw, &in_msg, 1, 0))
2763 /* PF reset VF event */
2764 if (in_msg == E1000_PF_CONTROL_MSG)
2765 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2769 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2771 struct e1000_interrupt *intr =
2772 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2774 if (intr->flags & E1000_FLAG_MAILBOX) {
2775 igbvf_mbx_process(dev);
2776 intr->flags &= ~E1000_FLAG_MAILBOX;
2779 igbvf_intr_enable(dev);
2780 rte_intr_enable(&dev->pci_dev->intr_handle);
2786 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2789 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2791 eth_igbvf_interrupt_get_status(dev);
2792 eth_igbvf_interrupt_action(dev);
2796 eth_igb_led_on(struct rte_eth_dev *dev)
2798 struct e1000_hw *hw;
2800 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2805 eth_igb_led_off(struct rte_eth_dev *dev)
2807 struct e1000_hw *hw;
2809 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2814 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2816 struct e1000_hw *hw;
2821 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822 fc_conf->pause_time = hw->fc.pause_time;
2823 fc_conf->high_water = hw->fc.high_water;
2824 fc_conf->low_water = hw->fc.low_water;
2825 fc_conf->send_xon = hw->fc.send_xon;
2826 fc_conf->autoneg = hw->mac.autoneg;
2829 * Return rx_pause and tx_pause status according to actual setting of
2830 * the TFCE and RFCE bits in the CTRL register.
2832 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2833 if (ctrl & E1000_CTRL_TFCE)
2838 if (ctrl & E1000_CTRL_RFCE)
2843 if (rx_pause && tx_pause)
2844 fc_conf->mode = RTE_FC_FULL;
2846 fc_conf->mode = RTE_FC_RX_PAUSE;
2848 fc_conf->mode = RTE_FC_TX_PAUSE;
2850 fc_conf->mode = RTE_FC_NONE;
2856 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2858 struct e1000_hw *hw;
2860 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2866 uint32_t rx_buf_size;
2867 uint32_t max_high_water;
2870 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871 if (fc_conf->autoneg != hw->mac.autoneg)
2873 rx_buf_size = igb_get_rx_buffer_size(hw);
2874 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2876 /* At least reserve one Ethernet frame for watermark */
2877 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2878 if ((fc_conf->high_water > max_high_water) ||
2879 (fc_conf->high_water < fc_conf->low_water)) {
2880 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2881 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2885 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2886 hw->fc.pause_time = fc_conf->pause_time;
2887 hw->fc.high_water = fc_conf->high_water;
2888 hw->fc.low_water = fc_conf->low_water;
2889 hw->fc.send_xon = fc_conf->send_xon;
2891 err = e1000_setup_link_generic(hw);
2892 if (err == E1000_SUCCESS) {
2894 /* check if we want to forward MAC frames - driver doesn't have native
2895 * capability to do that, so we'll write the registers ourselves */
2897 rctl = E1000_READ_REG(hw, E1000_RCTL);
2899 /* set or clear MFLCN.PMCF bit depending on configuration */
2900 if (fc_conf->mac_ctrl_frame_fwd != 0)
2901 rctl |= E1000_RCTL_PMCF;
2903 rctl &= ~E1000_RCTL_PMCF;
2905 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2906 E1000_WRITE_FLUSH(hw);
2911 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2915 #define E1000_RAH_POOLSEL_SHIFT (18)
2917 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2918 uint32_t index, __rte_unused uint32_t pool)
2920 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2924 rah = E1000_READ_REG(hw, E1000_RAH(index));
2925 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2926 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2930 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2932 uint8_t addr[ETHER_ADDR_LEN];
2933 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935 memset(addr, 0, sizeof(addr));
2937 e1000_rar_set(hw, addr, index);
2941 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2942 struct ether_addr *addr)
2944 eth_igb_rar_clear(dev, 0);
2946 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2949 * Virtual Function operations
2952 igbvf_intr_disable(struct e1000_hw *hw)
2954 PMD_INIT_FUNC_TRACE();
2956 /* Clear interrupt mask to stop from interrupts being generated */
2957 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2959 E1000_WRITE_FLUSH(hw);
2963 igbvf_stop_adapter(struct rte_eth_dev *dev)
2967 struct rte_eth_dev_info dev_info;
2968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970 memset(&dev_info, 0, sizeof(dev_info));
2971 eth_igbvf_infos_get(dev, &dev_info);
2973 /* Clear interrupt mask to stop from interrupts being generated */
2974 igbvf_intr_disable(hw);
2976 /* Clear any pending interrupts, flush previous writes */
2977 E1000_READ_REG(hw, E1000_EICR);
2979 /* Disable the transmit unit. Each queue must be disabled. */
2980 for (i = 0; i < dev_info.max_tx_queues; i++)
2981 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2983 /* Disable the receive unit by stopping each queue */
2984 for (i = 0; i < dev_info.max_rx_queues; i++) {
2985 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2986 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2987 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2988 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2992 /* flush all queues disables */
2993 E1000_WRITE_FLUSH(hw);
2997 static int eth_igbvf_link_update(struct e1000_hw *hw)
2999 struct e1000_mbx_info *mbx = &hw->mbx;
3000 struct e1000_mac_info *mac = &hw->mac;
3001 int ret_val = E1000_SUCCESS;
3003 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3006 * We only want to run this if there has been a rst asserted.
3007 * in this case that could mean a link change, device reset,
3008 * or a virtual function reset
3011 /* If we were hit with a reset or timeout drop the link */
3012 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3013 mac->get_link_status = TRUE;
3015 if (!mac->get_link_status)
3018 /* if link status is down no point in checking to see if pf is up */
3019 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3022 /* if we passed all the tests above then the link is up and we no
3023 * longer need to check for link */
3024 mac->get_link_status = FALSE;
3032 igbvf_dev_configure(struct rte_eth_dev *dev)
3034 struct rte_eth_conf* conf = &dev->data->dev_conf;
3036 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3037 dev->data->port_id);
3040 * VF has no ability to enable/disable HW CRC
3041 * Keep the persistent behavior the same as Host PF
3043 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3044 if (!conf->rxmode.hw_strip_crc) {
3045 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3046 conf->rxmode.hw_strip_crc = 1;
3049 if (conf->rxmode.hw_strip_crc) {
3050 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3051 conf->rxmode.hw_strip_crc = 0;
3059 igbvf_dev_start(struct rte_eth_dev *dev)
3061 struct e1000_hw *hw =
3062 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063 struct e1000_adapter *adapter =
3064 E1000_DEV_PRIVATE(dev->data->dev_private);
3066 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3067 uint32_t intr_vector = 0;
3069 PMD_INIT_FUNC_TRACE();
3071 hw->mac.ops.reset_hw(hw);
3072 adapter->stopped = 0;
3075 igbvf_set_vfta_all(dev,1);
3077 eth_igbvf_tx_init(dev);
3079 /* This can fail when allocating mbufs for descriptor rings */
3080 ret = eth_igbvf_rx_init(dev);
3082 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3083 igb_dev_clear_queues(dev);
3087 /* check and configure queue intr-vector mapping */
3088 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3089 intr_vector = dev->data->nb_rx_queues;
3090 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3095 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3096 intr_handle->intr_vec =
3097 rte_zmalloc("intr_vec",
3098 dev->data->nb_rx_queues * sizeof(int), 0);
3099 if (!intr_handle->intr_vec) {
3100 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3101 " intr_vec\n", dev->data->nb_rx_queues);
3106 eth_igbvf_configure_msix_intr(dev);
3108 /* enable uio/vfio intr/eventfd mapping */
3109 rte_intr_enable(intr_handle);
3111 /* resume enabled intr since hw reset */
3112 igbvf_intr_enable(dev);
3118 igbvf_dev_stop(struct rte_eth_dev *dev)
3120 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3122 PMD_INIT_FUNC_TRACE();
3124 igbvf_stop_adapter(dev);
3127 * Clear what we set, but we still keep shadow_vfta to
3128 * restore after device starts
3130 igbvf_set_vfta_all(dev,0);
3132 igb_dev_clear_queues(dev);
3134 /* disable intr eventfd mapping */
3135 rte_intr_disable(intr_handle);
3137 /* Clean datapath event and queue/vec mapping */
3138 rte_intr_efd_disable(intr_handle);
3139 if (intr_handle->intr_vec) {
3140 rte_free(intr_handle->intr_vec);
3141 intr_handle->intr_vec = NULL;
3146 igbvf_dev_close(struct rte_eth_dev *dev)
3148 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149 struct e1000_adapter *adapter =
3150 E1000_DEV_PRIVATE(dev->data->dev_private);
3151 struct ether_addr addr;
3153 PMD_INIT_FUNC_TRACE();
3157 igbvf_dev_stop(dev);
3158 adapter->stopped = 1;
3159 igb_dev_free_queues(dev);
3162 * reprogram the RAR with a zero mac address,
3163 * to ensure that the VF traffic goes to the PF
3164 * after stop, close and detach of the VF.
3167 memset(&addr, 0, sizeof(addr));
3168 igbvf_default_mac_addr_set(dev, &addr);
3172 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3174 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176 /* Set both unicast and multicast promisc */
3177 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3181 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3183 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185 /* If in allmulticast mode leave multicast promisc */
3186 if (dev->data->all_multicast == 1)
3187 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3189 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3193 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3195 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197 /* In promiscuous mode multicast promisc already set */
3198 if (dev->data->promiscuous == 0)
3199 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3203 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3205 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3207 /* In promiscuous mode leave multicast promisc enabled */
3208 if (dev->data->promiscuous == 0)
3209 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3212 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3214 struct e1000_mbx_info *mbx = &hw->mbx;
3218 /* After set vlan, vlan strip will also be enabled in igb driver*/
3219 msgbuf[0] = E1000_VF_SET_VLAN;
3221 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3223 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3225 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3229 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3233 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3234 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3241 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3243 struct e1000_hw *hw =
3244 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3245 struct e1000_vfta * shadow_vfta =
3246 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3247 int i = 0, j = 0, vfta = 0, mask = 1;
3249 for (i = 0; i < IGB_VFTA_SIZE; i++){
3250 vfta = shadow_vfta->vfta[i];
3253 for (j = 0; j < 32; j++){
3256 (uint16_t)((i<<5)+j), on);
3265 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3267 struct e1000_hw *hw =
3268 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269 struct e1000_vfta * shadow_vfta =
3270 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3271 uint32_t vid_idx = 0;
3272 uint32_t vid_bit = 0;
3275 PMD_INIT_FUNC_TRACE();
3277 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3278 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3280 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3283 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3284 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3286 /*Save what we set and retore it after device reset*/
3288 shadow_vfta->vfta[vid_idx] |= vid_bit;
3290 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3296 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3298 struct e1000_hw *hw =
3299 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301 /* index is not used by rar_set() */
3302 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3307 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3308 struct rte_eth_rss_reta_entry64 *reta_conf,
3313 uint16_t idx, shift;
3314 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3317 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3318 "(%d) doesn't match the number hardware can supported "
3319 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3323 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3324 idx = i / RTE_RETA_GROUP_SIZE;
3325 shift = i % RTE_RETA_GROUP_SIZE;
3326 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3330 if (mask == IGB_4_BIT_MASK)
3333 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3334 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3335 if (mask & (0x1 << j))
3336 reta |= reta_conf[idx].reta[shift + j] <<
3339 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3341 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3348 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3349 struct rte_eth_rss_reta_entry64 *reta_conf,
3354 uint16_t idx, shift;
3355 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3358 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3359 "(%d) doesn't match the number hardware can supported "
3360 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3364 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3365 idx = i / RTE_RETA_GROUP_SIZE;
3366 shift = i % RTE_RETA_GROUP_SIZE;
3367 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3371 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3372 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3373 if (mask & (0x1 << j))
3374 reta_conf[idx].reta[shift + j] =
3375 ((reta >> (CHAR_BIT * j)) &
3383 #define MAC_TYPE_FILTER_SUP(type) do {\
3384 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3385 (type) != e1000_82576)\
3390 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3391 struct rte_eth_syn_filter *filter,
3394 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395 uint32_t synqf, rfctl;
3397 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3400 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3403 if (synqf & E1000_SYN_FILTER_ENABLE)
3406 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3407 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3409 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3410 if (filter->hig_pri)
3411 rfctl |= E1000_RFCTL_SYNQFP;
3413 rfctl &= ~E1000_RFCTL_SYNQFP;
3415 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3417 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3422 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3423 E1000_WRITE_FLUSH(hw);
3428 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3429 struct rte_eth_syn_filter *filter)
3431 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432 uint32_t synqf, rfctl;
3434 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3435 if (synqf & E1000_SYN_FILTER_ENABLE) {
3436 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3437 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3438 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3439 E1000_SYN_FILTER_QUEUE_SHIFT);
3447 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3448 enum rte_filter_op filter_op,
3451 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454 MAC_TYPE_FILTER_SUP(hw->mac.type);
3456 if (filter_op == RTE_ETH_FILTER_NOP)
3460 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3465 switch (filter_op) {
3466 case RTE_ETH_FILTER_ADD:
3467 ret = eth_igb_syn_filter_set(dev,
3468 (struct rte_eth_syn_filter *)arg,
3471 case RTE_ETH_FILTER_DELETE:
3472 ret = eth_igb_syn_filter_set(dev,
3473 (struct rte_eth_syn_filter *)arg,
3476 case RTE_ETH_FILTER_GET:
3477 ret = eth_igb_syn_filter_get(dev,
3478 (struct rte_eth_syn_filter *)arg);
3481 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3489 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3490 if ((type) != e1000_82580 && (type) != e1000_i350)\
3494 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3496 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3497 struct e1000_2tuple_filter_info *filter_info)
3499 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3501 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3502 return -EINVAL; /* filter index is out of range. */
3503 if (filter->tcp_flags > TCP_FLAG_ALL)
3504 return -EINVAL; /* flags is invalid. */
3506 switch (filter->dst_port_mask) {
3508 filter_info->dst_port_mask = 0;
3509 filter_info->dst_port = filter->dst_port;
3512 filter_info->dst_port_mask = 1;
3515 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3519 switch (filter->proto_mask) {
3521 filter_info->proto_mask = 0;
3522 filter_info->proto = filter->proto;
3525 filter_info->proto_mask = 1;
3528 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3532 filter_info->priority = (uint8_t)filter->priority;
3533 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3534 filter_info->tcp_flags = filter->tcp_flags;
3536 filter_info->tcp_flags = 0;
3541 static inline struct e1000_2tuple_filter *
3542 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3543 struct e1000_2tuple_filter_info *key)
3545 struct e1000_2tuple_filter *it;
3547 TAILQ_FOREACH(it, filter_list, entries) {
3548 if (memcmp(key, &it->filter_info,
3549 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3557 * igb_add_2tuple_filter - add a 2tuple filter
3560 * dev: Pointer to struct rte_eth_dev.
3561 * ntuple_filter: ponter to the filter that will be added.
3564 * - On success, zero.
3565 * - On failure, a negative value.
3568 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3569 struct rte_eth_ntuple_filter *ntuple_filter)
3571 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572 struct e1000_filter_info *filter_info =
3573 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3574 struct e1000_2tuple_filter *filter;
3575 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3576 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3579 filter = rte_zmalloc("e1000_2tuple_filter",
3580 sizeof(struct e1000_2tuple_filter), 0);
3584 ret = ntuple_filter_to_2tuple(ntuple_filter,
3585 &filter->filter_info);
3590 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3591 &filter->filter_info) != NULL) {
3592 PMD_DRV_LOG(ERR, "filter exists.");
3596 filter->queue = ntuple_filter->queue;
3599 * look for an unused 2tuple filter index,
3600 * and insert the filter to list.
3602 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3603 if (!(filter_info->twotuple_mask & (1 << i))) {
3604 filter_info->twotuple_mask |= 1 << i;
3606 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3612 if (i >= E1000_MAX_TTQF_FILTERS) {
3613 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3618 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3619 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3620 imir |= E1000_IMIR_PORT_BP;
3622 imir &= ~E1000_IMIR_PORT_BP;
3624 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3626 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3627 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3628 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3629 if (filter->filter_info.proto_mask == 0)
3630 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3632 /* tcp flags bits setting. */
3633 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3634 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3635 imir_ext |= E1000_IMIREXT_CTRL_URG;
3636 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3637 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3638 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3639 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3640 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3641 imir_ext |= E1000_IMIREXT_CTRL_RST;
3642 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3643 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3644 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3645 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3647 imir_ext |= E1000_IMIREXT_CTRL_BP;
3648 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3649 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3650 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3655 * igb_remove_2tuple_filter - remove a 2tuple filter
3658 * dev: Pointer to struct rte_eth_dev.
3659 * ntuple_filter: ponter to the filter that will be removed.
3662 * - On success, zero.
3663 * - On failure, a negative value.
3666 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3667 struct rte_eth_ntuple_filter *ntuple_filter)
3669 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670 struct e1000_filter_info *filter_info =
3671 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3672 struct e1000_2tuple_filter_info filter_2tuple;
3673 struct e1000_2tuple_filter *filter;
3676 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3677 ret = ntuple_filter_to_2tuple(ntuple_filter,
3682 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3684 if (filter == NULL) {
3685 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3689 filter_info->twotuple_mask &= ~(1 << filter->index);
3690 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3693 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3694 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3695 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3699 static inline struct e1000_flex_filter *
3700 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3701 struct e1000_flex_filter_info *key)
3703 struct e1000_flex_filter *it;
3705 TAILQ_FOREACH(it, filter_list, entries) {
3706 if (memcmp(key, &it->filter_info,
3707 sizeof(struct e1000_flex_filter_info)) == 0)
3715 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3716 struct rte_eth_flex_filter *filter,
3719 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3720 struct e1000_filter_info *filter_info =
3721 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3722 struct e1000_flex_filter *flex_filter, *it;
3723 uint32_t wufc, queueing, mask;
3725 uint8_t shift, i, j = 0;
3727 flex_filter = rte_zmalloc("e1000_flex_filter",
3728 sizeof(struct e1000_flex_filter), 0);
3729 if (flex_filter == NULL)
3732 flex_filter->filter_info.len = filter->len;
3733 flex_filter->filter_info.priority = filter->priority;
3734 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3735 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3737 /* reverse bits in flex filter's mask*/
3738 for (shift = 0; shift < CHAR_BIT; shift++) {
3739 if (filter->mask[i] & (0x01 << shift))
3740 mask |= (0x80 >> shift);
3742 flex_filter->filter_info.mask[i] = mask;
3745 wufc = E1000_READ_REG(hw, E1000_WUFC);
3746 if (flex_filter->index < E1000_MAX_FHFT)
3747 reg_off = E1000_FHFT(flex_filter->index);
3749 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3752 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3753 &flex_filter->filter_info) != NULL) {
3754 PMD_DRV_LOG(ERR, "filter exists.");
3755 rte_free(flex_filter);
3758 flex_filter->queue = filter->queue;
3760 * look for an unused flex filter index
3761 * and insert the filter into the list.
3763 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3764 if (!(filter_info->flex_mask & (1 << i))) {
3765 filter_info->flex_mask |= 1 << i;
3766 flex_filter->index = i;
3767 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3773 if (i >= E1000_MAX_FLEX_FILTERS) {
3774 PMD_DRV_LOG(ERR, "flex filters are full.");
3775 rte_free(flex_filter);
3779 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3780 (E1000_WUFC_FLX0 << flex_filter->index));
3781 queueing = filter->len |
3782 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3783 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3784 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3786 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3787 E1000_WRITE_REG(hw, reg_off,
3788 flex_filter->filter_info.dwords[j]);
3789 reg_off += sizeof(uint32_t);
3790 E1000_WRITE_REG(hw, reg_off,
3791 flex_filter->filter_info.dwords[++j]);
3792 reg_off += sizeof(uint32_t);
3793 E1000_WRITE_REG(hw, reg_off,
3794 (uint32_t)flex_filter->filter_info.mask[i]);
3795 reg_off += sizeof(uint32_t) * 2;
3799 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3800 &flex_filter->filter_info);
3802 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3803 rte_free(flex_filter);
3807 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3808 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3809 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3810 (~(E1000_WUFC_FLX0 << it->index)));
3812 filter_info->flex_mask &= ~(1 << it->index);
3813 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3815 rte_free(flex_filter);
3822 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3823 struct rte_eth_flex_filter *filter)
3825 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826 struct e1000_filter_info *filter_info =
3827 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828 struct e1000_flex_filter flex_filter, *it;
3829 uint32_t wufc, queueing, wufc_en = 0;
3831 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3832 flex_filter.filter_info.len = filter->len;
3833 flex_filter.filter_info.priority = filter->priority;
3834 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3835 memcpy(flex_filter.filter_info.mask, filter->mask,
3836 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3838 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3839 &flex_filter.filter_info);
3841 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3845 wufc = E1000_READ_REG(hw, E1000_WUFC);
3846 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3848 if ((wufc & wufc_en) == wufc_en) {
3849 uint32_t reg_off = 0;
3850 if (it->index < E1000_MAX_FHFT)
3851 reg_off = E1000_FHFT(it->index);
3853 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3855 queueing = E1000_READ_REG(hw,
3856 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3857 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3858 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3859 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3860 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3861 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3868 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3869 enum rte_filter_op filter_op,
3872 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873 struct rte_eth_flex_filter *filter;
3876 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3878 if (filter_op == RTE_ETH_FILTER_NOP)
3882 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3887 filter = (struct rte_eth_flex_filter *)arg;
3888 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3889 || filter->len % sizeof(uint64_t) != 0) {
3890 PMD_DRV_LOG(ERR, "filter's length is out of range");
3893 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3894 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3898 switch (filter_op) {
3899 case RTE_ETH_FILTER_ADD:
3900 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3902 case RTE_ETH_FILTER_DELETE:
3903 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3905 case RTE_ETH_FILTER_GET:
3906 ret = eth_igb_get_flex_filter(dev, filter);
3909 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3917 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3919 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3920 struct e1000_5tuple_filter_info *filter_info)
3922 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3924 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3925 return -EINVAL; /* filter index is out of range. */
3926 if (filter->tcp_flags > TCP_FLAG_ALL)
3927 return -EINVAL; /* flags is invalid. */
3929 switch (filter->dst_ip_mask) {
3931 filter_info->dst_ip_mask = 0;
3932 filter_info->dst_ip = filter->dst_ip;
3935 filter_info->dst_ip_mask = 1;
3938 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3942 switch (filter->src_ip_mask) {
3944 filter_info->src_ip_mask = 0;
3945 filter_info->src_ip = filter->src_ip;
3948 filter_info->src_ip_mask = 1;
3951 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3955 switch (filter->dst_port_mask) {
3957 filter_info->dst_port_mask = 0;
3958 filter_info->dst_port = filter->dst_port;
3961 filter_info->dst_port_mask = 1;
3964 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3968 switch (filter->src_port_mask) {
3970 filter_info->src_port_mask = 0;
3971 filter_info->src_port = filter->src_port;
3974 filter_info->src_port_mask = 1;
3977 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3981 switch (filter->proto_mask) {
3983 filter_info->proto_mask = 0;
3984 filter_info->proto = filter->proto;
3987 filter_info->proto_mask = 1;
3990 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3994 filter_info->priority = (uint8_t)filter->priority;
3995 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3996 filter_info->tcp_flags = filter->tcp_flags;
3998 filter_info->tcp_flags = 0;
4003 static inline struct e1000_5tuple_filter *
4004 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4005 struct e1000_5tuple_filter_info *key)
4007 struct e1000_5tuple_filter *it;
4009 TAILQ_FOREACH(it, filter_list, entries) {
4010 if (memcmp(key, &it->filter_info,
4011 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4019 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4022 * dev: Pointer to struct rte_eth_dev.
4023 * ntuple_filter: ponter to the filter that will be added.
4026 * - On success, zero.
4027 * - On failure, a negative value.
4030 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4031 struct rte_eth_ntuple_filter *ntuple_filter)
4033 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034 struct e1000_filter_info *filter_info =
4035 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4036 struct e1000_5tuple_filter *filter;
4037 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4038 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4042 filter = rte_zmalloc("e1000_5tuple_filter",
4043 sizeof(struct e1000_5tuple_filter), 0);
4047 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4048 &filter->filter_info);
4054 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4055 &filter->filter_info) != NULL) {
4056 PMD_DRV_LOG(ERR, "filter exists.");
4060 filter->queue = ntuple_filter->queue;
4063 * look for an unused 5tuple filter index,
4064 * and insert the filter to list.
4066 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4067 if (!(filter_info->fivetuple_mask & (1 << i))) {
4068 filter_info->fivetuple_mask |= 1 << i;
4070 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4076 if (i >= E1000_MAX_FTQF_FILTERS) {
4077 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4082 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4083 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4084 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4085 if (filter->filter_info.dst_ip_mask == 0)
4086 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4087 if (filter->filter_info.src_port_mask == 0)
4088 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4089 if (filter->filter_info.proto_mask == 0)
4090 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4091 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4092 E1000_FTQF_QUEUE_MASK;
4093 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4094 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4095 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4096 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4098 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4099 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4101 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4102 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4103 imir |= E1000_IMIR_PORT_BP;
4105 imir &= ~E1000_IMIR_PORT_BP;
4106 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4108 /* tcp flags bits setting. */
4109 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4110 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4111 imir_ext |= E1000_IMIREXT_CTRL_URG;
4112 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4113 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4114 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4115 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4116 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4117 imir_ext |= E1000_IMIREXT_CTRL_RST;
4118 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4119 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4120 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4121 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4123 imir_ext |= E1000_IMIREXT_CTRL_BP;
4124 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4125 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4130 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4133 * dev: Pointer to struct rte_eth_dev.
4134 * ntuple_filter: ponter to the filter that will be removed.
4137 * - On success, zero.
4138 * - On failure, a negative value.
4141 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4142 struct rte_eth_ntuple_filter *ntuple_filter)
4144 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145 struct e1000_filter_info *filter_info =
4146 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4147 struct e1000_5tuple_filter_info filter_5tuple;
4148 struct e1000_5tuple_filter *filter;
4151 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4152 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4157 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4159 if (filter == NULL) {
4160 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4164 filter_info->fivetuple_mask &= ~(1 << filter->index);
4165 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4168 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4169 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4170 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4171 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4172 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4173 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4174 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4179 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4182 struct e1000_hw *hw;
4183 struct rte_eth_dev_info dev_info;
4184 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4187 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189 #ifdef RTE_LIBRTE_82571_SUPPORT
4190 /* XXX: not bigger than max_rx_pktlen */
4191 if (hw->mac.type == e1000_82571)
4194 eth_igb_infos_get(dev, &dev_info);
4196 /* check that mtu is within the allowed range */
4197 if ((mtu < ETHER_MIN_MTU) ||
4198 (frame_size > dev_info.max_rx_pktlen))
4201 /* refuse mtu that requires the support of scattered packets when this
4202 * feature has not been enabled before. */
4203 if (!dev->data->scattered_rx &&
4204 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4207 rctl = E1000_READ_REG(hw, E1000_RCTL);
4209 /* switch to jumbo mode if needed */
4210 if (frame_size > ETHER_MAX_LEN) {
4211 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4212 rctl |= E1000_RCTL_LPE;
4214 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4215 rctl &= ~E1000_RCTL_LPE;
4217 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4219 /* update max frame size */
4220 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4222 E1000_WRITE_REG(hw, E1000_RLPML,
4223 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4229 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4232 * dev: Pointer to struct rte_eth_dev.
4233 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4234 * add: if true, add filter, if false, remove filter
4237 * - On success, zero.
4238 * - On failure, a negative value.
4241 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4242 struct rte_eth_ntuple_filter *ntuple_filter,
4245 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4248 switch (ntuple_filter->flags) {
4249 case RTE_5TUPLE_FLAGS:
4250 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4251 if (hw->mac.type != e1000_82576)
4254 ret = igb_add_5tuple_filter_82576(dev,
4257 ret = igb_remove_5tuple_filter_82576(dev,
4260 case RTE_2TUPLE_FLAGS:
4261 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4262 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4265 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4267 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4278 * igb_get_ntuple_filter - get a ntuple filter
4281 * dev: Pointer to struct rte_eth_dev.
4282 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4285 * - On success, zero.
4286 * - On failure, a negative value.
4289 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4290 struct rte_eth_ntuple_filter *ntuple_filter)
4292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293 struct e1000_filter_info *filter_info =
4294 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4295 struct e1000_5tuple_filter_info filter_5tuple;
4296 struct e1000_2tuple_filter_info filter_2tuple;
4297 struct e1000_5tuple_filter *p_5tuple_filter;
4298 struct e1000_2tuple_filter *p_2tuple_filter;
4301 switch (ntuple_filter->flags) {
4302 case RTE_5TUPLE_FLAGS:
4303 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4304 if (hw->mac.type != e1000_82576)
4306 memset(&filter_5tuple,
4308 sizeof(struct e1000_5tuple_filter_info));
4309 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4313 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4314 &filter_info->fivetuple_list,
4316 if (p_5tuple_filter == NULL) {
4317 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4320 ntuple_filter->queue = p_5tuple_filter->queue;
4322 case RTE_2TUPLE_FLAGS:
4323 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4324 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4326 memset(&filter_2tuple,
4328 sizeof(struct e1000_2tuple_filter_info));
4329 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4332 p_2tuple_filter = igb_2tuple_filter_lookup(
4333 &filter_info->twotuple_list,
4335 if (p_2tuple_filter == NULL) {
4336 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4339 ntuple_filter->queue = p_2tuple_filter->queue;
4350 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4351 * @dev: pointer to rte_eth_dev structure
4352 * @filter_op:operation will be taken.
4353 * @arg: a pointer to specific structure corresponding to the filter_op
4356 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4357 enum rte_filter_op filter_op,
4360 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363 MAC_TYPE_FILTER_SUP(hw->mac.type);
4365 if (filter_op == RTE_ETH_FILTER_NOP)
4369 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4374 switch (filter_op) {
4375 case RTE_ETH_FILTER_ADD:
4376 ret = igb_add_del_ntuple_filter(dev,
4377 (struct rte_eth_ntuple_filter *)arg,
4380 case RTE_ETH_FILTER_DELETE:
4381 ret = igb_add_del_ntuple_filter(dev,
4382 (struct rte_eth_ntuple_filter *)arg,
4385 case RTE_ETH_FILTER_GET:
4386 ret = igb_get_ntuple_filter(dev,
4387 (struct rte_eth_ntuple_filter *)arg);
4390 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4398 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4403 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4404 if (filter_info->ethertype_filters[i] == ethertype &&
4405 (filter_info->ethertype_mask & (1 << i)))
4412 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4417 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4418 if (!(filter_info->ethertype_mask & (1 << i))) {
4419 filter_info->ethertype_mask |= 1 << i;
4420 filter_info->ethertype_filters[i] = ethertype;
4428 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4431 if (idx >= E1000_MAX_ETQF_FILTERS)
4433 filter_info->ethertype_mask &= ~(1 << idx);
4434 filter_info->ethertype_filters[idx] = 0;
4440 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4441 struct rte_eth_ethertype_filter *filter,
4444 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445 struct e1000_filter_info *filter_info =
4446 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4450 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4451 filter->ether_type == ETHER_TYPE_IPv6) {
4452 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4453 " ethertype filter.", filter->ether_type);
4457 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4458 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4461 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4462 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4466 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4467 if (ret >= 0 && add) {
4468 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4469 filter->ether_type);
4472 if (ret < 0 && !add) {
4473 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4474 filter->ether_type);
4479 ret = igb_ethertype_filter_insert(filter_info,
4480 filter->ether_type);
4482 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4486 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4487 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4488 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4490 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4494 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4495 E1000_WRITE_FLUSH(hw);
4501 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4502 struct rte_eth_ethertype_filter *filter)
4504 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505 struct e1000_filter_info *filter_info =
4506 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4510 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4512 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4513 filter->ether_type);
4517 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4518 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4519 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4521 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4522 E1000_ETQF_QUEUE_SHIFT;
4530 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4531 * @dev: pointer to rte_eth_dev structure
4532 * @filter_op:operation will be taken.
4533 * @arg: a pointer to specific structure corresponding to the filter_op
4536 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4537 enum rte_filter_op filter_op,
4540 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543 MAC_TYPE_FILTER_SUP(hw->mac.type);
4545 if (filter_op == RTE_ETH_FILTER_NOP)
4549 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4554 switch (filter_op) {
4555 case RTE_ETH_FILTER_ADD:
4556 ret = igb_add_del_ethertype_filter(dev,
4557 (struct rte_eth_ethertype_filter *)arg,
4560 case RTE_ETH_FILTER_DELETE:
4561 ret = igb_add_del_ethertype_filter(dev,
4562 (struct rte_eth_ethertype_filter *)arg,
4565 case RTE_ETH_FILTER_GET:
4566 ret = igb_get_ethertype_filter(dev,
4567 (struct rte_eth_ethertype_filter *)arg);
4570 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4578 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4579 enum rte_filter_type filter_type,
4580 enum rte_filter_op filter_op,
4585 switch (filter_type) {
4586 case RTE_ETH_FILTER_NTUPLE:
4587 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4589 case RTE_ETH_FILTER_ETHERTYPE:
4590 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4592 case RTE_ETH_FILTER_SYN:
4593 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4595 case RTE_ETH_FILTER_FLEXIBLE:
4596 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4599 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4608 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4609 struct ether_addr *mc_addr_set,
4610 uint32_t nb_mc_addr)
4612 struct e1000_hw *hw;
4614 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4620 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4622 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623 uint64_t systime_cycles;
4625 switch (hw->mac.type) {
4629 * Need to read System Time Residue Register to be able
4630 * to read the other two registers.
4632 E1000_READ_REG(hw, E1000_SYSTIMR);
4633 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4634 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4635 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4642 * Need to read System Time Residue Register to be able
4643 * to read the other two registers.
4645 E1000_READ_REG(hw, E1000_SYSTIMR);
4646 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4647 /* Only the 8 LSB are valid. */
4648 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4652 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4653 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4658 return systime_cycles;
4662 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4664 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665 uint64_t rx_tstamp_cycles;
4667 switch (hw->mac.type) {
4670 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4671 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4672 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4678 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4679 /* Only the 8 LSB are valid. */
4680 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4684 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4685 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4690 return rx_tstamp_cycles;
4694 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4696 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697 uint64_t tx_tstamp_cycles;
4699 switch (hw->mac.type) {
4702 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4703 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4704 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4710 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4711 /* Only the 8 LSB are valid. */
4712 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4716 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4717 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4722 return tx_tstamp_cycles;
4726 igb_start_timecounters(struct rte_eth_dev *dev)
4728 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729 struct e1000_adapter *adapter =
4730 (struct e1000_adapter *)dev->data->dev_private;
4731 uint32_t incval = 1;
4733 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4735 switch (hw->mac.type) {
4739 /* 32 LSB bits + 8 MSB bits = 40 bits */
4740 mask = (1ULL << 40) - 1;
4745 * Start incrementing the register
4746 * used to timestamp PTP packets.
4748 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4751 incval = E1000_INCVALUE_82576;
4752 shift = IGB_82576_TSYNC_SHIFT;
4753 E1000_WRITE_REG(hw, E1000_TIMINCA,
4754 E1000_INCPERIOD_82576 | incval);
4761 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4762 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4763 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4765 adapter->systime_tc.cc_mask = mask;
4766 adapter->systime_tc.cc_shift = shift;
4767 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4769 adapter->rx_tstamp_tc.cc_mask = mask;
4770 adapter->rx_tstamp_tc.cc_shift = shift;
4771 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4773 adapter->tx_tstamp_tc.cc_mask = mask;
4774 adapter->tx_tstamp_tc.cc_shift = shift;
4775 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4779 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4781 struct e1000_adapter *adapter =
4782 (struct e1000_adapter *)dev->data->dev_private;
4784 adapter->systime_tc.nsec += delta;
4785 adapter->rx_tstamp_tc.nsec += delta;
4786 adapter->tx_tstamp_tc.nsec += delta;
4792 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4795 struct e1000_adapter *adapter =
4796 (struct e1000_adapter *)dev->data->dev_private;
4798 ns = rte_timespec_to_ns(ts);
4800 /* Set the timecounters to a new value. */
4801 adapter->systime_tc.nsec = ns;
4802 adapter->rx_tstamp_tc.nsec = ns;
4803 adapter->tx_tstamp_tc.nsec = ns;
4809 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4811 uint64_t ns, systime_cycles;
4812 struct e1000_adapter *adapter =
4813 (struct e1000_adapter *)dev->data->dev_private;
4815 systime_cycles = igb_read_systime_cyclecounter(dev);
4816 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4817 *ts = rte_ns_to_timespec(ns);
4823 igb_timesync_enable(struct rte_eth_dev *dev)
4825 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829 /* Stop the timesync system time. */
4830 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4831 /* Reset the timesync system time value. */
4832 switch (hw->mac.type) {
4838 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4841 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4842 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4845 /* Not supported. */
4849 /* Enable system time for it isn't on by default. */
4850 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4851 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4852 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4854 igb_start_timecounters(dev);
4856 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4857 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4859 E1000_ETQF_FILTER_ENABLE |
4862 /* Enable timestamping of received PTP packets. */
4863 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4864 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4865 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4867 /* Enable Timestamping of transmitted PTP packets. */
4868 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4869 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4870 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4876 igb_timesync_disable(struct rte_eth_dev *dev)
4878 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881 /* Disable timestamping of transmitted PTP packets. */
4882 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4883 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4884 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4886 /* Disable timestamping of received PTP packets. */
4887 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4888 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4889 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4891 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4892 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4894 /* Stop incrementating the System Time registers. */
4895 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4901 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4902 struct timespec *timestamp,
4903 uint32_t flags __rte_unused)
4905 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906 struct e1000_adapter *adapter =
4907 (struct e1000_adapter *)dev->data->dev_private;
4908 uint32_t tsync_rxctl;
4909 uint64_t rx_tstamp_cycles;
4912 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4913 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4916 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4917 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4918 *timestamp = rte_ns_to_timespec(ns);
4924 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4925 struct timespec *timestamp)
4927 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928 struct e1000_adapter *adapter =
4929 (struct e1000_adapter *)dev->data->dev_private;
4930 uint32_t tsync_txctl;
4931 uint64_t tx_tstamp_cycles;
4934 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4935 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4938 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4939 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4940 *timestamp = rte_ns_to_timespec(ns);
4946 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4950 const struct reg_info *reg_group;
4952 while ((reg_group = igb_regs[g_ind++]))
4953 count += igb_reg_group_count(reg_group);
4959 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4963 const struct reg_info *reg_group;
4965 while ((reg_group = igbvf_regs[g_ind++]))
4966 count += igb_reg_group_count(reg_group);
4972 eth_igb_get_regs(struct rte_eth_dev *dev,
4973 struct rte_dev_reg_info *regs)
4975 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976 uint32_t *data = regs->data;
4979 const struct reg_info *reg_group;
4982 regs->length = eth_igb_get_reg_length(dev);
4983 regs->width = sizeof(uint32_t);
4987 /* Support only full register dump */
4988 if ((regs->length == 0) ||
4989 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4990 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4992 while ((reg_group = igb_regs[g_ind++]))
4993 count += igb_read_regs_group(dev, &data[count],
5002 igbvf_get_regs(struct rte_eth_dev *dev,
5003 struct rte_dev_reg_info *regs)
5005 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006 uint32_t *data = regs->data;
5009 const struct reg_info *reg_group;
5012 regs->length = igbvf_get_reg_length(dev);
5013 regs->width = sizeof(uint32_t);
5017 /* Support only full register dump */
5018 if ((regs->length == 0) ||
5019 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5020 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5022 while ((reg_group = igbvf_regs[g_ind++]))
5023 count += igb_read_regs_group(dev, &data[count],
5032 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5034 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5036 /* Return unit is byte count */
5037 return hw->nvm.word_size * 2;
5041 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5042 struct rte_dev_eeprom_info *in_eeprom)
5044 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045 struct e1000_nvm_info *nvm = &hw->nvm;
5046 uint16_t *data = in_eeprom->data;
5049 first = in_eeprom->offset >> 1;
5050 length = in_eeprom->length >> 1;
5051 if ((first >= hw->nvm.word_size) ||
5052 ((first + length) >= hw->nvm.word_size))
5055 in_eeprom->magic = hw->vendor_id |
5056 ((uint32_t)hw->device_id << 16);
5058 if ((nvm->ops.read) == NULL)
5061 return nvm->ops.read(hw, first, length, data);
5065 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5066 struct rte_dev_eeprom_info *in_eeprom)
5068 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069 struct e1000_nvm_info *nvm = &hw->nvm;
5070 uint16_t *data = in_eeprom->data;
5073 first = in_eeprom->offset >> 1;
5074 length = in_eeprom->length >> 1;
5075 if ((first >= hw->nvm.word_size) ||
5076 ((first + length) >= hw->nvm.word_size))
5079 in_eeprom->magic = (uint32_t)hw->vendor_id |
5080 ((uint32_t)hw->device_id << 16);
5082 if ((nvm->ops.write) == NULL)
5084 return nvm->ops.write(hw, first, length, data);
5087 static struct rte_driver pmd_igb_drv = {
5089 .init = rte_igb_pmd_init,
5092 static struct rte_driver pmd_igbvf_drv = {
5094 .init = rte_igbvf_pmd_init,
5098 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5100 struct e1000_hw *hw =
5101 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102 uint32_t mask = 1 << queue_id;
5104 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5105 E1000_WRITE_FLUSH(hw);
5111 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5113 struct e1000_hw *hw =
5114 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5115 uint32_t mask = 1 << queue_id;
5118 regval = E1000_READ_REG(hw, E1000_EIMS);
5119 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5120 E1000_WRITE_FLUSH(hw);
5122 rte_intr_enable(&dev->pci_dev->intr_handle);
5128 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5129 uint8_t index, uint8_t offset)
5131 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5134 val &= ~((uint32_t)0xFF << offset);
5136 /* write vector and valid bit */
5137 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5139 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5143 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5144 uint8_t queue, uint8_t msix_vector)
5148 if (hw->mac.type == e1000_82575) {
5150 tmp = E1000_EICR_RX_QUEUE0 << queue;
5151 else if (direction == 1)
5152 tmp = E1000_EICR_TX_QUEUE0 << queue;
5153 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5154 } else if (hw->mac.type == e1000_82576) {
5155 if ((direction == 0) || (direction == 1))
5156 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5157 ((queue & 0x8) << 1) +
5159 } else if ((hw->mac.type == e1000_82580) ||
5160 (hw->mac.type == e1000_i350) ||
5161 (hw->mac.type == e1000_i354) ||
5162 (hw->mac.type == e1000_i210) ||
5163 (hw->mac.type == e1000_i211)) {
5164 if ((direction == 0) || (direction == 1))
5165 eth_igb_write_ivar(hw, msix_vector,
5167 ((queue & 0x1) << 4) +
5172 /* Sets up the hardware to generate MSI-X interrupts properly
5174 * board private structure
5177 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5180 uint32_t tmpval, regval, intr_mask;
5181 struct e1000_hw *hw =
5182 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5183 uint32_t vec = E1000_MISC_VEC_ID;
5184 uint32_t base = E1000_MISC_VEC_ID;
5185 uint32_t misc_shift = 0;
5187 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5189 /* won't configure msix register if no mapping is done
5190 * between intr vector and event fd
5192 if (!rte_intr_dp_is_en(intr_handle))
5195 if (rte_intr_allow_others(intr_handle)) {
5196 vec = base = E1000_RX_VEC_START;
5200 /* set interrupt vector for other causes */
5201 if (hw->mac.type == e1000_82575) {
5202 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5203 /* enable MSI-X PBA support */
5204 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5206 /* Auto-Mask interrupts upon ICR read */
5207 tmpval |= E1000_CTRL_EXT_EIAME;
5208 tmpval |= E1000_CTRL_EXT_IRCA;
5210 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5212 /* enable msix_other interrupt */
5213 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5214 regval = E1000_READ_REG(hw, E1000_EIAC);
5215 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5216 regval = E1000_READ_REG(hw, E1000_EIAM);
5217 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5218 } else if ((hw->mac.type == e1000_82576) ||
5219 (hw->mac.type == e1000_82580) ||
5220 (hw->mac.type == e1000_i350) ||
5221 (hw->mac.type == e1000_i354) ||
5222 (hw->mac.type == e1000_i210) ||
5223 (hw->mac.type == e1000_i211)) {
5224 /* turn on MSI-X capability first */
5225 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5226 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5228 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5230 regval = E1000_READ_REG(hw, E1000_EIAC);
5231 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5233 /* enable msix_other interrupt */
5234 regval = E1000_READ_REG(hw, E1000_EIMS);
5235 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5236 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5237 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5240 /* use EIAM to auto-mask when MSI-X interrupt
5241 * is asserted, this saves a register write for every interrupt
5243 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5245 regval = E1000_READ_REG(hw, E1000_EIAM);
5246 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5248 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5249 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5250 intr_handle->intr_vec[queue_id] = vec;
5251 if (vec < base + intr_handle->nb_efd - 1)
5255 E1000_WRITE_FLUSH(hw);
5258 PMD_REGISTER_DRIVER(pmd_igb_drv, net_e1000_igb);
5259 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5260 PMD_REGISTER_DRIVER(pmd_igbvf_drv, net_e1000_igb_vf);
5261 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);