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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
65 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
66 #define IGB_DEFAULT_RX_HTHRESH 8
67 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
70 #define IGB_DEFAULT_TX_HTHRESH 1
71 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73 #define IGB_HKEY_MAX_INDEX 10
75 /* Bit shift and mask */
76 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
77 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
78 #define IGB_8_BIT_WIDTH CHAR_BIT
79 #define IGB_8_BIT_MASK UINT8_MAX
81 /* Additional timesync values. */
82 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
83 #define E1000_ETQF_FILTER_1588 3
84 #define IGB_82576_TSYNC_SHIFT 16
85 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
86 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89 #define E1000_VTIVAR_MISC 0x01740
90 #define E1000_VTIVAR_MISC_MASK 0xFF
91 #define E1000_VTIVAR_VALID 0x80
92 #define E1000_VTIVAR_MISC_MAILBOX 0
93 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
95 /* External VLAN Enable bit mask */
96 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
98 /* External VLAN Ether Type bit mask and shift */
99 #define E1000_VET_VET_EXT 0xFFFF0000
100 #define E1000_VET_VET_EXT_SHIFT 16
102 static int eth_igb_configure(struct rte_eth_dev *dev);
103 static int eth_igb_start(struct rte_eth_dev *dev);
104 static void eth_igb_stop(struct rte_eth_dev *dev);
105 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
107 static void eth_igb_close(struct rte_eth_dev *dev);
108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
112 static int eth_igb_link_update(struct rte_eth_dev *dev,
113 int wait_to_complete);
114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
115 struct rte_eth_stats *rte_stats);
116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
117 struct rte_eth_xstat *xstats, unsigned n);
118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
119 struct rte_eth_xstat_name *xstats_names,
121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
124 struct rte_eth_dev_info *dev_info);
125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
127 struct rte_eth_dev_info *dev_info);
128 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
129 struct rte_eth_fc_conf *fc_conf);
130 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
138 static int igb_hardware_init(struct e1000_hw *hw);
139 static void igb_hw_control_acquire(struct e1000_hw *hw);
140 static void igb_hw_control_release(struct e1000_hw *hw);
141 static void igb_init_manageability(struct e1000_hw *hw);
142 static void igb_release_manageability(struct e1000_hw *hw);
144 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
147 uint16_t vlan_id, int on);
148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
149 enum rte_vlan_type vlan_type,
151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int eth_igb_led_on(struct rte_eth_dev *dev);
161 static int eth_igb_led_off(struct rte_eth_dev *dev);
163 static void igb_intr_disable(struct e1000_hw *hw);
164 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
166 struct ether_addr *mac_addr,
167 uint32_t index, uint32_t pool);
168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
170 struct ether_addr *addr);
172 static void igbvf_intr_disable(struct e1000_hw *hw);
173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
174 static int igbvf_dev_start(struct rte_eth_dev *dev);
175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
176 static void igbvf_dev_close(struct rte_eth_dev *dev);
177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
181 static int eth_igbvf_link_update(struct e1000_hw *hw);
182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
183 struct rte_eth_stats *rte_stats);
184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
187 struct rte_eth_xstat_name *xstats_names,
189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
191 uint16_t vlan_id, int on);
192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
195 struct ether_addr *addr);
196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
197 static int igbvf_get_regs(struct rte_eth_dev *dev,
198 struct rte_dev_reg_info *regs);
200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
201 struct rte_eth_rss_reta_entry64 *reta_conf,
203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
204 struct rte_eth_rss_reta_entry64 *reta_conf,
207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
208 struct rte_eth_syn_filter *filter,
210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
211 struct rte_eth_syn_filter *filter);
212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ntuple_filter *ntuple_filter);
217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
218 struct rte_eth_ntuple_filter *ntuple_filter);
219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
220 struct rte_eth_flex_filter *filter,
222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
223 struct rte_eth_flex_filter *filter);
224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
225 enum rte_filter_op filter_op,
227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
228 struct rte_eth_ntuple_filter *ntuple_filter);
229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
230 struct rte_eth_ntuple_filter *ntuple_filter);
231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
232 struct rte_eth_ntuple_filter *filter,
234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter);
236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
237 enum rte_filter_op filter_op,
239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
240 struct rte_eth_ethertype_filter *filter,
242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
243 enum rte_filter_op filter_op,
245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
246 struct rte_eth_ethertype_filter *filter);
247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
248 enum rte_filter_type filter_type,
249 enum rte_filter_op filter_op,
251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
253 struct rte_dev_reg_info *regs);
254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
256 struct rte_dev_eeprom_info *eeprom);
257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
258 struct rte_dev_eeprom_info *eeprom);
259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
260 struct ether_addr *mc_addr_set,
261 uint32_t nb_mc_addr);
262 static int igb_timesync_enable(struct rte_eth_dev *dev);
263 static int igb_timesync_disable(struct rte_eth_dev *dev);
264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
265 struct timespec *timestamp,
267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
268 struct timespec *timestamp);
269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
271 struct timespec *timestamp);
272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
273 const struct timespec *timestamp);
274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
279 uint8_t queue, uint8_t msix_vector);
280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
281 uint8_t index, uint8_t offset);
282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
288 * Define VF Stats MACRO for Non "cleared on read" register
290 #define UPDATE_VF_STAT(reg, last, cur) \
292 u32 latest = E1000_READ_REG(hw, reg); \
293 cur += (latest - last) & UINT_MAX; \
297 #define IGB_FC_PAUSE_TIME 0x0680
298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
301 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
306 * The set of PCI devices this driver supports
308 static const struct rte_pci_id pci_id_igb_map[] = {
310 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
311 #include "rte_pci_dev_ids.h"
317 * The set of PCI devices this driver supports (for 82576&I350 VF)
319 static const struct rte_pci_id pci_id_igbvf_map[] = {
321 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
322 #include "rte_pci_dev_ids.h"
327 static const struct rte_eth_desc_lim rx_desc_lim = {
328 .nb_max = E1000_MAX_RING_DESC,
329 .nb_min = E1000_MIN_RING_DESC,
330 .nb_align = IGB_RXD_ALIGN,
333 static const struct rte_eth_desc_lim tx_desc_lim = {
334 .nb_max = E1000_MAX_RING_DESC,
335 .nb_min = E1000_MIN_RING_DESC,
336 .nb_align = IGB_RXD_ALIGN,
339 static const struct eth_dev_ops eth_igb_ops = {
340 .dev_configure = eth_igb_configure,
341 .dev_start = eth_igb_start,
342 .dev_stop = eth_igb_stop,
343 .dev_set_link_up = eth_igb_dev_set_link_up,
344 .dev_set_link_down = eth_igb_dev_set_link_down,
345 .dev_close = eth_igb_close,
346 .promiscuous_enable = eth_igb_promiscuous_enable,
347 .promiscuous_disable = eth_igb_promiscuous_disable,
348 .allmulticast_enable = eth_igb_allmulticast_enable,
349 .allmulticast_disable = eth_igb_allmulticast_disable,
350 .link_update = eth_igb_link_update,
351 .stats_get = eth_igb_stats_get,
352 .xstats_get = eth_igb_xstats_get,
353 .xstats_get_names = eth_igb_xstats_get_names,
354 .stats_reset = eth_igb_stats_reset,
355 .xstats_reset = eth_igb_xstats_reset,
356 .dev_infos_get = eth_igb_infos_get,
357 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
358 .mtu_set = eth_igb_mtu_set,
359 .vlan_filter_set = eth_igb_vlan_filter_set,
360 .vlan_tpid_set = eth_igb_vlan_tpid_set,
361 .vlan_offload_set = eth_igb_vlan_offload_set,
362 .rx_queue_setup = eth_igb_rx_queue_setup,
363 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
364 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
365 .rx_queue_release = eth_igb_rx_queue_release,
366 .rx_queue_count = eth_igb_rx_queue_count,
367 .rx_descriptor_done = eth_igb_rx_descriptor_done,
368 .tx_queue_setup = eth_igb_tx_queue_setup,
369 .tx_queue_release = eth_igb_tx_queue_release,
370 .dev_led_on = eth_igb_led_on,
371 .dev_led_off = eth_igb_led_off,
372 .flow_ctrl_get = eth_igb_flow_ctrl_get,
373 .flow_ctrl_set = eth_igb_flow_ctrl_set,
374 .mac_addr_add = eth_igb_rar_set,
375 .mac_addr_remove = eth_igb_rar_clear,
376 .mac_addr_set = eth_igb_default_mac_addr_set,
377 .reta_update = eth_igb_rss_reta_update,
378 .reta_query = eth_igb_rss_reta_query,
379 .rss_hash_update = eth_igb_rss_hash_update,
380 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
381 .filter_ctrl = eth_igb_filter_ctrl,
382 .set_mc_addr_list = eth_igb_set_mc_addr_list,
383 .rxq_info_get = igb_rxq_info_get,
384 .txq_info_get = igb_txq_info_get,
385 .timesync_enable = igb_timesync_enable,
386 .timesync_disable = igb_timesync_disable,
387 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
388 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
389 .get_reg = eth_igb_get_regs,
390 .get_eeprom_length = eth_igb_get_eeprom_length,
391 .get_eeprom = eth_igb_get_eeprom,
392 .set_eeprom = eth_igb_set_eeprom,
393 .timesync_adjust_time = igb_timesync_adjust_time,
394 .timesync_read_time = igb_timesync_read_time,
395 .timesync_write_time = igb_timesync_write_time,
399 * dev_ops for virtual function, bare necessities for basic vf
400 * operation have been implemented
402 static const struct eth_dev_ops igbvf_eth_dev_ops = {
403 .dev_configure = igbvf_dev_configure,
404 .dev_start = igbvf_dev_start,
405 .dev_stop = igbvf_dev_stop,
406 .dev_close = igbvf_dev_close,
407 .promiscuous_enable = igbvf_promiscuous_enable,
408 .promiscuous_disable = igbvf_promiscuous_disable,
409 .allmulticast_enable = igbvf_allmulticast_enable,
410 .allmulticast_disable = igbvf_allmulticast_disable,
411 .link_update = eth_igb_link_update,
412 .stats_get = eth_igbvf_stats_get,
413 .xstats_get = eth_igbvf_xstats_get,
414 .xstats_get_names = eth_igbvf_xstats_get_names,
415 .stats_reset = eth_igbvf_stats_reset,
416 .xstats_reset = eth_igbvf_stats_reset,
417 .vlan_filter_set = igbvf_vlan_filter_set,
418 .dev_infos_get = eth_igbvf_infos_get,
419 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
420 .rx_queue_setup = eth_igb_rx_queue_setup,
421 .rx_queue_release = eth_igb_rx_queue_release,
422 .tx_queue_setup = eth_igb_tx_queue_setup,
423 .tx_queue_release = eth_igb_tx_queue_release,
424 .set_mc_addr_list = eth_igb_set_mc_addr_list,
425 .rxq_info_get = igb_rxq_info_get,
426 .txq_info_get = igb_txq_info_get,
427 .mac_addr_set = igbvf_default_mac_addr_set,
428 .get_reg = igbvf_get_regs,
431 /* store statistics names and its offset in stats structure */
432 struct rte_igb_xstats_name_off {
433 char name[RTE_ETH_XSTATS_NAME_SIZE];
437 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
438 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
439 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
440 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
441 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
442 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
443 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
444 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
446 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
447 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
448 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
449 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
450 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
451 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
452 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
453 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
454 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
455 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
456 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
458 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
459 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
460 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
461 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
462 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
464 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
466 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
467 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
468 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
469 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
470 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
471 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
472 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
473 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
474 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
475 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
476 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
477 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
478 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
479 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
480 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
481 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
482 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
483 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
485 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
487 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
488 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
489 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
490 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
491 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
492 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
493 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
495 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
498 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
499 sizeof(rte_igb_stats_strings[0]))
501 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
502 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
503 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
504 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
505 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
506 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
509 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
510 sizeof(rte_igbvf_stats_strings[0]))
513 * Atomically reads the link status information from global
514 * structure rte_eth_dev.
517 * - Pointer to the structure rte_eth_dev to read from.
518 * - Pointer to the buffer to be saved with the link status.
521 * - On success, zero.
522 * - On failure, negative value.
525 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
526 struct rte_eth_link *link)
528 struct rte_eth_link *dst = link;
529 struct rte_eth_link *src = &(dev->data->dev_link);
531 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
532 *(uint64_t *)src) == 0)
539 * Atomically writes the link status information into global
540 * structure rte_eth_dev.
543 * - Pointer to the structure rte_eth_dev to read from.
544 * - Pointer to the buffer to be saved with the link status.
547 * - On success, zero.
548 * - On failure, negative value.
551 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
552 struct rte_eth_link *link)
554 struct rte_eth_link *dst = &(dev->data->dev_link);
555 struct rte_eth_link *src = link;
557 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
558 *(uint64_t *)src) == 0)
565 igb_intr_enable(struct rte_eth_dev *dev)
567 struct e1000_interrupt *intr =
568 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
569 struct e1000_hw *hw =
570 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
572 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
573 E1000_WRITE_FLUSH(hw);
577 igb_intr_disable(struct e1000_hw *hw)
579 E1000_WRITE_REG(hw, E1000_IMC, ~0);
580 E1000_WRITE_FLUSH(hw);
584 igbvf_intr_enable(struct rte_eth_dev *dev)
586 struct e1000_hw *hw =
587 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
589 /* only for mailbox */
590 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
591 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
592 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
593 E1000_WRITE_FLUSH(hw);
596 /* only for mailbox now. If RX/TX needed, should extend this function. */
598 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
603 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
604 tmp |= E1000_VTIVAR_VALID;
605 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
609 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
611 struct e1000_hw *hw =
612 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
614 /* Configure VF other cause ivar */
615 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
618 static inline int32_t
619 igb_pf_reset_hw(struct e1000_hw *hw)
624 status = e1000_reset_hw(hw);
626 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
627 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
628 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
629 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
630 E1000_WRITE_FLUSH(hw);
636 igb_identify_hardware(struct rte_eth_dev *dev)
638 struct e1000_hw *hw =
639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
641 hw->vendor_id = dev->pci_dev->id.vendor_id;
642 hw->device_id = dev->pci_dev->id.device_id;
643 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
644 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
646 e1000_set_mac_type(hw);
648 /* need to check if it is a vf device below */
652 igb_reset_swfw_lock(struct e1000_hw *hw)
657 * Do mac ops initialization manually here, since we will need
658 * some function pointers set by this call.
660 ret_val = e1000_init_mac_params(hw);
665 * SMBI lock should not fail in this early stage. If this is the case,
666 * it is due to an improper exit of the application.
667 * So force the release of the faulty lock.
669 if (e1000_get_hw_semaphore_generic(hw) < 0) {
670 PMD_DRV_LOG(DEBUG, "SMBI lock released");
672 e1000_put_hw_semaphore_generic(hw);
674 if (hw->mac.ops.acquire_swfw_sync != NULL) {
678 * Phy lock should not fail in this early stage. If this is the case,
679 * it is due to an improper exit of the application.
680 * So force the release of the faulty lock.
682 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
683 if (hw->bus.func > E1000_FUNC_1)
685 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
686 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
689 hw->mac.ops.release_swfw_sync(hw, mask);
692 * This one is more tricky since it is common to all ports; but
693 * swfw_sync retries last long enough (1s) to be almost sure that if
694 * lock can not be taken it is due to an improper lock of the
697 mask = E1000_SWFW_EEP_SM;
698 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
699 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
701 hw->mac.ops.release_swfw_sync(hw, mask);
704 return E1000_SUCCESS;
708 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
711 struct rte_pci_device *pci_dev;
712 struct e1000_hw *hw =
713 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
714 struct e1000_vfta * shadow_vfta =
715 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
716 struct e1000_filter_info *filter_info =
717 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
718 struct e1000_adapter *adapter =
719 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
723 pci_dev = eth_dev->pci_dev;
725 eth_dev->dev_ops = ð_igb_ops;
726 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
727 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
729 /* for secondary processes, we don't initialise any further as primary
730 * has already done this work. Only check we don't need a different
732 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
733 if (eth_dev->data->scattered_rx)
734 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
738 rte_eth_copy_pci_info(eth_dev, pci_dev);
740 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
742 igb_identify_hardware(eth_dev);
743 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
748 e1000_get_bus_info(hw);
750 /* Reset any pending lock */
751 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
756 /* Finish initialization */
757 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
763 hw->phy.autoneg_wait_to_complete = 0;
764 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
767 if (hw->phy.media_type == e1000_media_type_copper) {
768 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
769 hw->phy.disable_polarity_correction = 0;
770 hw->phy.ms_type = e1000_ms_hw_default;
774 * Start from a known state, this is important in reading the nvm
779 /* Make sure we have a good EEPROM before we read from it */
780 if (e1000_validate_nvm_checksum(hw) < 0) {
782 * Some PCI-E parts fail the first check due to
783 * the link being in sleep state, call it again,
784 * if it fails a second time its a real issue.
786 if (e1000_validate_nvm_checksum(hw) < 0) {
787 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
793 /* Read the permanent MAC address out of the EEPROM */
794 if (e1000_read_mac_addr(hw) != 0) {
795 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
800 /* Allocate memory for storing MAC addresses */
801 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
802 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
803 if (eth_dev->data->mac_addrs == NULL) {
804 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
805 "store MAC addresses",
806 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
811 /* Copy the permanent MAC address */
812 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
814 /* initialize the vfta */
815 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
817 /* Now initialize the hardware */
818 if (igb_hardware_init(hw) != 0) {
819 PMD_INIT_LOG(ERR, "Hardware initialization failed");
820 rte_free(eth_dev->data->mac_addrs);
821 eth_dev->data->mac_addrs = NULL;
825 hw->mac.get_link_status = 1;
826 adapter->stopped = 0;
828 /* Indicate SOL/IDER usage */
829 if (e1000_check_reset_block(hw) < 0) {
830 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
834 /* initialize PF if max_vfs not zero */
835 igb_pf_host_init(eth_dev);
837 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
838 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
839 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
840 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
841 E1000_WRITE_FLUSH(hw);
843 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
844 eth_dev->data->port_id, pci_dev->id.vendor_id,
845 pci_dev->id.device_id);
847 rte_intr_callback_register(&pci_dev->intr_handle,
848 eth_igb_interrupt_handler,
851 /* enable uio/vfio intr/eventfd mapping */
852 rte_intr_enable(&pci_dev->intr_handle);
854 /* enable support intr */
855 igb_intr_enable(eth_dev);
857 TAILQ_INIT(&filter_info->flex_list);
858 filter_info->flex_mask = 0;
859 TAILQ_INIT(&filter_info->twotuple_list);
860 filter_info->twotuple_mask = 0;
861 TAILQ_INIT(&filter_info->fivetuple_list);
862 filter_info->fivetuple_mask = 0;
867 igb_hw_control_release(hw);
873 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
875 struct rte_pci_device *pci_dev;
877 struct e1000_adapter *adapter =
878 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
880 PMD_INIT_FUNC_TRACE();
882 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
885 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
886 pci_dev = eth_dev->pci_dev;
888 if (adapter->stopped == 0)
889 eth_igb_close(eth_dev);
891 eth_dev->dev_ops = NULL;
892 eth_dev->rx_pkt_burst = NULL;
893 eth_dev->tx_pkt_burst = NULL;
895 /* Reset any pending lock */
896 igb_reset_swfw_lock(hw);
898 rte_free(eth_dev->data->mac_addrs);
899 eth_dev->data->mac_addrs = NULL;
901 /* uninitialize PF if max_vfs not zero */
902 igb_pf_host_uninit(eth_dev);
904 /* disable uio intr before callback unregister */
905 rte_intr_disable(&(pci_dev->intr_handle));
906 rte_intr_callback_unregister(&(pci_dev->intr_handle),
907 eth_igb_interrupt_handler, (void *)eth_dev);
913 * Virtual Function device init
916 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
918 struct rte_pci_device *pci_dev;
919 struct e1000_adapter *adapter =
920 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
921 struct e1000_hw *hw =
922 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
924 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
926 PMD_INIT_FUNC_TRACE();
928 eth_dev->dev_ops = &igbvf_eth_dev_ops;
929 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
930 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
932 /* for secondary processes, we don't initialise any further as primary
933 * has already done this work. Only check we don't need a different
935 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
936 if (eth_dev->data->scattered_rx)
937 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
941 pci_dev = eth_dev->pci_dev;
943 rte_eth_copy_pci_info(eth_dev, pci_dev);
945 hw->device_id = pci_dev->id.device_id;
946 hw->vendor_id = pci_dev->id.vendor_id;
947 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
948 adapter->stopped = 0;
950 /* Initialize the shared code (base driver) */
951 diag = e1000_setup_init_funcs(hw, TRUE);
953 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
958 /* init_mailbox_params */
959 hw->mbx.ops.init_params(hw);
961 /* Disable the interrupts for VF */
962 igbvf_intr_disable(hw);
964 diag = hw->mac.ops.reset_hw(hw);
966 /* Allocate memory for storing MAC addresses */
967 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
968 hw->mac.rar_entry_count, 0);
969 if (eth_dev->data->mac_addrs == NULL) {
971 "Failed to allocate %d bytes needed to store MAC "
973 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
977 /* Generate a random MAC address, if none was assigned by PF. */
978 if (is_zero_ether_addr(perm_addr)) {
979 eth_random_addr(perm_addr->addr_bytes);
980 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
982 rte_free(eth_dev->data->mac_addrs);
983 eth_dev->data->mac_addrs = NULL;
986 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
987 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
988 "%02x:%02x:%02x:%02x:%02x:%02x",
989 perm_addr->addr_bytes[0],
990 perm_addr->addr_bytes[1],
991 perm_addr->addr_bytes[2],
992 perm_addr->addr_bytes[3],
993 perm_addr->addr_bytes[4],
994 perm_addr->addr_bytes[5]);
997 /* Copy the permanent MAC address */
998 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
999 ð_dev->data->mac_addrs[0]);
1001 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1003 eth_dev->data->port_id, pci_dev->id.vendor_id,
1004 pci_dev->id.device_id, "igb_mac_82576_vf");
1006 rte_intr_callback_register(&pci_dev->intr_handle,
1007 eth_igbvf_interrupt_handler,
1014 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1016 struct e1000_adapter *adapter =
1017 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1018 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1020 PMD_INIT_FUNC_TRACE();
1022 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1025 if (adapter->stopped == 0)
1026 igbvf_dev_close(eth_dev);
1028 eth_dev->dev_ops = NULL;
1029 eth_dev->rx_pkt_burst = NULL;
1030 eth_dev->tx_pkt_burst = NULL;
1032 rte_free(eth_dev->data->mac_addrs);
1033 eth_dev->data->mac_addrs = NULL;
1035 /* disable uio intr before callback unregister */
1036 rte_intr_disable(&pci_dev->intr_handle);
1037 rte_intr_callback_unregister(&pci_dev->intr_handle,
1038 eth_igbvf_interrupt_handler,
1044 static struct eth_driver rte_igb_pmd = {
1046 .name = "rte_igb_pmd",
1047 .id_table = pci_id_igb_map,
1048 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1049 RTE_PCI_DRV_DETACHABLE,
1051 .eth_dev_init = eth_igb_dev_init,
1052 .eth_dev_uninit = eth_igb_dev_uninit,
1053 .dev_private_size = sizeof(struct e1000_adapter),
1057 * virtual function driver struct
1059 static struct eth_driver rte_igbvf_pmd = {
1061 .name = "rte_igbvf_pmd",
1062 .id_table = pci_id_igbvf_map,
1063 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1065 .eth_dev_init = eth_igbvf_dev_init,
1066 .eth_dev_uninit = eth_igbvf_dev_uninit,
1067 .dev_private_size = sizeof(struct e1000_adapter),
1071 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1073 rte_eth_driver_register(&rte_igb_pmd);
1078 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1080 struct e1000_hw *hw =
1081 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1082 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1083 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1084 rctl |= E1000_RCTL_VFE;
1085 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1089 * VF Driver initialization routine.
1090 * Invoked one at EAL init time.
1091 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1094 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1096 PMD_INIT_FUNC_TRACE();
1098 rte_eth_driver_register(&rte_igbvf_pmd);
1103 igb_check_mq_mode(struct rte_eth_dev *dev)
1105 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1106 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1107 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1108 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1110 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1111 tx_mq_mode == ETH_MQ_TX_DCB ||
1112 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1113 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1116 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1117 /* Check multi-queue mode.
1118 * To no break software we accept ETH_MQ_RX_NONE as this might
1119 * be used to turn off VLAN filter.
1122 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1123 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1124 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1125 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1127 /* Only support one queue on VFs.
1128 * RSS together with SRIOV is not supported.
1130 PMD_INIT_LOG(ERR, "SRIOV is active,"
1131 " wrong mq_mode rx %d.",
1135 /* TX mode is not used here, so mode might be ignored.*/
1136 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1137 /* SRIOV only works in VMDq enable mode */
1138 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1139 " TX mode %d is not supported. "
1140 " Driver will behave as %d mode.",
1141 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1144 /* check valid queue number */
1145 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1146 PMD_INIT_LOG(ERR, "SRIOV is active,"
1147 " only support one queue on VFs.");
1151 /* To no break software that set invalid mode, only display
1152 * warning if invalid mode is used.
1154 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1155 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1156 rx_mq_mode != ETH_MQ_RX_RSS) {
1157 /* RSS together with VMDq not supported*/
1158 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1163 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1164 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1165 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1166 " Due to txmode is meaningless in this"
1167 " driver, just ignore.",
1175 eth_igb_configure(struct rte_eth_dev *dev)
1177 struct e1000_interrupt *intr =
1178 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1181 PMD_INIT_FUNC_TRACE();
1183 /* multipe queue mode checking */
1184 ret = igb_check_mq_mode(dev);
1186 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1191 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1192 PMD_INIT_FUNC_TRACE();
1198 eth_igb_start(struct rte_eth_dev *dev)
1200 struct e1000_hw *hw =
1201 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202 struct e1000_adapter *adapter =
1203 E1000_DEV_PRIVATE(dev->data->dev_private);
1204 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1206 uint32_t intr_vector = 0;
1212 PMD_INIT_FUNC_TRACE();
1214 /* disable uio/vfio intr/eventfd mapping */
1215 rte_intr_disable(intr_handle);
1217 /* Power up the phy. Needed to make the link go Up */
1218 eth_igb_dev_set_link_up(dev);
1221 * Packet Buffer Allocation (PBA)
1222 * Writing PBA sets the receive portion of the buffer
1223 * the remainder is used for the transmit buffer.
1225 if (hw->mac.type == e1000_82575) {
1228 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1229 E1000_WRITE_REG(hw, E1000_PBA, pba);
1232 /* Put the address into the Receive Address Array */
1233 e1000_rar_set(hw, hw->mac.addr, 0);
1235 /* Initialize the hardware */
1236 if (igb_hardware_init(hw)) {
1237 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1240 adapter->stopped = 0;
1242 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1244 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1245 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1247 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1248 E1000_WRITE_FLUSH(hw);
1250 /* configure PF module if SRIOV enabled */
1251 igb_pf_host_configure(dev);
1253 /* check and configure queue intr-vector mapping */
1254 if ((rte_intr_cap_multiple(intr_handle) ||
1255 !RTE_ETH_DEV_SRIOV(dev).active) &&
1256 dev->data->dev_conf.intr_conf.rxq != 0) {
1257 intr_vector = dev->data->nb_rx_queues;
1258 if (rte_intr_efd_enable(intr_handle, intr_vector))
1262 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1263 intr_handle->intr_vec =
1264 rte_zmalloc("intr_vec",
1265 dev->data->nb_rx_queues * sizeof(int), 0);
1266 if (intr_handle->intr_vec == NULL) {
1267 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1268 " intr_vec\n", dev->data->nb_rx_queues);
1273 /* confiugre msix for rx interrupt */
1274 eth_igb_configure_msix_intr(dev);
1276 /* Configure for OS presence */
1277 igb_init_manageability(hw);
1279 eth_igb_tx_init(dev);
1281 /* This can fail when allocating mbufs for descriptor rings */
1282 ret = eth_igb_rx_init(dev);
1284 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1285 igb_dev_clear_queues(dev);
1289 e1000_clear_hw_cntrs_base_generic(hw);
1292 * VLAN Offload Settings
1294 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1295 ETH_VLAN_EXTEND_MASK;
1296 eth_igb_vlan_offload_set(dev, mask);
1298 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1299 /* Enable VLAN filter since VMDq always use VLAN filter */
1300 igb_vmdq_vlan_hw_filter_enable(dev);
1303 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1304 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1305 (hw->mac.type == e1000_i211)) {
1306 /* Configure EITR with the maximum possible value (0xFFFF) */
1307 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1310 /* Setup link speed and duplex */
1311 speeds = &dev->data->dev_conf.link_speeds;
1312 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1313 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1316 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1319 hw->phy.autoneg_advertised = 0;
1321 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1322 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1323 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1325 goto error_invalid_config;
1327 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1328 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1331 if (*speeds & ETH_LINK_SPEED_10M) {
1332 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1335 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1336 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1339 if (*speeds & ETH_LINK_SPEED_100M) {
1340 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1343 if (*speeds & ETH_LINK_SPEED_1G) {
1344 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1347 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1348 goto error_invalid_config;
1351 e1000_setup_link(hw);
1353 if (rte_intr_allow_others(intr_handle)) {
1354 /* check if lsc interrupt is enabled */
1355 if (dev->data->dev_conf.intr_conf.lsc != 0)
1356 eth_igb_lsc_interrupt_setup(dev);
1358 rte_intr_callback_unregister(intr_handle,
1359 eth_igb_interrupt_handler,
1361 if (dev->data->dev_conf.intr_conf.lsc != 0)
1362 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1363 " no intr multiplex\n");
1366 /* check if rxq interrupt is enabled */
1367 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1368 rte_intr_dp_is_en(intr_handle))
1369 eth_igb_rxq_interrupt_setup(dev);
1371 /* enable uio/vfio intr/eventfd mapping */
1372 rte_intr_enable(intr_handle);
1374 /* resume enabled intr since hw reset */
1375 igb_intr_enable(dev);
1377 PMD_INIT_LOG(DEBUG, "<<");
1381 error_invalid_config:
1382 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1383 dev->data->dev_conf.link_speeds, dev->data->port_id);
1384 igb_dev_clear_queues(dev);
1388 /*********************************************************************
1390 * This routine disables all traffic on the adapter by issuing a
1391 * global reset on the MAC.
1393 **********************************************************************/
1395 eth_igb_stop(struct rte_eth_dev *dev)
1397 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398 struct e1000_filter_info *filter_info =
1399 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1400 struct rte_eth_link link;
1401 struct e1000_flex_filter *p_flex;
1402 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1403 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1404 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1406 igb_intr_disable(hw);
1408 /* disable intr eventfd mapping */
1409 rte_intr_disable(intr_handle);
1411 igb_pf_reset_hw(hw);
1412 E1000_WRITE_REG(hw, E1000_WUC, 0);
1414 /* Set bit for Go Link disconnect */
1415 if (hw->mac.type >= e1000_82580) {
1418 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1419 phpm_reg |= E1000_82580_PM_GO_LINKD;
1420 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1423 /* Power down the phy. Needed to make the link go Down */
1424 eth_igb_dev_set_link_down(dev);
1426 igb_dev_clear_queues(dev);
1428 /* clear the recorded link status */
1429 memset(&link, 0, sizeof(link));
1430 rte_igb_dev_atomic_write_link_status(dev, &link);
1432 /* Remove all flex filters of the device */
1433 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1434 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1437 filter_info->flex_mask = 0;
1439 /* Remove all ntuple filters of the device */
1440 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1441 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1442 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1443 TAILQ_REMOVE(&filter_info->fivetuple_list,
1447 filter_info->fivetuple_mask = 0;
1448 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1449 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1450 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1451 TAILQ_REMOVE(&filter_info->twotuple_list,
1455 filter_info->twotuple_mask = 0;
1457 if (!rte_intr_allow_others(intr_handle))
1458 /* resume to the default handler */
1459 rte_intr_callback_register(intr_handle,
1460 eth_igb_interrupt_handler,
1463 /* Clean datapath event and queue/vec mapping */
1464 rte_intr_efd_disable(intr_handle);
1465 if (intr_handle->intr_vec != NULL) {
1466 rte_free(intr_handle->intr_vec);
1467 intr_handle->intr_vec = NULL;
1472 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1474 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1476 if (hw->phy.media_type == e1000_media_type_copper)
1477 e1000_power_up_phy(hw);
1479 e1000_power_up_fiber_serdes_link(hw);
1485 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1487 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489 if (hw->phy.media_type == e1000_media_type_copper)
1490 e1000_power_down_phy(hw);
1492 e1000_shutdown_fiber_serdes_link(hw);
1498 eth_igb_close(struct rte_eth_dev *dev)
1500 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501 struct e1000_adapter *adapter =
1502 E1000_DEV_PRIVATE(dev->data->dev_private);
1503 struct rte_eth_link link;
1504 struct rte_pci_device *pci_dev;
1507 adapter->stopped = 1;
1509 e1000_phy_hw_reset(hw);
1510 igb_release_manageability(hw);
1511 igb_hw_control_release(hw);
1513 /* Clear bit for Go Link disconnect */
1514 if (hw->mac.type >= e1000_82580) {
1517 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1518 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1519 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1522 igb_dev_free_queues(dev);
1524 pci_dev = dev->pci_dev;
1525 if (pci_dev->intr_handle.intr_vec) {
1526 rte_free(pci_dev->intr_handle.intr_vec);
1527 pci_dev->intr_handle.intr_vec = NULL;
1530 memset(&link, 0, sizeof(link));
1531 rte_igb_dev_atomic_write_link_status(dev, &link);
1535 igb_get_rx_buffer_size(struct e1000_hw *hw)
1537 uint32_t rx_buf_size;
1538 if (hw->mac.type == e1000_82576) {
1539 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1540 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1541 /* PBS needs to be translated according to a lookup table */
1542 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1543 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1544 rx_buf_size = (rx_buf_size << 10);
1545 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1546 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1548 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1554 /*********************************************************************
1556 * Initialize the hardware
1558 **********************************************************************/
1560 igb_hardware_init(struct e1000_hw *hw)
1562 uint32_t rx_buf_size;
1565 /* Let the firmware know the OS is in control */
1566 igb_hw_control_acquire(hw);
1569 * These parameters control the automatic generation (Tx) and
1570 * response (Rx) to Ethernet PAUSE frames.
1571 * - High water mark should allow for at least two standard size (1518)
1572 * frames to be received after sending an XOFF.
1573 * - Low water mark works best when it is very near the high water mark.
1574 * This allows the receiver to restart by sending XON when it has
1575 * drained a bit. Here we use an arbitrary value of 1500 which will
1576 * restart after one full frame is pulled from the buffer. There
1577 * could be several smaller frames in the buffer and if so they will
1578 * not trigger the XON until their total number reduces the buffer
1580 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1582 rx_buf_size = igb_get_rx_buffer_size(hw);
1584 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1585 hw->fc.low_water = hw->fc.high_water - 1500;
1586 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1587 hw->fc.send_xon = 1;
1589 /* Set Flow control, use the tunable location if sane */
1590 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1591 hw->fc.requested_mode = igb_fc_setting;
1593 hw->fc.requested_mode = e1000_fc_none;
1595 /* Issue a global reset */
1596 igb_pf_reset_hw(hw);
1597 E1000_WRITE_REG(hw, E1000_WUC, 0);
1599 diag = e1000_init_hw(hw);
1603 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1604 e1000_get_phy_info(hw);
1605 e1000_check_for_link(hw);
1610 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1612 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1616 uint64_t old_gprc = stats->gprc;
1617 uint64_t old_gptc = stats->gptc;
1618 uint64_t old_tpr = stats->tpr;
1619 uint64_t old_tpt = stats->tpt;
1620 uint64_t old_rpthc = stats->rpthc;
1621 uint64_t old_hgptc = stats->hgptc;
1623 if(hw->phy.media_type == e1000_media_type_copper ||
1624 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1626 E1000_READ_REG(hw,E1000_SYMERRS);
1627 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1630 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1631 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1632 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1633 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1635 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1636 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1637 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1638 stats->dc += E1000_READ_REG(hw, E1000_DC);
1639 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1640 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1641 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1643 ** For watchdog management we need to know if we have been
1644 ** paused during the last interval, so capture that here.
1646 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1647 stats->xoffrxc += pause_frames;
1648 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1649 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1650 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1651 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1652 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1653 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1654 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1655 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1656 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1657 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1658 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1659 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1661 /* For the 64-bit byte counters the low dword must be read first. */
1662 /* Both registers clear on the read of the high dword */
1664 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1665 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1666 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1667 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1668 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1669 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1670 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1672 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1673 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1674 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1675 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1676 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1678 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1679 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1681 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1682 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1683 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1684 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1685 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1686 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1688 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1689 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1690 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1691 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1692 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1693 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1694 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1695 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1697 /* Interrupt Counts */
1699 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1700 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1701 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1702 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1703 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1704 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1705 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1706 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1707 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1709 /* Host to Card Statistics */
1711 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1712 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1713 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1714 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1715 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1716 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1717 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1718 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1719 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1720 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1721 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1722 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1723 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1724 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1725 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1726 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1728 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1729 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1730 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1731 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1732 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1733 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1737 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1739 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740 struct e1000_hw_stats *stats =
1741 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1743 igb_read_stats_registers(hw, stats);
1745 if (rte_stats == NULL)
1749 rte_stats->imissed = stats->mpc;
1750 rte_stats->ierrors = stats->crcerrs +
1751 stats->rlec + stats->ruc + stats->roc +
1752 stats->rxerrc + stats->algnerrc + stats->cexterr;
1755 rte_stats->oerrors = stats->ecol + stats->latecol;
1757 rte_stats->ipackets = stats->gprc;
1758 rte_stats->opackets = stats->gptc;
1759 rte_stats->ibytes = stats->gorc;
1760 rte_stats->obytes = stats->gotc;
1764 eth_igb_stats_reset(struct rte_eth_dev *dev)
1766 struct e1000_hw_stats *hw_stats =
1767 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1769 /* HW registers are cleared on read */
1770 eth_igb_stats_get(dev, NULL);
1772 /* Reset software totals */
1773 memset(hw_stats, 0, sizeof(*hw_stats));
1777 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1779 struct e1000_hw_stats *stats =
1780 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1782 /* HW registers are cleared on read */
1783 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1785 /* Reset software totals */
1786 memset(stats, 0, sizeof(*stats));
1789 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1790 struct rte_eth_xstat_name *xstats_names,
1791 __rte_unused unsigned limit)
1795 if (xstats_names == NULL)
1796 return IGB_NB_XSTATS;
1798 /* Note: limit checked in rte_eth_xstats_names() */
1800 for (i = 0; i < IGB_NB_XSTATS; i++) {
1801 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1802 "%s", rte_igb_stats_strings[i].name);
1805 return IGB_NB_XSTATS;
1809 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1812 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 struct e1000_hw_stats *hw_stats =
1814 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817 if (n < IGB_NB_XSTATS)
1818 return IGB_NB_XSTATS;
1820 igb_read_stats_registers(hw, hw_stats);
1822 /* If this is a reset xstats is NULL, and we have cleared the
1823 * registers by reading them.
1828 /* Extended stats */
1829 for (i = 0; i < IGB_NB_XSTATS; i++) {
1831 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1832 rte_igb_stats_strings[i].offset);
1835 return IGB_NB_XSTATS;
1839 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1841 /* Good Rx packets, include VF loopback */
1842 UPDATE_VF_STAT(E1000_VFGPRC,
1843 hw_stats->last_gprc, hw_stats->gprc);
1845 /* Good Rx octets, include VF loopback */
1846 UPDATE_VF_STAT(E1000_VFGORC,
1847 hw_stats->last_gorc, hw_stats->gorc);
1849 /* Good Tx packets, include VF loopback */
1850 UPDATE_VF_STAT(E1000_VFGPTC,
1851 hw_stats->last_gptc, hw_stats->gptc);
1853 /* Good Tx octets, include VF loopback */
1854 UPDATE_VF_STAT(E1000_VFGOTC,
1855 hw_stats->last_gotc, hw_stats->gotc);
1857 /* Rx Multicst packets */
1858 UPDATE_VF_STAT(E1000_VFMPRC,
1859 hw_stats->last_mprc, hw_stats->mprc);
1861 /* Good Rx loopback packets */
1862 UPDATE_VF_STAT(E1000_VFGPRLBC,
1863 hw_stats->last_gprlbc, hw_stats->gprlbc);
1865 /* Good Rx loopback octets */
1866 UPDATE_VF_STAT(E1000_VFGORLBC,
1867 hw_stats->last_gorlbc, hw_stats->gorlbc);
1869 /* Good Tx loopback packets */
1870 UPDATE_VF_STAT(E1000_VFGPTLBC,
1871 hw_stats->last_gptlbc, hw_stats->gptlbc);
1873 /* Good Tx loopback octets */
1874 UPDATE_VF_STAT(E1000_VFGOTLBC,
1875 hw_stats->last_gotlbc, hw_stats->gotlbc);
1878 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1879 struct rte_eth_xstat_name *xstats_names,
1880 __rte_unused unsigned limit)
1884 if (xstats_names != NULL)
1885 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1886 snprintf(xstats_names[i].name,
1887 sizeof(xstats_names[i].name), "%s",
1888 rte_igbvf_stats_strings[i].name);
1890 return IGBVF_NB_XSTATS;
1894 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1897 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1899 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1902 if (n < IGBVF_NB_XSTATS)
1903 return IGBVF_NB_XSTATS;
1905 igbvf_read_stats_registers(hw, hw_stats);
1910 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1912 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1913 rte_igbvf_stats_strings[i].offset);
1916 return IGBVF_NB_XSTATS;
1920 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1922 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1924 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1926 igbvf_read_stats_registers(hw, hw_stats);
1928 if (rte_stats == NULL)
1931 rte_stats->ipackets = hw_stats->gprc;
1932 rte_stats->ibytes = hw_stats->gorc;
1933 rte_stats->opackets = hw_stats->gptc;
1934 rte_stats->obytes = hw_stats->gotc;
1938 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1940 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1941 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1943 /* Sync HW register to the last stats */
1944 eth_igbvf_stats_get(dev, NULL);
1946 /* reset HW current stats*/
1947 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1948 offsetof(struct e1000_vf_stats, gprc));
1952 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1954 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1957 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1958 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1959 dev_info->rx_offload_capa =
1960 DEV_RX_OFFLOAD_VLAN_STRIP |
1961 DEV_RX_OFFLOAD_IPV4_CKSUM |
1962 DEV_RX_OFFLOAD_UDP_CKSUM |
1963 DEV_RX_OFFLOAD_TCP_CKSUM;
1964 dev_info->tx_offload_capa =
1965 DEV_TX_OFFLOAD_VLAN_INSERT |
1966 DEV_TX_OFFLOAD_IPV4_CKSUM |
1967 DEV_TX_OFFLOAD_UDP_CKSUM |
1968 DEV_TX_OFFLOAD_TCP_CKSUM |
1969 DEV_TX_OFFLOAD_SCTP_CKSUM |
1970 DEV_TX_OFFLOAD_TCP_TSO;
1972 switch (hw->mac.type) {
1974 dev_info->max_rx_queues = 4;
1975 dev_info->max_tx_queues = 4;
1976 dev_info->max_vmdq_pools = 0;
1980 dev_info->max_rx_queues = 16;
1981 dev_info->max_tx_queues = 16;
1982 dev_info->max_vmdq_pools = ETH_8_POOLS;
1983 dev_info->vmdq_queue_num = 16;
1987 dev_info->max_rx_queues = 8;
1988 dev_info->max_tx_queues = 8;
1989 dev_info->max_vmdq_pools = ETH_8_POOLS;
1990 dev_info->vmdq_queue_num = 8;
1994 dev_info->max_rx_queues = 8;
1995 dev_info->max_tx_queues = 8;
1996 dev_info->max_vmdq_pools = ETH_8_POOLS;
1997 dev_info->vmdq_queue_num = 8;
2001 dev_info->max_rx_queues = 8;
2002 dev_info->max_tx_queues = 8;
2006 dev_info->max_rx_queues = 4;
2007 dev_info->max_tx_queues = 4;
2008 dev_info->max_vmdq_pools = 0;
2012 dev_info->max_rx_queues = 2;
2013 dev_info->max_tx_queues = 2;
2014 dev_info->max_vmdq_pools = 0;
2018 /* Should not happen */
2021 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2022 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2023 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2025 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2027 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2028 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2029 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2031 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2035 dev_info->default_txconf = (struct rte_eth_txconf) {
2037 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2038 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2039 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2044 dev_info->rx_desc_lim = rx_desc_lim;
2045 dev_info->tx_desc_lim = tx_desc_lim;
2047 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2048 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2052 static const uint32_t *
2053 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2055 static const uint32_t ptypes[] = {
2056 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2059 RTE_PTYPE_L3_IPV4_EXT,
2061 RTE_PTYPE_L3_IPV6_EXT,
2065 RTE_PTYPE_TUNNEL_IP,
2066 RTE_PTYPE_INNER_L3_IPV6,
2067 RTE_PTYPE_INNER_L3_IPV6_EXT,
2068 RTE_PTYPE_INNER_L4_TCP,
2069 RTE_PTYPE_INNER_L4_UDP,
2073 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2074 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2080 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2082 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2085 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2086 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2087 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2088 DEV_RX_OFFLOAD_IPV4_CKSUM |
2089 DEV_RX_OFFLOAD_UDP_CKSUM |
2090 DEV_RX_OFFLOAD_TCP_CKSUM;
2091 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2092 DEV_TX_OFFLOAD_IPV4_CKSUM |
2093 DEV_TX_OFFLOAD_UDP_CKSUM |
2094 DEV_TX_OFFLOAD_TCP_CKSUM |
2095 DEV_TX_OFFLOAD_SCTP_CKSUM |
2096 DEV_TX_OFFLOAD_TCP_TSO;
2097 switch (hw->mac.type) {
2099 dev_info->max_rx_queues = 2;
2100 dev_info->max_tx_queues = 2;
2102 case e1000_vfadapt_i350:
2103 dev_info->max_rx_queues = 1;
2104 dev_info->max_tx_queues = 1;
2107 /* Should not happen */
2111 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2113 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2114 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2115 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2117 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2121 dev_info->default_txconf = (struct rte_eth_txconf) {
2123 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2124 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2125 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2130 dev_info->rx_desc_lim = rx_desc_lim;
2131 dev_info->tx_desc_lim = tx_desc_lim;
2134 /* return 0 means link status changed, -1 means not changed */
2136 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2138 struct e1000_hw *hw =
2139 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140 struct rte_eth_link link, old;
2141 int link_check, count;
2144 hw->mac.get_link_status = 1;
2146 /* possible wait-to-complete in up to 9 seconds */
2147 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2148 /* Read the real link status */
2149 switch (hw->phy.media_type) {
2150 case e1000_media_type_copper:
2151 /* Do the work to read phy */
2152 e1000_check_for_link(hw);
2153 link_check = !hw->mac.get_link_status;
2156 case e1000_media_type_fiber:
2157 e1000_check_for_link(hw);
2158 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2162 case e1000_media_type_internal_serdes:
2163 e1000_check_for_link(hw);
2164 link_check = hw->mac.serdes_has_link;
2167 /* VF device is type_unknown */
2168 case e1000_media_type_unknown:
2169 eth_igbvf_link_update(hw);
2170 link_check = !hw->mac.get_link_status;
2176 if (link_check || wait_to_complete == 0)
2178 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2180 memset(&link, 0, sizeof(link));
2181 rte_igb_dev_atomic_read_link_status(dev, &link);
2184 /* Now we check if a transition has happened */
2186 uint16_t duplex, speed;
2187 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2188 link.link_duplex = (duplex == FULL_DUPLEX) ?
2189 ETH_LINK_FULL_DUPLEX :
2190 ETH_LINK_HALF_DUPLEX;
2191 link.link_speed = speed;
2192 link.link_status = ETH_LINK_UP;
2193 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2194 ETH_LINK_SPEED_FIXED);
2195 } else if (!link_check) {
2196 link.link_speed = 0;
2197 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2198 link.link_status = ETH_LINK_DOWN;
2199 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2201 rte_igb_dev_atomic_write_link_status(dev, &link);
2204 if (old.link_status == link.link_status)
2212 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2213 * For ASF and Pass Through versions of f/w this means
2214 * that the driver is loaded.
2217 igb_hw_control_acquire(struct e1000_hw *hw)
2221 /* Let firmware know the driver has taken over */
2222 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2223 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2227 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2228 * For ASF and Pass Through versions of f/w this means that the
2229 * driver is no longer loaded.
2232 igb_hw_control_release(struct e1000_hw *hw)
2236 /* Let firmware taken over control of h/w */
2237 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2238 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2239 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2243 * Bit of a misnomer, what this really means is
2244 * to enable OS management of the system... aka
2245 * to disable special hardware management features.
2248 igb_init_manageability(struct e1000_hw *hw)
2250 if (e1000_enable_mng_pass_thru(hw)) {
2251 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2252 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2254 /* disable hardware interception of ARP */
2255 manc &= ~(E1000_MANC_ARP_EN);
2257 /* enable receiving management packets to the host */
2258 manc |= E1000_MANC_EN_MNG2HOST;
2259 manc2h |= 1 << 5; /* Mng Port 623 */
2260 manc2h |= 1 << 6; /* Mng Port 664 */
2261 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2262 E1000_WRITE_REG(hw, E1000_MANC, manc);
2267 igb_release_manageability(struct e1000_hw *hw)
2269 if (e1000_enable_mng_pass_thru(hw)) {
2270 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2272 manc |= E1000_MANC_ARP_EN;
2273 manc &= ~E1000_MANC_EN_MNG2HOST;
2275 E1000_WRITE_REG(hw, E1000_MANC, manc);
2280 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2282 struct e1000_hw *hw =
2283 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286 rctl = E1000_READ_REG(hw, E1000_RCTL);
2287 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2288 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2292 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2294 struct e1000_hw *hw =
2295 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298 rctl = E1000_READ_REG(hw, E1000_RCTL);
2299 rctl &= (~E1000_RCTL_UPE);
2300 if (dev->data->all_multicast == 1)
2301 rctl |= E1000_RCTL_MPE;
2303 rctl &= (~E1000_RCTL_MPE);
2304 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2308 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2310 struct e1000_hw *hw =
2311 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314 rctl = E1000_READ_REG(hw, E1000_RCTL);
2315 rctl |= E1000_RCTL_MPE;
2316 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2320 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2322 struct e1000_hw *hw =
2323 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326 if (dev->data->promiscuous == 1)
2327 return; /* must remain in all_multicast mode */
2328 rctl = E1000_READ_REG(hw, E1000_RCTL);
2329 rctl &= (~E1000_RCTL_MPE);
2330 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2334 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2336 struct e1000_hw *hw =
2337 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2338 struct e1000_vfta * shadow_vfta =
2339 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2344 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2345 E1000_VFTA_ENTRY_MASK);
2346 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2347 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2352 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2354 /* update local VFTA copy */
2355 shadow_vfta->vfta[vid_idx] = vfta;
2361 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2362 enum rte_vlan_type vlan_type,
2365 struct e1000_hw *hw =
2366 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2370 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2372 /* only outer TPID of double VLAN can be configured*/
2373 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2374 reg = E1000_READ_REG(hw, E1000_VET);
2375 reg = (reg & (~E1000_VET_VET_EXT)) |
2376 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2377 E1000_WRITE_REG(hw, E1000_VET, reg);
2382 /* all other TPID values are read-only*/
2383 PMD_DRV_LOG(ERR, "Not supported");
2389 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2391 struct e1000_hw *hw =
2392 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395 /* Filter Table Disable */
2396 reg = E1000_READ_REG(hw, E1000_RCTL);
2397 reg &= ~E1000_RCTL_CFIEN;
2398 reg &= ~E1000_RCTL_VFE;
2399 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2403 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2405 struct e1000_hw *hw =
2406 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407 struct e1000_vfta * shadow_vfta =
2408 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2412 /* Filter Table Enable, CFI not used for packet acceptance */
2413 reg = E1000_READ_REG(hw, E1000_RCTL);
2414 reg &= ~E1000_RCTL_CFIEN;
2415 reg |= E1000_RCTL_VFE;
2416 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2418 /* restore VFTA table */
2419 for (i = 0; i < IGB_VFTA_SIZE; i++)
2420 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2424 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2426 struct e1000_hw *hw =
2427 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 /* VLAN Mode Disable */
2431 reg = E1000_READ_REG(hw, E1000_CTRL);
2432 reg &= ~E1000_CTRL_VME;
2433 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2437 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2439 struct e1000_hw *hw =
2440 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443 /* VLAN Mode Enable */
2444 reg = E1000_READ_REG(hw, E1000_CTRL);
2445 reg |= E1000_CTRL_VME;
2446 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2450 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2452 struct e1000_hw *hw =
2453 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456 /* CTRL_EXT: Extended VLAN */
2457 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2458 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2459 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2461 /* Update maximum packet length */
2462 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2463 E1000_WRITE_REG(hw, E1000_RLPML,
2464 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2469 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2471 struct e1000_hw *hw =
2472 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 /* CTRL_EXT: Extended VLAN */
2476 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2478 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2480 /* Update maximum packet length */
2481 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2482 E1000_WRITE_REG(hw, E1000_RLPML,
2483 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2488 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2490 if(mask & ETH_VLAN_STRIP_MASK){
2491 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2492 igb_vlan_hw_strip_enable(dev);
2494 igb_vlan_hw_strip_disable(dev);
2497 if(mask & ETH_VLAN_FILTER_MASK){
2498 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2499 igb_vlan_hw_filter_enable(dev);
2501 igb_vlan_hw_filter_disable(dev);
2504 if(mask & ETH_VLAN_EXTEND_MASK){
2505 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2506 igb_vlan_hw_extend_enable(dev);
2508 igb_vlan_hw_extend_disable(dev);
2514 * It enables the interrupt mask and then enable the interrupt.
2517 * Pointer to struct rte_eth_dev.
2520 * - On success, zero.
2521 * - On failure, a negative value.
2524 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2526 struct e1000_interrupt *intr =
2527 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2529 intr->mask |= E1000_ICR_LSC;
2534 /* It clears the interrupt causes and enables the interrupt.
2535 * It will be called once only during nic initialized.
2538 * Pointer to struct rte_eth_dev.
2541 * - On success, zero.
2542 * - On failure, a negative value.
2544 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2546 uint32_t mask, regval;
2547 struct e1000_hw *hw =
2548 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 struct rte_eth_dev_info dev_info;
2551 memset(&dev_info, 0, sizeof(dev_info));
2552 eth_igb_infos_get(dev, &dev_info);
2554 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2555 regval = E1000_READ_REG(hw, E1000_EIMS);
2556 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2562 * It reads ICR and gets interrupt causes, check it and set a bit flag
2563 * to update link status.
2566 * Pointer to struct rte_eth_dev.
2569 * - On success, zero.
2570 * - On failure, a negative value.
2573 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2576 struct e1000_hw *hw =
2577 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 struct e1000_interrupt *intr =
2579 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2581 igb_intr_disable(hw);
2583 /* read-on-clear nic registers here */
2584 icr = E1000_READ_REG(hw, E1000_ICR);
2587 if (icr & E1000_ICR_LSC) {
2588 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2591 if (icr & E1000_ICR_VMMB)
2592 intr->flags |= E1000_FLAG_MAILBOX;
2598 * It executes link_update after knowing an interrupt is prsent.
2601 * Pointer to struct rte_eth_dev.
2604 * - On success, zero.
2605 * - On failure, a negative value.
2608 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2610 struct e1000_hw *hw =
2611 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612 struct e1000_interrupt *intr =
2613 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2614 uint32_t tctl, rctl;
2615 struct rte_eth_link link;
2618 if (intr->flags & E1000_FLAG_MAILBOX) {
2619 igb_pf_mbx_process(dev);
2620 intr->flags &= ~E1000_FLAG_MAILBOX;
2623 igb_intr_enable(dev);
2624 rte_intr_enable(&(dev->pci_dev->intr_handle));
2626 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2627 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2629 /* set get_link_status to check register later */
2630 hw->mac.get_link_status = 1;
2631 ret = eth_igb_link_update(dev, 0);
2633 /* check if link has changed */
2637 memset(&link, 0, sizeof(link));
2638 rte_igb_dev_atomic_read_link_status(dev, &link);
2639 if (link.link_status) {
2641 " Port %d: Link Up - speed %u Mbps - %s",
2643 (unsigned)link.link_speed,
2644 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2645 "full-duplex" : "half-duplex");
2647 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2648 dev->data->port_id);
2651 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2652 dev->pci_dev->addr.domain,
2653 dev->pci_dev->addr.bus,
2654 dev->pci_dev->addr.devid,
2655 dev->pci_dev->addr.function);
2656 tctl = E1000_READ_REG(hw, E1000_TCTL);
2657 rctl = E1000_READ_REG(hw, E1000_RCTL);
2658 if (link.link_status) {
2660 tctl |= E1000_TCTL_EN;
2661 rctl |= E1000_RCTL_EN;
2664 tctl &= ~E1000_TCTL_EN;
2665 rctl &= ~E1000_RCTL_EN;
2667 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2668 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2669 E1000_WRITE_FLUSH(hw);
2670 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2677 * Interrupt handler which shall be registered at first.
2680 * Pointer to interrupt handle.
2682 * The address of parameter (struct rte_eth_dev *) regsitered before.
2688 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2691 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2693 eth_igb_interrupt_get_status(dev);
2694 eth_igb_interrupt_action(dev);
2698 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2701 struct e1000_hw *hw =
2702 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703 struct e1000_interrupt *intr =
2704 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2706 igbvf_intr_disable(hw);
2708 /* read-on-clear nic registers here */
2709 eicr = E1000_READ_REG(hw, E1000_EICR);
2712 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2713 intr->flags |= E1000_FLAG_MAILBOX;
2718 void igbvf_mbx_process(struct rte_eth_dev *dev)
2720 struct e1000_hw *hw =
2721 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722 struct e1000_mbx_info *mbx = &hw->mbx;
2725 if (mbx->ops.read(hw, &in_msg, 1, 0))
2728 /* PF reset VF event */
2729 if (in_msg == E1000_PF_CONTROL_MSG)
2730 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2734 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2736 struct e1000_interrupt *intr =
2737 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2739 if (intr->flags & E1000_FLAG_MAILBOX) {
2740 igbvf_mbx_process(dev);
2741 intr->flags &= ~E1000_FLAG_MAILBOX;
2744 igbvf_intr_enable(dev);
2745 rte_intr_enable(&dev->pci_dev->intr_handle);
2751 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2754 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2756 eth_igbvf_interrupt_get_status(dev);
2757 eth_igbvf_interrupt_action(dev);
2761 eth_igb_led_on(struct rte_eth_dev *dev)
2763 struct e1000_hw *hw;
2765 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2770 eth_igb_led_off(struct rte_eth_dev *dev)
2772 struct e1000_hw *hw;
2774 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2779 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2781 struct e1000_hw *hw;
2786 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787 fc_conf->pause_time = hw->fc.pause_time;
2788 fc_conf->high_water = hw->fc.high_water;
2789 fc_conf->low_water = hw->fc.low_water;
2790 fc_conf->send_xon = hw->fc.send_xon;
2791 fc_conf->autoneg = hw->mac.autoneg;
2794 * Return rx_pause and tx_pause status according to actual setting of
2795 * the TFCE and RFCE bits in the CTRL register.
2797 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2798 if (ctrl & E1000_CTRL_TFCE)
2803 if (ctrl & E1000_CTRL_RFCE)
2808 if (rx_pause && tx_pause)
2809 fc_conf->mode = RTE_FC_FULL;
2811 fc_conf->mode = RTE_FC_RX_PAUSE;
2813 fc_conf->mode = RTE_FC_TX_PAUSE;
2815 fc_conf->mode = RTE_FC_NONE;
2821 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2823 struct e1000_hw *hw;
2825 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2831 uint32_t rx_buf_size;
2832 uint32_t max_high_water;
2835 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836 if (fc_conf->autoneg != hw->mac.autoneg)
2838 rx_buf_size = igb_get_rx_buffer_size(hw);
2839 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2841 /* At least reserve one Ethernet frame for watermark */
2842 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2843 if ((fc_conf->high_water > max_high_water) ||
2844 (fc_conf->high_water < fc_conf->low_water)) {
2845 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2846 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2850 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2851 hw->fc.pause_time = fc_conf->pause_time;
2852 hw->fc.high_water = fc_conf->high_water;
2853 hw->fc.low_water = fc_conf->low_water;
2854 hw->fc.send_xon = fc_conf->send_xon;
2856 err = e1000_setup_link_generic(hw);
2857 if (err == E1000_SUCCESS) {
2859 /* check if we want to forward MAC frames - driver doesn't have native
2860 * capability to do that, so we'll write the registers ourselves */
2862 rctl = E1000_READ_REG(hw, E1000_RCTL);
2864 /* set or clear MFLCN.PMCF bit depending on configuration */
2865 if (fc_conf->mac_ctrl_frame_fwd != 0)
2866 rctl |= E1000_RCTL_PMCF;
2868 rctl &= ~E1000_RCTL_PMCF;
2870 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2871 E1000_WRITE_FLUSH(hw);
2876 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2880 #define E1000_RAH_POOLSEL_SHIFT (18)
2882 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2883 uint32_t index, __rte_unused uint32_t pool)
2885 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2889 rah = E1000_READ_REG(hw, E1000_RAH(index));
2890 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2891 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2895 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2897 uint8_t addr[ETHER_ADDR_LEN];
2898 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900 memset(addr, 0, sizeof(addr));
2902 e1000_rar_set(hw, addr, index);
2906 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2907 struct ether_addr *addr)
2909 eth_igb_rar_clear(dev, 0);
2911 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2914 * Virtual Function operations
2917 igbvf_intr_disable(struct e1000_hw *hw)
2919 PMD_INIT_FUNC_TRACE();
2921 /* Clear interrupt mask to stop from interrupts being generated */
2922 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2924 E1000_WRITE_FLUSH(hw);
2928 igbvf_stop_adapter(struct rte_eth_dev *dev)
2932 struct rte_eth_dev_info dev_info;
2933 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935 memset(&dev_info, 0, sizeof(dev_info));
2936 eth_igbvf_infos_get(dev, &dev_info);
2938 /* Clear interrupt mask to stop from interrupts being generated */
2939 igbvf_intr_disable(hw);
2941 /* Clear any pending interrupts, flush previous writes */
2942 E1000_READ_REG(hw, E1000_EICR);
2944 /* Disable the transmit unit. Each queue must be disabled. */
2945 for (i = 0; i < dev_info.max_tx_queues; i++)
2946 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2948 /* Disable the receive unit by stopping each queue */
2949 for (i = 0; i < dev_info.max_rx_queues; i++) {
2950 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2951 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2952 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2953 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2957 /* flush all queues disables */
2958 E1000_WRITE_FLUSH(hw);
2962 static int eth_igbvf_link_update(struct e1000_hw *hw)
2964 struct e1000_mbx_info *mbx = &hw->mbx;
2965 struct e1000_mac_info *mac = &hw->mac;
2966 int ret_val = E1000_SUCCESS;
2968 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2971 * We only want to run this if there has been a rst asserted.
2972 * in this case that could mean a link change, device reset,
2973 * or a virtual function reset
2976 /* If we were hit with a reset or timeout drop the link */
2977 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2978 mac->get_link_status = TRUE;
2980 if (!mac->get_link_status)
2983 /* if link status is down no point in checking to see if pf is up */
2984 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2987 /* if we passed all the tests above then the link is up and we no
2988 * longer need to check for link */
2989 mac->get_link_status = FALSE;
2997 igbvf_dev_configure(struct rte_eth_dev *dev)
2999 struct rte_eth_conf* conf = &dev->data->dev_conf;
3001 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3002 dev->data->port_id);
3005 * VF has no ability to enable/disable HW CRC
3006 * Keep the persistent behavior the same as Host PF
3008 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3009 if (!conf->rxmode.hw_strip_crc) {
3010 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3011 conf->rxmode.hw_strip_crc = 1;
3014 if (conf->rxmode.hw_strip_crc) {
3015 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3016 conf->rxmode.hw_strip_crc = 0;
3024 igbvf_dev_start(struct rte_eth_dev *dev)
3026 struct e1000_hw *hw =
3027 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 struct e1000_adapter *adapter =
3029 E1000_DEV_PRIVATE(dev->data->dev_private);
3031 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3032 uint32_t intr_vector = 0;
3034 PMD_INIT_FUNC_TRACE();
3036 hw->mac.ops.reset_hw(hw);
3037 adapter->stopped = 0;
3040 igbvf_set_vfta_all(dev,1);
3042 eth_igbvf_tx_init(dev);
3044 /* This can fail when allocating mbufs for descriptor rings */
3045 ret = eth_igbvf_rx_init(dev);
3047 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3048 igb_dev_clear_queues(dev);
3052 /* check and configure queue intr-vector mapping */
3053 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3054 intr_vector = dev->data->nb_rx_queues;
3055 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3060 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3061 intr_handle->intr_vec =
3062 rte_zmalloc("intr_vec",
3063 dev->data->nb_rx_queues * sizeof(int), 0);
3064 if (!intr_handle->intr_vec) {
3065 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3066 " intr_vec\n", dev->data->nb_rx_queues);
3071 eth_igbvf_configure_msix_intr(dev);
3073 /* enable uio/vfio intr/eventfd mapping */
3074 rte_intr_enable(intr_handle);
3076 /* resume enabled intr since hw reset */
3077 igbvf_intr_enable(dev);
3083 igbvf_dev_stop(struct rte_eth_dev *dev)
3085 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3087 PMD_INIT_FUNC_TRACE();
3089 igbvf_stop_adapter(dev);
3092 * Clear what we set, but we still keep shadow_vfta to
3093 * restore after device starts
3095 igbvf_set_vfta_all(dev,0);
3097 igb_dev_clear_queues(dev);
3099 /* disable intr eventfd mapping */
3100 rte_intr_disable(intr_handle);
3102 /* Clean datapath event and queue/vec mapping */
3103 rte_intr_efd_disable(intr_handle);
3104 if (intr_handle->intr_vec) {
3105 rte_free(intr_handle->intr_vec);
3106 intr_handle->intr_vec = NULL;
3111 igbvf_dev_close(struct rte_eth_dev *dev)
3113 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3114 struct e1000_adapter *adapter =
3115 E1000_DEV_PRIVATE(dev->data->dev_private);
3116 struct ether_addr addr;
3118 PMD_INIT_FUNC_TRACE();
3122 igbvf_dev_stop(dev);
3123 adapter->stopped = 1;
3124 igb_dev_free_queues(dev);
3127 * reprogram the RAR with a zero mac address,
3128 * to ensure that the VF traffic goes to the PF
3129 * after stop, close and detach of the VF.
3132 memset(&addr, 0, sizeof(addr));
3133 igbvf_default_mac_addr_set(dev, &addr);
3137 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3139 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141 /* Set both unicast and multicast promisc */
3142 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3146 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3148 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3150 /* If in allmulticast mode leave multicast promisc */
3151 if (dev->data->all_multicast == 1)
3152 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3154 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3158 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3160 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162 /* In promiscuous mode multicast promisc already set */
3163 if (dev->data->promiscuous == 0)
3164 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3168 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3170 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3172 /* In promiscuous mode leave multicast promisc enabled */
3173 if (dev->data->promiscuous == 0)
3174 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3177 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3179 struct e1000_mbx_info *mbx = &hw->mbx;
3183 /* After set vlan, vlan strip will also be enabled in igb driver*/
3184 msgbuf[0] = E1000_VF_SET_VLAN;
3186 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3188 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3190 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3194 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3198 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3199 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3206 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3208 struct e1000_hw *hw =
3209 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3210 struct e1000_vfta * shadow_vfta =
3211 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3212 int i = 0, j = 0, vfta = 0, mask = 1;
3214 for (i = 0; i < IGB_VFTA_SIZE; i++){
3215 vfta = shadow_vfta->vfta[i];
3218 for (j = 0; j < 32; j++){
3221 (uint16_t)((i<<5)+j), on);
3230 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3232 struct e1000_hw *hw =
3233 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3234 struct e1000_vfta * shadow_vfta =
3235 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3236 uint32_t vid_idx = 0;
3237 uint32_t vid_bit = 0;
3240 PMD_INIT_FUNC_TRACE();
3242 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3243 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3245 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3248 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3249 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3251 /*Save what we set and retore it after device reset*/
3253 shadow_vfta->vfta[vid_idx] |= vid_bit;
3255 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3261 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3263 struct e1000_hw *hw =
3264 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3266 /* index is not used by rar_set() */
3267 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3272 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3273 struct rte_eth_rss_reta_entry64 *reta_conf,
3278 uint16_t idx, shift;
3279 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3282 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3283 "(%d) doesn't match the number hardware can supported "
3284 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3288 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3289 idx = i / RTE_RETA_GROUP_SIZE;
3290 shift = i % RTE_RETA_GROUP_SIZE;
3291 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3295 if (mask == IGB_4_BIT_MASK)
3298 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3299 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3300 if (mask & (0x1 << j))
3301 reta |= reta_conf[idx].reta[shift + j] <<
3304 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3306 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3313 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3314 struct rte_eth_rss_reta_entry64 *reta_conf,
3319 uint16_t idx, shift;
3320 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3323 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3324 "(%d) doesn't match the number hardware can supported "
3325 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3329 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3330 idx = i / RTE_RETA_GROUP_SIZE;
3331 shift = i % RTE_RETA_GROUP_SIZE;
3332 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3336 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3337 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3338 if (mask & (0x1 << j))
3339 reta_conf[idx].reta[shift + j] =
3340 ((reta >> (CHAR_BIT * j)) &
3348 #define MAC_TYPE_FILTER_SUP(type) do {\
3349 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3350 (type) != e1000_82576)\
3355 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3356 struct rte_eth_syn_filter *filter,
3359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360 uint32_t synqf, rfctl;
3362 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3365 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3368 if (synqf & E1000_SYN_FILTER_ENABLE)
3371 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3372 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3374 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3375 if (filter->hig_pri)
3376 rfctl |= E1000_RFCTL_SYNQFP;
3378 rfctl &= ~E1000_RFCTL_SYNQFP;
3380 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3382 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3387 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3388 E1000_WRITE_FLUSH(hw);
3393 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3394 struct rte_eth_syn_filter *filter)
3396 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397 uint32_t synqf, rfctl;
3399 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3400 if (synqf & E1000_SYN_FILTER_ENABLE) {
3401 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3402 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3403 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3404 E1000_SYN_FILTER_QUEUE_SHIFT);
3412 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3413 enum rte_filter_op filter_op,
3416 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419 MAC_TYPE_FILTER_SUP(hw->mac.type);
3421 if (filter_op == RTE_ETH_FILTER_NOP)
3425 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3430 switch (filter_op) {
3431 case RTE_ETH_FILTER_ADD:
3432 ret = eth_igb_syn_filter_set(dev,
3433 (struct rte_eth_syn_filter *)arg,
3436 case RTE_ETH_FILTER_DELETE:
3437 ret = eth_igb_syn_filter_set(dev,
3438 (struct rte_eth_syn_filter *)arg,
3441 case RTE_ETH_FILTER_GET:
3442 ret = eth_igb_syn_filter_get(dev,
3443 (struct rte_eth_syn_filter *)arg);
3446 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3454 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3455 if ((type) != e1000_82580 && (type) != e1000_i350)\
3459 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3461 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3462 struct e1000_2tuple_filter_info *filter_info)
3464 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3466 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3467 return -EINVAL; /* filter index is out of range. */
3468 if (filter->tcp_flags > TCP_FLAG_ALL)
3469 return -EINVAL; /* flags is invalid. */
3471 switch (filter->dst_port_mask) {
3473 filter_info->dst_port_mask = 0;
3474 filter_info->dst_port = filter->dst_port;
3477 filter_info->dst_port_mask = 1;
3480 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3484 switch (filter->proto_mask) {
3486 filter_info->proto_mask = 0;
3487 filter_info->proto = filter->proto;
3490 filter_info->proto_mask = 1;
3493 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3497 filter_info->priority = (uint8_t)filter->priority;
3498 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3499 filter_info->tcp_flags = filter->tcp_flags;
3501 filter_info->tcp_flags = 0;
3506 static inline struct e1000_2tuple_filter *
3507 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3508 struct e1000_2tuple_filter_info *key)
3510 struct e1000_2tuple_filter *it;
3512 TAILQ_FOREACH(it, filter_list, entries) {
3513 if (memcmp(key, &it->filter_info,
3514 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3522 * igb_add_2tuple_filter - add a 2tuple filter
3525 * dev: Pointer to struct rte_eth_dev.
3526 * ntuple_filter: ponter to the filter that will be added.
3529 * - On success, zero.
3530 * - On failure, a negative value.
3533 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3534 struct rte_eth_ntuple_filter *ntuple_filter)
3536 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3537 struct e1000_filter_info *filter_info =
3538 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3539 struct e1000_2tuple_filter *filter;
3540 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3541 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3544 filter = rte_zmalloc("e1000_2tuple_filter",
3545 sizeof(struct e1000_2tuple_filter), 0);
3549 ret = ntuple_filter_to_2tuple(ntuple_filter,
3550 &filter->filter_info);
3555 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3556 &filter->filter_info) != NULL) {
3557 PMD_DRV_LOG(ERR, "filter exists.");
3561 filter->queue = ntuple_filter->queue;
3564 * look for an unused 2tuple filter index,
3565 * and insert the filter to list.
3567 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3568 if (!(filter_info->twotuple_mask & (1 << i))) {
3569 filter_info->twotuple_mask |= 1 << i;
3571 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3577 if (i >= E1000_MAX_TTQF_FILTERS) {
3578 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3583 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3584 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3585 imir |= E1000_IMIR_PORT_BP;
3587 imir &= ~E1000_IMIR_PORT_BP;
3589 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3591 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3592 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3593 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3594 if (filter->filter_info.proto_mask == 0)
3595 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3597 /* tcp flags bits setting. */
3598 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3599 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3600 imir_ext |= E1000_IMIREXT_CTRL_URG;
3601 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3602 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3603 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3604 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3605 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3606 imir_ext |= E1000_IMIREXT_CTRL_RST;
3607 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3608 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3609 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3610 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3612 imir_ext |= E1000_IMIREXT_CTRL_BP;
3613 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3614 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3615 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3620 * igb_remove_2tuple_filter - remove a 2tuple filter
3623 * dev: Pointer to struct rte_eth_dev.
3624 * ntuple_filter: ponter to the filter that will be removed.
3627 * - On success, zero.
3628 * - On failure, a negative value.
3631 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3632 struct rte_eth_ntuple_filter *ntuple_filter)
3634 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635 struct e1000_filter_info *filter_info =
3636 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3637 struct e1000_2tuple_filter_info filter_2tuple;
3638 struct e1000_2tuple_filter *filter;
3641 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3642 ret = ntuple_filter_to_2tuple(ntuple_filter,
3647 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3649 if (filter == NULL) {
3650 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3654 filter_info->twotuple_mask &= ~(1 << filter->index);
3655 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3658 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3659 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3660 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3664 static inline struct e1000_flex_filter *
3665 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3666 struct e1000_flex_filter_info *key)
3668 struct e1000_flex_filter *it;
3670 TAILQ_FOREACH(it, filter_list, entries) {
3671 if (memcmp(key, &it->filter_info,
3672 sizeof(struct e1000_flex_filter_info)) == 0)
3680 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3681 struct rte_eth_flex_filter *filter,
3684 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3685 struct e1000_filter_info *filter_info =
3686 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3687 struct e1000_flex_filter *flex_filter, *it;
3688 uint32_t wufc, queueing, mask;
3690 uint8_t shift, i, j = 0;
3692 flex_filter = rte_zmalloc("e1000_flex_filter",
3693 sizeof(struct e1000_flex_filter), 0);
3694 if (flex_filter == NULL)
3697 flex_filter->filter_info.len = filter->len;
3698 flex_filter->filter_info.priority = filter->priority;
3699 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3700 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3702 /* reverse bits in flex filter's mask*/
3703 for (shift = 0; shift < CHAR_BIT; shift++) {
3704 if (filter->mask[i] & (0x01 << shift))
3705 mask |= (0x80 >> shift);
3707 flex_filter->filter_info.mask[i] = mask;
3710 wufc = E1000_READ_REG(hw, E1000_WUFC);
3711 if (flex_filter->index < E1000_MAX_FHFT)
3712 reg_off = E1000_FHFT(flex_filter->index);
3714 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3717 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3718 &flex_filter->filter_info) != NULL) {
3719 PMD_DRV_LOG(ERR, "filter exists.");
3720 rte_free(flex_filter);
3723 flex_filter->queue = filter->queue;
3725 * look for an unused flex filter index
3726 * and insert the filter into the list.
3728 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3729 if (!(filter_info->flex_mask & (1 << i))) {
3730 filter_info->flex_mask |= 1 << i;
3731 flex_filter->index = i;
3732 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3738 if (i >= E1000_MAX_FLEX_FILTERS) {
3739 PMD_DRV_LOG(ERR, "flex filters are full.");
3740 rte_free(flex_filter);
3744 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3745 (E1000_WUFC_FLX0 << flex_filter->index));
3746 queueing = filter->len |
3747 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3748 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3749 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3751 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3752 E1000_WRITE_REG(hw, reg_off,
3753 flex_filter->filter_info.dwords[j]);
3754 reg_off += sizeof(uint32_t);
3755 E1000_WRITE_REG(hw, reg_off,
3756 flex_filter->filter_info.dwords[++j]);
3757 reg_off += sizeof(uint32_t);
3758 E1000_WRITE_REG(hw, reg_off,
3759 (uint32_t)flex_filter->filter_info.mask[i]);
3760 reg_off += sizeof(uint32_t) * 2;
3764 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3765 &flex_filter->filter_info);
3767 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3768 rte_free(flex_filter);
3772 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3773 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3774 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3775 (~(E1000_WUFC_FLX0 << it->index)));
3777 filter_info->flex_mask &= ~(1 << it->index);
3778 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3780 rte_free(flex_filter);
3787 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3788 struct rte_eth_flex_filter *filter)
3790 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791 struct e1000_filter_info *filter_info =
3792 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3793 struct e1000_flex_filter flex_filter, *it;
3794 uint32_t wufc, queueing, wufc_en = 0;
3796 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3797 flex_filter.filter_info.len = filter->len;
3798 flex_filter.filter_info.priority = filter->priority;
3799 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3800 memcpy(flex_filter.filter_info.mask, filter->mask,
3801 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3803 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3804 &flex_filter.filter_info);
3806 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3810 wufc = E1000_READ_REG(hw, E1000_WUFC);
3811 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3813 if ((wufc & wufc_en) == wufc_en) {
3814 uint32_t reg_off = 0;
3815 if (it->index < E1000_MAX_FHFT)
3816 reg_off = E1000_FHFT(it->index);
3818 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3820 queueing = E1000_READ_REG(hw,
3821 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3822 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3823 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3824 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3825 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3826 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3833 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3834 enum rte_filter_op filter_op,
3837 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 struct rte_eth_flex_filter *filter;
3841 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3843 if (filter_op == RTE_ETH_FILTER_NOP)
3847 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3852 filter = (struct rte_eth_flex_filter *)arg;
3853 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3854 || filter->len % sizeof(uint64_t) != 0) {
3855 PMD_DRV_LOG(ERR, "filter's length is out of range");
3858 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3859 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3863 switch (filter_op) {
3864 case RTE_ETH_FILTER_ADD:
3865 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3867 case RTE_ETH_FILTER_DELETE:
3868 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3870 case RTE_ETH_FILTER_GET:
3871 ret = eth_igb_get_flex_filter(dev, filter);
3874 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3882 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3884 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3885 struct e1000_5tuple_filter_info *filter_info)
3887 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3889 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3890 return -EINVAL; /* filter index is out of range. */
3891 if (filter->tcp_flags > TCP_FLAG_ALL)
3892 return -EINVAL; /* flags is invalid. */
3894 switch (filter->dst_ip_mask) {
3896 filter_info->dst_ip_mask = 0;
3897 filter_info->dst_ip = filter->dst_ip;
3900 filter_info->dst_ip_mask = 1;
3903 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3907 switch (filter->src_ip_mask) {
3909 filter_info->src_ip_mask = 0;
3910 filter_info->src_ip = filter->src_ip;
3913 filter_info->src_ip_mask = 1;
3916 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3920 switch (filter->dst_port_mask) {
3922 filter_info->dst_port_mask = 0;
3923 filter_info->dst_port = filter->dst_port;
3926 filter_info->dst_port_mask = 1;
3929 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3933 switch (filter->src_port_mask) {
3935 filter_info->src_port_mask = 0;
3936 filter_info->src_port = filter->src_port;
3939 filter_info->src_port_mask = 1;
3942 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3946 switch (filter->proto_mask) {
3948 filter_info->proto_mask = 0;
3949 filter_info->proto = filter->proto;
3952 filter_info->proto_mask = 1;
3955 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3959 filter_info->priority = (uint8_t)filter->priority;
3960 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3961 filter_info->tcp_flags = filter->tcp_flags;
3963 filter_info->tcp_flags = 0;
3968 static inline struct e1000_5tuple_filter *
3969 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3970 struct e1000_5tuple_filter_info *key)
3972 struct e1000_5tuple_filter *it;
3974 TAILQ_FOREACH(it, filter_list, entries) {
3975 if (memcmp(key, &it->filter_info,
3976 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3984 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3987 * dev: Pointer to struct rte_eth_dev.
3988 * ntuple_filter: ponter to the filter that will be added.
3991 * - On success, zero.
3992 * - On failure, a negative value.
3995 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3996 struct rte_eth_ntuple_filter *ntuple_filter)
3998 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999 struct e1000_filter_info *filter_info =
4000 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4001 struct e1000_5tuple_filter *filter;
4002 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4003 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4007 filter = rte_zmalloc("e1000_5tuple_filter",
4008 sizeof(struct e1000_5tuple_filter), 0);
4012 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4013 &filter->filter_info);
4019 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4020 &filter->filter_info) != NULL) {
4021 PMD_DRV_LOG(ERR, "filter exists.");
4025 filter->queue = ntuple_filter->queue;
4028 * look for an unused 5tuple filter index,
4029 * and insert the filter to list.
4031 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4032 if (!(filter_info->fivetuple_mask & (1 << i))) {
4033 filter_info->fivetuple_mask |= 1 << i;
4035 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4041 if (i >= E1000_MAX_FTQF_FILTERS) {
4042 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4047 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4048 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4049 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4050 if (filter->filter_info.dst_ip_mask == 0)
4051 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4052 if (filter->filter_info.src_port_mask == 0)
4053 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4054 if (filter->filter_info.proto_mask == 0)
4055 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4056 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4057 E1000_FTQF_QUEUE_MASK;
4058 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4059 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4060 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4061 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4063 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4064 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4066 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4067 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4068 imir |= E1000_IMIR_PORT_BP;
4070 imir &= ~E1000_IMIR_PORT_BP;
4071 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4073 /* tcp flags bits setting. */
4074 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4075 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4076 imir_ext |= E1000_IMIREXT_CTRL_URG;
4077 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4078 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4079 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4080 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4081 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4082 imir_ext |= E1000_IMIREXT_CTRL_RST;
4083 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4084 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4085 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4086 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4088 imir_ext |= E1000_IMIREXT_CTRL_BP;
4089 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4090 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4095 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4098 * dev: Pointer to struct rte_eth_dev.
4099 * ntuple_filter: ponter to the filter that will be removed.
4102 * - On success, zero.
4103 * - On failure, a negative value.
4106 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4107 struct rte_eth_ntuple_filter *ntuple_filter)
4109 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110 struct e1000_filter_info *filter_info =
4111 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4112 struct e1000_5tuple_filter_info filter_5tuple;
4113 struct e1000_5tuple_filter *filter;
4116 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4117 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4122 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4124 if (filter == NULL) {
4125 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4129 filter_info->fivetuple_mask &= ~(1 << filter->index);
4130 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4133 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4134 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4135 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4136 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4137 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4138 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4139 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4144 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4147 struct e1000_hw *hw;
4148 struct rte_eth_dev_info dev_info;
4149 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4152 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4154 #ifdef RTE_LIBRTE_82571_SUPPORT
4155 /* XXX: not bigger than max_rx_pktlen */
4156 if (hw->mac.type == e1000_82571)
4159 eth_igb_infos_get(dev, &dev_info);
4161 /* check that mtu is within the allowed range */
4162 if ((mtu < ETHER_MIN_MTU) ||
4163 (frame_size > dev_info.max_rx_pktlen))
4166 /* refuse mtu that requires the support of scattered packets when this
4167 * feature has not been enabled before. */
4168 if (!dev->data->scattered_rx &&
4169 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4172 rctl = E1000_READ_REG(hw, E1000_RCTL);
4174 /* switch to jumbo mode if needed */
4175 if (frame_size > ETHER_MAX_LEN) {
4176 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4177 rctl |= E1000_RCTL_LPE;
4179 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4180 rctl &= ~E1000_RCTL_LPE;
4182 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4184 /* update max frame size */
4185 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4187 E1000_WRITE_REG(hw, E1000_RLPML,
4188 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4194 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4197 * dev: Pointer to struct rte_eth_dev.
4198 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4199 * add: if true, add filter, if false, remove filter
4202 * - On success, zero.
4203 * - On failure, a negative value.
4206 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4207 struct rte_eth_ntuple_filter *ntuple_filter,
4210 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213 switch (ntuple_filter->flags) {
4214 case RTE_5TUPLE_FLAGS:
4215 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4216 if (hw->mac.type != e1000_82576)
4219 ret = igb_add_5tuple_filter_82576(dev,
4222 ret = igb_remove_5tuple_filter_82576(dev,
4225 case RTE_2TUPLE_FLAGS:
4226 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4227 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4230 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4232 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4243 * igb_get_ntuple_filter - get a ntuple filter
4246 * dev: Pointer to struct rte_eth_dev.
4247 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4250 * - On success, zero.
4251 * - On failure, a negative value.
4254 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4255 struct rte_eth_ntuple_filter *ntuple_filter)
4257 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4258 struct e1000_filter_info *filter_info =
4259 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4260 struct e1000_5tuple_filter_info filter_5tuple;
4261 struct e1000_2tuple_filter_info filter_2tuple;
4262 struct e1000_5tuple_filter *p_5tuple_filter;
4263 struct e1000_2tuple_filter *p_2tuple_filter;
4266 switch (ntuple_filter->flags) {
4267 case RTE_5TUPLE_FLAGS:
4268 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4269 if (hw->mac.type != e1000_82576)
4271 memset(&filter_5tuple,
4273 sizeof(struct e1000_5tuple_filter_info));
4274 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4278 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4279 &filter_info->fivetuple_list,
4281 if (p_5tuple_filter == NULL) {
4282 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4285 ntuple_filter->queue = p_5tuple_filter->queue;
4287 case RTE_2TUPLE_FLAGS:
4288 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4289 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4291 memset(&filter_2tuple,
4293 sizeof(struct e1000_2tuple_filter_info));
4294 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4297 p_2tuple_filter = igb_2tuple_filter_lookup(
4298 &filter_info->twotuple_list,
4300 if (p_2tuple_filter == NULL) {
4301 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4304 ntuple_filter->queue = p_2tuple_filter->queue;
4315 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4316 * @dev: pointer to rte_eth_dev structure
4317 * @filter_op:operation will be taken.
4318 * @arg: a pointer to specific structure corresponding to the filter_op
4321 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4322 enum rte_filter_op filter_op,
4325 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328 MAC_TYPE_FILTER_SUP(hw->mac.type);
4330 if (filter_op == RTE_ETH_FILTER_NOP)
4334 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4339 switch (filter_op) {
4340 case RTE_ETH_FILTER_ADD:
4341 ret = igb_add_del_ntuple_filter(dev,
4342 (struct rte_eth_ntuple_filter *)arg,
4345 case RTE_ETH_FILTER_DELETE:
4346 ret = igb_add_del_ntuple_filter(dev,
4347 (struct rte_eth_ntuple_filter *)arg,
4350 case RTE_ETH_FILTER_GET:
4351 ret = igb_get_ntuple_filter(dev,
4352 (struct rte_eth_ntuple_filter *)arg);
4355 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4363 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4368 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4369 if (filter_info->ethertype_filters[i] == ethertype &&
4370 (filter_info->ethertype_mask & (1 << i)))
4377 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4382 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4383 if (!(filter_info->ethertype_mask & (1 << i))) {
4384 filter_info->ethertype_mask |= 1 << i;
4385 filter_info->ethertype_filters[i] = ethertype;
4393 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4396 if (idx >= E1000_MAX_ETQF_FILTERS)
4398 filter_info->ethertype_mask &= ~(1 << idx);
4399 filter_info->ethertype_filters[idx] = 0;
4405 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4406 struct rte_eth_ethertype_filter *filter,
4409 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4410 struct e1000_filter_info *filter_info =
4411 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4415 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4416 filter->ether_type == ETHER_TYPE_IPv6) {
4417 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4418 " ethertype filter.", filter->ether_type);
4422 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4423 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4426 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4427 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4431 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4432 if (ret >= 0 && add) {
4433 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4434 filter->ether_type);
4437 if (ret < 0 && !add) {
4438 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4439 filter->ether_type);
4444 ret = igb_ethertype_filter_insert(filter_info,
4445 filter->ether_type);
4447 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4451 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4452 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4453 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4455 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4459 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4460 E1000_WRITE_FLUSH(hw);
4466 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4467 struct rte_eth_ethertype_filter *filter)
4469 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470 struct e1000_filter_info *filter_info =
4471 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4475 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4477 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4478 filter->ether_type);
4482 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4483 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4484 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4486 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4487 E1000_ETQF_QUEUE_SHIFT;
4495 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4496 * @dev: pointer to rte_eth_dev structure
4497 * @filter_op:operation will be taken.
4498 * @arg: a pointer to specific structure corresponding to the filter_op
4501 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4502 enum rte_filter_op filter_op,
4505 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508 MAC_TYPE_FILTER_SUP(hw->mac.type);
4510 if (filter_op == RTE_ETH_FILTER_NOP)
4514 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4519 switch (filter_op) {
4520 case RTE_ETH_FILTER_ADD:
4521 ret = igb_add_del_ethertype_filter(dev,
4522 (struct rte_eth_ethertype_filter *)arg,
4525 case RTE_ETH_FILTER_DELETE:
4526 ret = igb_add_del_ethertype_filter(dev,
4527 (struct rte_eth_ethertype_filter *)arg,
4530 case RTE_ETH_FILTER_GET:
4531 ret = igb_get_ethertype_filter(dev,
4532 (struct rte_eth_ethertype_filter *)arg);
4535 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4543 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4544 enum rte_filter_type filter_type,
4545 enum rte_filter_op filter_op,
4550 switch (filter_type) {
4551 case RTE_ETH_FILTER_NTUPLE:
4552 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4554 case RTE_ETH_FILTER_ETHERTYPE:
4555 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4557 case RTE_ETH_FILTER_SYN:
4558 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4560 case RTE_ETH_FILTER_FLEXIBLE:
4561 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4564 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4573 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4574 struct ether_addr *mc_addr_set,
4575 uint32_t nb_mc_addr)
4577 struct e1000_hw *hw;
4579 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4580 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4585 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4587 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4588 uint64_t systime_cycles;
4590 switch (hw->mac.type) {
4594 * Need to read System Time Residue Register to be able
4595 * to read the other two registers.
4597 E1000_READ_REG(hw, E1000_SYSTIMR);
4598 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4599 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4600 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4607 * Need to read System Time Residue Register to be able
4608 * to read the other two registers.
4610 E1000_READ_REG(hw, E1000_SYSTIMR);
4611 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4612 /* Only the 8 LSB are valid. */
4613 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4617 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4618 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4623 return systime_cycles;
4627 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4629 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630 uint64_t rx_tstamp_cycles;
4632 switch (hw->mac.type) {
4635 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4636 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4637 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4643 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4644 /* Only the 8 LSB are valid. */
4645 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4649 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4650 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4655 return rx_tstamp_cycles;
4659 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4661 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4662 uint64_t tx_tstamp_cycles;
4664 switch (hw->mac.type) {
4667 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4668 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4669 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4675 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4676 /* Only the 8 LSB are valid. */
4677 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4681 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4682 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4687 return tx_tstamp_cycles;
4691 igb_start_timecounters(struct rte_eth_dev *dev)
4693 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694 struct e1000_adapter *adapter =
4695 (struct e1000_adapter *)dev->data->dev_private;
4696 uint32_t incval = 1;
4698 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4700 switch (hw->mac.type) {
4704 /* 32 LSB bits + 8 MSB bits = 40 bits */
4705 mask = (1ULL << 40) - 1;
4710 * Start incrementing the register
4711 * used to timestamp PTP packets.
4713 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4716 incval = E1000_INCVALUE_82576;
4717 shift = IGB_82576_TSYNC_SHIFT;
4718 E1000_WRITE_REG(hw, E1000_TIMINCA,
4719 E1000_INCPERIOD_82576 | incval);
4726 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4727 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4728 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4730 adapter->systime_tc.cc_mask = mask;
4731 adapter->systime_tc.cc_shift = shift;
4732 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4734 adapter->rx_tstamp_tc.cc_mask = mask;
4735 adapter->rx_tstamp_tc.cc_shift = shift;
4736 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4738 adapter->tx_tstamp_tc.cc_mask = mask;
4739 adapter->tx_tstamp_tc.cc_shift = shift;
4740 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4744 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4746 struct e1000_adapter *adapter =
4747 (struct e1000_adapter *)dev->data->dev_private;
4749 adapter->systime_tc.nsec += delta;
4750 adapter->rx_tstamp_tc.nsec += delta;
4751 adapter->tx_tstamp_tc.nsec += delta;
4757 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4760 struct e1000_adapter *adapter =
4761 (struct e1000_adapter *)dev->data->dev_private;
4763 ns = rte_timespec_to_ns(ts);
4765 /* Set the timecounters to a new value. */
4766 adapter->systime_tc.nsec = ns;
4767 adapter->rx_tstamp_tc.nsec = ns;
4768 adapter->tx_tstamp_tc.nsec = ns;
4774 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4776 uint64_t ns, systime_cycles;
4777 struct e1000_adapter *adapter =
4778 (struct e1000_adapter *)dev->data->dev_private;
4780 systime_cycles = igb_read_systime_cyclecounter(dev);
4781 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4782 *ts = rte_ns_to_timespec(ns);
4788 igb_timesync_enable(struct rte_eth_dev *dev)
4790 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4794 /* Stop the timesync system time. */
4795 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4796 /* Reset the timesync system time value. */
4797 switch (hw->mac.type) {
4803 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4806 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4807 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4810 /* Not supported. */
4814 /* Enable system time for it isn't on by default. */
4815 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4816 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4817 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4819 igb_start_timecounters(dev);
4821 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4822 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4824 E1000_ETQF_FILTER_ENABLE |
4827 /* Enable timestamping of received PTP packets. */
4828 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4829 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4830 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4832 /* Enable Timestamping of transmitted PTP packets. */
4833 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4834 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4835 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4841 igb_timesync_disable(struct rte_eth_dev *dev)
4843 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846 /* Disable timestamping of transmitted PTP packets. */
4847 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4848 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4849 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4851 /* Disable timestamping of received PTP packets. */
4852 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4853 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4854 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4856 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4857 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4859 /* Stop incrementating the System Time registers. */
4860 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4866 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4867 struct timespec *timestamp,
4868 uint32_t flags __rte_unused)
4870 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871 struct e1000_adapter *adapter =
4872 (struct e1000_adapter *)dev->data->dev_private;
4873 uint32_t tsync_rxctl;
4874 uint64_t rx_tstamp_cycles;
4877 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4878 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4881 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4882 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4883 *timestamp = rte_ns_to_timespec(ns);
4889 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4890 struct timespec *timestamp)
4892 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4893 struct e1000_adapter *adapter =
4894 (struct e1000_adapter *)dev->data->dev_private;
4895 uint32_t tsync_txctl;
4896 uint64_t tx_tstamp_cycles;
4899 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4900 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4903 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4904 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4905 *timestamp = rte_ns_to_timespec(ns);
4911 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4915 const struct reg_info *reg_group;
4917 while ((reg_group = igb_regs[g_ind++]))
4918 count += igb_reg_group_count(reg_group);
4924 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4928 const struct reg_info *reg_group;
4930 while ((reg_group = igbvf_regs[g_ind++]))
4931 count += igb_reg_group_count(reg_group);
4937 eth_igb_get_regs(struct rte_eth_dev *dev,
4938 struct rte_dev_reg_info *regs)
4940 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 uint32_t *data = regs->data;
4944 const struct reg_info *reg_group;
4947 regs->length = eth_igb_get_reg_length(dev);
4948 regs->width = sizeof(uint32_t);
4952 /* Support only full register dump */
4953 if ((regs->length == 0) ||
4954 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4955 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4957 while ((reg_group = igb_regs[g_ind++]))
4958 count += igb_read_regs_group(dev, &data[count],
4967 igbvf_get_regs(struct rte_eth_dev *dev,
4968 struct rte_dev_reg_info *regs)
4970 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971 uint32_t *data = regs->data;
4974 const struct reg_info *reg_group;
4977 regs->length = igbvf_get_reg_length(dev);
4978 regs->width = sizeof(uint32_t);
4982 /* Support only full register dump */
4983 if ((regs->length == 0) ||
4984 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4985 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4987 while ((reg_group = igbvf_regs[g_ind++]))
4988 count += igb_read_regs_group(dev, &data[count],
4997 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4999 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001 /* Return unit is byte count */
5002 return hw->nvm.word_size * 2;
5006 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5007 struct rte_dev_eeprom_info *in_eeprom)
5009 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5010 struct e1000_nvm_info *nvm = &hw->nvm;
5011 uint16_t *data = in_eeprom->data;
5014 first = in_eeprom->offset >> 1;
5015 length = in_eeprom->length >> 1;
5016 if ((first >= hw->nvm.word_size) ||
5017 ((first + length) >= hw->nvm.word_size))
5020 in_eeprom->magic = hw->vendor_id |
5021 ((uint32_t)hw->device_id << 16);
5023 if ((nvm->ops.read) == NULL)
5026 return nvm->ops.read(hw, first, length, data);
5030 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5031 struct rte_dev_eeprom_info *in_eeprom)
5033 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5034 struct e1000_nvm_info *nvm = &hw->nvm;
5035 uint16_t *data = in_eeprom->data;
5038 first = in_eeprom->offset >> 1;
5039 length = in_eeprom->length >> 1;
5040 if ((first >= hw->nvm.word_size) ||
5041 ((first + length) >= hw->nvm.word_size))
5044 in_eeprom->magic = (uint32_t)hw->vendor_id |
5045 ((uint32_t)hw->device_id << 16);
5047 if ((nvm->ops.write) == NULL)
5049 return nvm->ops.write(hw, first, length, data);
5052 static struct rte_driver pmd_igb_drv = {
5054 .init = rte_igb_pmd_init,
5057 static struct rte_driver pmd_igbvf_drv = {
5059 .init = rte_igbvf_pmd_init,
5063 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5065 struct e1000_hw *hw =
5066 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067 uint32_t mask = 1 << queue_id;
5069 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5070 E1000_WRITE_FLUSH(hw);
5076 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5078 struct e1000_hw *hw =
5079 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5080 uint32_t mask = 1 << queue_id;
5083 regval = E1000_READ_REG(hw, E1000_EIMS);
5084 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5085 E1000_WRITE_FLUSH(hw);
5087 rte_intr_enable(&dev->pci_dev->intr_handle);
5093 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5094 uint8_t index, uint8_t offset)
5096 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5099 val &= ~((uint32_t)0xFF << offset);
5101 /* write vector and valid bit */
5102 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5104 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5108 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5109 uint8_t queue, uint8_t msix_vector)
5113 if (hw->mac.type == e1000_82575) {
5115 tmp = E1000_EICR_RX_QUEUE0 << queue;
5116 else if (direction == 1)
5117 tmp = E1000_EICR_TX_QUEUE0 << queue;
5118 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5119 } else if (hw->mac.type == e1000_82576) {
5120 if ((direction == 0) || (direction == 1))
5121 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5122 ((queue & 0x8) << 1) +
5124 } else if ((hw->mac.type == e1000_82580) ||
5125 (hw->mac.type == e1000_i350) ||
5126 (hw->mac.type == e1000_i354) ||
5127 (hw->mac.type == e1000_i210) ||
5128 (hw->mac.type == e1000_i211)) {
5129 if ((direction == 0) || (direction == 1))
5130 eth_igb_write_ivar(hw, msix_vector,
5132 ((queue & 0x1) << 4) +
5137 /* Sets up the hardware to generate MSI-X interrupts properly
5139 * board private structure
5142 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5145 uint32_t tmpval, regval, intr_mask;
5146 struct e1000_hw *hw =
5147 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148 uint32_t vec = E1000_MISC_VEC_ID;
5149 uint32_t base = E1000_MISC_VEC_ID;
5150 uint32_t misc_shift = 0;
5152 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5154 /* won't configure msix register if no mapping is done
5155 * between intr vector and event fd
5157 if (!rte_intr_dp_is_en(intr_handle))
5160 if (rte_intr_allow_others(intr_handle)) {
5161 vec = base = E1000_RX_VEC_START;
5165 /* set interrupt vector for other causes */
5166 if (hw->mac.type == e1000_82575) {
5167 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5168 /* enable MSI-X PBA support */
5169 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5171 /* Auto-Mask interrupts upon ICR read */
5172 tmpval |= E1000_CTRL_EXT_EIAME;
5173 tmpval |= E1000_CTRL_EXT_IRCA;
5175 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5177 /* enable msix_other interrupt */
5178 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5179 regval = E1000_READ_REG(hw, E1000_EIAC);
5180 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5181 regval = E1000_READ_REG(hw, E1000_EIAM);
5182 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5183 } else if ((hw->mac.type == e1000_82576) ||
5184 (hw->mac.type == e1000_82580) ||
5185 (hw->mac.type == e1000_i350) ||
5186 (hw->mac.type == e1000_i354) ||
5187 (hw->mac.type == e1000_i210) ||
5188 (hw->mac.type == e1000_i211)) {
5189 /* turn on MSI-X capability first */
5190 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5191 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5193 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5195 regval = E1000_READ_REG(hw, E1000_EIAC);
5196 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5198 /* enable msix_other interrupt */
5199 regval = E1000_READ_REG(hw, E1000_EIMS);
5200 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5201 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5202 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5205 /* use EIAM to auto-mask when MSI-X interrupt
5206 * is asserted, this saves a register write for every interrupt
5208 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5210 regval = E1000_READ_REG(hw, E1000_EIAM);
5211 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5213 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5214 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5215 intr_handle->intr_vec[queue_id] = vec;
5216 if (vec < base + intr_handle->nb_efd - 1)
5220 E1000_WRITE_FLUSH(hw);
5223 PMD_REGISTER_DRIVER(pmd_igb_drv, igb);
5224 DRIVER_REGISTER_PCI_TABLE(igb, pci_id_igb_map);
5225 PMD_REGISTER_DRIVER(pmd_igbvf_drv, igbvf);
5226 DRIVER_REGISTER_PCI_TABLE(igbvf, pci_id_igbvf_map);