1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static void eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .rx_queue_count = eth_igb_rx_queue_count,
384 .rx_descriptor_done = eth_igb_rx_descriptor_done,
385 .rx_descriptor_status = eth_igb_rx_descriptor_status,
386 .tx_descriptor_status = eth_igb_tx_descriptor_status,
387 .tx_queue_setup = eth_igb_tx_queue_setup,
388 .tx_queue_release = eth_igb_tx_queue_release,
389 .tx_done_cleanup = eth_igb_tx_done_cleanup,
390 .dev_led_on = eth_igb_led_on,
391 .dev_led_off = eth_igb_led_off,
392 .flow_ctrl_get = eth_igb_flow_ctrl_get,
393 .flow_ctrl_set = eth_igb_flow_ctrl_set,
394 .mac_addr_add = eth_igb_rar_set,
395 .mac_addr_remove = eth_igb_rar_clear,
396 .mac_addr_set = eth_igb_default_mac_addr_set,
397 .reta_update = eth_igb_rss_reta_update,
398 .reta_query = eth_igb_rss_reta_query,
399 .rss_hash_update = eth_igb_rss_hash_update,
400 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
401 .filter_ctrl = eth_igb_filter_ctrl,
402 .set_mc_addr_list = eth_igb_set_mc_addr_list,
403 .rxq_info_get = igb_rxq_info_get,
404 .txq_info_get = igb_txq_info_get,
405 .timesync_enable = igb_timesync_enable,
406 .timesync_disable = igb_timesync_disable,
407 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
408 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
409 .get_reg = eth_igb_get_regs,
410 .get_eeprom_length = eth_igb_get_eeprom_length,
411 .get_eeprom = eth_igb_get_eeprom,
412 .set_eeprom = eth_igb_set_eeprom,
413 .get_module_info = eth_igb_get_module_info,
414 .get_module_eeprom = eth_igb_get_module_eeprom,
415 .timesync_adjust_time = igb_timesync_adjust_time,
416 .timesync_read_time = igb_timesync_read_time,
417 .timesync_write_time = igb_timesync_write_time,
421 * dev_ops for virtual function, bare necessities for basic vf
422 * operation have been implemented
424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
425 .dev_configure = igbvf_dev_configure,
426 .dev_start = igbvf_dev_start,
427 .dev_stop = igbvf_dev_stop,
428 .dev_close = igbvf_dev_close,
429 .promiscuous_enable = igbvf_promiscuous_enable,
430 .promiscuous_disable = igbvf_promiscuous_disable,
431 .allmulticast_enable = igbvf_allmulticast_enable,
432 .allmulticast_disable = igbvf_allmulticast_disable,
433 .link_update = eth_igb_link_update,
434 .stats_get = eth_igbvf_stats_get,
435 .xstats_get = eth_igbvf_xstats_get,
436 .xstats_get_names = eth_igbvf_xstats_get_names,
437 .stats_reset = eth_igbvf_stats_reset,
438 .xstats_reset = eth_igbvf_stats_reset,
439 .vlan_filter_set = igbvf_vlan_filter_set,
440 .dev_infos_get = eth_igbvf_infos_get,
441 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
442 .rx_queue_setup = eth_igb_rx_queue_setup,
443 .rx_queue_release = eth_igb_rx_queue_release,
444 .rx_descriptor_done = eth_igb_rx_descriptor_done,
445 .rx_descriptor_status = eth_igb_rx_descriptor_status,
446 .tx_descriptor_status = eth_igb_tx_descriptor_status,
447 .tx_queue_setup = eth_igb_tx_queue_setup,
448 .tx_queue_release = eth_igb_tx_queue_release,
449 .set_mc_addr_list = eth_igb_set_mc_addr_list,
450 .rxq_info_get = igb_rxq_info_get,
451 .txq_info_get = igb_txq_info_get,
452 .mac_addr_set = igbvf_default_mac_addr_set,
453 .get_reg = igbvf_get_regs,
456 /* store statistics names and its offset in stats structure */
457 struct rte_igb_xstats_name_off {
458 char name[RTE_ETH_XSTATS_NAME_SIZE];
462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
463 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
464 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
465 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
466 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
467 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
468 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
469 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
471 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
472 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
473 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
474 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
475 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
476 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
477 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
478 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
479 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
480 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
481 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
484 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
485 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
486 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
487 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
489 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
491 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
492 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
493 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
494 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
495 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
496 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
497 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
498 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
499 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
500 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
501 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
502 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
503 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
504 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
505 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
506 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
507 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
508 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
510 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
512 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
513 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
514 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
515 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
516 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
517 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
518 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
520 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
524 sizeof(rte_igb_stats_strings[0]))
526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
527 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
528 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
529 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
530 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
531 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
535 sizeof(rte_igbvf_stats_strings[0]))
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
548 if (rte_intr_allow_others(intr_handle) &&
549 dev->data->dev_conf.intr_conf.lsc != 0) {
550 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
553 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
554 E1000_WRITE_FLUSH(hw);
558 igb_intr_disable(struct rte_eth_dev *dev)
560 struct e1000_hw *hw =
561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
565 if (rte_intr_allow_others(intr_handle) &&
566 dev->data->dev_conf.intr_conf.lsc != 0) {
567 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
570 E1000_WRITE_REG(hw, E1000_IMC, ~0);
571 E1000_WRITE_FLUSH(hw);
575 igbvf_intr_enable(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 /* only for mailbox */
581 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
582 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
583 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
584 E1000_WRITE_FLUSH(hw);
587 /* only for mailbox now. If RX/TX needed, should extend this function. */
589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
594 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
595 tmp |= E1000_VTIVAR_VALID;
596 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
602 struct e1000_hw *hw =
603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 /* Configure VF other cause ivar */
606 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
609 static inline int32_t
610 igb_pf_reset_hw(struct e1000_hw *hw)
615 status = e1000_reset_hw(hw);
617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
618 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
619 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
620 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
621 E1000_WRITE_FLUSH(hw);
627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
629 struct e1000_hw *hw =
630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->device_id = pci_dev->id.device_id;
635 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
636 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
638 e1000_set_mac_type(hw);
640 /* need to check if it is a vf device below */
644 igb_reset_swfw_lock(struct e1000_hw *hw)
649 * Do mac ops initialization manually here, since we will need
650 * some function pointers set by this call.
652 ret_val = e1000_init_mac_params(hw);
657 * SMBI lock should not fail in this early stage. If this is the case,
658 * it is due to an improper exit of the application.
659 * So force the release of the faulty lock.
661 if (e1000_get_hw_semaphore_generic(hw) < 0) {
662 PMD_DRV_LOG(DEBUG, "SMBI lock released");
664 e1000_put_hw_semaphore_generic(hw);
666 if (hw->mac.ops.acquire_swfw_sync != NULL) {
670 * Phy lock should not fail in this early stage. If this is the case,
671 * it is due to an improper exit of the application.
672 * So force the release of the faulty lock.
674 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
675 if (hw->bus.func > E1000_FUNC_1)
677 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
678 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
681 hw->mac.ops.release_swfw_sync(hw, mask);
684 * This one is more tricky since it is common to all ports; but
685 * swfw_sync retries last long enough (1s) to be almost sure that if
686 * lock can not be taken it is due to an improper lock of the
689 mask = E1000_SWFW_EEP_SM;
690 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
693 hw->mac.ops.release_swfw_sync(hw, mask);
696 return E1000_SUCCESS;
699 /* Remove all ntuple filters of the device */
700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_5tuple_filter *p_5tuple;
705 struct e1000_2tuple_filter *p_2tuple;
707 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
708 TAILQ_REMOVE(&filter_info->fivetuple_list,
712 filter_info->fivetuple_mask = 0;
713 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
714 TAILQ_REMOVE(&filter_info->twotuple_list,
718 filter_info->twotuple_mask = 0;
723 /* Remove all flex filters of the device */
724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
726 struct e1000_filter_info *filter_info =
727 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
728 struct e1000_flex_filter *p_flex;
730 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
731 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
734 filter_info->flex_mask = 0;
740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
746 struct e1000_vfta * shadow_vfta =
747 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_adapter *adapter =
751 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
755 eth_dev->dev_ops = ð_igb_ops;
756 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
757 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
758 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
760 /* for secondary processes, we don't initialise any further as primary
761 * has already done this work. Only check we don't need a different
763 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
764 if (eth_dev->data->scattered_rx)
765 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
769 rte_eth_copy_pci_info(eth_dev, pci_dev);
771 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
773 igb_identify_hardware(eth_dev, pci_dev);
774 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 e1000_get_bus_info(hw);
781 /* Reset any pending lock */
782 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 /* Finish initialization */
788 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
794 hw->phy.autoneg_wait_to_complete = 0;
795 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
798 if (hw->phy.media_type == e1000_media_type_copper) {
799 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
800 hw->phy.disable_polarity_correction = 0;
801 hw->phy.ms_type = e1000_ms_hw_default;
805 * Start from a known state, this is important in reading the nvm
810 /* Make sure we have a good EEPROM before we read from it */
811 if (e1000_validate_nvm_checksum(hw) < 0) {
813 * Some PCI-E parts fail the first check due to
814 * the link being in sleep state, call it again,
815 * if it fails a second time its a real issue.
817 if (e1000_validate_nvm_checksum(hw) < 0) {
818 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
824 /* Read the permanent MAC address out of the EEPROM */
825 if (e1000_read_mac_addr(hw) != 0) {
826 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 /* Allocate memory for storing MAC addresses */
832 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
833 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
834 if (eth_dev->data->mac_addrs == NULL) {
835 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
836 "store MAC addresses",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 /* Copy the permanent MAC address */
843 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
844 ð_dev->data->mac_addrs[0]);
846 /* initialize the vfta */
847 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
849 /* Now initialize the hardware */
850 if (igb_hardware_init(hw) != 0) {
851 PMD_INIT_LOG(ERR, "Hardware initialization failed");
852 rte_free(eth_dev->data->mac_addrs);
853 eth_dev->data->mac_addrs = NULL;
857 hw->mac.get_link_status = 1;
858 adapter->stopped = 0;
860 /* Indicate SOL/IDER usage */
861 if (e1000_check_reset_block(hw) < 0) {
862 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
866 /* initialize PF if max_vfs not zero */
867 igb_pf_host_init(eth_dev);
869 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
870 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
871 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
873 E1000_WRITE_FLUSH(hw);
875 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
876 eth_dev->data->port_id, pci_dev->id.vendor_id,
877 pci_dev->id.device_id);
879 rte_intr_callback_register(&pci_dev->intr_handle,
880 eth_igb_interrupt_handler,
883 /* enable uio/vfio intr/eventfd mapping */
884 rte_intr_enable(&pci_dev->intr_handle);
886 /* enable support intr */
887 igb_intr_enable(eth_dev);
889 /* initialize filter info */
890 memset(filter_info, 0,
891 sizeof(struct e1000_filter_info));
893 TAILQ_INIT(&filter_info->flex_list);
894 TAILQ_INIT(&filter_info->twotuple_list);
895 TAILQ_INIT(&filter_info->fivetuple_list);
897 TAILQ_INIT(&igb_filter_ntuple_list);
898 TAILQ_INIT(&igb_filter_ethertype_list);
899 TAILQ_INIT(&igb_filter_syn_list);
900 TAILQ_INIT(&igb_filter_flex_list);
901 TAILQ_INIT(&igb_filter_rss_list);
902 TAILQ_INIT(&igb_flow_list);
907 igb_hw_control_release(hw);
913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
915 struct rte_pci_device *pci_dev;
916 struct rte_intr_handle *intr_handle;
918 struct e1000_adapter *adapter =
919 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
920 struct e1000_filter_info *filter_info =
921 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
923 PMD_INIT_FUNC_TRACE();
925 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
928 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
930 intr_handle = &pci_dev->intr_handle;
932 if (adapter->stopped == 0)
933 eth_igb_close(eth_dev);
935 eth_dev->dev_ops = NULL;
936 eth_dev->rx_pkt_burst = NULL;
937 eth_dev->tx_pkt_burst = NULL;
939 /* Reset any pending lock */
940 igb_reset_swfw_lock(hw);
942 /* uninitialize PF if max_vfs not zero */
943 igb_pf_host_uninit(eth_dev);
945 /* disable uio intr before callback unregister */
946 rte_intr_disable(intr_handle);
947 rte_intr_callback_unregister(intr_handle,
948 eth_igb_interrupt_handler, eth_dev);
950 /* clear the SYN filter info */
951 filter_info->syn_info = 0;
953 /* clear the ethertype filters info */
954 filter_info->ethertype_mask = 0;
955 memset(filter_info->ethertype_filters, 0,
956 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
958 /* clear the rss filter info */
959 memset(&filter_info->rss_info, 0,
960 sizeof(struct igb_rte_flow_rss_conf));
962 /* remove all ntuple filters of the device */
963 igb_ntuple_filter_uninit(eth_dev);
965 /* remove all flex filters of the device */
966 igb_flex_filter_uninit(eth_dev);
968 /* clear all the filters list */
969 igb_filterlist_flush(eth_dev);
975 * Virtual Function device init
978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
980 struct rte_pci_device *pci_dev;
981 struct rte_intr_handle *intr_handle;
982 struct e1000_adapter *adapter =
983 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
984 struct e1000_hw *hw =
985 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
987 struct rte_ether_addr *perm_addr =
988 (struct rte_ether_addr *)hw->mac.perm_addr;
990 PMD_INIT_FUNC_TRACE();
992 eth_dev->dev_ops = &igbvf_eth_dev_ops;
993 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
994 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
995 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
997 /* for secondary processes, we don't initialise any further as primary
998 * has already done this work. Only check we don't need a different
1000 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001 if (eth_dev->data->scattered_rx)
1002 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1006 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007 rte_eth_copy_pci_info(eth_dev, pci_dev);
1009 hw->device_id = pci_dev->id.device_id;
1010 hw->vendor_id = pci_dev->id.vendor_id;
1011 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012 adapter->stopped = 0;
1014 /* Initialize the shared code (base driver) */
1015 diag = e1000_setup_init_funcs(hw, TRUE);
1017 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1022 /* init_mailbox_params */
1023 hw->mbx.ops.init_params(hw);
1025 /* Disable the interrupts for VF */
1026 igbvf_intr_disable(hw);
1028 diag = hw->mac.ops.reset_hw(hw);
1030 /* Allocate memory for storing MAC addresses */
1031 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032 hw->mac.rar_entry_count, 0);
1033 if (eth_dev->data->mac_addrs == NULL) {
1035 "Failed to allocate %d bytes needed to store MAC "
1037 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1041 /* Generate a random MAC address, if none was assigned by PF. */
1042 if (rte_is_zero_ether_addr(perm_addr)) {
1043 rte_eth_random_addr(perm_addr->addr_bytes);
1044 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046 "%02x:%02x:%02x:%02x:%02x:%02x",
1047 perm_addr->addr_bytes[0],
1048 perm_addr->addr_bytes[1],
1049 perm_addr->addr_bytes[2],
1050 perm_addr->addr_bytes[3],
1051 perm_addr->addr_bytes[4],
1052 perm_addr->addr_bytes[5]);
1055 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1057 rte_free(eth_dev->data->mac_addrs);
1058 eth_dev->data->mac_addrs = NULL;
1061 /* Copy the permanent MAC address */
1062 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063 ð_dev->data->mac_addrs[0]);
1065 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1067 eth_dev->data->port_id, pci_dev->id.vendor_id,
1068 pci_dev->id.device_id, "igb_mac_82576_vf");
1070 intr_handle = &pci_dev->intr_handle;
1071 rte_intr_callback_register(intr_handle,
1072 eth_igbvf_interrupt_handler, eth_dev);
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1080 struct e1000_adapter *adapter =
1081 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1084 PMD_INIT_FUNC_TRACE();
1086 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1089 if (adapter->stopped == 0)
1090 igbvf_dev_close(eth_dev);
1092 eth_dev->dev_ops = NULL;
1093 eth_dev->rx_pkt_burst = NULL;
1094 eth_dev->tx_pkt_burst = NULL;
1096 /* disable uio intr before callback unregister */
1097 rte_intr_disable(&pci_dev->intr_handle);
1098 rte_intr_callback_unregister(&pci_dev->intr_handle,
1099 eth_igbvf_interrupt_handler,
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106 struct rte_pci_device *pci_dev)
1108 return rte_eth_dev_pci_generic_probe(pci_dev,
1109 sizeof(struct e1000_adapter), eth_igb_dev_init);
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1114 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1117 static struct rte_pci_driver rte_igb_pmd = {
1118 .id_table = pci_id_igb_map,
1119 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1120 .probe = eth_igb_pci_probe,
1121 .remove = eth_igb_pci_remove,
1125 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1126 struct rte_pci_device *pci_dev)
1128 return rte_eth_dev_pci_generic_probe(pci_dev,
1129 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1132 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1134 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1138 * virtual function driver struct
1140 static struct rte_pci_driver rte_igbvf_pmd = {
1141 .id_table = pci_id_igbvf_map,
1142 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1143 .probe = eth_igbvf_pci_probe,
1144 .remove = eth_igbvf_pci_remove,
1148 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1150 struct e1000_hw *hw =
1151 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1153 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1154 rctl |= E1000_RCTL_VFE;
1155 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1159 igb_check_mq_mode(struct rte_eth_dev *dev)
1161 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1162 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1163 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1164 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1166 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1167 tx_mq_mode == ETH_MQ_TX_DCB ||
1168 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1169 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1172 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1173 /* Check multi-queue mode.
1174 * To no break software we accept ETH_MQ_RX_NONE as this might
1175 * be used to turn off VLAN filter.
1178 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1179 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1180 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1181 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1183 /* Only support one queue on VFs.
1184 * RSS together with SRIOV is not supported.
1186 PMD_INIT_LOG(ERR, "SRIOV is active,"
1187 " wrong mq_mode rx %d.",
1191 /* TX mode is not used here, so mode might be ignored.*/
1192 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1193 /* SRIOV only works in VMDq enable mode */
1194 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1195 " TX mode %d is not supported. "
1196 " Driver will behave as %d mode.",
1197 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1200 /* check valid queue number */
1201 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1202 PMD_INIT_LOG(ERR, "SRIOV is active,"
1203 " only support one queue on VFs.");
1207 /* To no break software that set invalid mode, only display
1208 * warning if invalid mode is used.
1210 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1211 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1212 rx_mq_mode != ETH_MQ_RX_RSS) {
1213 /* RSS together with VMDq not supported*/
1214 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1219 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1220 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1221 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1222 " Due to txmode is meaningless in this"
1223 " driver, just ignore.",
1231 eth_igb_configure(struct rte_eth_dev *dev)
1233 struct e1000_interrupt *intr =
1234 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1237 PMD_INIT_FUNC_TRACE();
1239 /* multipe queue mode checking */
1240 ret = igb_check_mq_mode(dev);
1242 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1247 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1248 PMD_INIT_FUNC_TRACE();
1254 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1257 struct e1000_hw *hw =
1258 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259 uint32_t tctl, rctl;
1261 tctl = E1000_READ_REG(hw, E1000_TCTL);
1262 rctl = E1000_READ_REG(hw, E1000_RCTL);
1266 tctl |= E1000_TCTL_EN;
1267 rctl |= E1000_RCTL_EN;
1270 tctl &= ~E1000_TCTL_EN;
1271 rctl &= ~E1000_RCTL_EN;
1273 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1274 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1275 E1000_WRITE_FLUSH(hw);
1279 eth_igb_start(struct rte_eth_dev *dev)
1281 struct e1000_hw *hw =
1282 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283 struct e1000_adapter *adapter =
1284 E1000_DEV_PRIVATE(dev->data->dev_private);
1285 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1286 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288 uint32_t intr_vector = 0;
1294 PMD_INIT_FUNC_TRACE();
1296 /* disable uio/vfio intr/eventfd mapping */
1297 rte_intr_disable(intr_handle);
1299 /* Power up the phy. Needed to make the link go Up */
1300 eth_igb_dev_set_link_up(dev);
1303 * Packet Buffer Allocation (PBA)
1304 * Writing PBA sets the receive portion of the buffer
1305 * the remainder is used for the transmit buffer.
1307 if (hw->mac.type == e1000_82575) {
1310 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1311 E1000_WRITE_REG(hw, E1000_PBA, pba);
1314 /* Put the address into the Receive Address Array */
1315 e1000_rar_set(hw, hw->mac.addr, 0);
1317 /* Initialize the hardware */
1318 if (igb_hardware_init(hw)) {
1319 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1322 adapter->stopped = 0;
1324 E1000_WRITE_REG(hw, E1000_VET,
1325 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1327 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1329 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1330 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1331 E1000_WRITE_FLUSH(hw);
1333 /* configure PF module if SRIOV enabled */
1334 igb_pf_host_configure(dev);
1336 /* check and configure queue intr-vector mapping */
1337 if ((rte_intr_cap_multiple(intr_handle) ||
1338 !RTE_ETH_DEV_SRIOV(dev).active) &&
1339 dev->data->dev_conf.intr_conf.rxq != 0) {
1340 intr_vector = dev->data->nb_rx_queues;
1341 if (rte_intr_efd_enable(intr_handle, intr_vector))
1345 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1346 intr_handle->intr_vec =
1347 rte_zmalloc("intr_vec",
1348 dev->data->nb_rx_queues * sizeof(int), 0);
1349 if (intr_handle->intr_vec == NULL) {
1350 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1351 " intr_vec", dev->data->nb_rx_queues);
1356 /* confiugre msix for rx interrupt */
1357 eth_igb_configure_msix_intr(dev);
1359 /* Configure for OS presence */
1360 igb_init_manageability(hw);
1362 eth_igb_tx_init(dev);
1364 /* This can fail when allocating mbufs for descriptor rings */
1365 ret = eth_igb_rx_init(dev);
1367 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1368 igb_dev_clear_queues(dev);
1372 e1000_clear_hw_cntrs_base_generic(hw);
1375 * VLAN Offload Settings
1377 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1378 ETH_VLAN_EXTEND_MASK;
1379 ret = eth_igb_vlan_offload_set(dev, mask);
1381 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1382 igb_dev_clear_queues(dev);
1386 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1387 /* Enable VLAN filter since VMDq always use VLAN filter */
1388 igb_vmdq_vlan_hw_filter_enable(dev);
1391 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1392 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1393 (hw->mac.type == e1000_i211)) {
1394 /* Configure EITR with the maximum possible value (0xFFFF) */
1395 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1398 /* Setup link speed and duplex */
1399 speeds = &dev->data->dev_conf.link_speeds;
1400 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1401 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1402 hw->mac.autoneg = 1;
1405 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1408 hw->phy.autoneg_advertised = 0;
1410 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1411 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1412 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1414 goto error_invalid_config;
1416 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1417 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1420 if (*speeds & ETH_LINK_SPEED_10M) {
1421 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1424 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1425 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1428 if (*speeds & ETH_LINK_SPEED_100M) {
1429 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1432 if (*speeds & ETH_LINK_SPEED_1G) {
1433 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1436 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1437 goto error_invalid_config;
1439 /* Set/reset the mac.autoneg based on the link speed,
1443 hw->mac.autoneg = 0;
1444 hw->mac.forced_speed_duplex =
1445 hw->phy.autoneg_advertised;
1447 hw->mac.autoneg = 1;
1451 e1000_setup_link(hw);
1453 if (rte_intr_allow_others(intr_handle)) {
1454 /* check if lsc interrupt is enabled */
1455 if (dev->data->dev_conf.intr_conf.lsc != 0)
1456 eth_igb_lsc_interrupt_setup(dev, TRUE);
1458 eth_igb_lsc_interrupt_setup(dev, FALSE);
1460 rte_intr_callback_unregister(intr_handle,
1461 eth_igb_interrupt_handler,
1463 if (dev->data->dev_conf.intr_conf.lsc != 0)
1464 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1465 " no intr multiplex");
1468 /* check if rxq interrupt is enabled */
1469 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1470 rte_intr_dp_is_en(intr_handle))
1471 eth_igb_rxq_interrupt_setup(dev);
1473 /* enable uio/vfio intr/eventfd mapping */
1474 rte_intr_enable(intr_handle);
1476 /* resume enabled intr since hw reset */
1477 igb_intr_enable(dev);
1479 /* restore all types filter */
1480 igb_filter_restore(dev);
1482 eth_igb_rxtx_control(dev, true);
1483 eth_igb_link_update(dev, 0);
1485 PMD_INIT_LOG(DEBUG, "<<");
1489 error_invalid_config:
1490 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1491 dev->data->dev_conf.link_speeds, dev->data->port_id);
1492 igb_dev_clear_queues(dev);
1496 /*********************************************************************
1498 * This routine disables all traffic on the adapter by issuing a
1499 * global reset on the MAC.
1501 **********************************************************************/
1503 eth_igb_stop(struct rte_eth_dev *dev)
1505 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507 struct rte_eth_link link;
1508 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1510 eth_igb_rxtx_control(dev, false);
1512 igb_intr_disable(dev);
1514 /* disable intr eventfd mapping */
1515 rte_intr_disable(intr_handle);
1517 igb_pf_reset_hw(hw);
1518 E1000_WRITE_REG(hw, E1000_WUC, 0);
1520 /* Set bit for Go Link disconnect */
1521 if (hw->mac.type >= e1000_82580) {
1524 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1525 phpm_reg |= E1000_82580_PM_GO_LINKD;
1526 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1529 /* Power down the phy. Needed to make the link go Down */
1530 eth_igb_dev_set_link_down(dev);
1532 igb_dev_clear_queues(dev);
1534 /* clear the recorded link status */
1535 memset(&link, 0, sizeof(link));
1536 rte_eth_linkstatus_set(dev, &link);
1538 if (!rte_intr_allow_others(intr_handle))
1539 /* resume to the default handler */
1540 rte_intr_callback_register(intr_handle,
1541 eth_igb_interrupt_handler,
1544 /* Clean datapath event and queue/vec mapping */
1545 rte_intr_efd_disable(intr_handle);
1546 if (intr_handle->intr_vec != NULL) {
1547 rte_free(intr_handle->intr_vec);
1548 intr_handle->intr_vec = NULL;
1553 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1555 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557 if (hw->phy.media_type == e1000_media_type_copper)
1558 e1000_power_up_phy(hw);
1560 e1000_power_up_fiber_serdes_link(hw);
1566 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1568 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570 if (hw->phy.media_type == e1000_media_type_copper)
1571 e1000_power_down_phy(hw);
1573 e1000_shutdown_fiber_serdes_link(hw);
1579 eth_igb_close(struct rte_eth_dev *dev)
1581 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 struct e1000_adapter *adapter =
1583 E1000_DEV_PRIVATE(dev->data->dev_private);
1584 struct rte_eth_link link;
1585 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1589 adapter->stopped = 1;
1591 e1000_phy_hw_reset(hw);
1592 igb_release_manageability(hw);
1593 igb_hw_control_release(hw);
1595 /* Clear bit for Go Link disconnect */
1596 if (hw->mac.type >= e1000_82580) {
1599 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1600 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1601 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1604 igb_dev_free_queues(dev);
1606 if (intr_handle->intr_vec) {
1607 rte_free(intr_handle->intr_vec);
1608 intr_handle->intr_vec = NULL;
1611 memset(&link, 0, sizeof(link));
1612 rte_eth_linkstatus_set(dev, &link);
1619 eth_igb_reset(struct rte_eth_dev *dev)
1623 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1624 * its VF to make them align with it. The detailed notification
1625 * mechanism is PMD specific and is currently not implemented.
1626 * To avoid unexpected behavior in VF, currently reset of PF with
1627 * SR-IOV activation is not supported. It might be supported later.
1629 if (dev->data->sriov.active)
1632 ret = eth_igb_dev_uninit(dev);
1636 ret = eth_igb_dev_init(dev);
1643 igb_get_rx_buffer_size(struct e1000_hw *hw)
1645 uint32_t rx_buf_size;
1646 if (hw->mac.type == e1000_82576) {
1647 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1648 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1649 /* PBS needs to be translated according to a lookup table */
1650 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1651 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1652 rx_buf_size = (rx_buf_size << 10);
1653 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1654 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1656 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1662 /*********************************************************************
1664 * Initialize the hardware
1666 **********************************************************************/
1668 igb_hardware_init(struct e1000_hw *hw)
1670 uint32_t rx_buf_size;
1673 /* Let the firmware know the OS is in control */
1674 igb_hw_control_acquire(hw);
1677 * These parameters control the automatic generation (Tx) and
1678 * response (Rx) to Ethernet PAUSE frames.
1679 * - High water mark should allow for at least two standard size (1518)
1680 * frames to be received after sending an XOFF.
1681 * - Low water mark works best when it is very near the high water mark.
1682 * This allows the receiver to restart by sending XON when it has
1683 * drained a bit. Here we use an arbitrary value of 1500 which will
1684 * restart after one full frame is pulled from the buffer. There
1685 * could be several smaller frames in the buffer and if so they will
1686 * not trigger the XON until their total number reduces the buffer
1688 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1690 rx_buf_size = igb_get_rx_buffer_size(hw);
1692 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1693 hw->fc.low_water = hw->fc.high_water - 1500;
1694 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1695 hw->fc.send_xon = 1;
1697 /* Set Flow control, use the tunable location if sane */
1698 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1699 hw->fc.requested_mode = igb_fc_setting;
1701 hw->fc.requested_mode = e1000_fc_none;
1703 /* Issue a global reset */
1704 igb_pf_reset_hw(hw);
1705 E1000_WRITE_REG(hw, E1000_WUC, 0);
1707 diag = e1000_init_hw(hw);
1711 E1000_WRITE_REG(hw, E1000_VET,
1712 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1713 e1000_get_phy_info(hw);
1714 e1000_check_for_link(hw);
1719 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1721 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1725 uint64_t old_gprc = stats->gprc;
1726 uint64_t old_gptc = stats->gptc;
1727 uint64_t old_tpr = stats->tpr;
1728 uint64_t old_tpt = stats->tpt;
1729 uint64_t old_rpthc = stats->rpthc;
1730 uint64_t old_hgptc = stats->hgptc;
1732 if(hw->phy.media_type == e1000_media_type_copper ||
1733 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1735 E1000_READ_REG(hw,E1000_SYMERRS);
1736 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1739 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1740 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1741 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1742 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1744 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1745 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1746 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1747 stats->dc += E1000_READ_REG(hw, E1000_DC);
1748 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1749 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1750 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1752 ** For watchdog management we need to know if we have been
1753 ** paused during the last interval, so capture that here.
1755 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1756 stats->xoffrxc += pause_frames;
1757 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1758 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1759 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1760 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1761 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1762 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1763 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1764 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1765 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1766 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1767 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1768 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1770 /* For the 64-bit byte counters the low dword must be read first. */
1771 /* Both registers clear on the read of the high dword */
1773 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1774 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1775 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1776 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1777 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1778 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1779 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1781 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1782 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1783 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1784 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1785 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1787 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1788 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1790 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1791 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1792 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1793 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1794 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1795 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1797 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1798 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1799 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1800 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1801 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1802 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1803 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1804 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1806 /* Interrupt Counts */
1808 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1809 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1810 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1811 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1812 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1813 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1814 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1815 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1816 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1818 /* Host to Card Statistics */
1820 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1821 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1822 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1823 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1824 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1825 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1826 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1827 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1828 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1829 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1830 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1831 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1832 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1833 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1834 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1835 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1837 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1838 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1839 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1840 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1841 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1842 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1846 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1848 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849 struct e1000_hw_stats *stats =
1850 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1852 igb_read_stats_registers(hw, stats);
1854 if (rte_stats == NULL)
1858 rte_stats->imissed = stats->mpc;
1859 rte_stats->ierrors = stats->crcerrs +
1860 stats->rlec + stats->ruc + stats->roc +
1861 stats->rxerrc + stats->algnerrc + stats->cexterr;
1864 rte_stats->oerrors = stats->ecol + stats->latecol;
1866 rte_stats->ipackets = stats->gprc;
1867 rte_stats->opackets = stats->gptc;
1868 rte_stats->ibytes = stats->gorc;
1869 rte_stats->obytes = stats->gotc;
1874 eth_igb_stats_reset(struct rte_eth_dev *dev)
1876 struct e1000_hw_stats *hw_stats =
1877 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879 /* HW registers are cleared on read */
1880 eth_igb_stats_get(dev, NULL);
1882 /* Reset software totals */
1883 memset(hw_stats, 0, sizeof(*hw_stats));
1887 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1889 struct e1000_hw_stats *stats =
1890 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1892 /* HW registers are cleared on read */
1893 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1895 /* Reset software totals */
1896 memset(stats, 0, sizeof(*stats));
1899 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1900 struct rte_eth_xstat_name *xstats_names,
1901 __rte_unused unsigned int size)
1905 if (xstats_names == NULL)
1906 return IGB_NB_XSTATS;
1908 /* Note: limit checked in rte_eth_xstats_names() */
1910 for (i = 0; i < IGB_NB_XSTATS; i++) {
1911 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1912 sizeof(xstats_names[i].name));
1915 return IGB_NB_XSTATS;
1918 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1919 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1925 if (xstats_names == NULL)
1926 return IGB_NB_XSTATS;
1928 for (i = 0; i < IGB_NB_XSTATS; i++)
1929 strlcpy(xstats_names[i].name,
1930 rte_igb_stats_strings[i].name,
1931 sizeof(xstats_names[i].name));
1933 return IGB_NB_XSTATS;
1936 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1938 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1941 for (i = 0; i < limit; i++) {
1942 if (ids[i] >= IGB_NB_XSTATS) {
1943 PMD_INIT_LOG(ERR, "id value isn't valid");
1946 strcpy(xstats_names[i].name,
1947 xstats_names_copy[ids[i]].name);
1954 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1957 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958 struct e1000_hw_stats *hw_stats =
1959 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1962 if (n < IGB_NB_XSTATS)
1963 return IGB_NB_XSTATS;
1965 igb_read_stats_registers(hw, hw_stats);
1967 /* If this is a reset xstats is NULL, and we have cleared the
1968 * registers by reading them.
1973 /* Extended stats */
1974 for (i = 0; i < IGB_NB_XSTATS; i++) {
1976 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1977 rte_igb_stats_strings[i].offset);
1980 return IGB_NB_XSTATS;
1984 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1985 uint64_t *values, unsigned int n)
1990 struct e1000_hw *hw =
1991 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992 struct e1000_hw_stats *hw_stats =
1993 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1995 if (n < IGB_NB_XSTATS)
1996 return IGB_NB_XSTATS;
1998 igb_read_stats_registers(hw, hw_stats);
2000 /* If this is a reset xstats is NULL, and we have cleared the
2001 * registers by reading them.
2006 /* Extended stats */
2007 for (i = 0; i < IGB_NB_XSTATS; i++)
2008 values[i] = *(uint64_t *)(((char *)hw_stats) +
2009 rte_igb_stats_strings[i].offset);
2011 return IGB_NB_XSTATS;
2014 uint64_t values_copy[IGB_NB_XSTATS];
2016 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2019 for (i = 0; i < n; i++) {
2020 if (ids[i] >= IGB_NB_XSTATS) {
2021 PMD_INIT_LOG(ERR, "id value isn't valid");
2024 values[i] = values_copy[ids[i]];
2031 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2033 /* Good Rx packets, include VF loopback */
2034 UPDATE_VF_STAT(E1000_VFGPRC,
2035 hw_stats->last_gprc, hw_stats->gprc);
2037 /* Good Rx octets, include VF loopback */
2038 UPDATE_VF_STAT(E1000_VFGORC,
2039 hw_stats->last_gorc, hw_stats->gorc);
2041 /* Good Tx packets, include VF loopback */
2042 UPDATE_VF_STAT(E1000_VFGPTC,
2043 hw_stats->last_gptc, hw_stats->gptc);
2045 /* Good Tx octets, include VF loopback */
2046 UPDATE_VF_STAT(E1000_VFGOTC,
2047 hw_stats->last_gotc, hw_stats->gotc);
2049 /* Rx Multicst packets */
2050 UPDATE_VF_STAT(E1000_VFMPRC,
2051 hw_stats->last_mprc, hw_stats->mprc);
2053 /* Good Rx loopback packets */
2054 UPDATE_VF_STAT(E1000_VFGPRLBC,
2055 hw_stats->last_gprlbc, hw_stats->gprlbc);
2057 /* Good Rx loopback octets */
2058 UPDATE_VF_STAT(E1000_VFGORLBC,
2059 hw_stats->last_gorlbc, hw_stats->gorlbc);
2061 /* Good Tx loopback packets */
2062 UPDATE_VF_STAT(E1000_VFGPTLBC,
2063 hw_stats->last_gptlbc, hw_stats->gptlbc);
2065 /* Good Tx loopback octets */
2066 UPDATE_VF_STAT(E1000_VFGOTLBC,
2067 hw_stats->last_gotlbc, hw_stats->gotlbc);
2070 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2071 struct rte_eth_xstat_name *xstats_names,
2072 __rte_unused unsigned limit)
2076 if (xstats_names != NULL)
2077 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2078 strlcpy(xstats_names[i].name,
2079 rte_igbvf_stats_strings[i].name,
2080 sizeof(xstats_names[i].name));
2082 return IGBVF_NB_XSTATS;
2086 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2089 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2091 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2094 if (n < IGBVF_NB_XSTATS)
2095 return IGBVF_NB_XSTATS;
2097 igbvf_read_stats_registers(hw, hw_stats);
2102 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2104 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2105 rte_igbvf_stats_strings[i].offset);
2108 return IGBVF_NB_XSTATS;
2112 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2114 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2116 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2118 igbvf_read_stats_registers(hw, hw_stats);
2120 if (rte_stats == NULL)
2123 rte_stats->ipackets = hw_stats->gprc;
2124 rte_stats->ibytes = hw_stats->gorc;
2125 rte_stats->opackets = hw_stats->gptc;
2126 rte_stats->obytes = hw_stats->gotc;
2131 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2133 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2134 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2136 /* Sync HW register to the last stats */
2137 eth_igbvf_stats_get(dev, NULL);
2139 /* reset HW current stats*/
2140 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2141 offsetof(struct e1000_vf_stats, gprc));
2145 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2148 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149 struct e1000_fw_version fw;
2152 e1000_get_fw_version(hw, &fw);
2154 switch (hw->mac.type) {
2157 if (!(e1000_get_flash_presence_i210(hw))) {
2158 ret = snprintf(fw_version, fw_size,
2160 fw.invm_major, fw.invm_minor,
2166 /* if option rom is valid, display its version too */
2168 ret = snprintf(fw_version, fw_size,
2169 "%d.%d, 0x%08x, %d.%d.%d",
2170 fw.eep_major, fw.eep_minor, fw.etrack_id,
2171 fw.or_major, fw.or_build, fw.or_patch);
2174 if (fw.etrack_id != 0X0000) {
2175 ret = snprintf(fw_version, fw_size,
2177 fw.eep_major, fw.eep_minor,
2180 ret = snprintf(fw_version, fw_size,
2182 fw.eep_major, fw.eep_minor,
2189 ret += 1; /* add the size of '\0' */
2190 if (fw_size < (u32)ret)
2197 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2199 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2202 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2203 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2204 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2205 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2206 dev_info->rx_queue_offload_capa;
2207 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2208 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2209 dev_info->tx_queue_offload_capa;
2211 switch (hw->mac.type) {
2213 dev_info->max_rx_queues = 4;
2214 dev_info->max_tx_queues = 4;
2215 dev_info->max_vmdq_pools = 0;
2219 dev_info->max_rx_queues = 16;
2220 dev_info->max_tx_queues = 16;
2221 dev_info->max_vmdq_pools = ETH_8_POOLS;
2222 dev_info->vmdq_queue_num = 16;
2226 dev_info->max_rx_queues = 8;
2227 dev_info->max_tx_queues = 8;
2228 dev_info->max_vmdq_pools = ETH_8_POOLS;
2229 dev_info->vmdq_queue_num = 8;
2233 dev_info->max_rx_queues = 8;
2234 dev_info->max_tx_queues = 8;
2235 dev_info->max_vmdq_pools = ETH_8_POOLS;
2236 dev_info->vmdq_queue_num = 8;
2240 dev_info->max_rx_queues = 8;
2241 dev_info->max_tx_queues = 8;
2245 dev_info->max_rx_queues = 4;
2246 dev_info->max_tx_queues = 4;
2247 dev_info->max_vmdq_pools = 0;
2251 dev_info->max_rx_queues = 2;
2252 dev_info->max_tx_queues = 2;
2253 dev_info->max_vmdq_pools = 0;
2257 /* Should not happen */
2260 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2261 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2262 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2264 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2266 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2267 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2268 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2270 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2275 dev_info->default_txconf = (struct rte_eth_txconf) {
2277 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2278 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2279 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2284 dev_info->rx_desc_lim = rx_desc_lim;
2285 dev_info->tx_desc_lim = tx_desc_lim;
2287 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2288 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2291 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2292 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2296 static const uint32_t *
2297 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2299 static const uint32_t ptypes[] = {
2300 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2303 RTE_PTYPE_L3_IPV4_EXT,
2305 RTE_PTYPE_L3_IPV6_EXT,
2309 RTE_PTYPE_TUNNEL_IP,
2310 RTE_PTYPE_INNER_L3_IPV6,
2311 RTE_PTYPE_INNER_L3_IPV6_EXT,
2312 RTE_PTYPE_INNER_L4_TCP,
2313 RTE_PTYPE_INNER_L4_UDP,
2317 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2318 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2324 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2326 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2329 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2330 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2331 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2332 DEV_TX_OFFLOAD_IPV4_CKSUM |
2333 DEV_TX_OFFLOAD_UDP_CKSUM |
2334 DEV_TX_OFFLOAD_TCP_CKSUM |
2335 DEV_TX_OFFLOAD_SCTP_CKSUM |
2336 DEV_TX_OFFLOAD_TCP_TSO;
2337 switch (hw->mac.type) {
2339 dev_info->max_rx_queues = 2;
2340 dev_info->max_tx_queues = 2;
2342 case e1000_vfadapt_i350:
2343 dev_info->max_rx_queues = 1;
2344 dev_info->max_tx_queues = 1;
2347 /* Should not happen */
2351 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2352 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2353 dev_info->rx_queue_offload_capa;
2354 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2355 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2356 dev_info->tx_queue_offload_capa;
2358 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2360 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2361 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2362 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2364 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2369 dev_info->default_txconf = (struct rte_eth_txconf) {
2371 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2372 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2373 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2378 dev_info->rx_desc_lim = rx_desc_lim;
2379 dev_info->tx_desc_lim = tx_desc_lim;
2382 /* return 0 means link status changed, -1 means not changed */
2384 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2386 struct e1000_hw *hw =
2387 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388 struct rte_eth_link link;
2389 int link_check, count;
2392 hw->mac.get_link_status = 1;
2394 /* possible wait-to-complete in up to 9 seconds */
2395 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2396 /* Read the real link status */
2397 switch (hw->phy.media_type) {
2398 case e1000_media_type_copper:
2399 /* Do the work to read phy */
2400 e1000_check_for_link(hw);
2401 link_check = !hw->mac.get_link_status;
2404 case e1000_media_type_fiber:
2405 e1000_check_for_link(hw);
2406 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2410 case e1000_media_type_internal_serdes:
2411 e1000_check_for_link(hw);
2412 link_check = hw->mac.serdes_has_link;
2415 /* VF device is type_unknown */
2416 case e1000_media_type_unknown:
2417 eth_igbvf_link_update(hw);
2418 link_check = !hw->mac.get_link_status;
2424 if (link_check || wait_to_complete == 0)
2426 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2428 memset(&link, 0, sizeof(link));
2430 /* Now we check if a transition has happened */
2432 uint16_t duplex, speed;
2433 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2434 link.link_duplex = (duplex == FULL_DUPLEX) ?
2435 ETH_LINK_FULL_DUPLEX :
2436 ETH_LINK_HALF_DUPLEX;
2437 link.link_speed = speed;
2438 link.link_status = ETH_LINK_UP;
2439 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2440 ETH_LINK_SPEED_FIXED);
2441 } else if (!link_check) {
2442 link.link_speed = 0;
2443 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2444 link.link_status = ETH_LINK_DOWN;
2445 link.link_autoneg = ETH_LINK_FIXED;
2448 return rte_eth_linkstatus_set(dev, &link);
2452 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2453 * For ASF and Pass Through versions of f/w this means
2454 * that the driver is loaded.
2457 igb_hw_control_acquire(struct e1000_hw *hw)
2461 /* Let firmware know the driver has taken over */
2462 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2463 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2467 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2468 * For ASF and Pass Through versions of f/w this means that the
2469 * driver is no longer loaded.
2472 igb_hw_control_release(struct e1000_hw *hw)
2476 /* Let firmware taken over control of h/w */
2477 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2478 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2479 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2483 * Bit of a misnomer, what this really means is
2484 * to enable OS management of the system... aka
2485 * to disable special hardware management features.
2488 igb_init_manageability(struct e1000_hw *hw)
2490 if (e1000_enable_mng_pass_thru(hw)) {
2491 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2492 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2494 /* disable hardware interception of ARP */
2495 manc &= ~(E1000_MANC_ARP_EN);
2497 /* enable receiving management packets to the host */
2498 manc |= E1000_MANC_EN_MNG2HOST;
2499 manc2h |= 1 << 5; /* Mng Port 623 */
2500 manc2h |= 1 << 6; /* Mng Port 664 */
2501 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2502 E1000_WRITE_REG(hw, E1000_MANC, manc);
2507 igb_release_manageability(struct e1000_hw *hw)
2509 if (e1000_enable_mng_pass_thru(hw)) {
2510 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2512 manc |= E1000_MANC_ARP_EN;
2513 manc &= ~E1000_MANC_EN_MNG2HOST;
2515 E1000_WRITE_REG(hw, E1000_MANC, manc);
2520 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2522 struct e1000_hw *hw =
2523 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 rctl = E1000_READ_REG(hw, E1000_RCTL);
2527 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2528 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2534 struct e1000_hw *hw =
2535 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538 rctl = E1000_READ_REG(hw, E1000_RCTL);
2539 rctl &= (~E1000_RCTL_UPE);
2540 if (dev->data->all_multicast == 1)
2541 rctl |= E1000_RCTL_MPE;
2543 rctl &= (~E1000_RCTL_MPE);
2544 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2548 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2550 struct e1000_hw *hw =
2551 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554 rctl = E1000_READ_REG(hw, E1000_RCTL);
2555 rctl |= E1000_RCTL_MPE;
2556 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2560 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2562 struct e1000_hw *hw =
2563 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566 if (dev->data->promiscuous == 1)
2567 return; /* must remain in all_multicast mode */
2568 rctl = E1000_READ_REG(hw, E1000_RCTL);
2569 rctl &= (~E1000_RCTL_MPE);
2570 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2574 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2576 struct e1000_hw *hw =
2577 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 struct e1000_vfta * shadow_vfta =
2579 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2584 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2585 E1000_VFTA_ENTRY_MASK);
2586 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2587 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2592 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2594 /* update local VFTA copy */
2595 shadow_vfta->vfta[vid_idx] = vfta;
2601 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2602 enum rte_vlan_type vlan_type,
2605 struct e1000_hw *hw =
2606 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2609 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2610 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2612 /* only outer TPID of double VLAN can be configured*/
2613 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2614 reg = E1000_READ_REG(hw, E1000_VET);
2615 reg = (reg & (~E1000_VET_VET_EXT)) |
2616 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2617 E1000_WRITE_REG(hw, E1000_VET, reg);
2622 /* all other TPID values are read-only*/
2623 PMD_DRV_LOG(ERR, "Not supported");
2629 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2631 struct e1000_hw *hw =
2632 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2635 /* Filter Table Disable */
2636 reg = E1000_READ_REG(hw, E1000_RCTL);
2637 reg &= ~E1000_RCTL_CFIEN;
2638 reg &= ~E1000_RCTL_VFE;
2639 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2643 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2645 struct e1000_hw *hw =
2646 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 struct e1000_vfta * shadow_vfta =
2648 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2652 /* Filter Table Enable, CFI not used for packet acceptance */
2653 reg = E1000_READ_REG(hw, E1000_RCTL);
2654 reg &= ~E1000_RCTL_CFIEN;
2655 reg |= E1000_RCTL_VFE;
2656 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2658 /* restore VFTA table */
2659 for (i = 0; i < IGB_VFTA_SIZE; i++)
2660 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2664 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2666 struct e1000_hw *hw =
2667 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670 /* VLAN Mode Disable */
2671 reg = E1000_READ_REG(hw, E1000_CTRL);
2672 reg &= ~E1000_CTRL_VME;
2673 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2677 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2679 struct e1000_hw *hw =
2680 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683 /* VLAN Mode Enable */
2684 reg = E1000_READ_REG(hw, E1000_CTRL);
2685 reg |= E1000_CTRL_VME;
2686 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2690 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2692 struct e1000_hw *hw =
2693 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696 /* CTRL_EXT: Extended VLAN */
2697 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2698 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2699 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2701 /* Update maximum packet length */
2702 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2703 E1000_WRITE_REG(hw, E1000_RLPML,
2704 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2709 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2711 struct e1000_hw *hw =
2712 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715 /* CTRL_EXT: Extended VLAN */
2716 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2717 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2718 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2720 /* Update maximum packet length */
2721 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2722 E1000_WRITE_REG(hw, E1000_RLPML,
2723 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2728 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2730 struct rte_eth_rxmode *rxmode;
2732 rxmode = &dev->data->dev_conf.rxmode;
2733 if(mask & ETH_VLAN_STRIP_MASK){
2734 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2735 igb_vlan_hw_strip_enable(dev);
2737 igb_vlan_hw_strip_disable(dev);
2740 if(mask & ETH_VLAN_FILTER_MASK){
2741 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2742 igb_vlan_hw_filter_enable(dev);
2744 igb_vlan_hw_filter_disable(dev);
2747 if(mask & ETH_VLAN_EXTEND_MASK){
2748 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2749 igb_vlan_hw_extend_enable(dev);
2751 igb_vlan_hw_extend_disable(dev);
2759 * It enables the interrupt mask and then enable the interrupt.
2762 * Pointer to struct rte_eth_dev.
2767 * - On success, zero.
2768 * - On failure, a negative value.
2771 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2773 struct e1000_interrupt *intr =
2774 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2777 intr->mask |= E1000_ICR_LSC;
2779 intr->mask &= ~E1000_ICR_LSC;
2784 /* It clears the interrupt causes and enables the interrupt.
2785 * It will be called once only during nic initialized.
2788 * Pointer to struct rte_eth_dev.
2791 * - On success, zero.
2792 * - On failure, a negative value.
2794 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2796 uint32_t mask, regval;
2797 struct e1000_hw *hw =
2798 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2800 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2801 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2802 struct rte_eth_dev_info dev_info;
2804 memset(&dev_info, 0, sizeof(dev_info));
2805 eth_igb_infos_get(dev, &dev_info);
2807 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2808 regval = E1000_READ_REG(hw, E1000_EIMS);
2809 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2815 * It reads ICR and gets interrupt causes, check it and set a bit flag
2816 * to update link status.
2819 * Pointer to struct rte_eth_dev.
2822 * - On success, zero.
2823 * - On failure, a negative value.
2826 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2829 struct e1000_hw *hw =
2830 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831 struct e1000_interrupt *intr =
2832 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2834 igb_intr_disable(dev);
2836 /* read-on-clear nic registers here */
2837 icr = E1000_READ_REG(hw, E1000_ICR);
2840 if (icr & E1000_ICR_LSC) {
2841 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2844 if (icr & E1000_ICR_VMMB)
2845 intr->flags |= E1000_FLAG_MAILBOX;
2851 * It executes link_update after knowing an interrupt is prsent.
2854 * Pointer to struct rte_eth_dev.
2857 * - On success, zero.
2858 * - On failure, a negative value.
2861 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2862 struct rte_intr_handle *intr_handle)
2864 struct e1000_hw *hw =
2865 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2866 struct e1000_interrupt *intr =
2867 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2868 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2869 struct rte_eth_link link;
2872 if (intr->flags & E1000_FLAG_MAILBOX) {
2873 igb_pf_mbx_process(dev);
2874 intr->flags &= ~E1000_FLAG_MAILBOX;
2877 igb_intr_enable(dev);
2878 rte_intr_ack(intr_handle);
2880 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2881 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2883 /* set get_link_status to check register later */
2884 hw->mac.get_link_status = 1;
2885 ret = eth_igb_link_update(dev, 0);
2887 /* check if link has changed */
2891 rte_eth_linkstatus_get(dev, &link);
2892 if (link.link_status) {
2894 " Port %d: Link Up - speed %u Mbps - %s",
2896 (unsigned)link.link_speed,
2897 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2898 "full-duplex" : "half-duplex");
2900 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2901 dev->data->port_id);
2904 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2905 pci_dev->addr.domain,
2907 pci_dev->addr.devid,
2908 pci_dev->addr.function);
2909 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2917 * Interrupt handler which shall be registered at first.
2920 * Pointer to interrupt handle.
2922 * The address of parameter (struct rte_eth_dev *) regsitered before.
2928 eth_igb_interrupt_handler(void *param)
2930 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2932 eth_igb_interrupt_get_status(dev);
2933 eth_igb_interrupt_action(dev, dev->intr_handle);
2937 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2940 struct e1000_hw *hw =
2941 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942 struct e1000_interrupt *intr =
2943 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2945 igbvf_intr_disable(hw);
2947 /* read-on-clear nic registers here */
2948 eicr = E1000_READ_REG(hw, E1000_EICR);
2951 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2952 intr->flags |= E1000_FLAG_MAILBOX;
2957 void igbvf_mbx_process(struct rte_eth_dev *dev)
2959 struct e1000_hw *hw =
2960 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961 struct e1000_mbx_info *mbx = &hw->mbx;
2964 /* peek the message first */
2965 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2967 /* PF reset VF event */
2968 if (in_msg == E1000_PF_CONTROL_MSG) {
2969 /* dummy mbx read to ack pf */
2970 if (mbx->ops.read(hw, &in_msg, 1, 0))
2972 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2978 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2980 struct e1000_interrupt *intr =
2981 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2983 if (intr->flags & E1000_FLAG_MAILBOX) {
2984 igbvf_mbx_process(dev);
2985 intr->flags &= ~E1000_FLAG_MAILBOX;
2988 igbvf_intr_enable(dev);
2989 rte_intr_ack(intr_handle);
2995 eth_igbvf_interrupt_handler(void *param)
2997 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2999 eth_igbvf_interrupt_get_status(dev);
3000 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3004 eth_igb_led_on(struct rte_eth_dev *dev)
3006 struct e1000_hw *hw;
3008 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3013 eth_igb_led_off(struct rte_eth_dev *dev)
3015 struct e1000_hw *hw;
3017 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3022 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3024 struct e1000_hw *hw;
3029 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030 fc_conf->pause_time = hw->fc.pause_time;
3031 fc_conf->high_water = hw->fc.high_water;
3032 fc_conf->low_water = hw->fc.low_water;
3033 fc_conf->send_xon = hw->fc.send_xon;
3034 fc_conf->autoneg = hw->mac.autoneg;
3037 * Return rx_pause and tx_pause status according to actual setting of
3038 * the TFCE and RFCE bits in the CTRL register.
3040 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3041 if (ctrl & E1000_CTRL_TFCE)
3046 if (ctrl & E1000_CTRL_RFCE)
3051 if (rx_pause && tx_pause)
3052 fc_conf->mode = RTE_FC_FULL;
3054 fc_conf->mode = RTE_FC_RX_PAUSE;
3056 fc_conf->mode = RTE_FC_TX_PAUSE;
3058 fc_conf->mode = RTE_FC_NONE;
3064 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3066 struct e1000_hw *hw;
3068 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3074 uint32_t rx_buf_size;
3075 uint32_t max_high_water;
3078 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079 if (fc_conf->autoneg != hw->mac.autoneg)
3081 rx_buf_size = igb_get_rx_buffer_size(hw);
3082 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3084 /* At least reserve one Ethernet frame for watermark */
3085 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3086 if ((fc_conf->high_water > max_high_water) ||
3087 (fc_conf->high_water < fc_conf->low_water)) {
3088 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3089 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3093 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3094 hw->fc.pause_time = fc_conf->pause_time;
3095 hw->fc.high_water = fc_conf->high_water;
3096 hw->fc.low_water = fc_conf->low_water;
3097 hw->fc.send_xon = fc_conf->send_xon;
3099 err = e1000_setup_link_generic(hw);
3100 if (err == E1000_SUCCESS) {
3102 /* check if we want to forward MAC frames - driver doesn't have native
3103 * capability to do that, so we'll write the registers ourselves */
3105 rctl = E1000_READ_REG(hw, E1000_RCTL);
3107 /* set or clear MFLCN.PMCF bit depending on configuration */
3108 if (fc_conf->mac_ctrl_frame_fwd != 0)
3109 rctl |= E1000_RCTL_PMCF;
3111 rctl &= ~E1000_RCTL_PMCF;
3113 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3114 E1000_WRITE_FLUSH(hw);
3119 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3123 #define E1000_RAH_POOLSEL_SHIFT (18)
3125 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3126 uint32_t index, uint32_t pool)
3128 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3132 rah = E1000_READ_REG(hw, E1000_RAH(index));
3133 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3134 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3139 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3141 uint8_t addr[RTE_ETHER_ADDR_LEN];
3142 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144 memset(addr, 0, sizeof(addr));
3146 e1000_rar_set(hw, addr, index);
3150 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3151 struct rte_ether_addr *addr)
3153 eth_igb_rar_clear(dev, 0);
3154 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3159 * Virtual Function operations
3162 igbvf_intr_disable(struct e1000_hw *hw)
3164 PMD_INIT_FUNC_TRACE();
3166 /* Clear interrupt mask to stop from interrupts being generated */
3167 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3169 E1000_WRITE_FLUSH(hw);
3173 igbvf_stop_adapter(struct rte_eth_dev *dev)
3177 struct rte_eth_dev_info dev_info;
3178 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3180 memset(&dev_info, 0, sizeof(dev_info));
3181 eth_igbvf_infos_get(dev, &dev_info);
3183 /* Clear interrupt mask to stop from interrupts being generated */
3184 igbvf_intr_disable(hw);
3186 /* Clear any pending interrupts, flush previous writes */
3187 E1000_READ_REG(hw, E1000_EICR);
3189 /* Disable the transmit unit. Each queue must be disabled. */
3190 for (i = 0; i < dev_info.max_tx_queues; i++)
3191 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3193 /* Disable the receive unit by stopping each queue */
3194 for (i = 0; i < dev_info.max_rx_queues; i++) {
3195 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3196 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3197 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3198 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3202 /* flush all queues disables */
3203 E1000_WRITE_FLUSH(hw);
3207 static int eth_igbvf_link_update(struct e1000_hw *hw)
3209 struct e1000_mbx_info *mbx = &hw->mbx;
3210 struct e1000_mac_info *mac = &hw->mac;
3211 int ret_val = E1000_SUCCESS;
3213 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3216 * We only want to run this if there has been a rst asserted.
3217 * in this case that could mean a link change, device reset,
3218 * or a virtual function reset
3221 /* If we were hit with a reset or timeout drop the link */
3222 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3223 mac->get_link_status = TRUE;
3225 if (!mac->get_link_status)
3228 /* if link status is down no point in checking to see if pf is up */
3229 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3232 /* if we passed all the tests above then the link is up and we no
3233 * longer need to check for link */
3234 mac->get_link_status = FALSE;
3242 igbvf_dev_configure(struct rte_eth_dev *dev)
3244 struct rte_eth_conf* conf = &dev->data->dev_conf;
3246 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3247 dev->data->port_id);
3250 * VF has no ability to enable/disable HW CRC
3251 * Keep the persistent behavior the same as Host PF
3253 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3254 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3255 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3256 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3259 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3260 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3261 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3269 igbvf_dev_start(struct rte_eth_dev *dev)
3271 struct e1000_hw *hw =
3272 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3273 struct e1000_adapter *adapter =
3274 E1000_DEV_PRIVATE(dev->data->dev_private);
3275 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3276 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3278 uint32_t intr_vector = 0;
3280 PMD_INIT_FUNC_TRACE();
3282 hw->mac.ops.reset_hw(hw);
3283 adapter->stopped = 0;
3286 igbvf_set_vfta_all(dev,1);
3288 eth_igbvf_tx_init(dev);
3290 /* This can fail when allocating mbufs for descriptor rings */
3291 ret = eth_igbvf_rx_init(dev);
3293 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3294 igb_dev_clear_queues(dev);
3298 /* check and configure queue intr-vector mapping */
3299 if (rte_intr_cap_multiple(intr_handle) &&
3300 dev->data->dev_conf.intr_conf.rxq) {
3301 intr_vector = dev->data->nb_rx_queues;
3302 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3307 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3308 intr_handle->intr_vec =
3309 rte_zmalloc("intr_vec",
3310 dev->data->nb_rx_queues * sizeof(int), 0);
3311 if (!intr_handle->intr_vec) {
3312 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3313 " intr_vec", dev->data->nb_rx_queues);
3318 eth_igbvf_configure_msix_intr(dev);
3320 /* enable uio/vfio intr/eventfd mapping */
3321 rte_intr_enable(intr_handle);
3323 /* resume enabled intr since hw reset */
3324 igbvf_intr_enable(dev);
3330 igbvf_dev_stop(struct rte_eth_dev *dev)
3332 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3333 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3335 PMD_INIT_FUNC_TRACE();
3337 igbvf_stop_adapter(dev);
3340 * Clear what we set, but we still keep shadow_vfta to
3341 * restore after device starts
3343 igbvf_set_vfta_all(dev,0);
3345 igb_dev_clear_queues(dev);
3347 /* disable intr eventfd mapping */
3348 rte_intr_disable(intr_handle);
3350 /* Clean datapath event and queue/vec mapping */
3351 rte_intr_efd_disable(intr_handle);
3352 if (intr_handle->intr_vec) {
3353 rte_free(intr_handle->intr_vec);
3354 intr_handle->intr_vec = NULL;
3359 igbvf_dev_close(struct rte_eth_dev *dev)
3361 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362 struct e1000_adapter *adapter =
3363 E1000_DEV_PRIVATE(dev->data->dev_private);
3364 struct rte_ether_addr addr;
3366 PMD_INIT_FUNC_TRACE();
3370 igbvf_dev_stop(dev);
3371 adapter->stopped = 1;
3372 igb_dev_free_queues(dev);
3375 * reprogram the RAR with a zero mac address,
3376 * to ensure that the VF traffic goes to the PF
3377 * after stop, close and detach of the VF.
3380 memset(&addr, 0, sizeof(addr));
3381 igbvf_default_mac_addr_set(dev, &addr);
3385 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3389 /* Set both unicast and multicast promisc */
3390 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3394 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3396 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398 /* If in allmulticast mode leave multicast promisc */
3399 if (dev->data->all_multicast == 1)
3400 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3402 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3406 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3408 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410 /* In promiscuous mode multicast promisc already set */
3411 if (dev->data->promiscuous == 0)
3412 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3416 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3418 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420 /* In promiscuous mode leave multicast promisc enabled */
3421 if (dev->data->promiscuous == 0)
3422 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3425 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3427 struct e1000_mbx_info *mbx = &hw->mbx;
3431 /* After set vlan, vlan strip will also be enabled in igb driver*/
3432 msgbuf[0] = E1000_VF_SET_VLAN;
3434 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3436 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3438 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3442 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3446 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3447 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3454 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3456 struct e1000_hw *hw =
3457 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458 struct e1000_vfta * shadow_vfta =
3459 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3460 int i = 0, j = 0, vfta = 0, mask = 1;
3462 for (i = 0; i < IGB_VFTA_SIZE; i++){
3463 vfta = shadow_vfta->vfta[i];
3466 for (j = 0; j < 32; j++){
3469 (uint16_t)((i<<5)+j), on);
3478 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3480 struct e1000_hw *hw =
3481 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3482 struct e1000_vfta * shadow_vfta =
3483 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3484 uint32_t vid_idx = 0;
3485 uint32_t vid_bit = 0;
3488 PMD_INIT_FUNC_TRACE();
3490 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3491 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3493 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3496 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3497 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3499 /*Save what we set and retore it after device reset*/
3501 shadow_vfta->vfta[vid_idx] |= vid_bit;
3503 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3509 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3511 struct e1000_hw *hw =
3512 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514 /* index is not used by rar_set() */
3515 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3521 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3522 struct rte_eth_rss_reta_entry64 *reta_conf,
3527 uint16_t idx, shift;
3528 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3531 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3532 "(%d) doesn't match the number hardware can supported "
3533 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3537 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3538 idx = i / RTE_RETA_GROUP_SIZE;
3539 shift = i % RTE_RETA_GROUP_SIZE;
3540 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3544 if (mask == IGB_4_BIT_MASK)
3547 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3548 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3549 if (mask & (0x1 << j))
3550 reta |= reta_conf[idx].reta[shift + j] <<
3553 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3555 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3562 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3563 struct rte_eth_rss_reta_entry64 *reta_conf,
3568 uint16_t idx, shift;
3569 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3572 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3573 "(%d) doesn't match the number hardware can supported "
3574 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3578 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3579 idx = i / RTE_RETA_GROUP_SIZE;
3580 shift = i % RTE_RETA_GROUP_SIZE;
3581 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3585 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3586 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3587 if (mask & (0x1 << j))
3588 reta_conf[idx].reta[shift + j] =
3589 ((reta >> (CHAR_BIT * j)) &
3598 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3599 struct rte_eth_syn_filter *filter,
3602 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603 struct e1000_filter_info *filter_info =
3604 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3605 uint32_t synqf, rfctl;
3607 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3610 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3613 if (synqf & E1000_SYN_FILTER_ENABLE)
3616 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3617 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3619 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3620 if (filter->hig_pri)
3621 rfctl |= E1000_RFCTL_SYNQFP;
3623 rfctl &= ~E1000_RFCTL_SYNQFP;
3625 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3627 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3632 filter_info->syn_info = synqf;
3633 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3634 E1000_WRITE_FLUSH(hw);
3639 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3640 struct rte_eth_syn_filter *filter)
3642 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643 uint32_t synqf, rfctl;
3645 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3646 if (synqf & E1000_SYN_FILTER_ENABLE) {
3647 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3648 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3649 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3650 E1000_SYN_FILTER_QUEUE_SHIFT);
3658 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3659 enum rte_filter_op filter_op,
3662 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3665 MAC_TYPE_FILTER_SUP(hw->mac.type);
3667 if (filter_op == RTE_ETH_FILTER_NOP)
3671 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3676 switch (filter_op) {
3677 case RTE_ETH_FILTER_ADD:
3678 ret = eth_igb_syn_filter_set(dev,
3679 (struct rte_eth_syn_filter *)arg,
3682 case RTE_ETH_FILTER_DELETE:
3683 ret = eth_igb_syn_filter_set(dev,
3684 (struct rte_eth_syn_filter *)arg,
3687 case RTE_ETH_FILTER_GET:
3688 ret = eth_igb_syn_filter_get(dev,
3689 (struct rte_eth_syn_filter *)arg);
3692 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3700 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3702 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3703 struct e1000_2tuple_filter_info *filter_info)
3705 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3707 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3708 return -EINVAL; /* filter index is out of range. */
3709 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3710 return -EINVAL; /* flags is invalid. */
3712 switch (filter->dst_port_mask) {
3714 filter_info->dst_port_mask = 0;
3715 filter_info->dst_port = filter->dst_port;
3718 filter_info->dst_port_mask = 1;
3721 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3725 switch (filter->proto_mask) {
3727 filter_info->proto_mask = 0;
3728 filter_info->proto = filter->proto;
3731 filter_info->proto_mask = 1;
3734 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3738 filter_info->priority = (uint8_t)filter->priority;
3739 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3740 filter_info->tcp_flags = filter->tcp_flags;
3742 filter_info->tcp_flags = 0;
3747 static inline struct e1000_2tuple_filter *
3748 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3749 struct e1000_2tuple_filter_info *key)
3751 struct e1000_2tuple_filter *it;
3753 TAILQ_FOREACH(it, filter_list, entries) {
3754 if (memcmp(key, &it->filter_info,
3755 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3762 /* inject a igb 2tuple filter to HW */
3764 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3765 struct e1000_2tuple_filter *filter)
3767 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3768 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3769 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3773 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3774 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3775 imir |= E1000_IMIR_PORT_BP;
3777 imir &= ~E1000_IMIR_PORT_BP;
3779 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3781 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3782 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3783 ttqf |= (uint32_t)(filter->filter_info.proto &
3784 E1000_TTQF_PROTOCOL_MASK);
3785 if (filter->filter_info.proto_mask == 0)
3786 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3788 /* tcp flags bits setting. */
3789 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3790 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3791 imir_ext |= E1000_IMIREXT_CTRL_URG;
3792 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3793 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3794 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3795 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3796 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3797 imir_ext |= E1000_IMIREXT_CTRL_RST;
3798 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3799 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3800 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3801 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3803 imir_ext |= E1000_IMIREXT_CTRL_BP;
3805 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3806 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3807 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3811 * igb_add_2tuple_filter - add a 2tuple filter
3814 * dev: Pointer to struct rte_eth_dev.
3815 * ntuple_filter: ponter to the filter that will be added.
3818 * - On success, zero.
3819 * - On failure, a negative value.
3822 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3823 struct rte_eth_ntuple_filter *ntuple_filter)
3825 struct e1000_filter_info *filter_info =
3826 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3827 struct e1000_2tuple_filter *filter;
3830 filter = rte_zmalloc("e1000_2tuple_filter",
3831 sizeof(struct e1000_2tuple_filter), 0);
3835 ret = ntuple_filter_to_2tuple(ntuple_filter,
3836 &filter->filter_info);
3841 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3842 &filter->filter_info) != NULL) {
3843 PMD_DRV_LOG(ERR, "filter exists.");
3847 filter->queue = ntuple_filter->queue;
3850 * look for an unused 2tuple filter index,
3851 * and insert the filter to list.
3853 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3854 if (!(filter_info->twotuple_mask & (1 << i))) {
3855 filter_info->twotuple_mask |= 1 << i;
3857 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3863 if (i >= E1000_MAX_TTQF_FILTERS) {
3864 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3869 igb_inject_2uple_filter(dev, filter);
3874 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3875 struct e1000_2tuple_filter *filter)
3877 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3878 struct e1000_filter_info *filter_info =
3879 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3881 filter_info->twotuple_mask &= ~(1 << filter->index);
3882 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3885 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3886 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3887 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3892 * igb_remove_2tuple_filter - remove a 2tuple filter
3895 * dev: Pointer to struct rte_eth_dev.
3896 * ntuple_filter: ponter to the filter that will be removed.
3899 * - On success, zero.
3900 * - On failure, a negative value.
3903 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3904 struct rte_eth_ntuple_filter *ntuple_filter)
3906 struct e1000_filter_info *filter_info =
3907 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3908 struct e1000_2tuple_filter_info filter_2tuple;
3909 struct e1000_2tuple_filter *filter;
3912 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3913 ret = ntuple_filter_to_2tuple(ntuple_filter,
3918 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3920 if (filter == NULL) {
3921 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3925 igb_delete_2tuple_filter(dev, filter);
3930 /* inject a igb flex filter to HW */
3932 igb_inject_flex_filter(struct rte_eth_dev *dev,
3933 struct e1000_flex_filter *filter)
3935 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936 uint32_t wufc, queueing;
3940 wufc = E1000_READ_REG(hw, E1000_WUFC);
3941 if (filter->index < E1000_MAX_FHFT)
3942 reg_off = E1000_FHFT(filter->index);
3944 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3946 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3947 (E1000_WUFC_FLX0 << filter->index));
3948 queueing = filter->filter_info.len |
3949 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3950 (filter->filter_info.priority <<
3951 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3952 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3955 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3956 E1000_WRITE_REG(hw, reg_off,
3957 filter->filter_info.dwords[j]);
3958 reg_off += sizeof(uint32_t);
3959 E1000_WRITE_REG(hw, reg_off,
3960 filter->filter_info.dwords[++j]);
3961 reg_off += sizeof(uint32_t);
3962 E1000_WRITE_REG(hw, reg_off,
3963 (uint32_t)filter->filter_info.mask[i]);
3964 reg_off += sizeof(uint32_t) * 2;
3969 static inline struct e1000_flex_filter *
3970 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3971 struct e1000_flex_filter_info *key)
3973 struct e1000_flex_filter *it;
3975 TAILQ_FOREACH(it, filter_list, entries) {
3976 if (memcmp(key, &it->filter_info,
3977 sizeof(struct e1000_flex_filter_info)) == 0)
3984 /* remove a flex byte filter
3986 * dev: Pointer to struct rte_eth_dev.
3987 * filter: the pointer of the filter will be removed.
3990 igb_remove_flex_filter(struct rte_eth_dev *dev,
3991 struct e1000_flex_filter *filter)
3993 struct e1000_filter_info *filter_info =
3994 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3995 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999 wufc = E1000_READ_REG(hw, E1000_WUFC);
4000 if (filter->index < E1000_MAX_FHFT)
4001 reg_off = E1000_FHFT(filter->index);
4003 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4005 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4006 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4008 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4009 (~(E1000_WUFC_FLX0 << filter->index)));
4011 filter_info->flex_mask &= ~(1 << filter->index);
4012 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4017 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4018 struct rte_eth_flex_filter *filter,
4021 struct e1000_filter_info *filter_info =
4022 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4023 struct e1000_flex_filter *flex_filter, *it;
4027 flex_filter = rte_zmalloc("e1000_flex_filter",
4028 sizeof(struct e1000_flex_filter), 0);
4029 if (flex_filter == NULL)
4032 flex_filter->filter_info.len = filter->len;
4033 flex_filter->filter_info.priority = filter->priority;
4034 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4035 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4037 /* reverse bits in flex filter's mask*/
4038 for (shift = 0; shift < CHAR_BIT; shift++) {
4039 if (filter->mask[i] & (0x01 << shift))
4040 mask |= (0x80 >> shift);
4042 flex_filter->filter_info.mask[i] = mask;
4045 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4046 &flex_filter->filter_info);
4047 if (it == NULL && !add) {
4048 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4049 rte_free(flex_filter);
4052 if (it != NULL && add) {
4053 PMD_DRV_LOG(ERR, "filter exists.");
4054 rte_free(flex_filter);
4059 flex_filter->queue = filter->queue;
4061 * look for an unused flex filter index
4062 * and insert the filter into the list.
4064 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4065 if (!(filter_info->flex_mask & (1 << i))) {
4066 filter_info->flex_mask |= 1 << i;
4067 flex_filter->index = i;
4068 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4074 if (i >= E1000_MAX_FLEX_FILTERS) {
4075 PMD_DRV_LOG(ERR, "flex filters are full.");
4076 rte_free(flex_filter);
4080 igb_inject_flex_filter(dev, flex_filter);
4083 igb_remove_flex_filter(dev, it);
4084 rte_free(flex_filter);
4091 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4092 struct rte_eth_flex_filter *filter)
4094 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095 struct e1000_filter_info *filter_info =
4096 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4097 struct e1000_flex_filter flex_filter, *it;
4098 uint32_t wufc, queueing, wufc_en = 0;
4100 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4101 flex_filter.filter_info.len = filter->len;
4102 flex_filter.filter_info.priority = filter->priority;
4103 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4104 memcpy(flex_filter.filter_info.mask, filter->mask,
4105 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4107 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4108 &flex_filter.filter_info);
4110 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4114 wufc = E1000_READ_REG(hw, E1000_WUFC);
4115 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4117 if ((wufc & wufc_en) == wufc_en) {
4118 uint32_t reg_off = 0;
4119 if (it->index < E1000_MAX_FHFT)
4120 reg_off = E1000_FHFT(it->index);
4122 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4124 queueing = E1000_READ_REG(hw,
4125 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4126 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4127 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4128 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4129 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4130 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4137 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4138 enum rte_filter_op filter_op,
4141 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4142 struct rte_eth_flex_filter *filter;
4145 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4147 if (filter_op == RTE_ETH_FILTER_NOP)
4151 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4156 filter = (struct rte_eth_flex_filter *)arg;
4157 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4158 || filter->len % sizeof(uint64_t) != 0) {
4159 PMD_DRV_LOG(ERR, "filter's length is out of range");
4162 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4163 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4167 switch (filter_op) {
4168 case RTE_ETH_FILTER_ADD:
4169 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4171 case RTE_ETH_FILTER_DELETE:
4172 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4174 case RTE_ETH_FILTER_GET:
4175 ret = eth_igb_get_flex_filter(dev, filter);
4178 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4186 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4188 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4189 struct e1000_5tuple_filter_info *filter_info)
4191 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4193 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4194 return -EINVAL; /* filter index is out of range. */
4195 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4196 return -EINVAL; /* flags is invalid. */
4198 switch (filter->dst_ip_mask) {
4200 filter_info->dst_ip_mask = 0;
4201 filter_info->dst_ip = filter->dst_ip;
4204 filter_info->dst_ip_mask = 1;
4207 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4211 switch (filter->src_ip_mask) {
4213 filter_info->src_ip_mask = 0;
4214 filter_info->src_ip = filter->src_ip;
4217 filter_info->src_ip_mask = 1;
4220 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4224 switch (filter->dst_port_mask) {
4226 filter_info->dst_port_mask = 0;
4227 filter_info->dst_port = filter->dst_port;
4230 filter_info->dst_port_mask = 1;
4233 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4237 switch (filter->src_port_mask) {
4239 filter_info->src_port_mask = 0;
4240 filter_info->src_port = filter->src_port;
4243 filter_info->src_port_mask = 1;
4246 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4250 switch (filter->proto_mask) {
4252 filter_info->proto_mask = 0;
4253 filter_info->proto = filter->proto;
4256 filter_info->proto_mask = 1;
4259 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4263 filter_info->priority = (uint8_t)filter->priority;
4264 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4265 filter_info->tcp_flags = filter->tcp_flags;
4267 filter_info->tcp_flags = 0;
4272 static inline struct e1000_5tuple_filter *
4273 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4274 struct e1000_5tuple_filter_info *key)
4276 struct e1000_5tuple_filter *it;
4278 TAILQ_FOREACH(it, filter_list, entries) {
4279 if (memcmp(key, &it->filter_info,
4280 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4287 /* inject a igb 5-tuple filter to HW */
4289 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4290 struct e1000_5tuple_filter *filter)
4292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4294 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4298 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4299 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4300 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4301 if (filter->filter_info.dst_ip_mask == 0)
4302 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4303 if (filter->filter_info.src_port_mask == 0)
4304 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4305 if (filter->filter_info.proto_mask == 0)
4306 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4307 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4308 E1000_FTQF_QUEUE_MASK;
4309 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4310 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4311 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4312 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4314 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4315 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4317 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4318 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4319 imir |= E1000_IMIR_PORT_BP;
4321 imir &= ~E1000_IMIR_PORT_BP;
4322 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4324 /* tcp flags bits setting. */
4325 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4326 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4327 imir_ext |= E1000_IMIREXT_CTRL_URG;
4328 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4329 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4330 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4331 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4332 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4333 imir_ext |= E1000_IMIREXT_CTRL_RST;
4334 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4335 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4336 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4337 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4339 imir_ext |= E1000_IMIREXT_CTRL_BP;
4341 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4342 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4346 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4349 * dev: Pointer to struct rte_eth_dev.
4350 * ntuple_filter: ponter to the filter that will be added.
4353 * - On success, zero.
4354 * - On failure, a negative value.
4357 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4358 struct rte_eth_ntuple_filter *ntuple_filter)
4360 struct e1000_filter_info *filter_info =
4361 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4362 struct e1000_5tuple_filter *filter;
4366 filter = rte_zmalloc("e1000_5tuple_filter",
4367 sizeof(struct e1000_5tuple_filter), 0);
4371 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4372 &filter->filter_info);
4378 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4379 &filter->filter_info) != NULL) {
4380 PMD_DRV_LOG(ERR, "filter exists.");
4384 filter->queue = ntuple_filter->queue;
4387 * look for an unused 5tuple filter index,
4388 * and insert the filter to list.
4390 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4391 if (!(filter_info->fivetuple_mask & (1 << i))) {
4392 filter_info->fivetuple_mask |= 1 << i;
4394 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4400 if (i >= E1000_MAX_FTQF_FILTERS) {
4401 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4406 igb_inject_5tuple_filter_82576(dev, filter);
4411 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4412 struct e1000_5tuple_filter *filter)
4414 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415 struct e1000_filter_info *filter_info =
4416 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4418 filter_info->fivetuple_mask &= ~(1 << filter->index);
4419 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4422 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4423 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4424 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4425 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4426 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4427 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4428 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4433 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4436 * dev: Pointer to struct rte_eth_dev.
4437 * ntuple_filter: ponter to the filter that will be removed.
4440 * - On success, zero.
4441 * - On failure, a negative value.
4444 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4445 struct rte_eth_ntuple_filter *ntuple_filter)
4447 struct e1000_filter_info *filter_info =
4448 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4449 struct e1000_5tuple_filter_info filter_5tuple;
4450 struct e1000_5tuple_filter *filter;
4453 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4454 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4459 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4461 if (filter == NULL) {
4462 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4466 igb_delete_5tuple_filter_82576(dev, filter);
4472 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4475 struct e1000_hw *hw;
4476 struct rte_eth_dev_info dev_info;
4477 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4479 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481 #ifdef RTE_LIBRTE_82571_SUPPORT
4482 /* XXX: not bigger than max_rx_pktlen */
4483 if (hw->mac.type == e1000_82571)
4486 eth_igb_infos_get(dev, &dev_info);
4488 /* check that mtu is within the allowed range */
4489 if (mtu < RTE_ETHER_MIN_MTU ||
4490 frame_size > dev_info.max_rx_pktlen)
4493 /* refuse mtu that requires the support of scattered packets when this
4494 * feature has not been enabled before. */
4495 if (!dev->data->scattered_rx &&
4496 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4499 rctl = E1000_READ_REG(hw, E1000_RCTL);
4501 /* switch to jumbo mode if needed */
4502 if (frame_size > RTE_ETHER_MAX_LEN) {
4503 dev->data->dev_conf.rxmode.offloads |=
4504 DEV_RX_OFFLOAD_JUMBO_FRAME;
4505 rctl |= E1000_RCTL_LPE;
4507 dev->data->dev_conf.rxmode.offloads &=
4508 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4509 rctl &= ~E1000_RCTL_LPE;
4511 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4513 /* update max frame size */
4514 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4516 E1000_WRITE_REG(hw, E1000_RLPML,
4517 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4523 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4526 * dev: Pointer to struct rte_eth_dev.
4527 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4528 * add: if true, add filter, if false, remove filter
4531 * - On success, zero.
4532 * - On failure, a negative value.
4535 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4536 struct rte_eth_ntuple_filter *ntuple_filter,
4539 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4542 switch (ntuple_filter->flags) {
4543 case RTE_5TUPLE_FLAGS:
4544 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4545 if (hw->mac.type != e1000_82576)
4548 ret = igb_add_5tuple_filter_82576(dev,
4551 ret = igb_remove_5tuple_filter_82576(dev,
4554 case RTE_2TUPLE_FLAGS:
4555 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4556 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4557 hw->mac.type != e1000_i210 &&
4558 hw->mac.type != e1000_i211)
4561 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4563 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4574 * igb_get_ntuple_filter - get a ntuple filter
4577 * dev: Pointer to struct rte_eth_dev.
4578 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4581 * - On success, zero.
4582 * - On failure, a negative value.
4585 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4586 struct rte_eth_ntuple_filter *ntuple_filter)
4588 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589 struct e1000_filter_info *filter_info =
4590 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4591 struct e1000_5tuple_filter_info filter_5tuple;
4592 struct e1000_2tuple_filter_info filter_2tuple;
4593 struct e1000_5tuple_filter *p_5tuple_filter;
4594 struct e1000_2tuple_filter *p_2tuple_filter;
4597 switch (ntuple_filter->flags) {
4598 case RTE_5TUPLE_FLAGS:
4599 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4600 if (hw->mac.type != e1000_82576)
4602 memset(&filter_5tuple,
4604 sizeof(struct e1000_5tuple_filter_info));
4605 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4609 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4610 &filter_info->fivetuple_list,
4612 if (p_5tuple_filter == NULL) {
4613 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4616 ntuple_filter->queue = p_5tuple_filter->queue;
4618 case RTE_2TUPLE_FLAGS:
4619 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4620 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4622 memset(&filter_2tuple,
4624 sizeof(struct e1000_2tuple_filter_info));
4625 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4628 p_2tuple_filter = igb_2tuple_filter_lookup(
4629 &filter_info->twotuple_list,
4631 if (p_2tuple_filter == NULL) {
4632 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4635 ntuple_filter->queue = p_2tuple_filter->queue;
4646 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4647 * @dev: pointer to rte_eth_dev structure
4648 * @filter_op:operation will be taken.
4649 * @arg: a pointer to specific structure corresponding to the filter_op
4652 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4653 enum rte_filter_op filter_op,
4656 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4659 MAC_TYPE_FILTER_SUP(hw->mac.type);
4661 if (filter_op == RTE_ETH_FILTER_NOP)
4665 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4670 switch (filter_op) {
4671 case RTE_ETH_FILTER_ADD:
4672 ret = igb_add_del_ntuple_filter(dev,
4673 (struct rte_eth_ntuple_filter *)arg,
4676 case RTE_ETH_FILTER_DELETE:
4677 ret = igb_add_del_ntuple_filter(dev,
4678 (struct rte_eth_ntuple_filter *)arg,
4681 case RTE_ETH_FILTER_GET:
4682 ret = igb_get_ntuple_filter(dev,
4683 (struct rte_eth_ntuple_filter *)arg);
4686 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4694 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4699 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4700 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4701 (filter_info->ethertype_mask & (1 << i)))
4708 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4709 uint16_t ethertype, uint32_t etqf)
4713 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4714 if (!(filter_info->ethertype_mask & (1 << i))) {
4715 filter_info->ethertype_mask |= 1 << i;
4716 filter_info->ethertype_filters[i].ethertype = ethertype;
4717 filter_info->ethertype_filters[i].etqf = etqf;
4725 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4728 if (idx >= E1000_MAX_ETQF_FILTERS)
4730 filter_info->ethertype_mask &= ~(1 << idx);
4731 filter_info->ethertype_filters[idx].ethertype = 0;
4732 filter_info->ethertype_filters[idx].etqf = 0;
4738 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4739 struct rte_eth_ethertype_filter *filter,
4742 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743 struct e1000_filter_info *filter_info =
4744 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4748 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4749 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4750 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4751 " ethertype filter.", filter->ether_type);
4755 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4756 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4759 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4760 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4764 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4765 if (ret >= 0 && add) {
4766 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4767 filter->ether_type);
4770 if (ret < 0 && !add) {
4771 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4772 filter->ether_type);
4777 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4778 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4779 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4780 ret = igb_ethertype_filter_insert(filter_info,
4781 filter->ether_type, etqf);
4783 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4787 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4791 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4792 E1000_WRITE_FLUSH(hw);
4798 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4799 struct rte_eth_ethertype_filter *filter)
4801 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4802 struct e1000_filter_info *filter_info =
4803 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4807 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4809 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4810 filter->ether_type);
4814 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4815 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4816 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4818 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4819 E1000_ETQF_QUEUE_SHIFT;
4827 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4828 * @dev: pointer to rte_eth_dev structure
4829 * @filter_op:operation will be taken.
4830 * @arg: a pointer to specific structure corresponding to the filter_op
4833 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4834 enum rte_filter_op filter_op,
4837 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840 MAC_TYPE_FILTER_SUP(hw->mac.type);
4842 if (filter_op == RTE_ETH_FILTER_NOP)
4846 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4851 switch (filter_op) {
4852 case RTE_ETH_FILTER_ADD:
4853 ret = igb_add_del_ethertype_filter(dev,
4854 (struct rte_eth_ethertype_filter *)arg,
4857 case RTE_ETH_FILTER_DELETE:
4858 ret = igb_add_del_ethertype_filter(dev,
4859 (struct rte_eth_ethertype_filter *)arg,
4862 case RTE_ETH_FILTER_GET:
4863 ret = igb_get_ethertype_filter(dev,
4864 (struct rte_eth_ethertype_filter *)arg);
4867 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4875 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4876 enum rte_filter_type filter_type,
4877 enum rte_filter_op filter_op,
4882 switch (filter_type) {
4883 case RTE_ETH_FILTER_NTUPLE:
4884 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4886 case RTE_ETH_FILTER_ETHERTYPE:
4887 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4889 case RTE_ETH_FILTER_SYN:
4890 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4892 case RTE_ETH_FILTER_FLEXIBLE:
4893 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4895 case RTE_ETH_FILTER_GENERIC:
4896 if (filter_op != RTE_ETH_FILTER_GET)
4898 *(const void **)arg = &igb_flow_ops;
4901 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4910 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4911 struct rte_ether_addr *mc_addr_set,
4912 uint32_t nb_mc_addr)
4914 struct e1000_hw *hw;
4916 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4922 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4924 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4925 uint64_t systime_cycles;
4927 switch (hw->mac.type) {
4931 * Need to read System Time Residue Register to be able
4932 * to read the other two registers.
4934 E1000_READ_REG(hw, E1000_SYSTIMR);
4935 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4936 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4937 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4944 * Need to read System Time Residue Register to be able
4945 * to read the other two registers.
4947 E1000_READ_REG(hw, E1000_SYSTIMR);
4948 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4949 /* Only the 8 LSB are valid. */
4950 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4954 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4955 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4960 return systime_cycles;
4964 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4966 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967 uint64_t rx_tstamp_cycles;
4969 switch (hw->mac.type) {
4972 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4973 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4974 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4980 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4981 /* Only the 8 LSB are valid. */
4982 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4986 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4987 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4992 return rx_tstamp_cycles;
4996 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4998 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999 uint64_t tx_tstamp_cycles;
5001 switch (hw->mac.type) {
5004 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5005 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5006 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5012 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5013 /* Only the 8 LSB are valid. */
5014 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5018 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5019 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5024 return tx_tstamp_cycles;
5028 igb_start_timecounters(struct rte_eth_dev *dev)
5030 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031 struct e1000_adapter *adapter = dev->data->dev_private;
5032 uint32_t incval = 1;
5034 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5036 switch (hw->mac.type) {
5040 /* 32 LSB bits + 8 MSB bits = 40 bits */
5041 mask = (1ULL << 40) - 1;
5046 * Start incrementing the register
5047 * used to timestamp PTP packets.
5049 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5052 incval = E1000_INCVALUE_82576;
5053 shift = IGB_82576_TSYNC_SHIFT;
5054 E1000_WRITE_REG(hw, E1000_TIMINCA,
5055 E1000_INCPERIOD_82576 | incval);
5062 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5063 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5064 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5066 adapter->systime_tc.cc_mask = mask;
5067 adapter->systime_tc.cc_shift = shift;
5068 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5070 adapter->rx_tstamp_tc.cc_mask = mask;
5071 adapter->rx_tstamp_tc.cc_shift = shift;
5072 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5074 adapter->tx_tstamp_tc.cc_mask = mask;
5075 adapter->tx_tstamp_tc.cc_shift = shift;
5076 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5080 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5082 struct e1000_adapter *adapter = dev->data->dev_private;
5084 adapter->systime_tc.nsec += delta;
5085 adapter->rx_tstamp_tc.nsec += delta;
5086 adapter->tx_tstamp_tc.nsec += delta;
5092 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5095 struct e1000_adapter *adapter = dev->data->dev_private;
5097 ns = rte_timespec_to_ns(ts);
5099 /* Set the timecounters to a new value. */
5100 adapter->systime_tc.nsec = ns;
5101 adapter->rx_tstamp_tc.nsec = ns;
5102 adapter->tx_tstamp_tc.nsec = ns;
5108 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5110 uint64_t ns, systime_cycles;
5111 struct e1000_adapter *adapter = dev->data->dev_private;
5113 systime_cycles = igb_read_systime_cyclecounter(dev);
5114 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5115 *ts = rte_ns_to_timespec(ns);
5121 igb_timesync_enable(struct rte_eth_dev *dev)
5123 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5127 /* Stop the timesync system time. */
5128 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5129 /* Reset the timesync system time value. */
5130 switch (hw->mac.type) {
5136 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5139 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5140 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5143 /* Not supported. */
5147 /* Enable system time for it isn't on by default. */
5148 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5149 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5150 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5152 igb_start_timecounters(dev);
5154 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5155 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5156 (RTE_ETHER_TYPE_1588 |
5157 E1000_ETQF_FILTER_ENABLE |
5160 /* Enable timestamping of received PTP packets. */
5161 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5162 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5163 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5165 /* Enable Timestamping of transmitted PTP packets. */
5166 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5167 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5168 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5174 igb_timesync_disable(struct rte_eth_dev *dev)
5176 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179 /* Disable timestamping of transmitted PTP packets. */
5180 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5181 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5182 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5184 /* Disable timestamping of received PTP packets. */
5185 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5186 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5187 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5189 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5190 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5192 /* Stop incrementating the System Time registers. */
5193 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5199 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5200 struct timespec *timestamp,
5201 uint32_t flags __rte_unused)
5203 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204 struct e1000_adapter *adapter = dev->data->dev_private;
5205 uint32_t tsync_rxctl;
5206 uint64_t rx_tstamp_cycles;
5209 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5210 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5213 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5214 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5215 *timestamp = rte_ns_to_timespec(ns);
5221 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5222 struct timespec *timestamp)
5224 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225 struct e1000_adapter *adapter = dev->data->dev_private;
5226 uint32_t tsync_txctl;
5227 uint64_t tx_tstamp_cycles;
5230 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5231 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5234 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5235 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5236 *timestamp = rte_ns_to_timespec(ns);
5242 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5246 const struct reg_info *reg_group;
5248 while ((reg_group = igb_regs[g_ind++]))
5249 count += igb_reg_group_count(reg_group);
5255 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5259 const struct reg_info *reg_group;
5261 while ((reg_group = igbvf_regs[g_ind++]))
5262 count += igb_reg_group_count(reg_group);
5268 eth_igb_get_regs(struct rte_eth_dev *dev,
5269 struct rte_dev_reg_info *regs)
5271 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272 uint32_t *data = regs->data;
5275 const struct reg_info *reg_group;
5278 regs->length = eth_igb_get_reg_length(dev);
5279 regs->width = sizeof(uint32_t);
5283 /* Support only full register dump */
5284 if ((regs->length == 0) ||
5285 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5286 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5288 while ((reg_group = igb_regs[g_ind++]))
5289 count += igb_read_regs_group(dev, &data[count],
5298 igbvf_get_regs(struct rte_eth_dev *dev,
5299 struct rte_dev_reg_info *regs)
5301 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302 uint32_t *data = regs->data;
5305 const struct reg_info *reg_group;
5308 regs->length = igbvf_get_reg_length(dev);
5309 regs->width = sizeof(uint32_t);
5313 /* Support only full register dump */
5314 if ((regs->length == 0) ||
5315 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5316 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5318 while ((reg_group = igbvf_regs[g_ind++]))
5319 count += igb_read_regs_group(dev, &data[count],
5328 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5330 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5332 /* Return unit is byte count */
5333 return hw->nvm.word_size * 2;
5337 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5338 struct rte_dev_eeprom_info *in_eeprom)
5340 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341 struct e1000_nvm_info *nvm = &hw->nvm;
5342 uint16_t *data = in_eeprom->data;
5345 first = in_eeprom->offset >> 1;
5346 length = in_eeprom->length >> 1;
5347 if ((first >= hw->nvm.word_size) ||
5348 ((first + length) >= hw->nvm.word_size))
5351 in_eeprom->magic = hw->vendor_id |
5352 ((uint32_t)hw->device_id << 16);
5354 if ((nvm->ops.read) == NULL)
5357 return nvm->ops.read(hw, first, length, data);
5361 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5362 struct rte_dev_eeprom_info *in_eeprom)
5364 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365 struct e1000_nvm_info *nvm = &hw->nvm;
5366 uint16_t *data = in_eeprom->data;
5369 first = in_eeprom->offset >> 1;
5370 length = in_eeprom->length >> 1;
5371 if ((first >= hw->nvm.word_size) ||
5372 ((first + length) >= hw->nvm.word_size))
5375 in_eeprom->magic = (uint32_t)hw->vendor_id |
5376 ((uint32_t)hw->device_id << 16);
5378 if ((nvm->ops.write) == NULL)
5380 return nvm->ops.write(hw, first, length, data);
5384 eth_igb_get_module_info(struct rte_eth_dev *dev,
5385 struct rte_eth_dev_module_info *modinfo)
5387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389 uint32_t status = 0;
5390 uint16_t sff8472_rev, addr_mode;
5391 bool page_swap = false;
5393 if (hw->phy.media_type == e1000_media_type_copper ||
5394 hw->phy.media_type == e1000_media_type_unknown)
5397 /* Check whether we support SFF-8472 or not */
5398 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5402 /* addressing mode is not supported */
5403 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5407 /* addressing mode is not supported */
5408 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5410 "Address change required to access page 0xA2, "
5411 "but not supported. Please report the module "
5412 "type to the driver maintainers.\n");
5416 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5417 /* We have an SFP, but it does not support SFF-8472 */
5418 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5419 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5421 /* We have an SFP which supports a revision of SFF-8472 */
5422 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5423 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5430 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5431 struct rte_dev_eeprom_info *info)
5433 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5435 uint32_t status = 0;
5436 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5437 u16 first_word, last_word;
5440 if (info->length == 0)
5443 first_word = info->offset >> 1;
5444 last_word = (info->offset + info->length - 1) >> 1;
5446 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5447 for (i = 0; i < last_word - first_word + 1; i++) {
5448 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5451 /* Error occurred while reading module */
5455 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5458 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5464 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5466 struct e1000_hw *hw =
5467 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5469 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5470 uint32_t vec = E1000_MISC_VEC_ID;
5472 if (rte_intr_allow_others(intr_handle))
5473 vec = E1000_RX_VEC_START;
5475 uint32_t mask = 1 << (queue_id + vec);
5477 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5478 E1000_WRITE_FLUSH(hw);
5484 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5486 struct e1000_hw *hw =
5487 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5488 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5489 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5490 uint32_t vec = E1000_MISC_VEC_ID;
5492 if (rte_intr_allow_others(intr_handle))
5493 vec = E1000_RX_VEC_START;
5495 uint32_t mask = 1 << (queue_id + vec);
5498 regval = E1000_READ_REG(hw, E1000_EIMS);
5499 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5500 E1000_WRITE_FLUSH(hw);
5502 rte_intr_ack(intr_handle);
5508 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5509 uint8_t index, uint8_t offset)
5511 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5514 val &= ~((uint32_t)0xFF << offset);
5516 /* write vector and valid bit */
5517 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5519 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5523 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5524 uint8_t queue, uint8_t msix_vector)
5528 if (hw->mac.type == e1000_82575) {
5530 tmp = E1000_EICR_RX_QUEUE0 << queue;
5531 else if (direction == 1)
5532 tmp = E1000_EICR_TX_QUEUE0 << queue;
5533 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5534 } else if (hw->mac.type == e1000_82576) {
5535 if ((direction == 0) || (direction == 1))
5536 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5537 ((queue & 0x8) << 1) +
5539 } else if ((hw->mac.type == e1000_82580) ||
5540 (hw->mac.type == e1000_i350) ||
5541 (hw->mac.type == e1000_i354) ||
5542 (hw->mac.type == e1000_i210) ||
5543 (hw->mac.type == e1000_i211)) {
5544 if ((direction == 0) || (direction == 1))
5545 eth_igb_write_ivar(hw, msix_vector,
5547 ((queue & 0x1) << 4) +
5552 /* Sets up the hardware to generate MSI-X interrupts properly
5554 * board private structure
5557 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5560 uint32_t tmpval, regval, intr_mask;
5561 struct e1000_hw *hw =
5562 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5563 uint32_t vec = E1000_MISC_VEC_ID;
5564 uint32_t base = E1000_MISC_VEC_ID;
5565 uint32_t misc_shift = 0;
5566 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5567 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5569 /* won't configure msix register if no mapping is done
5570 * between intr vector and event fd
5572 if (!rte_intr_dp_is_en(intr_handle))
5575 if (rte_intr_allow_others(intr_handle)) {
5576 vec = base = E1000_RX_VEC_START;
5580 /* set interrupt vector for other causes */
5581 if (hw->mac.type == e1000_82575) {
5582 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5583 /* enable MSI-X PBA support */
5584 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5586 /* Auto-Mask interrupts upon ICR read */
5587 tmpval |= E1000_CTRL_EXT_EIAME;
5588 tmpval |= E1000_CTRL_EXT_IRCA;
5590 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5592 /* enable msix_other interrupt */
5593 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5594 regval = E1000_READ_REG(hw, E1000_EIAC);
5595 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5596 regval = E1000_READ_REG(hw, E1000_EIAM);
5597 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5598 } else if ((hw->mac.type == e1000_82576) ||
5599 (hw->mac.type == e1000_82580) ||
5600 (hw->mac.type == e1000_i350) ||
5601 (hw->mac.type == e1000_i354) ||
5602 (hw->mac.type == e1000_i210) ||
5603 (hw->mac.type == e1000_i211)) {
5604 /* turn on MSI-X capability first */
5605 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5606 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5608 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5611 if (dev->data->dev_conf.intr_conf.lsc != 0)
5612 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5614 regval = E1000_READ_REG(hw, E1000_EIAC);
5615 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5617 /* enable msix_other interrupt */
5618 regval = E1000_READ_REG(hw, E1000_EIMS);
5619 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5620 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5621 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5624 /* use EIAM to auto-mask when MSI-X interrupt
5625 * is asserted, this saves a register write for every interrupt
5627 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5630 if (dev->data->dev_conf.intr_conf.lsc != 0)
5631 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5633 regval = E1000_READ_REG(hw, E1000_EIAM);
5634 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5636 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5637 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5638 intr_handle->intr_vec[queue_id] = vec;
5639 if (vec < base + intr_handle->nb_efd - 1)
5643 E1000_WRITE_FLUSH(hw);
5646 /* restore n-tuple filter */
5648 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5650 struct e1000_filter_info *filter_info =
5651 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5652 struct e1000_5tuple_filter *p_5tuple;
5653 struct e1000_2tuple_filter *p_2tuple;
5655 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5656 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5659 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5660 igb_inject_2uple_filter(dev, p_2tuple);
5664 /* restore SYN filter */
5666 igb_syn_filter_restore(struct rte_eth_dev *dev)
5668 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5669 struct e1000_filter_info *filter_info =
5670 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5673 synqf = filter_info->syn_info;
5675 if (synqf & E1000_SYN_FILTER_ENABLE) {
5676 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5677 E1000_WRITE_FLUSH(hw);
5681 /* restore ethernet type filter */
5683 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5685 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5686 struct e1000_filter_info *filter_info =
5687 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5690 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5691 if (filter_info->ethertype_mask & (1 << i)) {
5692 E1000_WRITE_REG(hw, E1000_ETQF(i),
5693 filter_info->ethertype_filters[i].etqf);
5694 E1000_WRITE_FLUSH(hw);
5699 /* restore flex byte filter */
5701 igb_flex_filter_restore(struct rte_eth_dev *dev)
5703 struct e1000_filter_info *filter_info =
5704 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5705 struct e1000_flex_filter *flex_filter;
5707 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5708 igb_inject_flex_filter(dev, flex_filter);
5712 /* restore rss filter */
5714 igb_rss_filter_restore(struct rte_eth_dev *dev)
5716 struct e1000_filter_info *filter_info =
5717 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5719 if (filter_info->rss_info.conf.queue_num)
5720 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5723 /* restore all types filter */
5725 igb_filter_restore(struct rte_eth_dev *dev)
5727 igb_ntuple_filter_restore(dev);
5728 igb_ethertype_filter_restore(dev);
5729 igb_syn_filter_restore(dev);
5730 igb_flex_filter_restore(dev);
5731 igb_rss_filter_restore(dev);
5736 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5737 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5738 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5739 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5740 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5741 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5743 /* see e1000_logs.c */
5744 RTE_INIT(e1000_init_log)
5746 e1000_igb_init_log();