1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static int eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static int eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
158 static int igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
190 struct rte_eth_ntuple_filter *ntuple_filter);
191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ntuple_filter *ntuple_filter);
193 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
194 struct rte_eth_ntuple_filter *ntuple_filter);
195 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
196 struct rte_eth_ntuple_filter *ntuple_filter);
197 static int eth_igb_flow_ops_get(struct rte_eth_dev *dev,
198 const struct rte_flow_ops **ops);
199 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
200 static int eth_igb_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
202 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
203 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
204 struct rte_dev_eeprom_info *eeprom);
205 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
206 struct rte_dev_eeprom_info *eeprom);
207 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
208 struct rte_eth_dev_module_info *modinfo);
209 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
210 struct rte_dev_eeprom_info *info);
211 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
212 struct rte_ether_addr *mc_addr_set,
213 uint32_t nb_mc_addr);
214 static int igb_timesync_enable(struct rte_eth_dev *dev);
215 static int igb_timesync_disable(struct rte_eth_dev *dev);
216 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
217 struct timespec *timestamp,
219 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
220 struct timespec *timestamp);
221 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
222 static int igb_timesync_read_time(struct rte_eth_dev *dev,
223 struct timespec *timestamp);
224 static int igb_timesync_write_time(struct rte_eth_dev *dev,
225 const struct timespec *timestamp);
226 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
228 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
230 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
231 uint8_t queue, uint8_t msix_vector);
232 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
233 uint8_t index, uint8_t offset);
234 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
235 static void eth_igbvf_interrupt_handler(void *param);
236 static void igbvf_mbx_process(struct rte_eth_dev *dev);
237 static int igb_filter_restore(struct rte_eth_dev *dev);
240 * Define VF Stats MACRO for Non "cleared on read" register
242 #define UPDATE_VF_STAT(reg, last, cur) \
244 u32 latest = E1000_READ_REG(hw, reg); \
245 cur += (latest - last) & UINT_MAX; \
249 #define IGB_FC_PAUSE_TIME 0x0680
250 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
251 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
253 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
255 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
258 * The set of PCI devices this driver supports
260 static const struct rte_pci_id pci_id_igb_map[] = {
261 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
262 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
263 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
264 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
265 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
266 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
267 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
268 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
270 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
271 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
272 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
274 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
275 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
276 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
302 { .vendor_id = 0, /* sentinel */ },
306 * The set of PCI devices this driver supports (for 82576&I350 VF)
308 static const struct rte_pci_id pci_id_igbvf_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
313 { .vendor_id = 0, /* sentinel */ },
316 static const struct rte_eth_desc_lim rx_desc_lim = {
317 .nb_max = E1000_MAX_RING_DESC,
318 .nb_min = E1000_MIN_RING_DESC,
319 .nb_align = IGB_RXD_ALIGN,
322 static const struct rte_eth_desc_lim tx_desc_lim = {
323 .nb_max = E1000_MAX_RING_DESC,
324 .nb_min = E1000_MIN_RING_DESC,
325 .nb_align = IGB_RXD_ALIGN,
326 .nb_seg_max = IGB_TX_MAX_SEG,
327 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
330 static const struct eth_dev_ops eth_igb_ops = {
331 .dev_configure = eth_igb_configure,
332 .dev_start = eth_igb_start,
333 .dev_stop = eth_igb_stop,
334 .dev_set_link_up = eth_igb_dev_set_link_up,
335 .dev_set_link_down = eth_igb_dev_set_link_down,
336 .dev_close = eth_igb_close,
337 .dev_reset = eth_igb_reset,
338 .promiscuous_enable = eth_igb_promiscuous_enable,
339 .promiscuous_disable = eth_igb_promiscuous_disable,
340 .allmulticast_enable = eth_igb_allmulticast_enable,
341 .allmulticast_disable = eth_igb_allmulticast_disable,
342 .link_update = eth_igb_link_update,
343 .stats_get = eth_igb_stats_get,
344 .xstats_get = eth_igb_xstats_get,
345 .xstats_get_by_id = eth_igb_xstats_get_by_id,
346 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
347 .xstats_get_names = eth_igb_xstats_get_names,
348 .stats_reset = eth_igb_stats_reset,
349 .xstats_reset = eth_igb_xstats_reset,
350 .fw_version_get = eth_igb_fw_version_get,
351 .dev_infos_get = eth_igb_infos_get,
352 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
353 .mtu_set = eth_igb_mtu_set,
354 .vlan_filter_set = eth_igb_vlan_filter_set,
355 .vlan_tpid_set = eth_igb_vlan_tpid_set,
356 .vlan_offload_set = eth_igb_vlan_offload_set,
357 .rx_queue_setup = eth_igb_rx_queue_setup,
358 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
359 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
360 .rx_queue_release = eth_igb_rx_queue_release,
361 .tx_queue_setup = eth_igb_tx_queue_setup,
362 .tx_queue_release = eth_igb_tx_queue_release,
363 .tx_done_cleanup = eth_igb_tx_done_cleanup,
364 .dev_led_on = eth_igb_led_on,
365 .dev_led_off = eth_igb_led_off,
366 .flow_ctrl_get = eth_igb_flow_ctrl_get,
367 .flow_ctrl_set = eth_igb_flow_ctrl_set,
368 .mac_addr_add = eth_igb_rar_set,
369 .mac_addr_remove = eth_igb_rar_clear,
370 .mac_addr_set = eth_igb_default_mac_addr_set,
371 .reta_update = eth_igb_rss_reta_update,
372 .reta_query = eth_igb_rss_reta_query,
373 .rss_hash_update = eth_igb_rss_hash_update,
374 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
375 .flow_ops_get = eth_igb_flow_ops_get,
376 .set_mc_addr_list = eth_igb_set_mc_addr_list,
377 .rxq_info_get = igb_rxq_info_get,
378 .txq_info_get = igb_txq_info_get,
379 .timesync_enable = igb_timesync_enable,
380 .timesync_disable = igb_timesync_disable,
381 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
382 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
383 .get_reg = eth_igb_get_regs,
384 .get_eeprom_length = eth_igb_get_eeprom_length,
385 .get_eeprom = eth_igb_get_eeprom,
386 .set_eeprom = eth_igb_set_eeprom,
387 .get_module_info = eth_igb_get_module_info,
388 .get_module_eeprom = eth_igb_get_module_eeprom,
389 .timesync_adjust_time = igb_timesync_adjust_time,
390 .timesync_read_time = igb_timesync_read_time,
391 .timesync_write_time = igb_timesync_write_time,
395 * dev_ops for virtual function, bare necessities for basic vf
396 * operation have been implemented
398 static const struct eth_dev_ops igbvf_eth_dev_ops = {
399 .dev_configure = igbvf_dev_configure,
400 .dev_start = igbvf_dev_start,
401 .dev_stop = igbvf_dev_stop,
402 .dev_close = igbvf_dev_close,
403 .promiscuous_enable = igbvf_promiscuous_enable,
404 .promiscuous_disable = igbvf_promiscuous_disable,
405 .allmulticast_enable = igbvf_allmulticast_enable,
406 .allmulticast_disable = igbvf_allmulticast_disable,
407 .link_update = eth_igb_link_update,
408 .stats_get = eth_igbvf_stats_get,
409 .xstats_get = eth_igbvf_xstats_get,
410 .xstats_get_names = eth_igbvf_xstats_get_names,
411 .stats_reset = eth_igbvf_stats_reset,
412 .xstats_reset = eth_igbvf_stats_reset,
413 .vlan_filter_set = igbvf_vlan_filter_set,
414 .dev_infos_get = eth_igbvf_infos_get,
415 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
416 .rx_queue_setup = eth_igb_rx_queue_setup,
417 .rx_queue_release = eth_igb_rx_queue_release,
418 .tx_queue_setup = eth_igb_tx_queue_setup,
419 .tx_queue_release = eth_igb_tx_queue_release,
420 .tx_done_cleanup = eth_igb_tx_done_cleanup,
421 .set_mc_addr_list = eth_igb_set_mc_addr_list,
422 .rxq_info_get = igb_rxq_info_get,
423 .txq_info_get = igb_txq_info_get,
424 .mac_addr_set = igbvf_default_mac_addr_set,
425 .get_reg = igbvf_get_regs,
428 /* store statistics names and its offset in stats structure */
429 struct rte_igb_xstats_name_off {
430 char name[RTE_ETH_XSTATS_NAME_SIZE];
434 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
435 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
436 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
437 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
438 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
439 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
440 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
441 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
443 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
444 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
445 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
446 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
447 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
448 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
449 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
450 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
451 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
452 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
453 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
455 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
456 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
457 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
458 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
459 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
461 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
463 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
464 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
465 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
466 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
467 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
468 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
469 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
470 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
471 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
472 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
473 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
474 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
475 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
476 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
477 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
478 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
479 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
480 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
482 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
484 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
485 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
486 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
487 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
488 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
489 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
490 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
492 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
495 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
496 sizeof(rte_igb_stats_strings[0]))
498 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
499 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
500 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
501 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
502 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
503 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
506 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
507 sizeof(rte_igbvf_stats_strings[0]))
511 igb_intr_enable(struct rte_eth_dev *dev)
513 struct e1000_interrupt *intr =
514 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
518 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
520 if (rte_intr_allow_others(intr_handle) &&
521 dev->data->dev_conf.intr_conf.lsc != 0) {
522 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
525 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
526 E1000_WRITE_FLUSH(hw);
530 igb_intr_disable(struct rte_eth_dev *dev)
532 struct e1000_hw *hw =
533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
535 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
537 if (rte_intr_allow_others(intr_handle) &&
538 dev->data->dev_conf.intr_conf.lsc != 0) {
539 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
542 E1000_WRITE_REG(hw, E1000_IMC, ~0);
543 E1000_WRITE_FLUSH(hw);
547 igbvf_intr_enable(struct rte_eth_dev *dev)
549 struct e1000_hw *hw =
550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 /* only for mailbox */
553 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
554 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
555 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
556 E1000_WRITE_FLUSH(hw);
559 /* only for mailbox now. If RX/TX needed, should extend this function. */
561 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
566 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
567 tmp |= E1000_VTIVAR_VALID;
568 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
572 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
574 struct e1000_hw *hw =
575 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
577 /* Configure VF other cause ivar */
578 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
581 static inline int32_t
582 igb_pf_reset_hw(struct e1000_hw *hw)
587 status = e1000_reset_hw(hw);
589 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
590 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
591 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
592 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
593 E1000_WRITE_FLUSH(hw);
599 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
601 struct e1000_hw *hw =
602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 hw->vendor_id = pci_dev->id.vendor_id;
606 hw->device_id = pci_dev->id.device_id;
607 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
608 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
610 e1000_set_mac_type(hw);
612 /* need to check if it is a vf device below */
616 igb_reset_swfw_lock(struct e1000_hw *hw)
621 * Do mac ops initialization manually here, since we will need
622 * some function pointers set by this call.
624 ret_val = e1000_init_mac_params(hw);
629 * SMBI lock should not fail in this early stage. If this is the case,
630 * it is due to an improper exit of the application.
631 * So force the release of the faulty lock.
633 if (e1000_get_hw_semaphore_generic(hw) < 0) {
634 PMD_DRV_LOG(DEBUG, "SMBI lock released");
636 e1000_put_hw_semaphore_generic(hw);
638 if (hw->mac.ops.acquire_swfw_sync != NULL) {
642 * Phy lock should not fail in this early stage. If this is the case,
643 * it is due to an improper exit of the application.
644 * So force the release of the faulty lock.
646 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
647 if (hw->bus.func > E1000_FUNC_1)
649 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
650 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
653 hw->mac.ops.release_swfw_sync(hw, mask);
656 * This one is more tricky since it is common to all ports; but
657 * swfw_sync retries last long enough (1s) to be almost sure that if
658 * lock can not be taken it is due to an improper lock of the
661 mask = E1000_SWFW_EEP_SM;
662 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
663 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
665 hw->mac.ops.release_swfw_sync(hw, mask);
668 return E1000_SUCCESS;
671 /* Remove all ntuple filters of the device */
672 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
674 struct e1000_filter_info *filter_info =
675 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
676 struct e1000_5tuple_filter *p_5tuple;
677 struct e1000_2tuple_filter *p_2tuple;
679 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
680 TAILQ_REMOVE(&filter_info->fivetuple_list,
684 filter_info->fivetuple_mask = 0;
685 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
686 TAILQ_REMOVE(&filter_info->twotuple_list,
690 filter_info->twotuple_mask = 0;
695 /* Remove all flex filters of the device */
696 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
698 struct e1000_filter_info *filter_info =
699 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
700 struct e1000_flex_filter *p_flex;
702 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
703 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
706 filter_info->flex_mask = 0;
712 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
716 struct e1000_hw *hw =
717 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
718 struct e1000_vfta * shadow_vfta =
719 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
720 struct e1000_filter_info *filter_info =
721 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
722 struct e1000_adapter *adapter =
723 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
727 eth_dev->dev_ops = ð_igb_ops;
728 eth_dev->rx_queue_count = eth_igb_rx_queue_count;
729 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
730 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
731 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
732 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
733 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
735 /* for secondary processes, we don't initialise any further as primary
736 * has already done this work. Only check we don't need a different
738 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
739 if (eth_dev->data->scattered_rx)
740 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
744 rte_eth_copy_pci_info(eth_dev, pci_dev);
746 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
748 igb_identify_hardware(eth_dev, pci_dev);
749 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
754 e1000_get_bus_info(hw);
756 /* Reset any pending lock */
757 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
762 /* Finish initialization */
763 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
769 hw->phy.autoneg_wait_to_complete = 0;
770 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
773 if (hw->phy.media_type == e1000_media_type_copper) {
774 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
775 hw->phy.disable_polarity_correction = 0;
776 hw->phy.ms_type = e1000_ms_hw_default;
780 * Start from a known state, this is important in reading the nvm
785 /* Make sure we have a good EEPROM before we read from it */
786 if (e1000_validate_nvm_checksum(hw) < 0) {
788 * Some PCI-E parts fail the first check due to
789 * the link being in sleep state, call it again,
790 * if it fails a second time its a real issue.
792 if (e1000_validate_nvm_checksum(hw) < 0) {
793 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
799 /* Read the permanent MAC address out of the EEPROM */
800 if (e1000_read_mac_addr(hw) != 0) {
801 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
806 /* Allocate memory for storing MAC addresses */
807 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
808 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
809 if (eth_dev->data->mac_addrs == NULL) {
810 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
811 "store MAC addresses",
812 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
817 /* Copy the permanent MAC address */
818 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
819 ð_dev->data->mac_addrs[0]);
821 /* initialize the vfta */
822 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
824 /* Now initialize the hardware */
825 if (igb_hardware_init(hw) != 0) {
826 PMD_INIT_LOG(ERR, "Hardware initialization failed");
827 rte_free(eth_dev->data->mac_addrs);
828 eth_dev->data->mac_addrs = NULL;
832 hw->mac.get_link_status = 1;
833 adapter->stopped = 0;
835 /* Indicate SOL/IDER usage */
836 if (e1000_check_reset_block(hw) < 0) {
837 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
841 /* initialize PF if max_vfs not zero */
842 igb_pf_host_init(eth_dev);
844 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
845 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
846 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
847 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
848 E1000_WRITE_FLUSH(hw);
850 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
851 eth_dev->data->port_id, pci_dev->id.vendor_id,
852 pci_dev->id.device_id);
854 rte_intr_callback_register(pci_dev->intr_handle,
855 eth_igb_interrupt_handler,
858 /* enable uio/vfio intr/eventfd mapping */
859 rte_intr_enable(pci_dev->intr_handle);
861 /* enable support intr */
862 igb_intr_enable(eth_dev);
864 eth_igb_dev_set_link_down(eth_dev);
866 /* initialize filter info */
867 memset(filter_info, 0,
868 sizeof(struct e1000_filter_info));
870 TAILQ_INIT(&filter_info->flex_list);
871 TAILQ_INIT(&filter_info->twotuple_list);
872 TAILQ_INIT(&filter_info->fivetuple_list);
874 TAILQ_INIT(&igb_filter_ntuple_list);
875 TAILQ_INIT(&igb_filter_ethertype_list);
876 TAILQ_INIT(&igb_filter_syn_list);
877 TAILQ_INIT(&igb_filter_flex_list);
878 TAILQ_INIT(&igb_filter_rss_list);
879 TAILQ_INIT(&igb_flow_list);
884 igb_hw_control_release(hw);
890 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
892 PMD_INIT_FUNC_TRACE();
894 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
897 eth_igb_close(eth_dev);
903 * Virtual Function device init
906 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
908 struct rte_pci_device *pci_dev;
909 struct rte_intr_handle *intr_handle;
910 struct e1000_adapter *adapter =
911 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
912 struct e1000_hw *hw =
913 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
915 struct rte_ether_addr *perm_addr =
916 (struct rte_ether_addr *)hw->mac.perm_addr;
918 PMD_INIT_FUNC_TRACE();
920 eth_dev->dev_ops = &igbvf_eth_dev_ops;
921 eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
922 eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
923 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
924 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
925 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
927 /* for secondary processes, we don't initialise any further as primary
928 * has already done this work. Only check we don't need a different
930 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
931 if (eth_dev->data->scattered_rx)
932 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
936 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
937 rte_eth_copy_pci_info(eth_dev, pci_dev);
939 hw->device_id = pci_dev->id.device_id;
940 hw->vendor_id = pci_dev->id.vendor_id;
941 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
942 adapter->stopped = 0;
944 /* Initialize the shared code (base driver) */
945 diag = e1000_setup_init_funcs(hw, TRUE);
947 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
952 /* init_mailbox_params */
953 hw->mbx.ops.init_params(hw);
955 /* Disable the interrupts for VF */
956 igbvf_intr_disable(hw);
958 diag = hw->mac.ops.reset_hw(hw);
960 /* Allocate memory for storing MAC addresses */
961 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
962 hw->mac.rar_entry_count, 0);
963 if (eth_dev->data->mac_addrs == NULL) {
965 "Failed to allocate %d bytes needed to store MAC "
967 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
971 /* Generate a random MAC address, if none was assigned by PF. */
972 if (rte_is_zero_ether_addr(perm_addr)) {
973 rte_eth_random_addr(perm_addr->addr_bytes);
974 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
975 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
976 RTE_ETHER_ADDR_PRT_FMT,
977 RTE_ETHER_ADDR_BYTES(perm_addr));
980 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
982 rte_free(eth_dev->data->mac_addrs);
983 eth_dev->data->mac_addrs = NULL;
986 /* Copy the permanent MAC address */
987 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
988 ð_dev->data->mac_addrs[0]);
990 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
992 eth_dev->data->port_id, pci_dev->id.vendor_id,
993 pci_dev->id.device_id, "igb_mac_82576_vf");
995 intr_handle = pci_dev->intr_handle;
996 rte_intr_callback_register(intr_handle,
997 eth_igbvf_interrupt_handler, eth_dev);
1003 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1005 PMD_INIT_FUNC_TRACE();
1007 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1010 igbvf_dev_close(eth_dev);
1015 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1016 struct rte_pci_device *pci_dev)
1018 return rte_eth_dev_pci_generic_probe(pci_dev,
1019 sizeof(struct e1000_adapter), eth_igb_dev_init);
1022 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1024 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1027 static struct rte_pci_driver rte_igb_pmd = {
1028 .id_table = pci_id_igb_map,
1029 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1030 .probe = eth_igb_pci_probe,
1031 .remove = eth_igb_pci_remove,
1035 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1036 struct rte_pci_device *pci_dev)
1038 return rte_eth_dev_pci_generic_probe(pci_dev,
1039 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1042 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1044 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1048 * virtual function driver struct
1050 static struct rte_pci_driver rte_igbvf_pmd = {
1051 .id_table = pci_id_igbvf_map,
1052 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1053 .probe = eth_igbvf_pci_probe,
1054 .remove = eth_igbvf_pci_remove,
1058 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1060 struct e1000_hw *hw =
1061 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1062 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1063 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1064 rctl |= E1000_RCTL_VFE;
1065 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1069 igb_check_mq_mode(struct rte_eth_dev *dev)
1071 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1072 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1073 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1074 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1076 if ((rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) ||
1077 tx_mq_mode == RTE_ETH_MQ_TX_DCB ||
1078 tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) {
1079 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1082 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1083 /* Check multi-queue mode.
1084 * To no break software we accept RTE_ETH_MQ_RX_NONE as this might
1085 * be used to turn off VLAN filter.
1088 if (rx_mq_mode == RTE_ETH_MQ_RX_NONE ||
1089 rx_mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
1090 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_ONLY;
1091 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1093 /* Only support one queue on VFs.
1094 * RSS together with SRIOV is not supported.
1096 PMD_INIT_LOG(ERR, "SRIOV is active,"
1097 " wrong mq_mode rx %d.",
1101 /* TX mode is not used here, so mode might be ignored.*/
1102 if (tx_mq_mode != RTE_ETH_MQ_TX_VMDQ_ONLY) {
1103 /* SRIOV only works in VMDq enable mode */
1104 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1105 " TX mode %d is not supported. "
1106 " Driver will behave as %d mode.",
1107 tx_mq_mode, RTE_ETH_MQ_TX_VMDQ_ONLY);
1110 /* check valid queue number */
1111 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1112 PMD_INIT_LOG(ERR, "SRIOV is active,"
1113 " only support one queue on VFs.");
1117 /* To no break software that set invalid mode, only display
1118 * warning if invalid mode is used.
1120 if (rx_mq_mode != RTE_ETH_MQ_RX_NONE &&
1121 rx_mq_mode != RTE_ETH_MQ_RX_VMDQ_ONLY &&
1122 rx_mq_mode != RTE_ETH_MQ_RX_RSS) {
1123 /* RSS together with VMDq not supported*/
1124 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1129 if (tx_mq_mode != RTE_ETH_MQ_TX_NONE &&
1130 tx_mq_mode != RTE_ETH_MQ_TX_VMDQ_ONLY) {
1131 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1132 " Due to txmode is meaningless in this"
1133 " driver, just ignore.",
1141 eth_igb_configure(struct rte_eth_dev *dev)
1143 struct e1000_interrupt *intr =
1144 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1147 PMD_INIT_FUNC_TRACE();
1149 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1150 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1152 /* multipe queue mode checking */
1153 ret = igb_check_mq_mode(dev);
1155 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1160 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1161 PMD_INIT_FUNC_TRACE();
1167 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1170 struct e1000_hw *hw =
1171 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1172 uint32_t tctl, rctl;
1174 tctl = E1000_READ_REG(hw, E1000_TCTL);
1175 rctl = E1000_READ_REG(hw, E1000_RCTL);
1179 tctl |= E1000_TCTL_EN;
1180 rctl |= E1000_RCTL_EN;
1183 tctl &= ~E1000_TCTL_EN;
1184 rctl &= ~E1000_RCTL_EN;
1186 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1187 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1188 E1000_WRITE_FLUSH(hw);
1192 eth_igb_start(struct rte_eth_dev *dev)
1194 struct e1000_hw *hw =
1195 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196 struct e1000_adapter *adapter =
1197 E1000_DEV_PRIVATE(dev->data->dev_private);
1198 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1199 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1201 uint32_t intr_vector = 0;
1207 PMD_INIT_FUNC_TRACE();
1209 /* disable uio/vfio intr/eventfd mapping */
1210 rte_intr_disable(intr_handle);
1212 /* Power up the phy. Needed to make the link go Up */
1213 eth_igb_dev_set_link_up(dev);
1216 * Packet Buffer Allocation (PBA)
1217 * Writing PBA sets the receive portion of the buffer
1218 * the remainder is used for the transmit buffer.
1220 if (hw->mac.type == e1000_82575) {
1223 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1224 E1000_WRITE_REG(hw, E1000_PBA, pba);
1227 /* Put the address into the Receive Address Array */
1228 e1000_rar_set(hw, hw->mac.addr, 0);
1230 /* Initialize the hardware */
1231 if (igb_hardware_init(hw)) {
1232 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1235 adapter->stopped = 0;
1237 E1000_WRITE_REG(hw, E1000_VET,
1238 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1240 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1241 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1242 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1243 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1244 E1000_WRITE_FLUSH(hw);
1246 /* configure PF module if SRIOV enabled */
1247 igb_pf_host_configure(dev);
1249 /* check and configure queue intr-vector mapping */
1250 if ((rte_intr_cap_multiple(intr_handle) ||
1251 !RTE_ETH_DEV_SRIOV(dev).active) &&
1252 dev->data->dev_conf.intr_conf.rxq != 0) {
1253 intr_vector = dev->data->nb_rx_queues;
1254 if (rte_intr_efd_enable(intr_handle, intr_vector))
1258 /* Allocate the vector list */
1259 if (rte_intr_dp_is_en(intr_handle)) {
1260 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
1261 dev->data->nb_rx_queues)) {
1262 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1263 " intr_vec", dev->data->nb_rx_queues);
1268 /* confiugre msix for rx interrupt */
1269 eth_igb_configure_msix_intr(dev);
1271 /* Configure for OS presence */
1272 igb_init_manageability(hw);
1274 eth_igb_tx_init(dev);
1276 /* This can fail when allocating mbufs for descriptor rings */
1277 ret = eth_igb_rx_init(dev);
1279 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1280 igb_dev_clear_queues(dev);
1284 e1000_clear_hw_cntrs_base_generic(hw);
1287 * VLAN Offload Settings
1289 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
1290 RTE_ETH_VLAN_EXTEND_MASK;
1291 ret = eth_igb_vlan_offload_set(dev, mask);
1293 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1294 igb_dev_clear_queues(dev);
1298 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
1299 /* Enable VLAN filter since VMDq always use VLAN filter */
1300 igb_vmdq_vlan_hw_filter_enable(dev);
1303 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1304 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1305 (hw->mac.type == e1000_i211)) {
1306 /* Configure EITR with the maximum possible value (0xFFFF) */
1307 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1310 /* Setup link speed and duplex */
1311 speeds = &dev->data->dev_conf.link_speeds;
1312 if (*speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
1313 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1314 hw->mac.autoneg = 1;
1317 autoneg = (*speeds & RTE_ETH_LINK_SPEED_FIXED) == 0;
1320 hw->phy.autoneg_advertised = 0;
1322 if (*speeds & ~(RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M |
1323 RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M |
1324 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_FIXED)) {
1326 goto error_invalid_config;
1328 if (*speeds & RTE_ETH_LINK_SPEED_10M_HD) {
1329 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1332 if (*speeds & RTE_ETH_LINK_SPEED_10M) {
1333 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1336 if (*speeds & RTE_ETH_LINK_SPEED_100M_HD) {
1337 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1340 if (*speeds & RTE_ETH_LINK_SPEED_100M) {
1341 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1344 if (*speeds & RTE_ETH_LINK_SPEED_1G) {
1345 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1348 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1349 goto error_invalid_config;
1351 /* Set/reset the mac.autoneg based on the link speed,
1355 hw->mac.autoneg = 0;
1356 hw->mac.forced_speed_duplex =
1357 hw->phy.autoneg_advertised;
1359 hw->mac.autoneg = 1;
1363 e1000_setup_link(hw);
1365 if (rte_intr_allow_others(intr_handle)) {
1366 /* check if lsc interrupt is enabled */
1367 if (dev->data->dev_conf.intr_conf.lsc != 0)
1368 eth_igb_lsc_interrupt_setup(dev, TRUE);
1370 eth_igb_lsc_interrupt_setup(dev, FALSE);
1372 rte_intr_callback_unregister(intr_handle,
1373 eth_igb_interrupt_handler,
1375 if (dev->data->dev_conf.intr_conf.lsc != 0)
1376 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1377 " no intr multiplex");
1380 /* check if rxq interrupt is enabled */
1381 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1382 rte_intr_dp_is_en(intr_handle))
1383 eth_igb_rxq_interrupt_setup(dev);
1385 /* enable uio/vfio intr/eventfd mapping */
1386 rte_intr_enable(intr_handle);
1388 /* resume enabled intr since hw reset */
1389 igb_intr_enable(dev);
1391 /* restore all types filter */
1392 igb_filter_restore(dev);
1394 eth_igb_rxtx_control(dev, true);
1395 eth_igb_link_update(dev, 0);
1397 PMD_INIT_LOG(DEBUG, "<<");
1401 error_invalid_config:
1402 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1403 dev->data->dev_conf.link_speeds, dev->data->port_id);
1404 igb_dev_clear_queues(dev);
1408 /*********************************************************************
1410 * This routine disables all traffic on the adapter by issuing a
1411 * global reset on the MAC.
1413 **********************************************************************/
1415 eth_igb_stop(struct rte_eth_dev *dev)
1417 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1419 struct rte_eth_link link;
1420 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1421 struct e1000_adapter *adapter =
1422 E1000_DEV_PRIVATE(dev->data->dev_private);
1424 if (adapter->stopped)
1427 eth_igb_rxtx_control(dev, false);
1429 igb_intr_disable(dev);
1431 /* disable intr eventfd mapping */
1432 rte_intr_disable(intr_handle);
1434 igb_pf_reset_hw(hw);
1435 E1000_WRITE_REG(hw, E1000_WUC, 0);
1437 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1438 if (hw->mac.type >= e1000_82580 &&
1439 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1442 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1443 phpm_reg |= E1000_82580_PM_GO_LINKD;
1444 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1447 /* Power down the phy. Needed to make the link go Down */
1448 eth_igb_dev_set_link_down(dev);
1450 igb_dev_clear_queues(dev);
1452 /* clear the recorded link status */
1453 memset(&link, 0, sizeof(link));
1454 rte_eth_linkstatus_set(dev, &link);
1456 if (!rte_intr_allow_others(intr_handle))
1457 /* resume to the default handler */
1458 rte_intr_callback_register(intr_handle,
1459 eth_igb_interrupt_handler,
1462 /* Clean datapath event and queue/vec mapping */
1463 rte_intr_efd_disable(intr_handle);
1464 rte_intr_vec_list_free(intr_handle);
1466 adapter->stopped = true;
1467 dev->data->dev_started = 0;
1473 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1475 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477 if (hw->phy.media_type == e1000_media_type_copper)
1478 e1000_power_up_phy(hw);
1480 e1000_power_up_fiber_serdes_link(hw);
1486 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1488 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490 if (hw->phy.media_type == e1000_media_type_copper)
1491 e1000_power_down_phy(hw);
1493 e1000_shutdown_fiber_serdes_link(hw);
1499 eth_igb_close(struct rte_eth_dev *dev)
1501 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1502 struct rte_eth_link link;
1503 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1504 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1505 struct e1000_filter_info *filter_info =
1506 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1509 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1512 ret = eth_igb_stop(dev);
1514 e1000_phy_hw_reset(hw);
1515 igb_release_manageability(hw);
1516 igb_hw_control_release(hw);
1518 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1519 if (hw->mac.type >= e1000_82580 &&
1520 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1523 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1524 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1525 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1528 igb_dev_free_queues(dev);
1530 /* Cleanup vector list */
1531 rte_intr_vec_list_free(intr_handle);
1533 memset(&link, 0, sizeof(link));
1534 rte_eth_linkstatus_set(dev, &link);
1536 /* Reset any pending lock */
1537 igb_reset_swfw_lock(hw);
1539 /* uninitialize PF if max_vfs not zero */
1540 igb_pf_host_uninit(dev);
1542 rte_intr_callback_unregister(intr_handle,
1543 eth_igb_interrupt_handler, dev);
1545 /* clear the SYN filter info */
1546 filter_info->syn_info = 0;
1548 /* clear the ethertype filters info */
1549 filter_info->ethertype_mask = 0;
1550 memset(filter_info->ethertype_filters, 0,
1551 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1553 /* clear the rss filter info */
1554 memset(&filter_info->rss_info, 0,
1555 sizeof(struct igb_rte_flow_rss_conf));
1557 /* remove all ntuple filters of the device */
1558 igb_ntuple_filter_uninit(dev);
1560 /* remove all flex filters of the device */
1561 igb_flex_filter_uninit(dev);
1563 /* clear all the filters list */
1564 igb_filterlist_flush(dev);
1573 eth_igb_reset(struct rte_eth_dev *dev)
1577 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1578 * its VF to make them align with it. The detailed notification
1579 * mechanism is PMD specific and is currently not implemented.
1580 * To avoid unexpected behavior in VF, currently reset of PF with
1581 * SR-IOV activation is not supported. It might be supported later.
1583 if (dev->data->sriov.active)
1586 ret = eth_igb_dev_uninit(dev);
1590 ret = eth_igb_dev_init(dev);
1597 igb_get_rx_buffer_size(struct e1000_hw *hw)
1599 uint32_t rx_buf_size;
1600 if (hw->mac.type == e1000_82576) {
1601 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1602 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1603 /* PBS needs to be translated according to a lookup table */
1604 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1605 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1606 rx_buf_size = (rx_buf_size << 10);
1607 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1608 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1610 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1616 /*********************************************************************
1618 * Initialize the hardware
1620 **********************************************************************/
1622 igb_hardware_init(struct e1000_hw *hw)
1624 uint32_t rx_buf_size;
1627 /* Let the firmware know the OS is in control */
1628 igb_hw_control_acquire(hw);
1631 * These parameters control the automatic generation (Tx) and
1632 * response (Rx) to Ethernet PAUSE frames.
1633 * - High water mark should allow for at least two standard size (1518)
1634 * frames to be received after sending an XOFF.
1635 * - Low water mark works best when it is very near the high water mark.
1636 * This allows the receiver to restart by sending XON when it has
1637 * drained a bit. Here we use an arbitrary value of 1500 which will
1638 * restart after one full frame is pulled from the buffer. There
1639 * could be several smaller frames in the buffer and if so they will
1640 * not trigger the XON until their total number reduces the buffer
1642 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1644 rx_buf_size = igb_get_rx_buffer_size(hw);
1646 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1647 hw->fc.low_water = hw->fc.high_water - 1500;
1648 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1649 hw->fc.send_xon = 1;
1651 /* Set Flow control, use the tunable location if sane */
1652 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1653 hw->fc.requested_mode = igb_fc_setting;
1655 hw->fc.requested_mode = e1000_fc_none;
1657 /* Issue a global reset */
1658 igb_pf_reset_hw(hw);
1659 E1000_WRITE_REG(hw, E1000_WUC, 0);
1661 diag = e1000_init_hw(hw);
1665 E1000_WRITE_REG(hw, E1000_VET,
1666 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1667 e1000_get_phy_info(hw);
1668 e1000_check_for_link(hw);
1673 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1675 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1679 uint64_t old_gprc = stats->gprc;
1680 uint64_t old_gptc = stats->gptc;
1681 uint64_t old_tpr = stats->tpr;
1682 uint64_t old_tpt = stats->tpt;
1683 uint64_t old_rpthc = stats->rpthc;
1684 uint64_t old_hgptc = stats->hgptc;
1686 if(hw->phy.media_type == e1000_media_type_copper ||
1687 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1689 E1000_READ_REG(hw,E1000_SYMERRS);
1690 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1693 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1694 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1695 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1696 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1698 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1699 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1700 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1701 stats->dc += E1000_READ_REG(hw, E1000_DC);
1702 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1703 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1704 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1706 ** For watchdog management we need to know if we have been
1707 ** paused during the last interval, so capture that here.
1709 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1710 stats->xoffrxc += pause_frames;
1711 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1712 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1713 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1714 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1715 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1716 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1717 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1718 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1719 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1720 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1721 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1722 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1724 /* For the 64-bit byte counters the low dword must be read first. */
1725 /* Both registers clear on the read of the high dword */
1727 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1728 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1729 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1730 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1731 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1732 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1733 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1735 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1736 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1737 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1738 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1739 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1741 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1742 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1744 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1745 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1746 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1747 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1748 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1749 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1751 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1752 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1753 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1754 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1755 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1756 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1757 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1758 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1760 /* Interrupt Counts */
1762 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1763 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1764 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1765 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1766 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1767 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1768 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1769 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1770 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1772 /* Host to Card Statistics */
1774 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1775 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1776 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1777 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1778 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1779 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1780 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1781 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1782 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1783 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1784 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1785 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1786 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1787 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1788 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1789 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1791 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1792 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1793 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1794 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1795 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1796 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1800 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1802 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803 struct e1000_hw_stats *stats =
1804 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1806 igb_read_stats_registers(hw, stats);
1808 if (rte_stats == NULL)
1812 rte_stats->imissed = stats->mpc;
1813 rte_stats->ierrors = stats->crcerrs + stats->rlec +
1814 stats->rxerrc + stats->algnerrc + stats->cexterr;
1817 rte_stats->oerrors = stats->ecol + stats->latecol;
1819 rte_stats->ipackets = stats->gprc;
1820 rte_stats->opackets = stats->gptc;
1821 rte_stats->ibytes = stats->gorc;
1822 rte_stats->obytes = stats->gotc;
1827 eth_igb_stats_reset(struct rte_eth_dev *dev)
1829 struct e1000_hw_stats *hw_stats =
1830 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1832 /* HW registers are cleared on read */
1833 eth_igb_stats_get(dev, NULL);
1835 /* Reset software totals */
1836 memset(hw_stats, 0, sizeof(*hw_stats));
1842 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1844 struct e1000_hw_stats *stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847 /* HW registers are cleared on read */
1848 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1850 /* Reset software totals */
1851 memset(stats, 0, sizeof(*stats));
1856 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1857 struct rte_eth_xstat_name *xstats_names,
1858 __rte_unused unsigned int size)
1862 if (xstats_names == NULL)
1863 return IGB_NB_XSTATS;
1865 /* Note: limit checked in rte_eth_xstats_names() */
1867 for (i = 0; i < IGB_NB_XSTATS; i++) {
1868 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1869 sizeof(xstats_names[i].name));
1872 return IGB_NB_XSTATS;
1875 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1876 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
1882 if (xstats_names == NULL)
1883 return IGB_NB_XSTATS;
1885 for (i = 0; i < IGB_NB_XSTATS; i++)
1886 strlcpy(xstats_names[i].name,
1887 rte_igb_stats_strings[i].name,
1888 sizeof(xstats_names[i].name));
1890 return IGB_NB_XSTATS;
1893 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1895 eth_igb_xstats_get_names_by_id(dev, NULL, xstats_names_copy,
1898 for (i = 0; i < limit; i++) {
1899 if (ids[i] >= IGB_NB_XSTATS) {
1900 PMD_INIT_LOG(ERR, "id value isn't valid");
1903 strcpy(xstats_names[i].name,
1904 xstats_names_copy[ids[i]].name);
1911 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1914 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915 struct e1000_hw_stats *hw_stats =
1916 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1919 if (n < IGB_NB_XSTATS)
1920 return IGB_NB_XSTATS;
1922 igb_read_stats_registers(hw, hw_stats);
1924 /* If this is a reset xstats is NULL, and we have cleared the
1925 * registers by reading them.
1930 /* Extended stats */
1931 for (i = 0; i < IGB_NB_XSTATS; i++) {
1933 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1934 rte_igb_stats_strings[i].offset);
1937 return IGB_NB_XSTATS;
1941 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1942 uint64_t *values, unsigned int n)
1947 struct e1000_hw *hw =
1948 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949 struct e1000_hw_stats *hw_stats =
1950 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1952 if (n < IGB_NB_XSTATS)
1953 return IGB_NB_XSTATS;
1955 igb_read_stats_registers(hw, hw_stats);
1957 /* If this is a reset xstats is NULL, and we have cleared the
1958 * registers by reading them.
1963 /* Extended stats */
1964 for (i = 0; i < IGB_NB_XSTATS; i++)
1965 values[i] = *(uint64_t *)(((char *)hw_stats) +
1966 rte_igb_stats_strings[i].offset);
1968 return IGB_NB_XSTATS;
1971 uint64_t values_copy[IGB_NB_XSTATS];
1973 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1976 for (i = 0; i < n; i++) {
1977 if (ids[i] >= IGB_NB_XSTATS) {
1978 PMD_INIT_LOG(ERR, "id value isn't valid");
1981 values[i] = values_copy[ids[i]];
1988 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1990 /* Good Rx packets, include VF loopback */
1991 UPDATE_VF_STAT(E1000_VFGPRC,
1992 hw_stats->last_gprc, hw_stats->gprc);
1994 /* Good Rx octets, include VF loopback */
1995 UPDATE_VF_STAT(E1000_VFGORC,
1996 hw_stats->last_gorc, hw_stats->gorc);
1998 /* Good Tx packets, include VF loopback */
1999 UPDATE_VF_STAT(E1000_VFGPTC,
2000 hw_stats->last_gptc, hw_stats->gptc);
2002 /* Good Tx octets, include VF loopback */
2003 UPDATE_VF_STAT(E1000_VFGOTC,
2004 hw_stats->last_gotc, hw_stats->gotc);
2006 /* Rx Multicst packets */
2007 UPDATE_VF_STAT(E1000_VFMPRC,
2008 hw_stats->last_mprc, hw_stats->mprc);
2010 /* Good Rx loopback packets */
2011 UPDATE_VF_STAT(E1000_VFGPRLBC,
2012 hw_stats->last_gprlbc, hw_stats->gprlbc);
2014 /* Good Rx loopback octets */
2015 UPDATE_VF_STAT(E1000_VFGORLBC,
2016 hw_stats->last_gorlbc, hw_stats->gorlbc);
2018 /* Good Tx loopback packets */
2019 UPDATE_VF_STAT(E1000_VFGPTLBC,
2020 hw_stats->last_gptlbc, hw_stats->gptlbc);
2022 /* Good Tx loopback octets */
2023 UPDATE_VF_STAT(E1000_VFGOTLBC,
2024 hw_stats->last_gotlbc, hw_stats->gotlbc);
2027 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2028 struct rte_eth_xstat_name *xstats_names,
2029 __rte_unused unsigned limit)
2033 if (xstats_names != NULL)
2034 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2035 strlcpy(xstats_names[i].name,
2036 rte_igbvf_stats_strings[i].name,
2037 sizeof(xstats_names[i].name));
2039 return IGBVF_NB_XSTATS;
2043 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2048 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2051 if (n < IGBVF_NB_XSTATS)
2052 return IGBVF_NB_XSTATS;
2054 igbvf_read_stats_registers(hw, hw_stats);
2059 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2061 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2062 rte_igbvf_stats_strings[i].offset);
2065 return IGBVF_NB_XSTATS;
2069 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2071 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2073 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2075 igbvf_read_stats_registers(hw, hw_stats);
2077 if (rte_stats == NULL)
2080 rte_stats->ipackets = hw_stats->gprc;
2081 rte_stats->ibytes = hw_stats->gorc;
2082 rte_stats->opackets = hw_stats->gptc;
2083 rte_stats->obytes = hw_stats->gotc;
2088 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2090 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2091 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2093 /* Sync HW register to the last stats */
2094 eth_igbvf_stats_get(dev, NULL);
2096 /* reset HW current stats*/
2097 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2098 offsetof(struct e1000_vf_stats, gprc));
2104 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2107 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108 struct e1000_fw_version fw;
2111 e1000_get_fw_version(hw, &fw);
2113 switch (hw->mac.type) {
2116 if (!(e1000_get_flash_presence_i210(hw))) {
2117 ret = snprintf(fw_version, fw_size,
2119 fw.invm_major, fw.invm_minor,
2125 /* if option rom is valid, display its version too */
2127 ret = snprintf(fw_version, fw_size,
2128 "%d.%d, 0x%08x, %d.%d.%d",
2129 fw.eep_major, fw.eep_minor, fw.etrack_id,
2130 fw.or_major, fw.or_build, fw.or_patch);
2133 if (fw.etrack_id != 0X0000) {
2134 ret = snprintf(fw_version, fw_size,
2136 fw.eep_major, fw.eep_minor,
2139 ret = snprintf(fw_version, fw_size,
2141 fw.eep_major, fw.eep_minor,
2150 ret += 1; /* add the size of '\0' */
2151 if (fw_size < (size_t)ret)
2158 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2160 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2163 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2164 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2165 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2166 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2167 dev_info->rx_queue_offload_capa;
2168 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2169 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2170 dev_info->tx_queue_offload_capa;
2172 switch (hw->mac.type) {
2174 dev_info->max_rx_queues = 4;
2175 dev_info->max_tx_queues = 4;
2176 dev_info->max_vmdq_pools = 0;
2180 dev_info->max_rx_queues = 16;
2181 dev_info->max_tx_queues = 16;
2182 dev_info->max_vmdq_pools = RTE_ETH_8_POOLS;
2183 dev_info->vmdq_queue_num = 16;
2187 dev_info->max_rx_queues = 8;
2188 dev_info->max_tx_queues = 8;
2189 dev_info->max_vmdq_pools = RTE_ETH_8_POOLS;
2190 dev_info->vmdq_queue_num = 8;
2194 dev_info->max_rx_queues = 8;
2195 dev_info->max_tx_queues = 8;
2196 dev_info->max_vmdq_pools = RTE_ETH_8_POOLS;
2197 dev_info->vmdq_queue_num = 8;
2201 dev_info->max_rx_queues = 8;
2202 dev_info->max_tx_queues = 8;
2206 dev_info->max_rx_queues = 4;
2207 dev_info->max_tx_queues = 4;
2208 dev_info->max_vmdq_pools = 0;
2212 dev_info->max_rx_queues = 2;
2213 dev_info->max_tx_queues = 2;
2214 dev_info->max_vmdq_pools = 0;
2218 /* Should not happen */
2221 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2222 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128;
2223 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2225 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2227 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2228 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2229 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2231 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2236 dev_info->default_txconf = (struct rte_eth_txconf) {
2238 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2239 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2240 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2245 dev_info->rx_desc_lim = rx_desc_lim;
2246 dev_info->tx_desc_lim = tx_desc_lim;
2248 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD | RTE_ETH_LINK_SPEED_10M |
2249 RTE_ETH_LINK_SPEED_100M_HD | RTE_ETH_LINK_SPEED_100M |
2250 RTE_ETH_LINK_SPEED_1G;
2252 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2253 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2258 static const uint32_t *
2259 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2261 static const uint32_t ptypes[] = {
2262 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2265 RTE_PTYPE_L3_IPV4_EXT,
2267 RTE_PTYPE_L3_IPV6_EXT,
2271 RTE_PTYPE_TUNNEL_IP,
2272 RTE_PTYPE_INNER_L3_IPV6,
2273 RTE_PTYPE_INNER_L3_IPV6_EXT,
2274 RTE_PTYPE_INNER_L4_TCP,
2275 RTE_PTYPE_INNER_L4_UDP,
2279 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2280 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2286 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2288 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2290 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2291 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2292 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2293 dev_info->tx_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
2294 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2295 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2296 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2297 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2298 RTE_ETH_TX_OFFLOAD_TCP_TSO;
2299 switch (hw->mac.type) {
2301 dev_info->max_rx_queues = 2;
2302 dev_info->max_tx_queues = 2;
2304 case e1000_vfadapt_i350:
2305 dev_info->max_rx_queues = 1;
2306 dev_info->max_tx_queues = 1;
2309 /* Should not happen */
2313 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2314 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2315 dev_info->rx_queue_offload_capa;
2316 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2317 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2318 dev_info->tx_queue_offload_capa;
2320 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2322 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2323 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2324 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2326 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2331 dev_info->default_txconf = (struct rte_eth_txconf) {
2333 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2334 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2335 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2340 dev_info->rx_desc_lim = rx_desc_lim;
2341 dev_info->tx_desc_lim = tx_desc_lim;
2346 /* return 0 means link status changed, -1 means not changed */
2348 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2350 struct e1000_hw *hw =
2351 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352 struct rte_eth_link link;
2353 int link_check, count;
2356 hw->mac.get_link_status = 1;
2358 /* possible wait-to-complete in up to 9 seconds */
2359 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2360 /* Read the real link status */
2361 switch (hw->phy.media_type) {
2362 case e1000_media_type_copper:
2363 /* Do the work to read phy */
2364 e1000_check_for_link(hw);
2365 link_check = !hw->mac.get_link_status;
2368 case e1000_media_type_fiber:
2369 e1000_check_for_link(hw);
2370 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2374 case e1000_media_type_internal_serdes:
2375 e1000_check_for_link(hw);
2376 link_check = hw->mac.serdes_has_link;
2379 /* VF device is type_unknown */
2380 case e1000_media_type_unknown:
2381 eth_igbvf_link_update(hw);
2382 link_check = !hw->mac.get_link_status;
2388 if (link_check || wait_to_complete == 0)
2390 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2392 memset(&link, 0, sizeof(link));
2394 /* Now we check if a transition has happened */
2396 uint16_t duplex, speed;
2397 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2398 link.link_duplex = (duplex == FULL_DUPLEX) ?
2399 RTE_ETH_LINK_FULL_DUPLEX :
2400 RTE_ETH_LINK_HALF_DUPLEX;
2401 link.link_speed = speed;
2402 link.link_status = RTE_ETH_LINK_UP;
2403 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2404 RTE_ETH_LINK_SPEED_FIXED);
2405 } else if (!link_check) {
2406 link.link_speed = 0;
2407 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
2408 link.link_status = RTE_ETH_LINK_DOWN;
2409 link.link_autoneg = RTE_ETH_LINK_FIXED;
2412 return rte_eth_linkstatus_set(dev, &link);
2416 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2417 * For ASF and Pass Through versions of f/w this means
2418 * that the driver is loaded.
2421 igb_hw_control_acquire(struct e1000_hw *hw)
2425 /* Let firmware know the driver has taken over */
2426 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2427 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2431 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2432 * For ASF and Pass Through versions of f/w this means that the
2433 * driver is no longer loaded.
2436 igb_hw_control_release(struct e1000_hw *hw)
2440 /* Let firmware taken over control of h/w */
2441 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2442 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2443 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2447 * Bit of a misnomer, what this really means is
2448 * to enable OS management of the system... aka
2449 * to disable special hardware management features.
2452 igb_init_manageability(struct e1000_hw *hw)
2454 if (e1000_enable_mng_pass_thru(hw)) {
2455 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2456 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2458 /* disable hardware interception of ARP */
2459 manc &= ~(E1000_MANC_ARP_EN);
2461 /* enable receiving management packets to the host */
2462 manc |= E1000_MANC_EN_MNG2HOST;
2463 manc2h |= 1 << 5; /* Mng Port 623 */
2464 manc2h |= 1 << 6; /* Mng Port 664 */
2465 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2466 E1000_WRITE_REG(hw, E1000_MANC, manc);
2471 igb_release_manageability(struct e1000_hw *hw)
2473 if (e1000_enable_mng_pass_thru(hw)) {
2474 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2476 manc |= E1000_MANC_ARP_EN;
2477 manc &= ~E1000_MANC_EN_MNG2HOST;
2479 E1000_WRITE_REG(hw, E1000_MANC, manc);
2484 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2486 struct e1000_hw *hw =
2487 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 rctl = E1000_READ_REG(hw, E1000_RCTL);
2491 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2492 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2498 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2500 struct e1000_hw *hw =
2501 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504 rctl = E1000_READ_REG(hw, E1000_RCTL);
2505 rctl &= (~E1000_RCTL_UPE);
2506 if (dev->data->all_multicast == 1)
2507 rctl |= E1000_RCTL_MPE;
2509 rctl &= (~E1000_RCTL_MPE);
2510 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2516 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2518 struct e1000_hw *hw =
2519 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 rctl = E1000_READ_REG(hw, E1000_RCTL);
2523 rctl |= E1000_RCTL_MPE;
2524 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2530 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2532 struct e1000_hw *hw =
2533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 if (dev->data->promiscuous == 1)
2537 return 0; /* must remain in all_multicast mode */
2538 rctl = E1000_READ_REG(hw, E1000_RCTL);
2539 rctl &= (~E1000_RCTL_MPE);
2540 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2548 struct e1000_hw *hw =
2549 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550 struct e1000_vfta * shadow_vfta =
2551 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2556 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2557 E1000_VFTA_ENTRY_MASK);
2558 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2559 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2564 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2566 /* update local VFTA copy */
2567 shadow_vfta->vfta[vid_idx] = vfta;
2573 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2574 enum rte_vlan_type vlan_type,
2577 struct e1000_hw *hw =
2578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2582 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2584 /* only outer TPID of double VLAN can be configured*/
2585 if (qinq && vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2586 reg = E1000_READ_REG(hw, E1000_VET);
2587 reg = (reg & (~E1000_VET_VET_EXT)) |
2588 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2589 E1000_WRITE_REG(hw, E1000_VET, reg);
2594 /* all other TPID values are read-only*/
2595 PMD_DRV_LOG(ERR, "Not supported");
2601 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2603 struct e1000_hw *hw =
2604 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607 /* Filter Table Disable */
2608 reg = E1000_READ_REG(hw, E1000_RCTL);
2609 reg &= ~E1000_RCTL_CFIEN;
2610 reg &= ~E1000_RCTL_VFE;
2611 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2615 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2617 struct e1000_hw *hw =
2618 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619 struct e1000_vfta * shadow_vfta =
2620 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2624 /* Filter Table Enable, CFI not used for packet acceptance */
2625 reg = E1000_READ_REG(hw, E1000_RCTL);
2626 reg &= ~E1000_RCTL_CFIEN;
2627 reg |= E1000_RCTL_VFE;
2628 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2630 /* restore VFTA table */
2631 for (i = 0; i < IGB_VFTA_SIZE; i++)
2632 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2636 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 /* VLAN Mode Disable */
2643 reg = E1000_READ_REG(hw, E1000_CTRL);
2644 reg &= ~E1000_CTRL_VME;
2645 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2649 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2651 struct e1000_hw *hw =
2652 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655 /* VLAN Mode Enable */
2656 reg = E1000_READ_REG(hw, E1000_CTRL);
2657 reg |= E1000_CTRL_VME;
2658 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2662 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2664 struct e1000_hw *hw =
2665 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 /* CTRL_EXT: Extended VLAN */
2669 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2670 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2671 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2673 /* Update maximum packet length */
2674 E1000_WRITE_REG(hw, E1000_RLPML, dev->data->mtu + E1000_ETH_OVERHEAD);
2678 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2680 struct e1000_hw *hw =
2681 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684 /* CTRL_EXT: Extended VLAN */
2685 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2686 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2687 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2689 /* Update maximum packet length */
2690 E1000_WRITE_REG(hw, E1000_RLPML,
2691 dev->data->mtu + E1000_ETH_OVERHEAD + VLAN_TAG_SIZE);
2695 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2697 struct rte_eth_rxmode *rxmode;
2699 rxmode = &dev->data->dev_conf.rxmode;
2700 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2701 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
2702 igb_vlan_hw_strip_enable(dev);
2704 igb_vlan_hw_strip_disable(dev);
2707 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2708 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
2709 igb_vlan_hw_filter_enable(dev);
2711 igb_vlan_hw_filter_disable(dev);
2714 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2715 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2716 igb_vlan_hw_extend_enable(dev);
2718 igb_vlan_hw_extend_disable(dev);
2726 * It enables the interrupt mask and then enable the interrupt.
2729 * Pointer to struct rte_eth_dev.
2734 * - On success, zero.
2735 * - On failure, a negative value.
2738 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2740 struct e1000_interrupt *intr =
2741 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2744 intr->mask |= E1000_ICR_LSC;
2746 intr->mask &= ~E1000_ICR_LSC;
2751 /* It clears the interrupt causes and enables the interrupt.
2752 * It will be called once only during nic initialized.
2755 * Pointer to struct rte_eth_dev.
2758 * - On success, zero.
2759 * - On failure, a negative value.
2761 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2763 uint32_t mask, regval;
2765 struct e1000_hw *hw =
2766 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2768 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2769 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2770 struct rte_eth_dev_info dev_info;
2772 memset(&dev_info, 0, sizeof(dev_info));
2773 ret = eth_igb_infos_get(dev, &dev_info);
2777 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2778 regval = E1000_READ_REG(hw, E1000_EIMS);
2779 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2785 * It reads ICR and gets interrupt causes, check it and set a bit flag
2786 * to update link status.
2789 * Pointer to struct rte_eth_dev.
2792 * - On success, zero.
2793 * - On failure, a negative value.
2796 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2799 struct e1000_hw *hw =
2800 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801 struct e1000_interrupt *intr =
2802 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2804 igb_intr_disable(dev);
2806 /* read-on-clear nic registers here */
2807 icr = E1000_READ_REG(hw, E1000_ICR);
2810 if (icr & E1000_ICR_LSC) {
2811 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2814 if (icr & E1000_ICR_VMMB)
2815 intr->flags |= E1000_FLAG_MAILBOX;
2821 * It executes link_update after knowing an interrupt is prsent.
2824 * Pointer to struct rte_eth_dev.
2827 * - On success, zero.
2828 * - On failure, a negative value.
2831 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2832 struct rte_intr_handle *intr_handle)
2834 struct e1000_hw *hw =
2835 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836 struct e1000_interrupt *intr =
2837 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2838 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2839 struct rte_eth_link link;
2842 if (intr->flags & E1000_FLAG_MAILBOX) {
2843 igb_pf_mbx_process(dev);
2844 intr->flags &= ~E1000_FLAG_MAILBOX;
2847 igb_intr_enable(dev);
2848 rte_intr_ack(intr_handle);
2850 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2851 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2853 /* set get_link_status to check register later */
2854 hw->mac.get_link_status = 1;
2855 ret = eth_igb_link_update(dev, 0);
2857 /* check if link has changed */
2861 rte_eth_linkstatus_get(dev, &link);
2862 if (link.link_status) {
2864 " Port %d: Link Up - speed %u Mbps - %s",
2866 (unsigned)link.link_speed,
2867 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
2868 "full-duplex" : "half-duplex");
2870 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2871 dev->data->port_id);
2874 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2875 pci_dev->addr.domain,
2877 pci_dev->addr.devid,
2878 pci_dev->addr.function);
2879 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2886 * Interrupt handler which shall be registered at first.
2889 * Pointer to interrupt handle.
2891 * The address of parameter (struct rte_eth_dev *) regsitered before.
2897 eth_igb_interrupt_handler(void *param)
2899 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2901 eth_igb_interrupt_get_status(dev);
2902 eth_igb_interrupt_action(dev, dev->intr_handle);
2906 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2909 struct e1000_hw *hw =
2910 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911 struct e1000_interrupt *intr =
2912 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2914 igbvf_intr_disable(hw);
2916 /* read-on-clear nic registers here */
2917 eicr = E1000_READ_REG(hw, E1000_EICR);
2920 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2921 intr->flags |= E1000_FLAG_MAILBOX;
2926 void igbvf_mbx_process(struct rte_eth_dev *dev)
2928 struct e1000_hw *hw =
2929 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930 struct e1000_mbx_info *mbx = &hw->mbx;
2933 /* peek the message first */
2934 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2936 /* PF reset VF event */
2937 if (in_msg == E1000_PF_CONTROL_MSG) {
2938 /* dummy mbx read to ack pf */
2939 if (mbx->ops.read(hw, &in_msg, 1, 0))
2941 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2947 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2949 struct e1000_interrupt *intr =
2950 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2952 if (intr->flags & E1000_FLAG_MAILBOX) {
2953 igbvf_mbx_process(dev);
2954 intr->flags &= ~E1000_FLAG_MAILBOX;
2957 igbvf_intr_enable(dev);
2958 rte_intr_ack(intr_handle);
2964 eth_igbvf_interrupt_handler(void *param)
2966 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2968 eth_igbvf_interrupt_get_status(dev);
2969 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2973 eth_igb_led_on(struct rte_eth_dev *dev)
2975 struct e1000_hw *hw;
2977 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2982 eth_igb_led_off(struct rte_eth_dev *dev)
2984 struct e1000_hw *hw;
2986 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2987 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2991 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2993 struct e1000_hw *hw;
2998 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999 fc_conf->pause_time = hw->fc.pause_time;
3000 fc_conf->high_water = hw->fc.high_water;
3001 fc_conf->low_water = hw->fc.low_water;
3002 fc_conf->send_xon = hw->fc.send_xon;
3003 fc_conf->autoneg = hw->mac.autoneg;
3006 * Return rx_pause and tx_pause status according to actual setting of
3007 * the TFCE and RFCE bits in the CTRL register.
3009 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3010 if (ctrl & E1000_CTRL_TFCE)
3015 if (ctrl & E1000_CTRL_RFCE)
3020 if (rx_pause && tx_pause)
3021 fc_conf->mode = RTE_ETH_FC_FULL;
3023 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
3025 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
3027 fc_conf->mode = RTE_ETH_FC_NONE;
3033 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3035 struct e1000_hw *hw;
3037 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3043 uint32_t rx_buf_size;
3044 uint32_t max_high_water;
3048 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049 if (fc_conf->autoneg != hw->mac.autoneg)
3051 rx_buf_size = igb_get_rx_buffer_size(hw);
3052 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3054 /* At least reserve one Ethernet frame for watermark */
3055 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3056 if ((fc_conf->high_water > max_high_water) ||
3057 (fc_conf->high_water < fc_conf->low_water)) {
3058 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3059 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3063 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3064 hw->fc.pause_time = fc_conf->pause_time;
3065 hw->fc.high_water = fc_conf->high_water;
3066 hw->fc.low_water = fc_conf->low_water;
3067 hw->fc.send_xon = fc_conf->send_xon;
3069 err = e1000_setup_link_generic(hw);
3070 if (err == E1000_SUCCESS) {
3072 /* check if we want to forward MAC frames - driver doesn't have native
3073 * capability to do that, so we'll write the registers ourselves */
3075 rctl = E1000_READ_REG(hw, E1000_RCTL);
3077 /* set or clear MFLCN.PMCF bit depending on configuration */
3078 if (fc_conf->mac_ctrl_frame_fwd != 0)
3079 rctl |= E1000_RCTL_PMCF;
3081 rctl &= ~E1000_RCTL_PMCF;
3083 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3086 * check if we want to change flow control mode - driver doesn't have native
3087 * capability to do that, so we'll write the registers ourselves
3089 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3092 * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending
3095 switch (fc_conf->mode) {
3096 case RTE_ETH_FC_NONE:
3097 ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE;
3099 case RTE_ETH_FC_RX_PAUSE:
3100 ctrl |= E1000_CTRL_RFCE;
3101 ctrl &= ~E1000_CTRL_TFCE;
3103 case RTE_ETH_FC_TX_PAUSE:
3104 ctrl |= E1000_CTRL_TFCE;
3105 ctrl &= ~E1000_CTRL_RFCE;
3107 case RTE_ETH_FC_FULL:
3108 ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE;
3111 PMD_INIT_LOG(ERR, "invalid flow control mode");
3115 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3117 E1000_WRITE_FLUSH(hw);
3122 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3126 #define E1000_RAH_POOLSEL_SHIFT (18)
3128 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3129 uint32_t index, uint32_t pool)
3131 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3134 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3135 rah = E1000_READ_REG(hw, E1000_RAH(index));
3136 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3137 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3142 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3144 uint8_t addr[RTE_ETHER_ADDR_LEN];
3145 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3147 memset(addr, 0, sizeof(addr));
3149 e1000_rar_set(hw, addr, index);
3153 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3154 struct rte_ether_addr *addr)
3156 eth_igb_rar_clear(dev, 0);
3157 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3162 * Virtual Function operations
3165 igbvf_intr_disable(struct e1000_hw *hw)
3167 PMD_INIT_FUNC_TRACE();
3169 /* Clear interrupt mask to stop from interrupts being generated */
3170 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3172 E1000_WRITE_FLUSH(hw);
3176 igbvf_stop_adapter(struct rte_eth_dev *dev)
3180 struct rte_eth_dev_info dev_info;
3181 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184 memset(&dev_info, 0, sizeof(dev_info));
3185 ret = eth_igbvf_infos_get(dev, &dev_info);
3189 /* Clear interrupt mask to stop from interrupts being generated */
3190 igbvf_intr_disable(hw);
3192 /* Clear any pending interrupts, flush previous writes */
3193 E1000_READ_REG(hw, E1000_EICR);
3195 /* Disable the transmit unit. Each queue must be disabled. */
3196 for (i = 0; i < dev_info.max_tx_queues; i++)
3197 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3199 /* Disable the receive unit by stopping each queue */
3200 for (i = 0; i < dev_info.max_rx_queues; i++) {
3201 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3202 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3203 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3204 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3208 /* flush all queues disables */
3209 E1000_WRITE_FLUSH(hw);
3213 static int eth_igbvf_link_update(struct e1000_hw *hw)
3215 struct e1000_mbx_info *mbx = &hw->mbx;
3216 struct e1000_mac_info *mac = &hw->mac;
3217 int ret_val = E1000_SUCCESS;
3219 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3222 * We only want to run this if there has been a rst asserted.
3223 * in this case that could mean a link change, device reset,
3224 * or a virtual function reset
3227 /* If we were hit with a reset or timeout drop the link */
3228 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3229 mac->get_link_status = TRUE;
3231 if (!mac->get_link_status)
3234 /* if link status is down no point in checking to see if pf is up */
3235 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3238 /* if we passed all the tests above then the link is up and we no
3239 * longer need to check for link */
3240 mac->get_link_status = FALSE;
3248 igbvf_dev_configure(struct rte_eth_dev *dev)
3250 struct rte_eth_conf* conf = &dev->data->dev_conf;
3252 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3253 dev->data->port_id);
3255 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
3256 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
3259 * VF has no ability to enable/disable HW CRC
3260 * Keep the persistent behavior the same as Host PF
3262 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3263 if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
3264 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3265 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC;
3268 if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) {
3269 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3270 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC;
3278 igbvf_dev_start(struct rte_eth_dev *dev)
3280 struct e1000_hw *hw =
3281 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282 struct e1000_adapter *adapter =
3283 E1000_DEV_PRIVATE(dev->data->dev_private);
3284 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3285 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3287 uint32_t intr_vector = 0;
3289 PMD_INIT_FUNC_TRACE();
3291 hw->mac.ops.reset_hw(hw);
3292 adapter->stopped = 0;
3295 igbvf_set_vfta_all(dev,1);
3297 eth_igbvf_tx_init(dev);
3299 /* This can fail when allocating mbufs for descriptor rings */
3300 ret = eth_igbvf_rx_init(dev);
3302 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3303 igb_dev_clear_queues(dev);
3307 /* check and configure queue intr-vector mapping */
3308 if (rte_intr_cap_multiple(intr_handle) &&
3309 dev->data->dev_conf.intr_conf.rxq) {
3310 intr_vector = dev->data->nb_rx_queues;
3311 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3316 /* Allocate the vector list */
3317 if (rte_intr_dp_is_en(intr_handle)) {
3318 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3319 dev->data->nb_rx_queues)) {
3320 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3321 " intr_vec", dev->data->nb_rx_queues);
3326 eth_igbvf_configure_msix_intr(dev);
3328 /* enable uio/vfio intr/eventfd mapping */
3329 rte_intr_enable(intr_handle);
3331 /* resume enabled intr since hw reset */
3332 igbvf_intr_enable(dev);
3338 igbvf_dev_stop(struct rte_eth_dev *dev)
3340 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3341 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3342 struct e1000_adapter *adapter =
3343 E1000_DEV_PRIVATE(dev->data->dev_private);
3345 if (adapter->stopped)
3348 PMD_INIT_FUNC_TRACE();
3350 igbvf_stop_adapter(dev);
3353 * Clear what we set, but we still keep shadow_vfta to
3354 * restore after device starts
3356 igbvf_set_vfta_all(dev,0);
3358 igb_dev_clear_queues(dev);
3360 /* disable intr eventfd mapping */
3361 rte_intr_disable(intr_handle);
3363 /* Clean datapath event and queue/vec mapping */
3364 rte_intr_efd_disable(intr_handle);
3366 /* Clean vector list */
3367 rte_intr_vec_list_free(intr_handle);
3369 adapter->stopped = true;
3370 dev->data->dev_started = 0;
3376 igbvf_dev_close(struct rte_eth_dev *dev)
3378 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379 struct rte_ether_addr addr;
3380 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3383 PMD_INIT_FUNC_TRACE();
3385 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3390 ret = igbvf_dev_stop(dev);
3394 igb_dev_free_queues(dev);
3397 * reprogram the RAR with a zero mac address,
3398 * to ensure that the VF traffic goes to the PF
3399 * after stop, close and detach of the VF.
3402 memset(&addr, 0, sizeof(addr));
3403 igbvf_default_mac_addr_set(dev, &addr);
3405 rte_intr_callback_unregister(pci_dev->intr_handle,
3406 eth_igbvf_interrupt_handler,
3413 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3415 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417 /* Set both unicast and multicast promisc */
3418 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3424 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3426 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428 /* If in allmulticast mode leave multicast promisc */
3429 if (dev->data->all_multicast == 1)
3430 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3432 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3438 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3440 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 /* In promiscuous mode multicast promisc already set */
3443 if (dev->data->promiscuous == 0)
3444 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3450 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3452 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454 /* In promiscuous mode leave multicast promisc enabled */
3455 if (dev->data->promiscuous == 0)
3456 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3461 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3463 struct e1000_mbx_info *mbx = &hw->mbx;
3467 /* After set vlan, vlan strip will also be enabled in igb driver*/
3468 msgbuf[0] = E1000_VF_SET_VLAN;
3470 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3472 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3474 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3478 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3482 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3483 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3490 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3492 struct e1000_hw *hw =
3493 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494 struct e1000_vfta * shadow_vfta =
3495 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3496 int i = 0, j = 0, vfta = 0, mask = 1;
3498 for (i = 0; i < IGB_VFTA_SIZE; i++){
3499 vfta = shadow_vfta->vfta[i];
3502 for (j = 0; j < 32; j++){
3505 (uint16_t)((i<<5)+j), on);
3514 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3516 struct e1000_hw *hw =
3517 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 struct e1000_vfta * shadow_vfta =
3519 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3520 uint32_t vid_idx = 0;
3521 uint32_t vid_bit = 0;
3524 PMD_INIT_FUNC_TRACE();
3526 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3527 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3529 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3532 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3533 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3535 /*Save what we set and retore it after device reset*/
3537 shadow_vfta->vfta[vid_idx] |= vid_bit;
3539 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3545 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3547 struct e1000_hw *hw =
3548 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550 /* index is not used by rar_set() */
3551 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3557 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3558 struct rte_eth_rss_reta_entry64 *reta_conf,
3563 uint16_t idx, shift;
3564 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3566 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) {
3567 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3568 "(%d) doesn't match the number hardware can supported "
3569 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128);
3573 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3574 idx = i / RTE_ETH_RETA_GROUP_SIZE;
3575 shift = i % RTE_ETH_RETA_GROUP_SIZE;
3576 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3580 if (mask == IGB_4_BIT_MASK)
3583 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3584 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3585 if (mask & (0x1 << j))
3586 reta |= reta_conf[idx].reta[shift + j] <<
3589 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3591 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3598 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3599 struct rte_eth_rss_reta_entry64 *reta_conf,
3604 uint16_t idx, shift;
3605 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) {
3608 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3609 "(%d) doesn't match the number hardware can supported "
3610 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128);
3614 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3615 idx = i / RTE_ETH_RETA_GROUP_SIZE;
3616 shift = i % RTE_ETH_RETA_GROUP_SIZE;
3617 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3621 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3622 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3623 if (mask & (0x1 << j))
3624 reta_conf[idx].reta[shift + j] =
3625 ((reta >> (CHAR_BIT * j)) &
3634 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3635 struct rte_eth_syn_filter *filter,
3638 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639 struct e1000_filter_info *filter_info =
3640 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3641 uint32_t synqf, rfctl;
3643 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3646 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3649 if (synqf & E1000_SYN_FILTER_ENABLE)
3652 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3653 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3655 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3656 if (filter->hig_pri)
3657 rfctl |= E1000_RFCTL_SYNQFP;
3659 rfctl &= ~E1000_RFCTL_SYNQFP;
3661 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3663 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3668 filter_info->syn_info = synqf;
3669 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3670 E1000_WRITE_FLUSH(hw);
3674 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3676 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3677 struct e1000_2tuple_filter_info *filter_info)
3679 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3681 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3682 return -EINVAL; /* filter index is out of range. */
3683 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3684 return -EINVAL; /* flags is invalid. */
3686 switch (filter->dst_port_mask) {
3688 filter_info->dst_port_mask = 0;
3689 filter_info->dst_port = filter->dst_port;
3692 filter_info->dst_port_mask = 1;
3695 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3699 switch (filter->proto_mask) {
3701 filter_info->proto_mask = 0;
3702 filter_info->proto = filter->proto;
3705 filter_info->proto_mask = 1;
3708 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3712 filter_info->priority = (uint8_t)filter->priority;
3713 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3714 filter_info->tcp_flags = filter->tcp_flags;
3716 filter_info->tcp_flags = 0;
3721 static inline struct e1000_2tuple_filter *
3722 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3723 struct e1000_2tuple_filter_info *key)
3725 struct e1000_2tuple_filter *it;
3727 TAILQ_FOREACH(it, filter_list, entries) {
3728 if (memcmp(key, &it->filter_info,
3729 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3736 /* inject a igb 2tuple filter to HW */
3738 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3739 struct e1000_2tuple_filter *filter)
3741 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3743 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3747 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3748 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3749 imir |= E1000_IMIR_PORT_BP;
3751 imir &= ~E1000_IMIR_PORT_BP;
3753 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3755 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3756 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3757 ttqf |= (uint32_t)(filter->filter_info.proto &
3758 E1000_TTQF_PROTOCOL_MASK);
3759 if (filter->filter_info.proto_mask == 0)
3760 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3762 /* tcp flags bits setting. */
3763 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3764 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3765 imir_ext |= E1000_IMIREXT_CTRL_URG;
3766 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3767 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3768 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3769 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3770 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3771 imir_ext |= E1000_IMIREXT_CTRL_RST;
3772 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3773 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3774 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3775 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3777 imir_ext |= E1000_IMIREXT_CTRL_BP;
3779 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3780 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3781 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3785 * igb_add_2tuple_filter - add a 2tuple filter
3788 * dev: Pointer to struct rte_eth_dev.
3789 * ntuple_filter: ponter to the filter that will be added.
3792 * - On success, zero.
3793 * - On failure, a negative value.
3796 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3797 struct rte_eth_ntuple_filter *ntuple_filter)
3799 struct e1000_filter_info *filter_info =
3800 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3801 struct e1000_2tuple_filter *filter;
3804 filter = rte_zmalloc("e1000_2tuple_filter",
3805 sizeof(struct e1000_2tuple_filter), 0);
3809 ret = ntuple_filter_to_2tuple(ntuple_filter,
3810 &filter->filter_info);
3815 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3816 &filter->filter_info) != NULL) {
3817 PMD_DRV_LOG(ERR, "filter exists.");
3821 filter->queue = ntuple_filter->queue;
3824 * look for an unused 2tuple filter index,
3825 * and insert the filter to list.
3827 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3828 if (!(filter_info->twotuple_mask & (1 << i))) {
3829 filter_info->twotuple_mask |= 1 << i;
3831 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3837 if (i >= E1000_MAX_TTQF_FILTERS) {
3838 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3843 igb_inject_2uple_filter(dev, filter);
3848 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3849 struct e1000_2tuple_filter *filter)
3851 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852 struct e1000_filter_info *filter_info =
3853 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3855 filter_info->twotuple_mask &= ~(1 << filter->index);
3856 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3859 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3860 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3861 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3866 * igb_remove_2tuple_filter - remove a 2tuple filter
3869 * dev: Pointer to struct rte_eth_dev.
3870 * ntuple_filter: ponter to the filter that will be removed.
3873 * - On success, zero.
3874 * - On failure, a negative value.
3877 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3878 struct rte_eth_ntuple_filter *ntuple_filter)
3880 struct e1000_filter_info *filter_info =
3881 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3882 struct e1000_2tuple_filter_info filter_2tuple;
3883 struct e1000_2tuple_filter *filter;
3886 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3887 ret = ntuple_filter_to_2tuple(ntuple_filter,
3892 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3894 if (filter == NULL) {
3895 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3899 igb_delete_2tuple_filter(dev, filter);
3904 /* inject a igb flex filter to HW */
3906 igb_inject_flex_filter(struct rte_eth_dev *dev,
3907 struct e1000_flex_filter *filter)
3909 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910 uint32_t wufc, queueing;
3914 wufc = E1000_READ_REG(hw, E1000_WUFC);
3915 if (filter->index < E1000_MAX_FHFT)
3916 reg_off = E1000_FHFT(filter->index);
3918 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3920 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3921 (E1000_WUFC_FLX0 << filter->index));
3922 queueing = filter->filter_info.len |
3923 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3924 (filter->filter_info.priority <<
3925 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3926 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3929 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3930 E1000_WRITE_REG(hw, reg_off,
3931 filter->filter_info.dwords[j]);
3932 reg_off += sizeof(uint32_t);
3933 E1000_WRITE_REG(hw, reg_off,
3934 filter->filter_info.dwords[++j]);
3935 reg_off += sizeof(uint32_t);
3936 E1000_WRITE_REG(hw, reg_off,
3937 (uint32_t)filter->filter_info.mask[i]);
3938 reg_off += sizeof(uint32_t) * 2;
3943 static inline struct e1000_flex_filter *
3944 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3945 struct e1000_flex_filter_info *key)
3947 struct e1000_flex_filter *it;
3949 TAILQ_FOREACH(it, filter_list, entries) {
3950 if (memcmp(key, &it->filter_info,
3951 sizeof(struct e1000_flex_filter_info)) == 0)
3958 /* remove a flex byte filter
3960 * dev: Pointer to struct rte_eth_dev.
3961 * filter: the pointer of the filter will be removed.
3964 igb_remove_flex_filter(struct rte_eth_dev *dev,
3965 struct e1000_flex_filter *filter)
3967 struct e1000_filter_info *filter_info =
3968 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3969 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973 wufc = E1000_READ_REG(hw, E1000_WUFC);
3974 if (filter->index < E1000_MAX_FHFT)
3975 reg_off = E1000_FHFT(filter->index);
3977 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3979 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3980 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3982 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3983 (~(E1000_WUFC_FLX0 << filter->index)));
3985 filter_info->flex_mask &= ~(1 << filter->index);
3986 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3991 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3992 struct igb_flex_filter *filter,
3995 struct e1000_filter_info *filter_info =
3996 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3997 struct e1000_flex_filter *flex_filter, *it;
4001 flex_filter = rte_zmalloc("e1000_flex_filter",
4002 sizeof(struct e1000_flex_filter), 0);
4003 if (flex_filter == NULL)
4006 flex_filter->filter_info.len = filter->len;
4007 flex_filter->filter_info.priority = filter->priority;
4008 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4009 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4011 /* reverse bits in flex filter's mask*/
4012 for (shift = 0; shift < CHAR_BIT; shift++) {
4013 if (filter->mask[i] & (0x01 << shift))
4014 mask |= (0x80 >> shift);
4016 flex_filter->filter_info.mask[i] = mask;
4019 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4020 &flex_filter->filter_info);
4021 if (it == NULL && !add) {
4022 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4023 rte_free(flex_filter);
4026 if (it != NULL && add) {
4027 PMD_DRV_LOG(ERR, "filter exists.");
4028 rte_free(flex_filter);
4033 flex_filter->queue = filter->queue;
4035 * look for an unused flex filter index
4036 * and insert the filter into the list.
4038 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4039 if (!(filter_info->flex_mask & (1 << i))) {
4040 filter_info->flex_mask |= 1 << i;
4041 flex_filter->index = i;
4042 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4048 if (i >= E1000_MAX_FLEX_FILTERS) {
4049 PMD_DRV_LOG(ERR, "flex filters are full.");
4050 rte_free(flex_filter);
4054 igb_inject_flex_filter(dev, flex_filter);
4057 igb_remove_flex_filter(dev, it);
4058 rte_free(flex_filter);
4064 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4066 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4067 struct e1000_5tuple_filter_info *filter_info)
4069 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4071 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4072 return -EINVAL; /* filter index is out of range. */
4073 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4074 return -EINVAL; /* flags is invalid. */
4076 switch (filter->dst_ip_mask) {
4078 filter_info->dst_ip_mask = 0;
4079 filter_info->dst_ip = filter->dst_ip;
4082 filter_info->dst_ip_mask = 1;
4085 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4089 switch (filter->src_ip_mask) {
4091 filter_info->src_ip_mask = 0;
4092 filter_info->src_ip = filter->src_ip;
4095 filter_info->src_ip_mask = 1;
4098 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4102 switch (filter->dst_port_mask) {
4104 filter_info->dst_port_mask = 0;
4105 filter_info->dst_port = filter->dst_port;
4108 filter_info->dst_port_mask = 1;
4111 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4115 switch (filter->src_port_mask) {
4117 filter_info->src_port_mask = 0;
4118 filter_info->src_port = filter->src_port;
4121 filter_info->src_port_mask = 1;
4124 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4128 switch (filter->proto_mask) {
4130 filter_info->proto_mask = 0;
4131 filter_info->proto = filter->proto;
4134 filter_info->proto_mask = 1;
4137 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4141 filter_info->priority = (uint8_t)filter->priority;
4142 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4143 filter_info->tcp_flags = filter->tcp_flags;
4145 filter_info->tcp_flags = 0;
4150 static inline struct e1000_5tuple_filter *
4151 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4152 struct e1000_5tuple_filter_info *key)
4154 struct e1000_5tuple_filter *it;
4156 TAILQ_FOREACH(it, filter_list, entries) {
4157 if (memcmp(key, &it->filter_info,
4158 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4165 /* inject a igb 5-tuple filter to HW */
4167 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4168 struct e1000_5tuple_filter *filter)
4170 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4171 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4172 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4176 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4177 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4178 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4179 if (filter->filter_info.dst_ip_mask == 0)
4180 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4181 if (filter->filter_info.src_port_mask == 0)
4182 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4183 if (filter->filter_info.proto_mask == 0)
4184 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4185 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4186 E1000_FTQF_QUEUE_MASK;
4187 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4188 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4189 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4190 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4192 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4193 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4195 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4196 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4197 imir |= E1000_IMIR_PORT_BP;
4199 imir &= ~E1000_IMIR_PORT_BP;
4200 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4202 /* tcp flags bits setting. */
4203 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4204 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4205 imir_ext |= E1000_IMIREXT_CTRL_URG;
4206 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4207 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4208 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4209 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4210 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4211 imir_ext |= E1000_IMIREXT_CTRL_RST;
4212 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4213 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4214 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4215 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4217 imir_ext |= E1000_IMIREXT_CTRL_BP;
4219 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4220 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4224 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4227 * dev: Pointer to struct rte_eth_dev.
4228 * ntuple_filter: ponter to the filter that will be added.
4231 * - On success, zero.
4232 * - On failure, a negative value.
4235 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4236 struct rte_eth_ntuple_filter *ntuple_filter)
4238 struct e1000_filter_info *filter_info =
4239 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4240 struct e1000_5tuple_filter *filter;
4244 filter = rte_zmalloc("e1000_5tuple_filter",
4245 sizeof(struct e1000_5tuple_filter), 0);
4249 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4250 &filter->filter_info);
4256 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4257 &filter->filter_info) != NULL) {
4258 PMD_DRV_LOG(ERR, "filter exists.");
4262 filter->queue = ntuple_filter->queue;
4265 * look for an unused 5tuple filter index,
4266 * and insert the filter to list.
4268 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4269 if (!(filter_info->fivetuple_mask & (1 << i))) {
4270 filter_info->fivetuple_mask |= 1 << i;
4272 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4278 if (i >= E1000_MAX_FTQF_FILTERS) {
4279 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4284 igb_inject_5tuple_filter_82576(dev, filter);
4289 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4290 struct e1000_5tuple_filter *filter)
4292 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293 struct e1000_filter_info *filter_info =
4294 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4296 filter_info->fivetuple_mask &= ~(1 << filter->index);
4297 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4300 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4301 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4302 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4303 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4304 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4305 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4306 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4311 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4314 * dev: Pointer to struct rte_eth_dev.
4315 * ntuple_filter: ponter to the filter that will be removed.
4318 * - On success, zero.
4319 * - On failure, a negative value.
4322 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4323 struct rte_eth_ntuple_filter *ntuple_filter)
4325 struct e1000_filter_info *filter_info =
4326 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4327 struct e1000_5tuple_filter_info filter_5tuple;
4328 struct e1000_5tuple_filter *filter;
4331 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4332 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4337 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4339 if (filter == NULL) {
4340 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4344 igb_delete_5tuple_filter_82576(dev, filter);
4350 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4353 struct e1000_hw *hw;
4354 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4356 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 #ifdef RTE_LIBRTE_82571_SUPPORT
4359 /* XXX: not bigger than max_rx_pktlen */
4360 if (hw->mac.type == e1000_82571)
4364 * If device is started, refuse mtu that requires the support of
4365 * scattered packets when this feature has not been enabled before.
4367 if (dev->data->dev_started && !dev->data->scattered_rx &&
4368 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
4369 PMD_INIT_LOG(ERR, "Stop port first.");
4373 rctl = E1000_READ_REG(hw, E1000_RCTL);
4375 /* switch to jumbo mode if needed */
4376 if (mtu > RTE_ETHER_MTU)
4377 rctl |= E1000_RCTL_LPE;
4379 rctl &= ~E1000_RCTL_LPE;
4380 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4382 E1000_WRITE_REG(hw, E1000_RLPML, frame_size);
4388 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4391 * dev: Pointer to struct rte_eth_dev.
4392 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4393 * add: if true, add filter, if false, remove filter
4396 * - On success, zero.
4397 * - On failure, a negative value.
4400 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4401 struct rte_eth_ntuple_filter *ntuple_filter,
4404 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407 switch (ntuple_filter->flags) {
4408 case RTE_5TUPLE_FLAGS:
4409 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4410 if (hw->mac.type != e1000_82576)
4413 ret = igb_add_5tuple_filter_82576(dev,
4416 ret = igb_remove_5tuple_filter_82576(dev,
4419 case RTE_2TUPLE_FLAGS:
4420 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4421 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4422 hw->mac.type != e1000_i210 &&
4423 hw->mac.type != e1000_i211)
4426 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4428 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4439 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4444 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4445 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4446 (filter_info->ethertype_mask & (1 << i)))
4453 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4454 uint16_t ethertype, uint32_t etqf)
4458 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4459 if (!(filter_info->ethertype_mask & (1 << i))) {
4460 filter_info->ethertype_mask |= 1 << i;
4461 filter_info->ethertype_filters[i].ethertype = ethertype;
4462 filter_info->ethertype_filters[i].etqf = etqf;
4470 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4473 if (idx >= E1000_MAX_ETQF_FILTERS)
4475 filter_info->ethertype_mask &= ~(1 << idx);
4476 filter_info->ethertype_filters[idx].ethertype = 0;
4477 filter_info->ethertype_filters[idx].etqf = 0;
4483 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4484 struct rte_eth_ethertype_filter *filter,
4487 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488 struct e1000_filter_info *filter_info =
4489 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4493 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4494 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4495 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4496 " ethertype filter.", filter->ether_type);
4500 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4501 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4504 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4505 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4509 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4510 if (ret >= 0 && add) {
4511 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4512 filter->ether_type);
4515 if (ret < 0 && !add) {
4516 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4517 filter->ether_type);
4522 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4523 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4524 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4525 ret = igb_ethertype_filter_insert(filter_info,
4526 filter->ether_type, etqf);
4528 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4532 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4536 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4537 E1000_WRITE_FLUSH(hw);
4543 eth_igb_flow_ops_get(struct rte_eth_dev *dev __rte_unused,
4544 const struct rte_flow_ops **ops)
4546 *ops = &igb_flow_ops;
4551 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4552 struct rte_ether_addr *mc_addr_set,
4553 uint32_t nb_mc_addr)
4555 struct e1000_hw *hw;
4557 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4558 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4563 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566 uint64_t systime_cycles;
4568 switch (hw->mac.type) {
4572 * Need to read System Time Residue Register to be able
4573 * to read the other two registers.
4575 E1000_READ_REG(hw, E1000_SYSTIMR);
4576 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4577 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4578 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4585 * Need to read System Time Residue Register to be able
4586 * to read the other two registers.
4588 E1000_READ_REG(hw, E1000_SYSTIMR);
4589 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4590 /* Only the 8 LSB are valid. */
4591 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4595 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4596 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4601 return systime_cycles;
4605 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4607 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608 uint64_t rx_tstamp_cycles;
4610 switch (hw->mac.type) {
4613 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4614 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4615 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4621 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4622 /* Only the 8 LSB are valid. */
4623 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4627 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4628 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4633 return rx_tstamp_cycles;
4637 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4639 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4640 uint64_t tx_tstamp_cycles;
4642 switch (hw->mac.type) {
4645 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4646 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4647 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4653 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4654 /* Only the 8 LSB are valid. */
4655 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4659 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4660 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4665 return tx_tstamp_cycles;
4669 igb_start_timecounters(struct rte_eth_dev *dev)
4671 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4672 struct e1000_adapter *adapter = dev->data->dev_private;
4673 uint32_t incval = 1;
4675 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4677 switch (hw->mac.type) {
4681 /* 32 LSB bits + 8 MSB bits = 40 bits */
4682 mask = (1ULL << 40) - 1;
4687 * Start incrementing the register
4688 * used to timestamp PTP packets.
4690 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4693 incval = E1000_INCVALUE_82576;
4694 shift = IGB_82576_TSYNC_SHIFT;
4695 E1000_WRITE_REG(hw, E1000_TIMINCA,
4696 E1000_INCPERIOD_82576 | incval);
4703 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4704 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4705 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4707 adapter->systime_tc.cc_mask = mask;
4708 adapter->systime_tc.cc_shift = shift;
4709 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4711 adapter->rx_tstamp_tc.cc_mask = mask;
4712 adapter->rx_tstamp_tc.cc_shift = shift;
4713 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4715 adapter->tx_tstamp_tc.cc_mask = mask;
4716 adapter->tx_tstamp_tc.cc_shift = shift;
4717 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4721 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4723 struct e1000_adapter *adapter = dev->data->dev_private;
4725 adapter->systime_tc.nsec += delta;
4726 adapter->rx_tstamp_tc.nsec += delta;
4727 adapter->tx_tstamp_tc.nsec += delta;
4733 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4736 struct e1000_adapter *adapter = dev->data->dev_private;
4738 ns = rte_timespec_to_ns(ts);
4740 /* Set the timecounters to a new value. */
4741 adapter->systime_tc.nsec = ns;
4742 adapter->rx_tstamp_tc.nsec = ns;
4743 adapter->tx_tstamp_tc.nsec = ns;
4749 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4751 uint64_t ns, systime_cycles;
4752 struct e1000_adapter *adapter = dev->data->dev_private;
4754 systime_cycles = igb_read_systime_cyclecounter(dev);
4755 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4756 *ts = rte_ns_to_timespec(ns);
4762 igb_timesync_enable(struct rte_eth_dev *dev)
4764 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768 /* Stop the timesync system time. */
4769 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4770 /* Reset the timesync system time value. */
4771 switch (hw->mac.type) {
4777 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4780 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4781 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4784 /* Not supported. */
4788 /* Enable system time for it isn't on by default. */
4789 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4790 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4791 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4793 igb_start_timecounters(dev);
4795 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4796 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4797 (RTE_ETHER_TYPE_1588 |
4798 E1000_ETQF_FILTER_ENABLE |
4801 /* Enable timestamping of received PTP packets. */
4802 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4803 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4804 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4806 /* Enable Timestamping of transmitted PTP packets. */
4807 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4808 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4809 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4815 igb_timesync_disable(struct rte_eth_dev *dev)
4817 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820 /* Disable timestamping of transmitted PTP packets. */
4821 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4822 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4823 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4825 /* Disable timestamping of received PTP packets. */
4826 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4827 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4828 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4830 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4831 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4833 /* Stop incrementating the System Time registers. */
4834 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4840 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4841 struct timespec *timestamp,
4842 uint32_t flags __rte_unused)
4844 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 struct e1000_adapter *adapter = dev->data->dev_private;
4846 uint32_t tsync_rxctl;
4847 uint64_t rx_tstamp_cycles;
4850 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4851 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4854 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4855 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4856 *timestamp = rte_ns_to_timespec(ns);
4862 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4863 struct timespec *timestamp)
4865 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866 struct e1000_adapter *adapter = dev->data->dev_private;
4867 uint32_t tsync_txctl;
4868 uint64_t tx_tstamp_cycles;
4871 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4872 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4875 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4876 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4877 *timestamp = rte_ns_to_timespec(ns);
4883 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4887 const struct reg_info *reg_group;
4889 while ((reg_group = igb_regs[g_ind++]))
4890 count += igb_reg_group_count(reg_group);
4896 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4900 const struct reg_info *reg_group;
4902 while ((reg_group = igbvf_regs[g_ind++]))
4903 count += igb_reg_group_count(reg_group);
4909 eth_igb_get_regs(struct rte_eth_dev *dev,
4910 struct rte_dev_reg_info *regs)
4912 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913 uint32_t *data = regs->data;
4916 const struct reg_info *reg_group;
4919 regs->length = eth_igb_get_reg_length(dev);
4920 regs->width = sizeof(uint32_t);
4924 /* Support only full register dump */
4925 if ((regs->length == 0) ||
4926 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4927 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4929 while ((reg_group = igb_regs[g_ind++]))
4930 count += igb_read_regs_group(dev, &data[count],
4939 igbvf_get_regs(struct rte_eth_dev *dev,
4940 struct rte_dev_reg_info *regs)
4942 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943 uint32_t *data = regs->data;
4946 const struct reg_info *reg_group;
4949 regs->length = igbvf_get_reg_length(dev);
4950 regs->width = sizeof(uint32_t);
4954 /* Support only full register dump */
4955 if ((regs->length == 0) ||
4956 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4957 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4959 while ((reg_group = igbvf_regs[g_ind++]))
4960 count += igb_read_regs_group(dev, &data[count],
4969 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4971 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973 /* Return unit is byte count */
4974 return hw->nvm.word_size * 2;
4978 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4979 struct rte_dev_eeprom_info *in_eeprom)
4981 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982 struct e1000_nvm_info *nvm = &hw->nvm;
4983 uint16_t *data = in_eeprom->data;
4986 first = in_eeprom->offset >> 1;
4987 length = in_eeprom->length >> 1;
4988 if ((first >= hw->nvm.word_size) ||
4989 ((first + length) >= hw->nvm.word_size))
4992 in_eeprom->magic = hw->vendor_id |
4993 ((uint32_t)hw->device_id << 16);
4995 if ((nvm->ops.read) == NULL)
4998 return nvm->ops.read(hw, first, length, data);
5002 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5003 struct rte_dev_eeprom_info *in_eeprom)
5005 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006 struct e1000_nvm_info *nvm = &hw->nvm;
5007 uint16_t *data = in_eeprom->data;
5010 first = in_eeprom->offset >> 1;
5011 length = in_eeprom->length >> 1;
5012 if ((first >= hw->nvm.word_size) ||
5013 ((first + length) >= hw->nvm.word_size))
5016 in_eeprom->magic = (uint32_t)hw->vendor_id |
5017 ((uint32_t)hw->device_id << 16);
5019 if ((nvm->ops.write) == NULL)
5021 return nvm->ops.write(hw, first, length, data);
5025 eth_igb_get_module_info(struct rte_eth_dev *dev,
5026 struct rte_eth_dev_module_info *modinfo)
5028 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030 uint32_t status = 0;
5031 uint16_t sff8472_rev, addr_mode;
5032 bool page_swap = false;
5034 if (hw->phy.media_type == e1000_media_type_copper ||
5035 hw->phy.media_type == e1000_media_type_unknown)
5038 /* Check whether we support SFF-8472 or not */
5039 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5043 /* addressing mode is not supported */
5044 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5048 /* addressing mode is not supported */
5049 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5051 "Address change required to access page 0xA2, "
5052 "but not supported. Please report the module "
5053 "type to the driver maintainers.\n");
5057 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5058 /* We have an SFP, but it does not support SFF-8472 */
5059 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5060 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5062 /* We have an SFP which supports a revision of SFF-8472 */
5063 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5064 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5071 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5072 struct rte_dev_eeprom_info *info)
5074 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076 uint32_t status = 0;
5077 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5078 u16 first_word, last_word;
5081 first_word = info->offset >> 1;
5082 last_word = (info->offset + info->length - 1) >> 1;
5084 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5085 for (i = 0; i < last_word - first_word + 1; i++) {
5086 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5089 /* Error occurred while reading module */
5093 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5096 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5102 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5104 struct e1000_hw *hw =
5105 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5106 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5107 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5108 uint32_t vec = E1000_MISC_VEC_ID;
5110 if (rte_intr_allow_others(intr_handle))
5111 vec = E1000_RX_VEC_START;
5113 uint32_t mask = 1 << (queue_id + vec);
5115 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5116 E1000_WRITE_FLUSH(hw);
5122 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5124 struct e1000_hw *hw =
5125 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5127 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5128 uint32_t vec = E1000_MISC_VEC_ID;
5130 if (rte_intr_allow_others(intr_handle))
5131 vec = E1000_RX_VEC_START;
5133 uint32_t mask = 1 << (queue_id + vec);
5136 regval = E1000_READ_REG(hw, E1000_EIMS);
5137 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5138 E1000_WRITE_FLUSH(hw);
5140 rte_intr_ack(intr_handle);
5146 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5147 uint8_t index, uint8_t offset)
5149 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5152 val &= ~((uint32_t)0xFF << offset);
5154 /* write vector and valid bit */
5155 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5157 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5161 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5162 uint8_t queue, uint8_t msix_vector)
5166 if (hw->mac.type == e1000_82575) {
5168 tmp = E1000_EICR_RX_QUEUE0 << queue;
5169 else if (direction == 1)
5170 tmp = E1000_EICR_TX_QUEUE0 << queue;
5171 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5172 } else if (hw->mac.type == e1000_82576) {
5173 if ((direction == 0) || (direction == 1))
5174 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5175 ((queue & 0x8) << 1) +
5177 } else if ((hw->mac.type == e1000_82580) ||
5178 (hw->mac.type == e1000_i350) ||
5179 (hw->mac.type == e1000_i354) ||
5180 (hw->mac.type == e1000_i210) ||
5181 (hw->mac.type == e1000_i211)) {
5182 if ((direction == 0) || (direction == 1))
5183 eth_igb_write_ivar(hw, msix_vector,
5185 ((queue & 0x1) << 4) +
5190 /* Sets up the hardware to generate MSI-X interrupts properly
5192 * board private structure
5195 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5198 uint32_t tmpval, regval, intr_mask;
5199 struct e1000_hw *hw =
5200 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201 uint32_t vec = E1000_MISC_VEC_ID;
5202 uint32_t base = E1000_MISC_VEC_ID;
5203 uint32_t misc_shift = 0;
5204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5205 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5207 /* won't configure msix register if no mapping is done
5208 * between intr vector and event fd
5210 if (!rte_intr_dp_is_en(intr_handle))
5213 if (rte_intr_allow_others(intr_handle)) {
5214 vec = base = E1000_RX_VEC_START;
5218 /* set interrupt vector for other causes */
5219 if (hw->mac.type == e1000_82575) {
5220 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5221 /* enable MSI-X PBA support */
5222 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5224 /* Auto-Mask interrupts upon ICR read */
5225 tmpval |= E1000_CTRL_EXT_EIAME;
5226 tmpval |= E1000_CTRL_EXT_IRCA;
5228 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5230 /* enable msix_other interrupt */
5231 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5232 regval = E1000_READ_REG(hw, E1000_EIAC);
5233 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5234 regval = E1000_READ_REG(hw, E1000_EIAM);
5235 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5236 } else if ((hw->mac.type == e1000_82576) ||
5237 (hw->mac.type == e1000_82580) ||
5238 (hw->mac.type == e1000_i350) ||
5239 (hw->mac.type == e1000_i354) ||
5240 (hw->mac.type == e1000_i210) ||
5241 (hw->mac.type == e1000_i211)) {
5242 /* turn on MSI-X capability first */
5243 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5244 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5247 RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle),
5248 uint32_t) << misc_shift;
5250 if (dev->data->dev_conf.intr_conf.lsc != 0)
5251 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5253 regval = E1000_READ_REG(hw, E1000_EIAC);
5254 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5256 /* enable msix_other interrupt */
5257 regval = E1000_READ_REG(hw, E1000_EIMS);
5258 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5259 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5260 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5263 /* use EIAM to auto-mask when MSI-X interrupt
5264 * is asserted, this saves a register write for every interrupt
5266 intr_mask = RTE_LEN2MASK(rte_intr_nb_efd_get(intr_handle),
5267 uint32_t) << misc_shift;
5269 if (dev->data->dev_conf.intr_conf.lsc != 0)
5270 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5272 regval = E1000_READ_REG(hw, E1000_EIAM);
5273 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5275 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5276 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5277 rte_intr_vec_list_index_set(intr_handle, queue_id, vec);
5278 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5282 E1000_WRITE_FLUSH(hw);
5285 /* restore n-tuple filter */
5287 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5289 struct e1000_filter_info *filter_info =
5290 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5291 struct e1000_5tuple_filter *p_5tuple;
5292 struct e1000_2tuple_filter *p_2tuple;
5294 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5295 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5298 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5299 igb_inject_2uple_filter(dev, p_2tuple);
5303 /* restore SYN filter */
5305 igb_syn_filter_restore(struct rte_eth_dev *dev)
5307 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5308 struct e1000_filter_info *filter_info =
5309 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5312 synqf = filter_info->syn_info;
5314 if (synqf & E1000_SYN_FILTER_ENABLE) {
5315 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5316 E1000_WRITE_FLUSH(hw);
5320 /* restore ethernet type filter */
5322 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5324 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325 struct e1000_filter_info *filter_info =
5326 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5329 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5330 if (filter_info->ethertype_mask & (1 << i)) {
5331 E1000_WRITE_REG(hw, E1000_ETQF(i),
5332 filter_info->ethertype_filters[i].etqf);
5333 E1000_WRITE_FLUSH(hw);
5338 /* restore flex byte filter */
5340 igb_flex_filter_restore(struct rte_eth_dev *dev)
5342 struct e1000_filter_info *filter_info =
5343 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5344 struct e1000_flex_filter *flex_filter;
5346 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5347 igb_inject_flex_filter(dev, flex_filter);
5351 /* restore rss filter */
5353 igb_rss_filter_restore(struct rte_eth_dev *dev)
5355 struct e1000_filter_info *filter_info =
5356 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5358 if (filter_info->rss_info.conf.queue_num)
5359 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5362 /* restore all types filter */
5364 igb_filter_restore(struct rte_eth_dev *dev)
5366 igb_ntuple_filter_restore(dev);
5367 igb_ethertype_filter_restore(dev);
5368 igb_syn_filter_restore(dev);
5369 igb_flex_filter_restore(dev);
5370 igb_rss_filter_restore(dev);
5375 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5376 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5377 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5378 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5379 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5380 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");