drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffff
  82 #define E1000_ETQF_FILTER_1588       3
  83 #define IGB_82576_TSYNC_SHIFT        16
  84 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  85 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  86 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  87
  88 static int  eth_igb_configure(struct rte_eth_dev *dev);
  89 static int  eth_igb_start(struct rte_eth_dev *dev);
  90 static void eth_igb_stop(struct rte_eth_dev *dev);
  91 static void eth_igb_close(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  96 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  99                                 struct rte_eth_stats *rte_stats);
 100 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_xstats *xstats, unsigned n);
 102 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 105                               struct rte_eth_dev_info *dev_info);
 106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_fc_conf *fc_conf);
 110 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 116 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 117                                                         void *param);
 118 static int  igb_hardware_init(struct e1000_hw *hw);
 119 static void igb_hw_control_acquire(struct e1000_hw *hw);
 120 static void igb_hw_control_release(struct e1000_hw *hw);
 121 static void igb_init_manageability(struct e1000_hw *hw);
 122 static void igb_release_manageability(struct e1000_hw *hw);
 123
 124 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 125
 126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 127                 uint16_t vlan_id, int on);
 128 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 129 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 130
 131 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int eth_igb_led_on(struct rte_eth_dev *dev);
 139 static int eth_igb_led_off(struct rte_eth_dev *dev);
 140
 141 static void igb_intr_disable(struct e1000_hw *hw);
 142 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 143 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 144                 struct ether_addr *mac_addr,
 145                 uint32_t index, uint32_t pool);
 146 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 147 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 148                 struct ether_addr *addr);
 149
 150 static void igbvf_intr_disable(struct e1000_hw *hw);
 151 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 152 static int igbvf_dev_start(struct rte_eth_dev *dev);
 153 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 154 static void igbvf_dev_close(struct rte_eth_dev *dev);
 155 static int eth_igbvf_link_update(struct e1000_hw *hw);
 156 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 157                                 struct rte_eth_stats *rte_stats);
 158 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_xstats *xstats, unsigned n);
 160 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 161 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 164 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 165 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *addr);
 167 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 168 static int igbvf_get_regs(struct rte_eth_dev *dev,
 169                 struct rte_dev_reg_info *regs);
 170
 171 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 172                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 173                                    uint16_t reta_size);
 174 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 175                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 176                                   uint16_t reta_size);
 177
 178 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 179                         struct rte_eth_syn_filter *filter,
 180                         bool add);
 181 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 182                         struct rte_eth_syn_filter *filter);
 183 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 184                         enum rte_filter_op filter_op,
 185                         void *arg);
 186 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 187                         struct rte_eth_ntuple_filter *ntuple_filter);
 188 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 189                         struct rte_eth_ntuple_filter *ntuple_filter);
 190 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 191                         struct rte_eth_flex_filter *filter,
 192                         bool add);
 193 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_flex_filter *filter);
 195 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 196                         enum rte_filter_op filter_op,
 197                         void *arg);
 198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *ntuple_filter);
 200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *filter,
 204                         bool add);
 205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *filter);
 207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ethertype_filter *filter,
 212                         bool add);
 213 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ethertype_filter *filter);
 218 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 219                      enum rte_filter_type filter_type,
 220                      enum rte_filter_op filter_op,
 221                      void *arg);
 222 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 223 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 224                 struct rte_dev_reg_info *regs);
 225 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 226 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 227                 struct rte_dev_eeprom_info *eeprom);
 228 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 229                 struct rte_dev_eeprom_info *eeprom);
 230 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 231                                     struct ether_addr *mc_addr_set,
 232                                     uint32_t nb_mc_addr);
 233 static int igb_timesync_enable(struct rte_eth_dev *dev);
 234 static int igb_timesync_disable(struct rte_eth_dev *dev);
 235 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 236                                           struct timespec *timestamp,
 237                                           uint32_t flags);
 238 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp);
 240 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 241 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 242                                   struct timespec *timestamp);
 243 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 244                                    const struct timespec *timestamp);
 245 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 246                                         uint16_t queue_id);
 247 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 248                                          uint16_t queue_id);
 249 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 250                                        uint8_t queue, uint8_t msix_vector);
 251 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 252                                uint8_t index, uint8_t offset);
 253 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)            \
 259 {                                                 \
 260         u32 latest = E1000_READ_REG(hw, reg);     \
 261         cur += (latest - last) & UINT_MAX;        \
 262         last = latest;                            \
 263 }
 264
 265 #define IGB_FC_PAUSE_TIME 0x0680
 266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 268
 269 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 270
 271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 272
 273 /*
 274  * The set of PCI devices this driver supports
 275  */
 276 static const struct rte_pci_id pci_id_igb_map[] = {
 277
 278 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 279 #include "rte_pci_dev_ids.h"
 280
 281 {0},
 282 };
 283
 284 /*
 285  * The set of PCI devices this driver supports (for 82576&I350 VF)
 286  */
 287 static const struct rte_pci_id pci_id_igbvf_map[] = {
 288
 289 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 290 #include "rte_pci_dev_ids.h"
 291
 292 {0},
 293 };
 294
 295 static const struct rte_eth_desc_lim rx_desc_lim = {
 296         .nb_max = E1000_MAX_RING_DESC,
 297         .nb_min = E1000_MIN_RING_DESC,
 298         .nb_align = IGB_RXD_ALIGN,
 299 };
 300
 301 static const struct rte_eth_desc_lim tx_desc_lim = {
 302         .nb_max = E1000_MAX_RING_DESC,
 303         .nb_min = E1000_MIN_RING_DESC,
 304         .nb_align = IGB_RXD_ALIGN,
 305 };
 306
 307 static const struct eth_dev_ops eth_igb_ops = {
 308         .dev_configure        = eth_igb_configure,
 309         .dev_start            = eth_igb_start,
 310         .dev_stop             = eth_igb_stop,
 311         .dev_close            = eth_igb_close,
 312         .promiscuous_enable   = eth_igb_promiscuous_enable,
 313         .promiscuous_disable  = eth_igb_promiscuous_disable,
 314         .allmulticast_enable  = eth_igb_allmulticast_enable,
 315         .allmulticast_disable = eth_igb_allmulticast_disable,
 316         .link_update          = eth_igb_link_update,
 317         .stats_get            = eth_igb_stats_get,
 318         .xstats_get           = eth_igb_xstats_get,
 319         .stats_reset          = eth_igb_stats_reset,
 320         .xstats_reset         = eth_igb_xstats_reset,
 321         .dev_infos_get        = eth_igb_infos_get,
 322         .mtu_set              = eth_igb_mtu_set,
 323         .vlan_filter_set      = eth_igb_vlan_filter_set,
 324         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 325         .vlan_offload_set     = eth_igb_vlan_offload_set,
 326         .rx_queue_setup       = eth_igb_rx_queue_setup,
 327         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 328         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 329         .rx_queue_release     = eth_igb_rx_queue_release,
 330         .rx_queue_count       = eth_igb_rx_queue_count,
 331         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 332         .tx_queue_setup       = eth_igb_tx_queue_setup,
 333         .tx_queue_release     = eth_igb_tx_queue_release,
 334         .dev_led_on           = eth_igb_led_on,
 335         .dev_led_off          = eth_igb_led_off,
 336         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 337         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 338         .mac_addr_add         = eth_igb_rar_set,
 339         .mac_addr_remove      = eth_igb_rar_clear,
 340         .mac_addr_set         = eth_igb_default_mac_addr_set,
 341         .reta_update          = eth_igb_rss_reta_update,
 342         .reta_query           = eth_igb_rss_reta_query,
 343         .rss_hash_update      = eth_igb_rss_hash_update,
 344         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 345         .filter_ctrl          = eth_igb_filter_ctrl,
 346         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 347         .rxq_info_get         = igb_rxq_info_get,
 348         .txq_info_get         = igb_txq_info_get,
 349         .timesync_enable      = igb_timesync_enable,
 350         .timesync_disable     = igb_timesync_disable,
 351         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 352         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 353         .get_reg_length       = eth_igb_get_reg_length,
 354         .get_reg              = eth_igb_get_regs,
 355         .get_eeprom_length    = eth_igb_get_eeprom_length,
 356         .get_eeprom           = eth_igb_get_eeprom,
 357         .set_eeprom           = eth_igb_set_eeprom,
 358         .timesync_adjust_time = igb_timesync_adjust_time,
 359         .timesync_read_time   = igb_timesync_read_time,
 360         .timesync_write_time  = igb_timesync_write_time,
 361 };
 362
 363 /*
 364  * dev_ops for virtual function, bare necessities for basic vf
 365  * operation have been implemented
 366  */
 367 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 368         .dev_configure        = igbvf_dev_configure,
 369         .dev_start            = igbvf_dev_start,
 370         .dev_stop             = igbvf_dev_stop,
 371         .dev_close            = igbvf_dev_close,
 372         .link_update          = eth_igb_link_update,
 373         .stats_get            = eth_igbvf_stats_get,
 374         .xstats_get           = eth_igbvf_xstats_get,
 375         .stats_reset          = eth_igbvf_stats_reset,
 376         .xstats_reset         = eth_igbvf_stats_reset,
 377         .vlan_filter_set      = igbvf_vlan_filter_set,
 378         .dev_infos_get        = eth_igbvf_infos_get,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_release     = eth_igb_rx_queue_release,
 381         .tx_queue_setup       = eth_igb_tx_queue_setup,
 382         .tx_queue_release     = eth_igb_tx_queue_release,
 383         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 384         .rxq_info_get         = igb_rxq_info_get,
 385         .txq_info_get         = igb_txq_info_get,
 386         .mac_addr_set         = igbvf_default_mac_addr_set,
 387         .get_reg_length       = igbvf_get_reg_length,
 388         .get_reg              = igbvf_get_regs,
 389 };
 390
 391 /* store statistics names and its offset in stats structure */
 392 struct rte_igb_xstats_name_off {
 393         char name[RTE_ETH_XSTATS_NAME_SIZE];
 394         unsigned offset;
 395 };
 396
 397 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 398         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 399         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 400         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 401         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 402         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 403         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 404         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 405                 ecol)},
 406         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 407         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 408         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 409         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 410         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 411         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 412         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 413         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 414         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 415         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 416         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 417                 fcruc)},
 418         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 419         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 420         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 421         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 422         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 423                 prc1023)},
 424         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 425                 prc1522)},
 426         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 427         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 428         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 429         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 430         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 431         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 432         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 433         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 434         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 435         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 436         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 437         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 438         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 439         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 440         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 441         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 442         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 443         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 444                 ptc1023)},
 445         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 446                 ptc1522)},
 447         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 448         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 449         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 450         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 451         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 452         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 453         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 454
 455         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 456 };
 457
 458 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 459                 sizeof(rte_igb_stats_strings[0]))
 460
 461 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 462         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 463         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 464         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 465         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 466         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 467 };
 468
 469 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 470                 sizeof(rte_igbvf_stats_strings[0]))
 471
 472 /**
 473  * Atomically reads the link status information from global
 474  * structure rte_eth_dev.
 475  *
 476  * @param dev
 477  *   - Pointer to the structure rte_eth_dev to read from.
 478  *   - Pointer to the buffer to be saved with the link status.
 479  *
 480  * @return
 481  *   - On success, zero.
 482  *   - On failure, negative value.
 483  */
 484 static inline int
 485 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 486                                 struct rte_eth_link *link)
 487 {
 488         struct rte_eth_link *dst = link;
 489         struct rte_eth_link *src = &(dev->data->dev_link);
 490
 491         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 492                                         *(uint64_t *)src) == 0)
 493                 return -1;
 494
 495         return 0;
 496 }
 497
 498 /**
 499  * Atomically writes the link status information into global
 500  * structure rte_eth_dev.
 501  *
 502  * @param dev
 503  *   - Pointer to the structure rte_eth_dev to read from.
 504  *   - Pointer to the buffer to be saved with the link status.
 505  *
 506  * @return
 507  *   - On success, zero.
 508  *   - On failure, negative value.
 509  */
 510 static inline int
 511 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 512                                 struct rte_eth_link *link)
 513 {
 514         struct rte_eth_link *dst = &(dev->data->dev_link);
 515         struct rte_eth_link *src = link;
 516
 517         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 518                                         *(uint64_t *)src) == 0)
 519                 return -1;
 520
 521         return 0;
 522 }
 523
 524 static inline void
 525 igb_intr_enable(struct rte_eth_dev *dev)
 526 {
 527         struct e1000_interrupt *intr =
 528                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 529         struct e1000_hw *hw =
 530                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531
 532         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 533         E1000_WRITE_FLUSH(hw);
 534 }
 535
 536 static void
 537 igb_intr_disable(struct e1000_hw *hw)
 538 {
 539         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 540         E1000_WRITE_FLUSH(hw);
 541 }
 542
 543 static inline int32_t
 544 igb_pf_reset_hw(struct e1000_hw *hw)
 545 {
 546         uint32_t ctrl_ext;
 547         int32_t status;
 548
 549         status = e1000_reset_hw(hw);
 550
 551         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 552         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 553         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 554         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 555         E1000_WRITE_FLUSH(hw);
 556
 557         return status;
 558 }
 559
 560 static void
 561 igb_identify_hardware(struct rte_eth_dev *dev)
 562 {
 563         struct e1000_hw *hw =
 564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 565
 566         hw->vendor_id = dev->pci_dev->id.vendor_id;
 567         hw->device_id = dev->pci_dev->id.device_id;
 568         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 569         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 570
 571         e1000_set_mac_type(hw);
 572
 573         /* need to check if it is a vf device below */
 574 }
 575
 576 static int
 577 igb_reset_swfw_lock(struct e1000_hw *hw)
 578 {
 579         int ret_val;
 580
 581         /*
 582          * Do mac ops initialization manually here, since we will need
 583          * some function pointers set by this call.
 584          */
 585         ret_val = e1000_init_mac_params(hw);
 586         if (ret_val)
 587                 return ret_val;
 588
 589         /*
 590          * SMBI lock should not fail in this early stage. If this is the case,
 591          * it is due to an improper exit of the application.
 592          * So force the release of the faulty lock.
 593          */
 594         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 595                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 596         }
 597         e1000_put_hw_semaphore_generic(hw);
 598
 599         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 600                 uint16_t mask;
 601
 602                 /*
 603                  * Phy lock should not fail in this early stage. If this is the case,
 604                  * it is due to an improper exit of the application.
 605                  * So force the release of the faulty lock.
 606                  */
 607                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 608                 if (hw->bus.func > E1000_FUNC_1)
 609                         mask <<= 2;
 610                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 611                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 612                                     hw->bus.func);
 613                 }
 614                 hw->mac.ops.release_swfw_sync(hw, mask);
 615
 616                 /*
 617                  * This one is more tricky since it is common to all ports; but
 618                  * swfw_sync retries last long enough (1s) to be almost sure that if
 619                  * lock can not be taken it is due to an improper lock of the
 620                  * semaphore.
 621                  */
 622                 mask = E1000_SWFW_EEP_SM;
 623                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 624                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 625                 }
 626                 hw->mac.ops.release_swfw_sync(hw, mask);
 627         }
 628
 629         return E1000_SUCCESS;
 630 }
 631
 632 static int
 633 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 634 {
 635         int error = 0;
 636         struct rte_pci_device *pci_dev;
 637         struct e1000_hw *hw =
 638                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 639         struct e1000_vfta * shadow_vfta =
 640                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 641         struct e1000_filter_info *filter_info =
 642                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 643         struct e1000_adapter *adapter =
 644                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 645
 646         uint32_t ctrl_ext;
 647
 648         pci_dev = eth_dev->pci_dev;
 649
 650         eth_dev->dev_ops = &eth_igb_ops;
 651         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 652         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 653
 654         /* for secondary processes, we don't initialise any further as primary
 655          * has already done this work. Only check we don't need a different
 656          * RX function */
 657         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 658                 if (eth_dev->data->scattered_rx)
 659                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 660                 return 0;
 661         }
 662
 663         rte_eth_copy_pci_info(eth_dev, pci_dev);
 664
 665         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 666
 667         igb_identify_hardware(eth_dev);
 668         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 669                 error = -EIO;
 670                 goto err_late;
 671         }
 672
 673         e1000_get_bus_info(hw);
 674
 675         /* Reset any pending lock */
 676         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 677                 error = -EIO;
 678                 goto err_late;
 679         }
 680
 681         /* Finish initialization */
 682         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 683                 error = -EIO;
 684                 goto err_late;
 685         }
 686
 687         hw->mac.autoneg = 1;
 688         hw->phy.autoneg_wait_to_complete = 0;
 689         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 690
 691         /* Copper options */
 692         if (hw->phy.media_type == e1000_media_type_copper) {
 693                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 694                 hw->phy.disable_polarity_correction = 0;
 695                 hw->phy.ms_type = e1000_ms_hw_default;
 696         }
 697
 698         /*
 699          * Start from a known state, this is important in reading the nvm
 700          * and mac from that.
 701          */
 702         igb_pf_reset_hw(hw);
 703
 704         /* Make sure we have a good EEPROM before we read from it */
 705         if (e1000_validate_nvm_checksum(hw) < 0) {
 706                 /*
 707                  * Some PCI-E parts fail the first check due to
 708                  * the link being in sleep state, call it again,
 709                  * if it fails a second time its a real issue.
 710                  */
 711                 if (e1000_validate_nvm_checksum(hw) < 0) {
 712                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 713                         error = -EIO;
 714                         goto err_late;
 715                 }
 716         }
 717
 718         /* Read the permanent MAC address out of the EEPROM */
 719         if (e1000_read_mac_addr(hw) != 0) {
 720                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 721                 error = -EIO;
 722                 goto err_late;
 723         }
 724
 725         /* Allocate memory for storing MAC addresses */
 726         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 727                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 728         if (eth_dev->data->mac_addrs == NULL) {
 729                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 730                                                 "store MAC addresses",
 731                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 732                 error = -ENOMEM;
 733                 goto err_late;
 734         }
 735
 736         /* Copy the permanent MAC address */
 737         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 738
 739         /* initialize the vfta */
 740         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 741
 742         /* Now initialize the hardware */
 743         if (igb_hardware_init(hw) != 0) {
 744                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 745                 rte_free(eth_dev->data->mac_addrs);
 746                 eth_dev->data->mac_addrs = NULL;
 747                 error = -ENODEV;
 748                 goto err_late;
 749         }
 750         hw->mac.get_link_status = 1;
 751         adapter->stopped = 0;
 752
 753         /* Indicate SOL/IDER usage */
 754         if (e1000_check_reset_block(hw) < 0) {
 755                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 756                                         "SOL/IDER session");
 757         }
 758
 759         /* initialize PF if max_vfs not zero */
 760         igb_pf_host_init(eth_dev);
 761
 762         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 763         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 764         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 765         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 766         E1000_WRITE_FLUSH(hw);
 767
 768         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 769                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 770                      pci_dev->id.device_id);
 771
 772         rte_intr_callback_register(&pci_dev->intr_handle,
 773                                    eth_igb_interrupt_handler,
 774                                    (void *)eth_dev);
 775
 776         /* enable uio/vfio intr/eventfd mapping */
 777         rte_intr_enable(&pci_dev->intr_handle);
 778
 779         /* enable support intr */
 780         igb_intr_enable(eth_dev);
 781
 782         TAILQ_INIT(&filter_info->flex_list);
 783         filter_info->flex_mask = 0;
 784         TAILQ_INIT(&filter_info->twotuple_list);
 785         filter_info->twotuple_mask = 0;
 786         TAILQ_INIT(&filter_info->fivetuple_list);
 787         filter_info->fivetuple_mask = 0;
 788
 789         return 0;
 790
 791 err_late:
 792         igb_hw_control_release(hw);
 793
 794         return (error);
 795 }
 796
 797 static int
 798 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 799 {
 800         struct rte_pci_device *pci_dev;
 801         struct e1000_hw *hw;
 802         struct e1000_adapter *adapter =
 803                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 804
 805         PMD_INIT_FUNC_TRACE();
 806
 807         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 808                 return -EPERM;
 809
 810         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 811         pci_dev = eth_dev->pci_dev;
 812
 813         if (adapter->stopped == 0)
 814                 eth_igb_close(eth_dev);
 815
 816         eth_dev->dev_ops = NULL;
 817         eth_dev->rx_pkt_burst = NULL;
 818         eth_dev->tx_pkt_burst = NULL;
 819
 820         /* Reset any pending lock */
 821         igb_reset_swfw_lock(hw);
 822
 823         rte_free(eth_dev->data->mac_addrs);
 824         eth_dev->data->mac_addrs = NULL;
 825
 826         /* uninitialize PF if max_vfs not zero */
 827         igb_pf_host_uninit(eth_dev);
 828
 829         /* disable uio intr before callback unregister */
 830         rte_intr_disable(&(pci_dev->intr_handle));
 831         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 832                 eth_igb_interrupt_handler, (void *)eth_dev);
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * Virtual Function device init
 839  */
 840 static int
 841 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 842 {
 843         struct rte_pci_device *pci_dev;
 844         struct e1000_adapter *adapter =
 845                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 846         struct e1000_hw *hw =
 847                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 848         int diag;
 849
 850         PMD_INIT_FUNC_TRACE();
 851
 852         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 853         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 854         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 855
 856         /* for secondary processes, we don't initialise any further as primary
 857          * has already done this work. Only check we don't need a different
 858          * RX function */
 859         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 860                 if (eth_dev->data->scattered_rx)
 861                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 862                 return 0;
 863         }
 864
 865         pci_dev = eth_dev->pci_dev;
 866
 867         rte_eth_copy_pci_info(eth_dev, pci_dev);
 868
 869         hw->device_id = pci_dev->id.device_id;
 870         hw->vendor_id = pci_dev->id.vendor_id;
 871         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 872         adapter->stopped = 0;
 873
 874         /* Initialize the shared code (base driver) */
 875         diag = e1000_setup_init_funcs(hw, TRUE);
 876         if (diag != 0) {
 877                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 878                         diag);
 879                 return -EIO;
 880         }
 881
 882         /* init_mailbox_params */
 883         hw->mbx.ops.init_params(hw);
 884
 885         /* Disable the interrupts for VF */
 886         igbvf_intr_disable(hw);
 887
 888         diag = hw->mac.ops.reset_hw(hw);
 889
 890         /* Allocate memory for storing MAC addresses */
 891         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 892                 hw->mac.rar_entry_count, 0);
 893         if (eth_dev->data->mac_addrs == NULL) {
 894                 PMD_INIT_LOG(ERR,
 895                         "Failed to allocate %d bytes needed to store MAC "
 896                         "addresses",
 897                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 898                 return -ENOMEM;
 899         }
 900
 901         /* Copy the permanent MAC address */
 902         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 903                         &eth_dev->data->mac_addrs[0]);
 904
 905         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 906                      "mac.type=%s",
 907                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 908                      pci_dev->id.device_id, "igb_mac_82576_vf");
 909
 910         return 0;
 911 }
 912
 913 static int
 914 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 915 {
 916         struct e1000_adapter *adapter =
 917                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 918
 919         PMD_INIT_FUNC_TRACE();
 920
 921         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 922                 return -EPERM;
 923
 924         if (adapter->stopped == 0)
 925                 igbvf_dev_close(eth_dev);
 926
 927         eth_dev->dev_ops = NULL;
 928         eth_dev->rx_pkt_burst = NULL;
 929         eth_dev->tx_pkt_burst = NULL;
 930
 931         rte_free(eth_dev->data->mac_addrs);
 932         eth_dev->data->mac_addrs = NULL;
 933
 934         return 0;
 935 }
 936
 937 static struct eth_driver rte_igb_pmd = {
 938         .pci_drv = {
 939                 .name = "rte_igb_pmd",
 940                 .id_table = pci_id_igb_map,
 941                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 942                         RTE_PCI_DRV_DETACHABLE,
 943         },
 944         .eth_dev_init = eth_igb_dev_init,
 945         .eth_dev_uninit = eth_igb_dev_uninit,
 946         .dev_private_size = sizeof(struct e1000_adapter),
 947 };
 948
 949 /*
 950  * virtual function driver struct
 951  */
 952 static struct eth_driver rte_igbvf_pmd = {
 953         .pci_drv = {
 954                 .name = "rte_igbvf_pmd",
 955                 .id_table = pci_id_igbvf_map,
 956                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 957         },
 958         .eth_dev_init = eth_igbvf_dev_init,
 959         .eth_dev_uninit = eth_igbvf_dev_uninit,
 960         .dev_private_size = sizeof(struct e1000_adapter),
 961 };
 962
 963 static int
 964 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 965 {
 966         rte_eth_driver_register(&rte_igb_pmd);
 967         return 0;
 968 }
 969
 970 static void
 971 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 972 {
 973         struct e1000_hw *hw =
 974                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 975         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 976         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 977         rctl |= E1000_RCTL_VFE;
 978         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 979 }
 980
 981 /*
 982  * VF Driver initialization routine.
 983  * Invoked one at EAL init time.
 984  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 985  */
 986 static int
 987 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 988 {
 989         PMD_INIT_FUNC_TRACE();
 990
 991         rte_eth_driver_register(&rte_igbvf_pmd);
 992         return (0);
 993 }
 994
 995 static int
 996 igb_check_mq_mode(struct rte_eth_dev *dev)
 997 {
 998         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 999         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1000         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1001         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1002
1003         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1004             tx_mq_mode == ETH_MQ_TX_DCB ||
1005             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1006                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1007                 return -EINVAL;
1008         }
1009         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1010                 /* Check multi-queue mode.
1011                  * To no break software we accept ETH_MQ_RX_NONE as this might
1012                  * be used to turn off VLAN filter.
1013                  */
1014
1015                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1016                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1017                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1018                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1019                 } else {
1020                         /* Only support one queue on VFs.
1021                          * RSS together with SRIOV is not supported.
1022                          */
1023                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1024                                         " wrong mq_mode rx %d.",
1025                                         rx_mq_mode);
1026                         return -EINVAL;
1027                 }
1028                 /* TX mode is not used here, so mode might be ignored.*/
1029                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1030                         /* SRIOV only works in VMDq enable mode */
1031                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1032                                         " TX mode %d is not supported. "
1033                                         " Driver will behave as %d mode.",
1034                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1035                 }
1036
1037                 /* check valid queue number */
1038                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1039                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1040                                         " only support one queue on VFs.");
1041                         return -EINVAL;
1042                 }
1043         } else {
1044                 /* To no break software that set invalid mode, only display
1045                  * warning if invalid mode is used.
1046                  */
1047                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1048                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1049                     rx_mq_mode != ETH_MQ_RX_RSS) {
1050                         /* RSS together with VMDq not supported*/
1051                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1052                                      rx_mq_mode);
1053                         return -EINVAL;
1054                 }
1055
1056                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1057                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1058                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1059                                         " Due to txmode is meaningless in this"
1060                                         " driver, just ignore.",
1061                                         tx_mq_mode);
1062                 }
1063         }
1064         return 0;
1065 }
1066
1067 static int
1068 eth_igb_configure(struct rte_eth_dev *dev)
1069 {
1070         struct e1000_interrupt *intr =
1071                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1072         int ret;
1073
1074         PMD_INIT_FUNC_TRACE();
1075
1076         /* multipe queue mode checking */
1077         ret  = igb_check_mq_mode(dev);
1078         if (ret != 0) {
1079                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1080                             ret);
1081                 return ret;
1082         }
1083
1084         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1085         PMD_INIT_FUNC_TRACE();
1086
1087         return 0;
1088 }
1089
1090 static int
1091 eth_igb_start(struct rte_eth_dev *dev)
1092 {
1093         struct e1000_hw *hw =
1094                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1095         struct e1000_adapter *adapter =
1096                 E1000_DEV_PRIVATE(dev->data->dev_private);
1097         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1098         int ret, mask;
1099         uint32_t intr_vector = 0;
1100         uint32_t ctrl_ext;
1101
1102         PMD_INIT_FUNC_TRACE();
1103
1104         /* Power up the phy. Needed to make the link go Up */
1105         e1000_power_up_phy(hw);
1106
1107         /*
1108          * Packet Buffer Allocation (PBA)
1109          * Writing PBA sets the receive portion of the buffer
1110          * the remainder is used for the transmit buffer.
1111          */
1112         if (hw->mac.type == e1000_82575) {
1113                 uint32_t pba;
1114
1115                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1116                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1117         }
1118
1119         /* Put the address into the Receive Address Array */
1120         e1000_rar_set(hw, hw->mac.addr, 0);
1121
1122         /* Initialize the hardware */
1123         if (igb_hardware_init(hw)) {
1124                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1125                 return (-EIO);
1126         }
1127         adapter->stopped = 0;
1128
1129         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1130
1131         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1132         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1133         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1134         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1135         E1000_WRITE_FLUSH(hw);
1136
1137         /* configure PF module if SRIOV enabled */
1138         igb_pf_host_configure(dev);
1139
1140         /* check and configure queue intr-vector mapping */
1141         if ((rte_intr_cap_multiple(intr_handle) ||
1142              !RTE_ETH_DEV_SRIOV(dev).active) &&
1143             dev->data->dev_conf.intr_conf.rxq != 0) {
1144                 intr_vector = dev->data->nb_rx_queues;
1145                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1146                         return -1;
1147         }
1148
1149         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1150                 intr_handle->intr_vec =
1151                         rte_zmalloc("intr_vec",
1152                                     dev->data->nb_rx_queues * sizeof(int), 0);
1153                 if (intr_handle->intr_vec == NULL) {
1154                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1155                                      " intr_vec\n", dev->data->nb_rx_queues);
1156                         return -ENOMEM;
1157                 }
1158         }
1159
1160         /* confiugre msix for rx interrupt */
1161         eth_igb_configure_msix_intr(dev);
1162
1163         /* Configure for OS presence */
1164         igb_init_manageability(hw);
1165
1166         eth_igb_tx_init(dev);
1167
1168         /* This can fail when allocating mbufs for descriptor rings */
1169         ret = eth_igb_rx_init(dev);
1170         if (ret) {
1171                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1172                 igb_dev_clear_queues(dev);
1173                 return ret;
1174         }
1175
1176         e1000_clear_hw_cntrs_base_generic(hw);
1177
1178         /*
1179          * VLAN Offload Settings
1180          */
1181         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1182                         ETH_VLAN_EXTEND_MASK;
1183         eth_igb_vlan_offload_set(dev, mask);
1184
1185         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1186                 /* Enable VLAN filter since VMDq always use VLAN filter */
1187                 igb_vmdq_vlan_hw_filter_enable(dev);
1188         }
1189
1190         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1191                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1192                 (hw->mac.type == e1000_i211)) {
1193                 /* Configure EITR with the maximum possible value (0xFFFF) */
1194                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1195         }
1196
1197         /* Setup link speed and duplex */
1198         switch (dev->data->dev_conf.link_speed) {
1199         case ETH_LINK_SPEED_AUTONEG:
1200                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1201                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1202                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1203                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1204                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1205                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1206                 else
1207                         goto error_invalid_config;
1208                 break;
1209         case ETH_LINK_SPEED_10:
1210                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1211                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1212                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1213                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1214                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1215                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1216                 else
1217                         goto error_invalid_config;
1218                 break;
1219         case ETH_LINK_SPEED_100:
1220                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1221                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1222                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1223                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1224                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1225                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1226                 else
1227                         goto error_invalid_config;
1228                 break;
1229         case ETH_LINK_SPEED_1000:
1230                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1231                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1232                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1233                 else
1234                         goto error_invalid_config;
1235                 break;
1236         case ETH_LINK_SPEED_10000:
1237         default:
1238                 goto error_invalid_config;
1239         }
1240         e1000_setup_link(hw);
1241
1242         if (rte_intr_allow_others(intr_handle)) {
1243                 /* check if lsc interrupt is enabled */
1244                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1245                         eth_igb_lsc_interrupt_setup(dev);
1246         } else {
1247                 rte_intr_callback_unregister(intr_handle,
1248                                              eth_igb_interrupt_handler,
1249                                              (void *)dev);
1250                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1251                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1252                                      " no intr multiplex\n");
1253         }
1254
1255         /* check if rxq interrupt is enabled */
1256         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1257             rte_intr_dp_is_en(intr_handle))
1258                 eth_igb_rxq_interrupt_setup(dev);
1259
1260         /* enable uio/vfio intr/eventfd mapping */
1261         rte_intr_enable(intr_handle);
1262
1263         /* resume enabled intr since hw reset */
1264         igb_intr_enable(dev);
1265
1266         PMD_INIT_LOG(DEBUG, "<<");
1267
1268         return (0);
1269
1270 error_invalid_config:
1271         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1272                      dev->data->dev_conf.link_speed,
1273                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1274         igb_dev_clear_queues(dev);
1275         return (-EINVAL);
1276 }
1277
1278 /*********************************************************************
1279  *
1280  *  This routine disables all traffic on the adapter by issuing a
1281  *  global reset on the MAC.
1282  *
1283  **********************************************************************/
1284 static void
1285 eth_igb_stop(struct rte_eth_dev *dev)
1286 {
1287         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288         struct e1000_filter_info *filter_info =
1289                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1290         struct rte_eth_link link;
1291         struct e1000_flex_filter *p_flex;
1292         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1293         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1294         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1295
1296         igb_intr_disable(hw);
1297
1298         /* disable intr eventfd mapping */
1299         rte_intr_disable(intr_handle);
1300
1301         igb_pf_reset_hw(hw);
1302         E1000_WRITE_REG(hw, E1000_WUC, 0);
1303
1304         /* Set bit for Go Link disconnect */
1305         if (hw->mac.type >= e1000_82580) {
1306                 uint32_t phpm_reg;
1307
1308                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1309                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1310                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1311         }
1312
1313         /* Power down the phy. Needed to make the link go Down */
1314         if (hw->phy.media_type == e1000_media_type_copper)
1315                 e1000_power_down_phy(hw);
1316         else
1317                 e1000_shutdown_fiber_serdes_link(hw);
1318
1319         igb_dev_clear_queues(dev);
1320
1321         /* clear the recorded link status */
1322         memset(&link, 0, sizeof(link));
1323         rte_igb_dev_atomic_write_link_status(dev, &link);
1324
1325         /* Remove all flex filters of the device */
1326         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1327                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1328                 rte_free(p_flex);
1329         }
1330         filter_info->flex_mask = 0;
1331
1332         /* Remove all ntuple filters of the device */
1333         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1334              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1335                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1336                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1337                              p_5tuple, entries);
1338                 rte_free(p_5tuple);
1339         }
1340         filter_info->fivetuple_mask = 0;
1341         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1342              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1343                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1344                 TAILQ_REMOVE(&filter_info->twotuple_list,
1345                              p_2tuple, entries);
1346                 rte_free(p_2tuple);
1347         }
1348         filter_info->twotuple_mask = 0;
1349
1350         if (!rte_intr_allow_others(intr_handle))
1351                 /* resume to the default handler */
1352                 rte_intr_callback_register(intr_handle,
1353                                            eth_igb_interrupt_handler,
1354                                            (void *)dev);
1355
1356         /* Clean datapath event and queue/vec mapping */
1357         rte_intr_efd_disable(intr_handle);
1358         if (intr_handle->intr_vec != NULL) {
1359                 rte_free(intr_handle->intr_vec);
1360                 intr_handle->intr_vec = NULL;
1361         }
1362 }
1363
1364 static void
1365 eth_igb_close(struct rte_eth_dev *dev)
1366 {
1367         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368         struct e1000_adapter *adapter =
1369                 E1000_DEV_PRIVATE(dev->data->dev_private);
1370         struct rte_eth_link link;
1371         struct rte_pci_device *pci_dev;
1372
1373         eth_igb_stop(dev);
1374         adapter->stopped = 1;
1375
1376         e1000_phy_hw_reset(hw);
1377         igb_release_manageability(hw);
1378         igb_hw_control_release(hw);
1379
1380         /* Clear bit for Go Link disconnect */
1381         if (hw->mac.type >= e1000_82580) {
1382                 uint32_t phpm_reg;
1383
1384                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1385                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1386                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1387         }
1388
1389         igb_dev_free_queues(dev);
1390
1391         pci_dev = dev->pci_dev;
1392         if (pci_dev->intr_handle.intr_vec) {
1393                 rte_free(pci_dev->intr_handle.intr_vec);
1394                 pci_dev->intr_handle.intr_vec = NULL;
1395         }
1396
1397         memset(&link, 0, sizeof(link));
1398         rte_igb_dev_atomic_write_link_status(dev, &link);
1399 }
1400
1401 static int
1402 igb_get_rx_buffer_size(struct e1000_hw *hw)
1403 {
1404         uint32_t rx_buf_size;
1405         if (hw->mac.type == e1000_82576) {
1406                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1407         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1408                 /* PBS needs to be translated according to a lookup table */
1409                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1410                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1411                 rx_buf_size = (rx_buf_size << 10);
1412         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1413                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1414         } else {
1415                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1416         }
1417
1418         return rx_buf_size;
1419 }
1420
1421 /*********************************************************************
1422  *
1423  *  Initialize the hardware
1424  *
1425  **********************************************************************/
1426 static int
1427 igb_hardware_init(struct e1000_hw *hw)
1428 {
1429         uint32_t rx_buf_size;
1430         int diag;
1431
1432         /* Let the firmware know the OS is in control */
1433         igb_hw_control_acquire(hw);
1434
1435         /*
1436          * These parameters control the automatic generation (Tx) and
1437          * response (Rx) to Ethernet PAUSE frames.
1438          * - High water mark should allow for at least two standard size (1518)
1439          *   frames to be received after sending an XOFF.
1440          * - Low water mark works best when it is very near the high water mark.
1441          *   This allows the receiver to restart by sending XON when it has
1442          *   drained a bit. Here we use an arbitrary value of 1500 which will
1443          *   restart after one full frame is pulled from the buffer. There
1444          *   could be several smaller frames in the buffer and if so they will
1445          *   not trigger the XON until their total number reduces the buffer
1446          *   by 1500.
1447          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1448          */
1449         rx_buf_size = igb_get_rx_buffer_size(hw);
1450
1451         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1452         hw->fc.low_water = hw->fc.high_water - 1500;
1453         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1454         hw->fc.send_xon = 1;
1455
1456         /* Set Flow control, use the tunable location if sane */
1457         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1458                 hw->fc.requested_mode = igb_fc_setting;
1459         else
1460                 hw->fc.requested_mode = e1000_fc_none;
1461
1462         /* Issue a global reset */
1463         igb_pf_reset_hw(hw);
1464         E1000_WRITE_REG(hw, E1000_WUC, 0);
1465
1466         diag = e1000_init_hw(hw);
1467         if (diag < 0)
1468                 return (diag);
1469
1470         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1471         e1000_get_phy_info(hw);
1472         e1000_check_for_link(hw);
1473
1474         return (0);
1475 }
1476
1477 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1478 static void
1479 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1480 {
1481         int pause_frames;
1482
1483         uint64_t old_gprc  = stats->gprc;
1484         uint64_t old_gptc  = stats->gptc;
1485         uint64_t old_tpr   = stats->tpr;
1486         uint64_t old_tpt   = stats->tpt;
1487         uint64_t old_rpthc = stats->rpthc;
1488         uint64_t old_hgptc = stats->hgptc;
1489
1490         if(hw->phy.media_type == e1000_media_type_copper ||
1491             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1492                 stats->symerrs +=
1493                     E1000_READ_REG(hw,E1000_SYMERRS);
1494                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1495         }
1496
1497         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1498         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1499         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1500         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1501
1502         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1503         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1504         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1505         stats->dc += E1000_READ_REG(hw, E1000_DC);
1506         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1507         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1508         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1509         /*
1510         ** For watchdog management we need to know if we have been
1511         ** paused during the last interval, so capture that here.
1512         */
1513         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1514         stats->xoffrxc += pause_frames;
1515         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1516         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1517         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1518         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1519         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1520         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1521         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1522         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1523         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1524         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1525         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1526         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1527
1528         /* For the 64-bit byte counters the low dword must be read first. */
1529         /* Both registers clear on the read of the high dword */
1530
1531         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1532         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1533         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1534         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1535         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1536         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1537         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1538
1539         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1540         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1541         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1542         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1543         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1544
1545         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1546         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1547
1548         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1549         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1550         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1551         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1552         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1553         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1554
1555         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1556         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1557         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1558         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1559         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1560         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1561         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1562         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1563
1564         /* Interrupt Counts */
1565
1566         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1567         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1568         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1569         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1570         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1571         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1572         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1573         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1574         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1575
1576         /* Host to Card Statistics */
1577
1578         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1579         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1580         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1581         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1582         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1583         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1584         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1585         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1586         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1587         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1588         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1589         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1590         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1591         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1592         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1593         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1594
1595         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1596         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1597         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1598         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1599         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1600         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1601 }
1602
1603 static void
1604 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1605 {
1606         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607         struct e1000_hw_stats *stats =
1608                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1609
1610         igb_read_stats_registers(hw, stats);
1611
1612         if (rte_stats == NULL)
1613                 return;
1614
1615         /* Rx Errors */
1616         rte_stats->imissed = stats->mpc;
1617         rte_stats->ierrors = stats->crcerrs +
1618                              stats->rlec + stats->ruc + stats->roc +
1619                              rte_stats->imissed +
1620                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1621
1622         /* Tx Errors */
1623         rte_stats->oerrors = stats->ecol + stats->latecol;
1624
1625         rte_stats->ipackets = stats->gprc;
1626         rte_stats->opackets = stats->gptc;
1627         rte_stats->ibytes   = stats->gorc;
1628         rte_stats->obytes   = stats->gotc;
1629 }
1630
1631 static void
1632 eth_igb_stats_reset(struct rte_eth_dev *dev)
1633 {
1634         struct e1000_hw_stats *hw_stats =
1635                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1636
1637         /* HW registers are cleared on read */
1638         eth_igb_stats_get(dev, NULL);
1639
1640         /* Reset software totals */
1641         memset(hw_stats, 0, sizeof(*hw_stats));
1642 }
1643
1644 static void
1645 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1646 {
1647         struct e1000_hw_stats *stats =
1648                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1649
1650         /* HW registers are cleared on read */
1651         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1652
1653         /* Reset software totals */
1654         memset(stats, 0, sizeof(*stats));
1655 }
1656
1657 static int
1658 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1659                    unsigned n)
1660 {
1661         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662         struct e1000_hw_stats *hw_stats =
1663                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1664         unsigned i;
1665
1666         if (n < IGB_NB_XSTATS)
1667                 return IGB_NB_XSTATS;
1668
1669         igb_read_stats_registers(hw, hw_stats);
1670
1671         /* If this is a reset xstats is NULL, and we have cleared the
1672          * registers by reading them.
1673          */
1674         if (!xstats)
1675                 return 0;
1676
1677         /* Extended stats */
1678         for (i = 0; i < IGB_NB_XSTATS; i++) {
1679                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1680                          "%s", rte_igb_stats_strings[i].name);
1681                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1682                         rte_igb_stats_strings[i].offset);
1683         }
1684
1685         return IGB_NB_XSTATS;
1686 }
1687
1688 static void
1689 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1690 {
1691         /* Good Rx packets, include VF loopback */
1692         UPDATE_VF_STAT(E1000_VFGPRC,
1693             hw_stats->last_gprc, hw_stats->gprc);
1694
1695         /* Good Rx octets, include VF loopback */
1696         UPDATE_VF_STAT(E1000_VFGORC,
1697             hw_stats->last_gorc, hw_stats->gorc);
1698
1699         /* Good Tx packets, include VF loopback */
1700         UPDATE_VF_STAT(E1000_VFGPTC,
1701             hw_stats->last_gptc, hw_stats->gptc);
1702
1703         /* Good Tx octets, include VF loopback */
1704         UPDATE_VF_STAT(E1000_VFGOTC,
1705             hw_stats->last_gotc, hw_stats->gotc);
1706
1707         /* Rx Multicst packets */
1708         UPDATE_VF_STAT(E1000_VFMPRC,
1709             hw_stats->last_mprc, hw_stats->mprc);
1710
1711         /* Good Rx loopback packets */
1712         UPDATE_VF_STAT(E1000_VFGPRLBC,
1713             hw_stats->last_gprlbc, hw_stats->gprlbc);
1714
1715         /* Good Rx loopback octets */
1716         UPDATE_VF_STAT(E1000_VFGORLBC,
1717             hw_stats->last_gorlbc, hw_stats->gorlbc);
1718
1719         /* Good Tx loopback packets */
1720         UPDATE_VF_STAT(E1000_VFGPTLBC,
1721             hw_stats->last_gptlbc, hw_stats->gptlbc);
1722
1723         /* Good Tx loopback octets */
1724         UPDATE_VF_STAT(E1000_VFGOTLBC,
1725             hw_stats->last_gotlbc, hw_stats->gotlbc);
1726 }
1727
1728 static int
1729 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1730                      unsigned n)
1731 {
1732         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1734                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1735         unsigned i;
1736
1737         if (n < IGBVF_NB_XSTATS)
1738                 return IGBVF_NB_XSTATS;
1739
1740         igbvf_read_stats_registers(hw, hw_stats);
1741
1742         if (!xstats)
1743                 return 0;
1744
1745         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1746                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1747                          rte_igbvf_stats_strings[i].name);
1748                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1749                         rte_igbvf_stats_strings[i].offset);
1750         }
1751
1752         return IGBVF_NB_XSTATS;
1753 }
1754
1755 static void
1756 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1757 {
1758         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1760                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1761
1762         igbvf_read_stats_registers(hw, hw_stats);
1763
1764         if (rte_stats == NULL)
1765                 return;
1766
1767         rte_stats->ipackets = hw_stats->gprc;
1768         rte_stats->ibytes = hw_stats->gorc;
1769         rte_stats->opackets = hw_stats->gptc;
1770         rte_stats->obytes = hw_stats->gotc;
1771         rte_stats->imcasts = hw_stats->mprc;
1772         rte_stats->ilbpackets = hw_stats->gprlbc;
1773         rte_stats->ilbbytes = hw_stats->gorlbc;
1774         rte_stats->olbpackets = hw_stats->gptlbc;
1775         rte_stats->olbbytes = hw_stats->gotlbc;
1776 }
1777
1778 static void
1779 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1780 {
1781         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1782                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1783
1784         /* Sync HW register to the last stats */
1785         eth_igbvf_stats_get(dev, NULL);
1786
1787         /* reset HW current stats*/
1788         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1789                offsetof(struct e1000_vf_stats, gprc));
1790 }
1791
1792 static void
1793 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1794 {
1795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796
1797         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1798         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1799         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1800         dev_info->rx_offload_capa =
1801                 DEV_RX_OFFLOAD_VLAN_STRIP |
1802                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1803                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1804                 DEV_RX_OFFLOAD_TCP_CKSUM;
1805         dev_info->tx_offload_capa =
1806                 DEV_TX_OFFLOAD_VLAN_INSERT |
1807                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1808                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1809                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1810                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1811                 DEV_TX_OFFLOAD_TCP_TSO;
1812
1813         switch (hw->mac.type) {
1814         case e1000_82575:
1815                 dev_info->max_rx_queues = 4;
1816                 dev_info->max_tx_queues = 4;
1817                 dev_info->max_vmdq_pools = 0;
1818                 break;
1819
1820         case e1000_82576:
1821                 dev_info->max_rx_queues = 16;
1822                 dev_info->max_tx_queues = 16;
1823                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1824                 dev_info->vmdq_queue_num = 16;
1825                 break;
1826
1827         case e1000_82580:
1828                 dev_info->max_rx_queues = 8;
1829                 dev_info->max_tx_queues = 8;
1830                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1831                 dev_info->vmdq_queue_num = 8;
1832                 break;
1833
1834         case e1000_i350:
1835                 dev_info->max_rx_queues = 8;
1836                 dev_info->max_tx_queues = 8;
1837                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1838                 dev_info->vmdq_queue_num = 8;
1839                 break;
1840
1841         case e1000_i354:
1842                 dev_info->max_rx_queues = 8;
1843                 dev_info->max_tx_queues = 8;
1844                 break;
1845
1846         case e1000_i210:
1847                 dev_info->max_rx_queues = 4;
1848                 dev_info->max_tx_queues = 4;
1849                 dev_info->max_vmdq_pools = 0;
1850                 break;
1851
1852         case e1000_i211:
1853                 dev_info->max_rx_queues = 2;
1854                 dev_info->max_tx_queues = 2;
1855                 dev_info->max_vmdq_pools = 0;
1856                 break;
1857
1858         default:
1859                 /* Should not happen */
1860                 break;
1861         }
1862         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1863         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1864         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1865
1866         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1867                 .rx_thresh = {
1868                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1869                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1870                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1871                 },
1872                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1873                 .rx_drop_en = 0,
1874         };
1875
1876         dev_info->default_txconf = (struct rte_eth_txconf) {
1877                 .tx_thresh = {
1878                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1879                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1880                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1881                 },
1882                 .txq_flags = 0,
1883         };
1884
1885         dev_info->rx_desc_lim = rx_desc_lim;
1886         dev_info->tx_desc_lim = tx_desc_lim;
1887 }
1888
1889 static void
1890 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1891 {
1892         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893
1894         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1895         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1896         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1897         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1898                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1899                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1900                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1901         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1902                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1903                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1904                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1905                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1906                                 DEV_TX_OFFLOAD_TCP_TSO;
1907         switch (hw->mac.type) {
1908         case e1000_vfadapt:
1909                 dev_info->max_rx_queues = 2;
1910                 dev_info->max_tx_queues = 2;
1911                 break;
1912         case e1000_vfadapt_i350:
1913                 dev_info->max_rx_queues = 1;
1914                 dev_info->max_tx_queues = 1;
1915                 break;
1916         default:
1917                 /* Should not happen */
1918                 break;
1919         }
1920
1921         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1922                 .rx_thresh = {
1923                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1924                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1925                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1926                 },
1927                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1928                 .rx_drop_en = 0,
1929         };
1930
1931         dev_info->default_txconf = (struct rte_eth_txconf) {
1932                 .tx_thresh = {
1933                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1934                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1935                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1936                 },
1937                 .txq_flags = 0,
1938         };
1939
1940         dev_info->rx_desc_lim = rx_desc_lim;
1941         dev_info->tx_desc_lim = tx_desc_lim;
1942 }
1943
1944 /* return 0 means link status changed, -1 means not changed */
1945 static int
1946 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1947 {
1948         struct e1000_hw *hw =
1949                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         struct rte_eth_link link, old;
1951         int link_check, count;
1952
1953         link_check = 0;
1954         hw->mac.get_link_status = 1;
1955
1956         /* possible wait-to-complete in up to 9 seconds */
1957         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1958                 /* Read the real link status */
1959                 switch (hw->phy.media_type) {
1960                 case e1000_media_type_copper:
1961                         /* Do the work to read phy */
1962                         e1000_check_for_link(hw);
1963                         link_check = !hw->mac.get_link_status;
1964                         break;
1965
1966                 case e1000_media_type_fiber:
1967                         e1000_check_for_link(hw);
1968                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1969                                       E1000_STATUS_LU);
1970                         break;
1971
1972                 case e1000_media_type_internal_serdes:
1973                         e1000_check_for_link(hw);
1974                         link_check = hw->mac.serdes_has_link;
1975                         break;
1976
1977                 /* VF device is type_unknown */
1978                 case e1000_media_type_unknown:
1979                         eth_igbvf_link_update(hw);
1980                         link_check = !hw->mac.get_link_status;
1981                         break;
1982
1983                 default:
1984                         break;
1985                 }
1986                 if (link_check || wait_to_complete == 0)
1987                         break;
1988                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1989         }
1990         memset(&link, 0, sizeof(link));
1991         rte_igb_dev_atomic_read_link_status(dev, &link);
1992         old = link;
1993
1994         /* Now we check if a transition has happened */
1995         if (link_check) {
1996                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1997                                           &link.link_duplex);
1998                 link.link_status = 1;
1999         } else if (!link_check) {
2000                 link.link_speed = 0;
2001                 link.link_duplex = 0;
2002                 link.link_status = 0;
2003         }
2004         rte_igb_dev_atomic_write_link_status(dev, &link);
2005
2006         /* not changed */
2007         if (old.link_status == link.link_status)
2008                 return -1;
2009
2010         /* changed */
2011         return 0;
2012 }
2013
2014 /*
2015  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2016  * For ASF and Pass Through versions of f/w this means
2017  * that the driver is loaded.
2018  */
2019 static void
2020 igb_hw_control_acquire(struct e1000_hw *hw)
2021 {
2022         uint32_t ctrl_ext;
2023
2024         /* Let firmware know the driver has taken over */
2025         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2026         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2027 }
2028
2029 /*
2030  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2031  * For ASF and Pass Through versions of f/w this means that the
2032  * driver is no longer loaded.
2033  */
2034 static void
2035 igb_hw_control_release(struct e1000_hw *hw)
2036 {
2037         uint32_t ctrl_ext;
2038
2039         /* Let firmware taken over control of h/w */
2040         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2041         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2042                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2043 }
2044
2045 /*
2046  * Bit of a misnomer, what this really means is
2047  * to enable OS management of the system... aka
2048  * to disable special hardware management features.
2049  */
2050 static void
2051 igb_init_manageability(struct e1000_hw *hw)
2052 {
2053         if (e1000_enable_mng_pass_thru(hw)) {
2054                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2055                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2056
2057                 /* disable hardware interception of ARP */
2058                 manc &= ~(E1000_MANC_ARP_EN);
2059
2060                 /* enable receiving management packets to the host */
2061                 manc |= E1000_MANC_EN_MNG2HOST;
2062                 manc2h |= 1 << 5;  /* Mng Port 623 */
2063                 manc2h |= 1 << 6;  /* Mng Port 664 */
2064                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2065                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2066         }
2067 }
2068
2069 static void
2070 igb_release_manageability(struct e1000_hw *hw)
2071 {
2072         if (e1000_enable_mng_pass_thru(hw)) {
2073                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2074
2075                 manc |= E1000_MANC_ARP_EN;
2076                 manc &= ~E1000_MANC_EN_MNG2HOST;
2077
2078                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2079         }
2080 }
2081
2082 static void
2083 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2084 {
2085         struct e1000_hw *hw =
2086                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         uint32_t rctl;
2088
2089         rctl = E1000_READ_REG(hw, E1000_RCTL);
2090         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2091         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2092 }
2093
2094 static void
2095 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2096 {
2097         struct e1000_hw *hw =
2098                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t rctl;
2100
2101         rctl = E1000_READ_REG(hw, E1000_RCTL);
2102         rctl &= (~E1000_RCTL_UPE);
2103         if (dev->data->all_multicast == 1)
2104                 rctl |= E1000_RCTL_MPE;
2105         else
2106                 rctl &= (~E1000_RCTL_MPE);
2107         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2108 }
2109
2110 static void
2111 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2112 {
2113         struct e1000_hw *hw =
2114                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115         uint32_t rctl;
2116
2117         rctl = E1000_READ_REG(hw, E1000_RCTL);
2118         rctl |= E1000_RCTL_MPE;
2119         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2120 }
2121
2122 static void
2123 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2124 {
2125         struct e1000_hw *hw =
2126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         uint32_t rctl;
2128
2129         if (dev->data->promiscuous == 1)
2130                 return; /* must remain in all_multicast mode */
2131         rctl = E1000_READ_REG(hw, E1000_RCTL);
2132         rctl &= (~E1000_RCTL_MPE);
2133         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2134 }
2135
2136 static int
2137 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2138 {
2139         struct e1000_hw *hw =
2140                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         struct e1000_vfta * shadow_vfta =
2142                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2143         uint32_t vfta;
2144         uint32_t vid_idx;
2145         uint32_t vid_bit;
2146
2147         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2148                               E1000_VFTA_ENTRY_MASK);
2149         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2150         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2151         if (on)
2152                 vfta |= vid_bit;
2153         else
2154                 vfta &= ~vid_bit;
2155         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2156
2157         /* update local VFTA copy */
2158         shadow_vfta->vfta[vid_idx] = vfta;
2159
2160         return 0;
2161 }
2162
2163 static void
2164 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2165 {
2166         struct e1000_hw *hw =
2167                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         uint32_t reg = ETHER_TYPE_VLAN ;
2169
2170         reg |= (tpid << 16);
2171         E1000_WRITE_REG(hw, E1000_VET, reg);
2172 }
2173
2174 static void
2175 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2176 {
2177         struct e1000_hw *hw =
2178                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         uint32_t reg;
2180
2181         /* Filter Table Disable */
2182         reg = E1000_READ_REG(hw, E1000_RCTL);
2183         reg &= ~E1000_RCTL_CFIEN;
2184         reg &= ~E1000_RCTL_VFE;
2185         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2186 }
2187
2188 static void
2189 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2190 {
2191         struct e1000_hw *hw =
2192                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         struct e1000_vfta * shadow_vfta =
2194                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2195         uint32_t reg;
2196         int i;
2197
2198         /* Filter Table Enable, CFI not used for packet acceptance */
2199         reg = E1000_READ_REG(hw, E1000_RCTL);
2200         reg &= ~E1000_RCTL_CFIEN;
2201         reg |= E1000_RCTL_VFE;
2202         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2203
2204         /* restore VFTA table */
2205         for (i = 0; i < IGB_VFTA_SIZE; i++)
2206                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2207 }
2208
2209 static void
2210 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2211 {
2212         struct e1000_hw *hw =
2213                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214         uint32_t reg;
2215
2216         /* VLAN Mode Disable */
2217         reg = E1000_READ_REG(hw, E1000_CTRL);
2218         reg &= ~E1000_CTRL_VME;
2219         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2220 }
2221
2222 static void
2223 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2224 {
2225         struct e1000_hw *hw =
2226                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         uint32_t reg;
2228
2229         /* VLAN Mode Enable */
2230         reg = E1000_READ_REG(hw, E1000_CTRL);
2231         reg |= E1000_CTRL_VME;
2232         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2233 }
2234
2235 static void
2236 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2237 {
2238         struct e1000_hw *hw =
2239                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         uint32_t reg;
2241
2242         /* CTRL_EXT: Extended VLAN */
2243         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2244         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2245         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2246
2247         /* Update maximum packet length */
2248         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2249                 E1000_WRITE_REG(hw, E1000_RLPML,
2250                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2251                                                 VLAN_TAG_SIZE);
2252 }
2253
2254 static void
2255 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2256 {
2257         struct e1000_hw *hw =
2258                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2259         uint32_t reg;
2260
2261         /* CTRL_EXT: Extended VLAN */
2262         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2263         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2264         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2265
2266         /* Update maximum packet length */
2267         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2268                 E1000_WRITE_REG(hw, E1000_RLPML,
2269                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2270                                                 2 * VLAN_TAG_SIZE);
2271 }
2272
2273 static void
2274 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2275 {
2276         if(mask & ETH_VLAN_STRIP_MASK){
2277                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2278                         igb_vlan_hw_strip_enable(dev);
2279                 else
2280                         igb_vlan_hw_strip_disable(dev);
2281         }
2282
2283         if(mask & ETH_VLAN_FILTER_MASK){
2284                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2285                         igb_vlan_hw_filter_enable(dev);
2286                 else
2287                         igb_vlan_hw_filter_disable(dev);
2288         }
2289
2290         if(mask & ETH_VLAN_EXTEND_MASK){
2291                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2292                         igb_vlan_hw_extend_enable(dev);
2293                 else
2294                         igb_vlan_hw_extend_disable(dev);
2295         }
2296 }
2297
2298
2299 /**
2300  * It enables the interrupt mask and then enable the interrupt.
2301  *
2302  * @param dev
2303  *  Pointer to struct rte_eth_dev.
2304  *
2305  * @return
2306  *  - On success, zero.
2307  *  - On failure, a negative value.
2308  */
2309 static int
2310 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2311 {
2312         struct e1000_interrupt *intr =
2313                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2314
2315         intr->mask |= E1000_ICR_LSC;
2316
2317         return 0;
2318 }
2319
2320 /* It clears the interrupt causes and enables the interrupt.
2321  * It will be called once only during nic initialized.
2322  *
2323  * @param dev
2324  *  Pointer to struct rte_eth_dev.
2325  *
2326  * @return
2327  *  - On success, zero.
2328  *  - On failure, a negative value.
2329  */
2330 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2331 {
2332         uint32_t mask, regval;
2333         struct e1000_hw *hw =
2334                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335         struct rte_eth_dev_info dev_info;
2336
2337         memset(&dev_info, 0, sizeof(dev_info));
2338         eth_igb_infos_get(dev, &dev_info);
2339
2340         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2341         regval = E1000_READ_REG(hw, E1000_EIMS);
2342         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2343
2344         return 0;
2345 }
2346
2347 /*
2348  * It reads ICR and gets interrupt causes, check it and set a bit flag
2349  * to update link status.
2350  *
2351  * @param dev
2352  *  Pointer to struct rte_eth_dev.
2353  *
2354  * @return
2355  *  - On success, zero.
2356  *  - On failure, a negative value.
2357  */
2358 static int
2359 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2360 {
2361         uint32_t icr;
2362         struct e1000_hw *hw =
2363                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364         struct e1000_interrupt *intr =
2365                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2366
2367         igb_intr_disable(hw);
2368
2369         /* read-on-clear nic registers here */
2370         icr = E1000_READ_REG(hw, E1000_ICR);
2371
2372         intr->flags = 0;
2373         if (icr & E1000_ICR_LSC) {
2374                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2375         }
2376
2377         if (icr & E1000_ICR_VMMB)
2378                 intr->flags |= E1000_FLAG_MAILBOX;
2379
2380         return 0;
2381 }
2382
2383 /*
2384  * It executes link_update after knowing an interrupt is prsent.
2385  *
2386  * @param dev
2387  *  Pointer to struct rte_eth_dev.
2388  *
2389  * @return
2390  *  - On success, zero.
2391  *  - On failure, a negative value.
2392  */
2393 static int
2394 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2395 {
2396         struct e1000_hw *hw =
2397                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         struct e1000_interrupt *intr =
2399                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400         uint32_t tctl, rctl;
2401         struct rte_eth_link link;
2402         int ret;
2403
2404         if (intr->flags & E1000_FLAG_MAILBOX) {
2405                 igb_pf_mbx_process(dev);
2406                 intr->flags &= ~E1000_FLAG_MAILBOX;
2407         }
2408
2409         igb_intr_enable(dev);
2410         rte_intr_enable(&(dev->pci_dev->intr_handle));
2411
2412         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2413                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2414
2415                 /* set get_link_status to check register later */
2416                 hw->mac.get_link_status = 1;
2417                 ret = eth_igb_link_update(dev, 0);
2418
2419                 /* check if link has changed */
2420                 if (ret < 0)
2421                         return 0;
2422
2423                 memset(&link, 0, sizeof(link));
2424                 rte_igb_dev_atomic_read_link_status(dev, &link);
2425                 if (link.link_status) {
2426                         PMD_INIT_LOG(INFO,
2427                                      " Port %d: Link Up - speed %u Mbps - %s",
2428                                      dev->data->port_id,
2429                                      (unsigned)link.link_speed,
2430                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2431                                      "full-duplex" : "half-duplex");
2432                 } else {
2433                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2434                                      dev->data->port_id);
2435                 }
2436
2437                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2438                              dev->pci_dev->addr.domain,
2439                              dev->pci_dev->addr.bus,
2440                              dev->pci_dev->addr.devid,
2441                              dev->pci_dev->addr.function);
2442                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2443                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2444                 if (link.link_status) {
2445                         /* enable Tx/Rx */
2446                         tctl |= E1000_TCTL_EN;
2447                         rctl |= E1000_RCTL_EN;
2448                 } else {
2449                         /* disable Tx/Rx */
2450                         tctl &= ~E1000_TCTL_EN;
2451                         rctl &= ~E1000_RCTL_EN;
2452                 }
2453                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2454                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2455                 E1000_WRITE_FLUSH(hw);
2456                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2457         }
2458
2459         return 0;
2460 }
2461
2462 /**
2463  * Interrupt handler which shall be registered at first.
2464  *
2465  * @param handle
2466  *  Pointer to interrupt handle.
2467  * @param param
2468  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2469  *
2470  * @return
2471  *  void
2472  */
2473 static void
2474 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2475                                                         void *param)
2476 {
2477         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2478
2479         eth_igb_interrupt_get_status(dev);
2480         eth_igb_interrupt_action(dev);
2481 }
2482
2483 static int
2484 eth_igb_led_on(struct rte_eth_dev *dev)
2485 {
2486         struct e1000_hw *hw;
2487
2488         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2490 }
2491
2492 static int
2493 eth_igb_led_off(struct rte_eth_dev *dev)
2494 {
2495         struct e1000_hw *hw;
2496
2497         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2499 }
2500
2501 static int
2502 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2503 {
2504         struct e1000_hw *hw;
2505         uint32_t ctrl;
2506         int tx_pause;
2507         int rx_pause;
2508
2509         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510         fc_conf->pause_time = hw->fc.pause_time;
2511         fc_conf->high_water = hw->fc.high_water;
2512         fc_conf->low_water = hw->fc.low_water;
2513         fc_conf->send_xon = hw->fc.send_xon;
2514         fc_conf->autoneg = hw->mac.autoneg;
2515
2516         /*
2517          * Return rx_pause and tx_pause status according to actual setting of
2518          * the TFCE and RFCE bits in the CTRL register.
2519          */
2520         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2521         if (ctrl & E1000_CTRL_TFCE)
2522                 tx_pause = 1;
2523         else
2524                 tx_pause = 0;
2525
2526         if (ctrl & E1000_CTRL_RFCE)
2527                 rx_pause = 1;
2528         else
2529                 rx_pause = 0;
2530
2531         if (rx_pause && tx_pause)
2532                 fc_conf->mode = RTE_FC_FULL;
2533         else if (rx_pause)
2534                 fc_conf->mode = RTE_FC_RX_PAUSE;
2535         else if (tx_pause)
2536                 fc_conf->mode = RTE_FC_TX_PAUSE;
2537         else
2538                 fc_conf->mode = RTE_FC_NONE;
2539
2540         return 0;
2541 }
2542
2543 static int
2544 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2545 {
2546         struct e1000_hw *hw;
2547         int err;
2548         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2549                 e1000_fc_none,
2550                 e1000_fc_rx_pause,
2551                 e1000_fc_tx_pause,
2552                 e1000_fc_full
2553         };
2554         uint32_t rx_buf_size;
2555         uint32_t max_high_water;
2556         uint32_t rctl;
2557
2558         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559         if (fc_conf->autoneg != hw->mac.autoneg)
2560                 return -ENOTSUP;
2561         rx_buf_size = igb_get_rx_buffer_size(hw);
2562         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2563
2564         /* At least reserve one Ethernet frame for watermark */
2565         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2566         if ((fc_conf->high_water > max_high_water) ||
2567             (fc_conf->high_water < fc_conf->low_water)) {
2568                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2569                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2570                 return (-EINVAL);
2571         }
2572
2573         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2574         hw->fc.pause_time     = fc_conf->pause_time;
2575         hw->fc.high_water     = fc_conf->high_water;
2576         hw->fc.low_water      = fc_conf->low_water;
2577         hw->fc.send_xon       = fc_conf->send_xon;
2578
2579         err = e1000_setup_link_generic(hw);
2580         if (err == E1000_SUCCESS) {
2581
2582                 /* check if we want to forward MAC frames - driver doesn't have native
2583                  * capability to do that, so we'll write the registers ourselves */
2584
2585                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2586
2587                 /* set or clear MFLCN.PMCF bit depending on configuration */
2588                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2589                         rctl |= E1000_RCTL_PMCF;
2590                 else
2591                         rctl &= ~E1000_RCTL_PMCF;
2592
2593                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2594                 E1000_WRITE_FLUSH(hw);
2595
2596                 return 0;
2597         }
2598
2599         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2600         return (-EIO);
2601 }
2602
2603 #define E1000_RAH_POOLSEL_SHIFT      (18)
2604 static void
2605 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2606                 uint32_t index, __rte_unused uint32_t pool)
2607 {
2608         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2609         uint32_t rah;
2610
2611         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2612         rah = E1000_READ_REG(hw, E1000_RAH(index));
2613         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2614         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2615 }
2616
2617 static void
2618 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2619 {
2620         uint8_t addr[ETHER_ADDR_LEN];
2621         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622
2623         memset(addr, 0, sizeof(addr));
2624
2625         e1000_rar_set(hw, addr, index);
2626 }
2627
2628 static void
2629 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2630                                 struct ether_addr *addr)
2631 {
2632         eth_igb_rar_clear(dev, 0);
2633
2634         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2635 }
2636 /*
2637  * Virtual Function operations
2638  */
2639 static void
2640 igbvf_intr_disable(struct e1000_hw *hw)
2641 {
2642         PMD_INIT_FUNC_TRACE();
2643
2644         /* Clear interrupt mask to stop from interrupts being generated */
2645         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2646
2647         E1000_WRITE_FLUSH(hw);
2648 }
2649
2650 static void
2651 igbvf_stop_adapter(struct rte_eth_dev *dev)
2652 {
2653         u32 reg_val;
2654         u16 i;
2655         struct rte_eth_dev_info dev_info;
2656         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657
2658         memset(&dev_info, 0, sizeof(dev_info));
2659         eth_igbvf_infos_get(dev, &dev_info);
2660
2661         /* Clear interrupt mask to stop from interrupts being generated */
2662         igbvf_intr_disable(hw);
2663
2664         /* Clear any pending interrupts, flush previous writes */
2665         E1000_READ_REG(hw, E1000_EICR);
2666
2667         /* Disable the transmit unit.  Each queue must be disabled. */
2668         for (i = 0; i < dev_info.max_tx_queues; i++)
2669                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2670
2671         /* Disable the receive unit by stopping each queue */
2672         for (i = 0; i < dev_info.max_rx_queues; i++) {
2673                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2674                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2675                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2676                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2677                         ;
2678         }
2679
2680         /* flush all queues disables */
2681         E1000_WRITE_FLUSH(hw);
2682         msec_delay(2);
2683 }
2684
2685 static int eth_igbvf_link_update(struct e1000_hw *hw)
2686 {
2687         struct e1000_mbx_info *mbx = &hw->mbx;
2688         struct e1000_mac_info *mac = &hw->mac;
2689         int ret_val = E1000_SUCCESS;
2690
2691         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2692
2693         /*
2694          * We only want to run this if there has been a rst asserted.
2695          * in this case that could mean a link change, device reset,
2696          * or a virtual function reset
2697          */
2698
2699         /* If we were hit with a reset or timeout drop the link */
2700         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2701                 mac->get_link_status = TRUE;
2702
2703         if (!mac->get_link_status)
2704                 goto out;
2705
2706         /* if link status is down no point in checking to see if pf is up */
2707         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2708                 goto out;
2709
2710         /* if we passed all the tests above then the link is up and we no
2711          * longer need to check for link */
2712         mac->get_link_status = FALSE;
2713
2714 out:
2715         return ret_val;
2716 }
2717
2718
2719 static int
2720 igbvf_dev_configure(struct rte_eth_dev *dev)
2721 {
2722         struct rte_eth_conf* conf = &dev->data->dev_conf;
2723
2724         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2725                      dev->data->port_id);
2726
2727         /*
2728          * VF has no ability to enable/disable HW CRC
2729          * Keep the persistent behavior the same as Host PF
2730          */
2731 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2732         if (!conf->rxmode.hw_strip_crc) {
2733                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2734                 conf->rxmode.hw_strip_crc = 1;
2735         }
2736 #else
2737         if (conf->rxmode.hw_strip_crc) {
2738                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2739                 conf->rxmode.hw_strip_crc = 0;
2740         }
2741 #endif
2742
2743         return 0;
2744 }
2745
2746 static int
2747 igbvf_dev_start(struct rte_eth_dev *dev)
2748 {
2749         struct e1000_hw *hw =
2750                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751         struct e1000_adapter *adapter =
2752                 E1000_DEV_PRIVATE(dev->data->dev_private);
2753         int ret;
2754
2755         PMD_INIT_FUNC_TRACE();
2756
2757         hw->mac.ops.reset_hw(hw);
2758         adapter->stopped = 0;
2759
2760         /* Set all vfta */
2761         igbvf_set_vfta_all(dev,1);
2762
2763         eth_igbvf_tx_init(dev);
2764
2765         /* This can fail when allocating mbufs for descriptor rings */
2766         ret = eth_igbvf_rx_init(dev);
2767         if (ret) {
2768                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2769                 igb_dev_clear_queues(dev);
2770                 return ret;
2771         }
2772
2773         return 0;
2774 }
2775
2776 static void
2777 igbvf_dev_stop(struct rte_eth_dev *dev)
2778 {
2779         PMD_INIT_FUNC_TRACE();
2780
2781         igbvf_stop_adapter(dev);
2782
2783         /*
2784           * Clear what we set, but we still keep shadow_vfta to
2785           * restore after device starts
2786           */
2787         igbvf_set_vfta_all(dev,0);
2788
2789         igb_dev_clear_queues(dev);
2790 }
2791
2792 static void
2793 igbvf_dev_close(struct rte_eth_dev *dev)
2794 {
2795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796         struct e1000_adapter *adapter =
2797                 E1000_DEV_PRIVATE(dev->data->dev_private);
2798
2799         PMD_INIT_FUNC_TRACE();
2800
2801         e1000_reset_hw(hw);
2802
2803         igbvf_dev_stop(dev);
2804         adapter->stopped = 1;
2805         igb_dev_free_queues(dev);
2806 }
2807
2808 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2809 {
2810         struct e1000_mbx_info *mbx = &hw->mbx;
2811         uint32_t msgbuf[2];
2812         s32 err;
2813
2814         /* After set vlan, vlan strip will also be enabled in igb driver*/
2815         msgbuf[0] = E1000_VF_SET_VLAN;
2816         msgbuf[1] = vid;
2817         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2818         if (on)
2819                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2820
2821         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2822         if (err)
2823                 goto mbx_err;
2824
2825         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2826         if (err)
2827                 goto mbx_err;
2828
2829         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2830         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2831                 err = -EINVAL;
2832
2833 mbx_err:
2834         return err;
2835 }
2836
2837 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2838 {
2839         struct e1000_hw *hw =
2840                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         struct e1000_vfta * shadow_vfta =
2842                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2843         int i = 0, j = 0, vfta = 0, mask = 1;
2844
2845         for (i = 0; i < IGB_VFTA_SIZE; i++){
2846                 vfta = shadow_vfta->vfta[i];
2847                 if(vfta){
2848                         mask = 1;
2849                         for (j = 0; j < 32; j++){
2850                                 if(vfta & mask)
2851                                         igbvf_set_vfta(hw,
2852                                                 (uint16_t)((i<<5)+j), on);
2853                                 mask<<=1;
2854                         }
2855                 }
2856         }
2857
2858 }
2859
2860 static int
2861 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2862 {
2863         struct e1000_hw *hw =
2864                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct e1000_vfta * shadow_vfta =
2866                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2867         uint32_t vid_idx = 0;
2868         uint32_t vid_bit = 0;
2869         int ret = 0;
2870
2871         PMD_INIT_FUNC_TRACE();
2872
2873         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2874         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2875         if(ret){
2876                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2877                 return ret;
2878         }
2879         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2880         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2881
2882         /*Save what we set and retore it after device reset*/
2883         if (on)
2884                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2885         else
2886                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2887
2888         return 0;
2889 }
2890
2891 static void
2892 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2893 {
2894         struct e1000_hw *hw =
2895                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896
2897         /* index is not used by rar_set() */
2898         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2899 }
2900
2901
2902 static int
2903 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2904                         struct rte_eth_rss_reta_entry64 *reta_conf,
2905                         uint16_t reta_size)
2906 {
2907         uint8_t i, j, mask;
2908         uint32_t reta, r;
2909         uint16_t idx, shift;
2910         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911
2912         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2913                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2914                         "(%d) doesn't match the number hardware can supported "
2915                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2916                 return -EINVAL;
2917         }
2918
2919         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2920                 idx = i / RTE_RETA_GROUP_SIZE;
2921                 shift = i % RTE_RETA_GROUP_SIZE;
2922                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2923                                                 IGB_4_BIT_MASK);
2924                 if (!mask)
2925                         continue;
2926                 if (mask == IGB_4_BIT_MASK)
2927                         r = 0;
2928                 else
2929                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2930                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2931                         if (mask & (0x1 << j))
2932                                 reta |= reta_conf[idx].reta[shift + j] <<
2933                                                         (CHAR_BIT * j);
2934                         else
2935                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2936                 }
2937                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2938         }
2939
2940         return 0;
2941 }
2942
2943 static int
2944 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2945                        struct rte_eth_rss_reta_entry64 *reta_conf,
2946                        uint16_t reta_size)
2947 {
2948         uint8_t i, j, mask;
2949         uint32_t reta;
2950         uint16_t idx, shift;
2951         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952
2953         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2954                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2955                         "(%d) doesn't match the number hardware can supported "
2956                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2957                 return -EINVAL;
2958         }
2959
2960         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2961                 idx = i / RTE_RETA_GROUP_SIZE;
2962                 shift = i % RTE_RETA_GROUP_SIZE;
2963                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2964                                                 IGB_4_BIT_MASK);
2965                 if (!mask)
2966                         continue;
2967                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2968                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2969                         if (mask & (0x1 << j))
2970                                 reta_conf[idx].reta[shift + j] =
2971                                         ((reta >> (CHAR_BIT * j)) &
2972                                                 IGB_8_BIT_MASK);
2973                 }
2974         }
2975
2976         return 0;
2977 }
2978
2979 #define MAC_TYPE_FILTER_SUP(type)    do {\
2980         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2981                 (type) != e1000_82576)\
2982                 return -ENOTSUP;\
2983 } while (0)
2984
2985 static int
2986 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2987                         struct rte_eth_syn_filter *filter,
2988                         bool add)
2989 {
2990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2991         uint32_t synqf, rfctl;
2992
2993         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2994                 return -EINVAL;
2995
2996         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2997
2998         if (add) {
2999                 if (synqf & E1000_SYN_FILTER_ENABLE)
3000                         return -EINVAL;
3001
3002                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3003                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3004
3005                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3006                 if (filter->hig_pri)
3007                         rfctl |= E1000_RFCTL_SYNQFP;
3008                 else
3009                         rfctl &= ~E1000_RFCTL_SYNQFP;
3010
3011                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3012         } else {
3013                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3014                         return -ENOENT;
3015                 synqf = 0;
3016         }
3017
3018         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3019         E1000_WRITE_FLUSH(hw);
3020         return 0;
3021 }
3022
3023 static int
3024 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3025                         struct rte_eth_syn_filter *filter)
3026 {
3027         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028         uint32_t synqf, rfctl;
3029
3030         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3031         if (synqf & E1000_SYN_FILTER_ENABLE) {
3032                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3033                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3034                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3035                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3036                 return 0;
3037         }
3038
3039         return -ENOENT;
3040 }
3041
3042 static int
3043 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3044                         enum rte_filter_op filter_op,
3045                         void *arg)
3046 {
3047         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048         int ret;
3049
3050         MAC_TYPE_FILTER_SUP(hw->mac.type);
3051
3052         if (filter_op == RTE_ETH_FILTER_NOP)
3053                 return 0;
3054
3055         if (arg == NULL) {
3056                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3057                             filter_op);
3058                 return -EINVAL;
3059         }
3060
3061         switch (filter_op) {
3062         case RTE_ETH_FILTER_ADD:
3063                 ret = eth_igb_syn_filter_set(dev,
3064                                 (struct rte_eth_syn_filter *)arg,
3065                                 TRUE);
3066                 break;
3067         case RTE_ETH_FILTER_DELETE:
3068                 ret = eth_igb_syn_filter_set(dev,
3069                                 (struct rte_eth_syn_filter *)arg,
3070                                 FALSE);
3071                 break;
3072         case RTE_ETH_FILTER_GET:
3073                 ret = eth_igb_syn_filter_get(dev,
3074                                 (struct rte_eth_syn_filter *)arg);
3075                 break;
3076         default:
3077                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3078                 ret = -EINVAL;
3079                 break;
3080         }
3081
3082         return ret;
3083 }
3084
3085 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3086         if ((type) != e1000_82580 && (type) != e1000_i350)\
3087                 return -ENOSYS; \
3088 } while (0)
3089
3090 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3091 static inline int
3092 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3093                         struct e1000_2tuple_filter_info *filter_info)
3094 {
3095         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3096                 return -EINVAL;
3097         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3098                 return -EINVAL;  /* filter index is out of range. */
3099         if (filter->tcp_flags > TCP_FLAG_ALL)
3100                 return -EINVAL;  /* flags is invalid. */
3101
3102         switch (filter->dst_port_mask) {
3103         case UINT16_MAX:
3104                 filter_info->dst_port_mask = 0;
3105                 filter_info->dst_port = filter->dst_port;
3106                 break;
3107         case 0:
3108                 filter_info->dst_port_mask = 1;
3109                 break;
3110         default:
3111                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3112                 return -EINVAL;
3113         }
3114
3115         switch (filter->proto_mask) {
3116         case UINT8_MAX:
3117                 filter_info->proto_mask = 0;
3118                 filter_info->proto = filter->proto;
3119                 break;
3120         case 0:
3121                 filter_info->proto_mask = 1;
3122                 break;
3123         default:
3124                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3125                 return -EINVAL;
3126         }
3127
3128         filter_info->priority = (uint8_t)filter->priority;
3129         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3130                 filter_info->tcp_flags = filter->tcp_flags;
3131         else
3132                 filter_info->tcp_flags = 0;
3133
3134         return 0;
3135 }
3136
3137 static inline struct e1000_2tuple_filter *
3138 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3139                         struct e1000_2tuple_filter_info *key)
3140 {
3141         struct e1000_2tuple_filter *it;
3142
3143         TAILQ_FOREACH(it, filter_list, entries) {
3144                 if (memcmp(key, &it->filter_info,
3145                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3146                         return it;
3147                 }
3148         }
3149         return NULL;
3150 }
3151
3152 /*
3153  * igb_add_2tuple_filter - add a 2tuple filter
3154  *
3155  * @param
3156  * dev: Pointer to struct rte_eth_dev.
3157  * ntuple_filter: ponter to the filter that will be added.
3158  *
3159  * @return
3160  *    - On success, zero.
3161  *    - On failure, a negative value.
3162  */
3163 static int
3164 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3165                         struct rte_eth_ntuple_filter *ntuple_filter)
3166 {
3167         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3168         struct e1000_filter_info *filter_info =
3169                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3170         struct e1000_2tuple_filter *filter;
3171         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3172         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3173         int i, ret;
3174
3175         filter = rte_zmalloc("e1000_2tuple_filter",
3176                         sizeof(struct e1000_2tuple_filter), 0);
3177         if (filter == NULL)
3178                 return -ENOMEM;
3179
3180         ret = ntuple_filter_to_2tuple(ntuple_filter,
3181                                       &filter->filter_info);
3182         if (ret < 0) {
3183                 rte_free(filter);
3184                 return ret;
3185         }
3186         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3187                                          &filter->filter_info) != NULL) {
3188                 PMD_DRV_LOG(ERR, "filter exists.");
3189                 rte_free(filter);
3190                 return -EEXIST;
3191         }
3192         filter->queue = ntuple_filter->queue;
3193
3194         /*
3195          * look for an unused 2tuple filter index,
3196          * and insert the filter to list.
3197          */
3198         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3199                 if (!(filter_info->twotuple_mask & (1 << i))) {
3200                         filter_info->twotuple_mask |= 1 << i;
3201                         filter->index = i;
3202                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3203                                           filter,
3204                                           entries);
3205                         break;
3206                 }
3207         }
3208         if (i >= E1000_MAX_TTQF_FILTERS) {
3209                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3210                 rte_free(filter);
3211                 return -ENOSYS;
3212         }
3213
3214         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3215         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3216                 imir |= E1000_IMIR_PORT_BP;
3217         else
3218                 imir &= ~E1000_IMIR_PORT_BP;
3219
3220         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3221
3222         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3223         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3224         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3225         if (filter->filter_info.proto_mask == 0)
3226                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3227
3228         /* tcp flags bits setting. */
3229         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3230                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3231                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3232                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3233                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3234                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3235                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3236                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3237                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3238                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3239                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3240                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3241                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3242         } else
3243                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3244         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3245         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3246         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3247         return 0;
3248 }
3249
3250 /*
3251  * igb_remove_2tuple_filter - remove a 2tuple filter
3252  *
3253  * @param
3254  * dev: Pointer to struct rte_eth_dev.
3255  * ntuple_filter: ponter to the filter that will be removed.
3256  *
3257  * @return
3258  *    - On success, zero.
3259  *    - On failure, a negative value.
3260  */
3261 static int
3262 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3263                         struct rte_eth_ntuple_filter *ntuple_filter)
3264 {
3265         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3266         struct e1000_filter_info *filter_info =
3267                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3268         struct e1000_2tuple_filter_info filter_2tuple;
3269         struct e1000_2tuple_filter *filter;
3270         int ret;
3271
3272         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3273         ret = ntuple_filter_to_2tuple(ntuple_filter,
3274                                       &filter_2tuple);
3275         if (ret < 0)
3276                 return ret;
3277
3278         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3279                                          &filter_2tuple);
3280         if (filter == NULL) {
3281                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3282                 return -ENOENT;
3283         }
3284
3285         filter_info->twotuple_mask &= ~(1 << filter->index);
3286         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3287         rte_free(filter);
3288
3289         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3290         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3291         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3292         return 0;
3293 }
3294
3295 static inline struct e1000_flex_filter *
3296 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3297                         struct e1000_flex_filter_info *key)
3298 {
3299         struct e1000_flex_filter *it;
3300
3301         TAILQ_FOREACH(it, filter_list, entries) {
3302                 if (memcmp(key, &it->filter_info,
3303                         sizeof(struct e1000_flex_filter_info)) == 0)
3304                         return it;
3305         }
3306
3307         return NULL;
3308 }
3309
3310 static int
3311 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3312                         struct rte_eth_flex_filter *filter,
3313                         bool add)
3314 {
3315         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316         struct e1000_filter_info *filter_info =
3317                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3318         struct e1000_flex_filter *flex_filter, *it;
3319         uint32_t wufc, queueing, mask;
3320         uint32_t reg_off;
3321         uint8_t shift, i, j = 0;
3322
3323         flex_filter = rte_zmalloc("e1000_flex_filter",
3324                         sizeof(struct e1000_flex_filter), 0);
3325         if (flex_filter == NULL)
3326                 return -ENOMEM;
3327
3328         flex_filter->filter_info.len = filter->len;
3329         flex_filter->filter_info.priority = filter->priority;
3330         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3331         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3332                 mask = 0;
3333                 /* reverse bits in flex filter's mask*/
3334                 for (shift = 0; shift < CHAR_BIT; shift++) {
3335                         if (filter->mask[i] & (0x01 << shift))
3336                                 mask |= (0x80 >> shift);
3337                 }
3338                 flex_filter->filter_info.mask[i] = mask;
3339         }
3340
3341         wufc = E1000_READ_REG(hw, E1000_WUFC);
3342         if (flex_filter->index < E1000_MAX_FHFT)
3343                 reg_off = E1000_FHFT(flex_filter->index);
3344         else
3345                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3346
3347         if (add) {
3348                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3349                                 &flex_filter->filter_info) != NULL) {
3350                         PMD_DRV_LOG(ERR, "filter exists.");
3351                         rte_free(flex_filter);
3352                         return -EEXIST;
3353                 }
3354                 flex_filter->queue = filter->queue;
3355                 /*
3356                  * look for an unused flex filter index
3357                  * and insert the filter into the list.
3358                  */
3359                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3360                         if (!(filter_info->flex_mask & (1 << i))) {
3361                                 filter_info->flex_mask |= 1 << i;
3362                                 flex_filter->index = i;
3363                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3364                                         flex_filter,
3365                                         entries);
3366                                 break;
3367                         }
3368                 }
3369                 if (i >= E1000_MAX_FLEX_FILTERS) {
3370                         PMD_DRV_LOG(ERR, "flex filters are full.");
3371                         rte_free(flex_filter);
3372                         return -ENOSYS;
3373                 }
3374
3375                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3376                                 (E1000_WUFC_FLX0 << flex_filter->index));
3377                 queueing = filter->len |
3378                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3379                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3380                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3381                                 queueing);
3382                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3383                         E1000_WRITE_REG(hw, reg_off,
3384                                         flex_filter->filter_info.dwords[j]);
3385                         reg_off += sizeof(uint32_t);
3386                         E1000_WRITE_REG(hw, reg_off,
3387                                         flex_filter->filter_info.dwords[++j]);
3388                         reg_off += sizeof(uint32_t);
3389                         E1000_WRITE_REG(hw, reg_off,
3390                                 (uint32_t)flex_filter->filter_info.mask[i]);
3391                         reg_off += sizeof(uint32_t) * 2;
3392                         ++j;
3393                 }
3394         } else {
3395                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3396                                 &flex_filter->filter_info);
3397                 if (it == NULL) {
3398                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3399                         rte_free(flex_filter);
3400                         return -ENOENT;
3401                 }
3402
3403                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3404                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3405                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3406                         (~(E1000_WUFC_FLX0 << it->index)));
3407
3408                 filter_info->flex_mask &= ~(1 << it->index);
3409                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3410                 rte_free(it);
3411                 rte_free(flex_filter);
3412         }
3413
3414         return 0;
3415 }
3416
3417 static int
3418 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3419                         struct rte_eth_flex_filter *filter)
3420 {
3421         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422         struct e1000_filter_info *filter_info =
3423                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3424         struct e1000_flex_filter flex_filter, *it;
3425         uint32_t wufc, queueing, wufc_en = 0;
3426
3427         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3428         flex_filter.filter_info.len = filter->len;
3429         flex_filter.filter_info.priority = filter->priority;
3430         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3431         memcpy(flex_filter.filter_info.mask, filter->mask,
3432                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3433
3434         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3435                                 &flex_filter.filter_info);
3436         if (it == NULL) {
3437                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3438                 return -ENOENT;
3439         }
3440
3441         wufc = E1000_READ_REG(hw, E1000_WUFC);
3442         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3443
3444         if ((wufc & wufc_en) == wufc_en) {
3445                 uint32_t reg_off = 0;
3446                 if (it->index < E1000_MAX_FHFT)
3447                         reg_off = E1000_FHFT(it->index);
3448                 else
3449                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3450
3451                 queueing = E1000_READ_REG(hw,
3452                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3453                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3454                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3455                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3456                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3457                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3458                 return 0;
3459         }
3460         return -ENOENT;
3461 }
3462
3463 static int
3464 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3465                         enum rte_filter_op filter_op,
3466                         void *arg)
3467 {
3468         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469         struct rte_eth_flex_filter *filter;
3470         int ret = 0;
3471
3472         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3473
3474         if (filter_op == RTE_ETH_FILTER_NOP)
3475                 return ret;
3476
3477         if (arg == NULL) {
3478                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3479                             filter_op);
3480                 return -EINVAL;
3481         }
3482
3483         filter = (struct rte_eth_flex_filter *)arg;
3484         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3485             || filter->len % sizeof(uint64_t) != 0) {
3486                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3487                 return -EINVAL;
3488         }
3489         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3490                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3491                 return -EINVAL;
3492         }
3493
3494         switch (filter_op) {
3495         case RTE_ETH_FILTER_ADD:
3496                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3497                 break;
3498         case RTE_ETH_FILTER_DELETE:
3499                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3500                 break;
3501         case RTE_ETH_FILTER_GET:
3502                 ret = eth_igb_get_flex_filter(dev, filter);
3503                 break;
3504         default:
3505                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3506                 ret = -EINVAL;
3507                 break;
3508         }
3509
3510         return ret;
3511 }
3512
3513 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3514 static inline int
3515 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3516                         struct e1000_5tuple_filter_info *filter_info)
3517 {
3518         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3519                 return -EINVAL;
3520         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3521                 return -EINVAL;  /* filter index is out of range. */
3522         if (filter->tcp_flags > TCP_FLAG_ALL)
3523                 return -EINVAL;  /* flags is invalid. */
3524
3525         switch (filter->dst_ip_mask) {
3526         case UINT32_MAX:
3527                 filter_info->dst_ip_mask = 0;
3528                 filter_info->dst_ip = filter->dst_ip;
3529                 break;
3530         case 0:
3531                 filter_info->dst_ip_mask = 1;
3532                 break;
3533         default:
3534                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3535                 return -EINVAL;
3536         }
3537
3538         switch (filter->src_ip_mask) {
3539         case UINT32_MAX:
3540                 filter_info->src_ip_mask = 0;
3541                 filter_info->src_ip = filter->src_ip;
3542                 break;
3543         case 0:
3544                 filter_info->src_ip_mask = 1;
3545                 break;
3546         default:
3547                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3548                 return -EINVAL;
3549         }
3550
3551         switch (filter->dst_port_mask) {
3552         case UINT16_MAX:
3553                 filter_info->dst_port_mask = 0;
3554                 filter_info->dst_port = filter->dst_port;
3555                 break;
3556         case 0:
3557                 filter_info->dst_port_mask = 1;
3558                 break;
3559         default:
3560                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3561                 return -EINVAL;
3562         }
3563
3564         switch (filter->src_port_mask) {
3565         case UINT16_MAX:
3566                 filter_info->src_port_mask = 0;
3567                 filter_info->src_port = filter->src_port;
3568                 break;
3569         case 0:
3570                 filter_info->src_port_mask = 1;
3571                 break;
3572         default:
3573                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3574                 return -EINVAL;
3575         }
3576
3577         switch (filter->proto_mask) {
3578         case UINT8_MAX:
3579                 filter_info->proto_mask = 0;
3580                 filter_info->proto = filter->proto;
3581                 break;
3582         case 0:
3583                 filter_info->proto_mask = 1;
3584                 break;
3585         default:
3586                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3587                 return -EINVAL;
3588         }
3589
3590         filter_info->priority = (uint8_t)filter->priority;
3591         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3592                 filter_info->tcp_flags = filter->tcp_flags;
3593         else
3594                 filter_info->tcp_flags = 0;
3595
3596         return 0;
3597 }
3598
3599 static inline struct e1000_5tuple_filter *
3600 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3601                         struct e1000_5tuple_filter_info *key)
3602 {
3603         struct e1000_5tuple_filter *it;
3604
3605         TAILQ_FOREACH(it, filter_list, entries) {
3606                 if (memcmp(key, &it->filter_info,
3607                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3608                         return it;
3609                 }
3610         }
3611         return NULL;
3612 }
3613
3614 /*
3615  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3616  *
3617  * @param
3618  * dev: Pointer to struct rte_eth_dev.
3619  * ntuple_filter: ponter to the filter that will be added.
3620  *
3621  * @return
3622  *    - On success, zero.
3623  *    - On failure, a negative value.
3624  */
3625 static int
3626 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3627                         struct rte_eth_ntuple_filter *ntuple_filter)
3628 {
3629         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3630         struct e1000_filter_info *filter_info =
3631                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3632         struct e1000_5tuple_filter *filter;
3633         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3634         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3635         uint8_t i;
3636         int ret;
3637
3638         filter = rte_zmalloc("e1000_5tuple_filter",
3639                         sizeof(struct e1000_5tuple_filter), 0);
3640         if (filter == NULL)
3641                 return -ENOMEM;
3642
3643         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3644                                             &filter->filter_info);
3645         if (ret < 0) {
3646                 rte_free(filter);
3647                 return ret;
3648         }
3649
3650         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3651                                          &filter->filter_info) != NULL) {
3652                 PMD_DRV_LOG(ERR, "filter exists.");
3653                 rte_free(filter);
3654                 return -EEXIST;
3655         }
3656         filter->queue = ntuple_filter->queue;
3657
3658         /*
3659          * look for an unused 5tuple filter index,
3660          * and insert the filter to list.
3661          */
3662         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3663                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3664                         filter_info->fivetuple_mask |= 1 << i;
3665                         filter->index = i;
3666                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3667                                           filter,
3668                                           entries);
3669                         break;
3670                 }
3671         }
3672         if (i >= E1000_MAX_FTQF_FILTERS) {
3673                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3674                 rte_free(filter);
3675                 return -ENOSYS;
3676         }
3677
3678         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3679         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3680                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3681         if (filter->filter_info.dst_ip_mask == 0)
3682                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3683         if (filter->filter_info.src_port_mask == 0)
3684                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3685         if (filter->filter_info.proto_mask == 0)
3686                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3687         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3688                 E1000_FTQF_QUEUE_MASK;
3689         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3690         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3691         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3692         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3693
3694         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3695         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3696
3697         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3698         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3699                 imir |= E1000_IMIR_PORT_BP;
3700         else
3701                 imir &= ~E1000_IMIR_PORT_BP;
3702         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3703
3704         /* tcp flags bits setting. */
3705         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3706                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3707                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3708                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3709                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3710                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3711                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3712                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3713                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3714                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3715                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3716                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3717                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3718         } else
3719                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3720         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3721         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3722         return 0;
3723 }
3724
3725 /*
3726  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3727  *
3728  * @param
3729  * dev: Pointer to struct rte_eth_dev.
3730  * ntuple_filter: ponter to the filter that will be removed.
3731  *
3732  * @return
3733  *    - On success, zero.
3734  *    - On failure, a negative value.
3735  */
3736 static int
3737 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3738                                 struct rte_eth_ntuple_filter *ntuple_filter)
3739 {
3740         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741         struct e1000_filter_info *filter_info =
3742                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3743         struct e1000_5tuple_filter_info filter_5tuple;
3744         struct e1000_5tuple_filter *filter;
3745         int ret;
3746
3747         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3748         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3749                                             &filter_5tuple);
3750         if (ret < 0)
3751                 return ret;
3752
3753         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3754                                          &filter_5tuple);
3755         if (filter == NULL) {
3756                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3757                 return -ENOENT;
3758         }
3759
3760         filter_info->fivetuple_mask &= ~(1 << filter->index);
3761         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3762         rte_free(filter);
3763
3764         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3765                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3766         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3767         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3768         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3769         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3770         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3771         return 0;
3772 }
3773
3774 static int
3775 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3776 {
3777         uint32_t rctl;
3778         struct e1000_hw *hw;
3779         struct rte_eth_dev_info dev_info;
3780         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3781                                      VLAN_TAG_SIZE);
3782
3783         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784
3785 #ifdef RTE_LIBRTE_82571_SUPPORT
3786         /* XXX: not bigger than max_rx_pktlen */
3787         if (hw->mac.type == e1000_82571)
3788                 return -ENOTSUP;
3789 #endif
3790         eth_igb_infos_get(dev, &dev_info);
3791
3792         /* check that mtu is within the allowed range */
3793         if ((mtu < ETHER_MIN_MTU) ||
3794             (frame_size > dev_info.max_rx_pktlen))
3795                 return -EINVAL;
3796
3797         /* refuse mtu that requires the support of scattered packets when this
3798          * feature has not been enabled before. */
3799         if (!dev->data->scattered_rx &&
3800             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3801                 return -EINVAL;
3802
3803         rctl = E1000_READ_REG(hw, E1000_RCTL);
3804
3805         /* switch to jumbo mode if needed */
3806         if (frame_size > ETHER_MAX_LEN) {
3807                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3808                 rctl |= E1000_RCTL_LPE;
3809         } else {
3810                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3811                 rctl &= ~E1000_RCTL_LPE;
3812         }
3813         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3814
3815         /* update max frame size */
3816         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3817
3818         E1000_WRITE_REG(hw, E1000_RLPML,
3819                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3820
3821         return 0;
3822 }
3823
3824 /*
3825  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3826  *
3827  * @param
3828  * dev: Pointer to struct rte_eth_dev.
3829  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3830  * add: if true, add filter, if false, remove filter
3831  *
3832  * @return
3833  *    - On success, zero.
3834  *    - On failure, a negative value.
3835  */
3836 static int
3837 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3838                         struct rte_eth_ntuple_filter *ntuple_filter,
3839                         bool add)
3840 {
3841         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842         int ret;
3843
3844         switch (ntuple_filter->flags) {
3845         case RTE_5TUPLE_FLAGS:
3846         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3847                 if (hw->mac.type != e1000_82576)
3848                         return -ENOTSUP;
3849                 if (add)
3850                         ret = igb_add_5tuple_filter_82576(dev,
3851                                                           ntuple_filter);
3852                 else
3853                         ret = igb_remove_5tuple_filter_82576(dev,
3854                                                              ntuple_filter);
3855                 break;
3856         case RTE_2TUPLE_FLAGS:
3857         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3858                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3859                         return -ENOTSUP;
3860                 if (add)
3861                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3862                 else
3863                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3864                 break;
3865         default:
3866                 ret = -EINVAL;
3867                 break;
3868         }
3869
3870         return ret;
3871 }
3872
3873 /*
3874  * igb_get_ntuple_filter - get a ntuple filter
3875  *
3876  * @param
3877  * dev: Pointer to struct rte_eth_dev.
3878  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3879  *
3880  * @return
3881  *    - On success, zero.
3882  *    - On failure, a negative value.
3883  */
3884 static int
3885 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3886                         struct rte_eth_ntuple_filter *ntuple_filter)
3887 {
3888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889         struct e1000_filter_info *filter_info =
3890                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3891         struct e1000_5tuple_filter_info filter_5tuple;
3892         struct e1000_2tuple_filter_info filter_2tuple;
3893         struct e1000_5tuple_filter *p_5tuple_filter;
3894         struct e1000_2tuple_filter *p_2tuple_filter;
3895         int ret;
3896
3897         switch (ntuple_filter->flags) {
3898         case RTE_5TUPLE_FLAGS:
3899         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3900                 if (hw->mac.type != e1000_82576)
3901                         return -ENOTSUP;
3902                 memset(&filter_5tuple,
3903                         0,
3904                         sizeof(struct e1000_5tuple_filter_info));
3905                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3906                                                     &filter_5tuple);
3907                 if (ret < 0)
3908                         return ret;
3909                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3910                                         &filter_info->fivetuple_list,
3911                                         &filter_5tuple);
3912                 if (p_5tuple_filter == NULL) {
3913                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3914                         return -ENOENT;
3915                 }
3916                 ntuple_filter->queue = p_5tuple_filter->queue;
3917                 break;
3918         case RTE_2TUPLE_FLAGS:
3919         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3920                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3921                         return -ENOTSUP;
3922                 memset(&filter_2tuple,
3923                         0,
3924                         sizeof(struct e1000_2tuple_filter_info));
3925                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3926                 if (ret < 0)
3927                         return ret;
3928                 p_2tuple_filter = igb_2tuple_filter_lookup(
3929                                         &filter_info->twotuple_list,
3930                                         &filter_2tuple);
3931                 if (p_2tuple_filter == NULL) {
3932                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3933                         return -ENOENT;
3934                 }
3935                 ntuple_filter->queue = p_2tuple_filter->queue;
3936                 break;
3937         default:
3938                 ret = -EINVAL;
3939                 break;
3940         }
3941
3942         return 0;
3943 }
3944
3945 /*
3946  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3947  * @dev: pointer to rte_eth_dev structure
3948  * @filter_op:operation will be taken.
3949  * @arg: a pointer to specific structure corresponding to the filter_op
3950  */
3951 static int
3952 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3953                                 enum rte_filter_op filter_op,
3954                                 void *arg)
3955 {
3956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957         int ret;
3958
3959         MAC_TYPE_FILTER_SUP(hw->mac.type);
3960
3961         if (filter_op == RTE_ETH_FILTER_NOP)
3962                 return 0;
3963
3964         if (arg == NULL) {
3965                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3966                             filter_op);
3967                 return -EINVAL;
3968         }
3969
3970         switch (filter_op) {
3971         case RTE_ETH_FILTER_ADD:
3972                 ret = igb_add_del_ntuple_filter(dev,
3973                         (struct rte_eth_ntuple_filter *)arg,
3974                         TRUE);
3975                 break;
3976         case RTE_ETH_FILTER_DELETE:
3977                 ret = igb_add_del_ntuple_filter(dev,
3978                         (struct rte_eth_ntuple_filter *)arg,
3979                         FALSE);
3980                 break;
3981         case RTE_ETH_FILTER_GET:
3982                 ret = igb_get_ntuple_filter(dev,
3983                         (struct rte_eth_ntuple_filter *)arg);
3984                 break;
3985         default:
3986                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3987                 ret = -EINVAL;
3988                 break;
3989         }
3990         return ret;
3991 }
3992
3993 static inline int
3994 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3995                         uint16_t ethertype)
3996 {
3997         int i;
3998
3999         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4000                 if (filter_info->ethertype_filters[i] == ethertype &&
4001                     (filter_info->ethertype_mask & (1 << i)))
4002                         return i;
4003         }
4004         return -1;
4005 }
4006
4007 static inline int
4008 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4009                         uint16_t ethertype)
4010 {
4011         int i;
4012
4013         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4014                 if (!(filter_info->ethertype_mask & (1 << i))) {
4015                         filter_info->ethertype_mask |= 1 << i;
4016                         filter_info->ethertype_filters[i] = ethertype;
4017                         return i;
4018                 }
4019         }
4020         return -1;
4021 }
4022
4023 static inline int
4024 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4025                         uint8_t idx)
4026 {
4027         if (idx >= E1000_MAX_ETQF_FILTERS)
4028                 return -1;
4029         filter_info->ethertype_mask &= ~(1 << idx);
4030         filter_info->ethertype_filters[idx] = 0;
4031         return idx;
4032 }
4033
4034
4035 static int
4036 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4037                         struct rte_eth_ethertype_filter *filter,
4038                         bool add)
4039 {
4040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         struct e1000_filter_info *filter_info =
4042                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4043         uint32_t etqf = 0;
4044         int ret;
4045
4046         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4047                 filter->ether_type == ETHER_TYPE_IPv6) {
4048                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4049                         " ethertype filter.", filter->ether_type);
4050                 return -EINVAL;
4051         }
4052
4053         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4054                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4055                 return -EINVAL;
4056         }
4057         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4058                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4059                 return -EINVAL;
4060         }
4061
4062         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4063         if (ret >= 0 && add) {
4064                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4065                             filter->ether_type);
4066                 return -EEXIST;
4067         }
4068         if (ret < 0 && !add) {
4069                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4070                             filter->ether_type);
4071                 return -ENOENT;
4072         }
4073
4074         if (add) {
4075                 ret = igb_ethertype_filter_insert(filter_info,
4076                         filter->ether_type);
4077                 if (ret < 0) {
4078                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4079                         return -ENOSYS;
4080                 }
4081
4082                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4083                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4084                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4085         } else {
4086                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4087                 if (ret < 0)
4088                         return -ENOSYS;
4089         }
4090         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4091         E1000_WRITE_FLUSH(hw);
4092
4093         return 0;
4094 }
4095
4096 static int
4097 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4098                         struct rte_eth_ethertype_filter *filter)
4099 {
4100         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         struct e1000_filter_info *filter_info =
4102                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4103         uint32_t etqf;
4104         int ret;
4105
4106         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4107         if (ret < 0) {
4108                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4109                             filter->ether_type);
4110                 return -ENOENT;
4111         }
4112
4113         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4114         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4115                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4116                 filter->flags = 0;
4117                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4118                                 E1000_ETQF_QUEUE_SHIFT;
4119                 return 0;
4120         }
4121
4122         return -ENOENT;
4123 }
4124
4125 /*
4126  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4127  * @dev: pointer to rte_eth_dev structure
4128  * @filter_op:operation will be taken.
4129  * @arg: a pointer to specific structure corresponding to the filter_op
4130  */
4131 static int
4132 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4133                                 enum rte_filter_op filter_op,
4134                                 void *arg)
4135 {
4136         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4137         int ret;
4138
4139         MAC_TYPE_FILTER_SUP(hw->mac.type);
4140
4141         if (filter_op == RTE_ETH_FILTER_NOP)
4142                 return 0;
4143
4144         if (arg == NULL) {
4145                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4146                             filter_op);
4147                 return -EINVAL;
4148         }
4149
4150         switch (filter_op) {
4151         case RTE_ETH_FILTER_ADD:
4152                 ret = igb_add_del_ethertype_filter(dev,
4153                         (struct rte_eth_ethertype_filter *)arg,
4154                         TRUE);
4155                 break;
4156         case RTE_ETH_FILTER_DELETE:
4157                 ret = igb_add_del_ethertype_filter(dev,
4158                         (struct rte_eth_ethertype_filter *)arg,
4159                         FALSE);
4160                 break;
4161         case RTE_ETH_FILTER_GET:
4162                 ret = igb_get_ethertype_filter(dev,
4163                         (struct rte_eth_ethertype_filter *)arg);
4164                 break;
4165         default:
4166                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4167                 ret = -EINVAL;
4168                 break;
4169         }
4170         return ret;
4171 }
4172
4173 static int
4174 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4175                      enum rte_filter_type filter_type,
4176                      enum rte_filter_op filter_op,
4177                      void *arg)
4178 {
4179         int ret = -EINVAL;
4180
4181         switch (filter_type) {
4182         case RTE_ETH_FILTER_NTUPLE:
4183                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4184                 break;
4185         case RTE_ETH_FILTER_ETHERTYPE:
4186                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4187                 break;
4188         case RTE_ETH_FILTER_SYN:
4189                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4190                 break;
4191         case RTE_ETH_FILTER_FLEXIBLE:
4192                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4193                 break;
4194         default:
4195                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4196                                                         filter_type);
4197                 break;
4198         }
4199
4200         return ret;
4201 }
4202
4203 static int
4204 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4205                          struct ether_addr *mc_addr_set,
4206                          uint32_t nb_mc_addr)
4207 {
4208         struct e1000_hw *hw;
4209
4210         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4212         return 0;
4213 }
4214
4215 static uint64_t
4216 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4217 {
4218         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4219         uint64_t systime_cycles;
4220
4221         switch (hw->mac.type) {
4222         case e1000_i210:
4223         case e1000_i211:
4224                 /*
4225                  * Need to read System Time Residue Register to be able
4226                  * to read the other two registers.
4227                  */
4228                 E1000_READ_REG(hw, E1000_SYSTIMR);
4229                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4230                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4231                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4232                                 * NSEC_PER_SEC;
4233                 break;
4234         case e1000_82580:
4235         case e1000_i350:
4236         case e1000_i354:
4237                 /*
4238                  * Need to read System Time Residue Register to be able
4239                  * to read the other two registers.
4240                  */
4241                 E1000_READ_REG(hw, E1000_SYSTIMR);
4242                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4243                 /* Only the 8 LSB are valid. */
4244                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4245                                 & 0xff) << 32;
4246                 break;
4247         default:
4248                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4249                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4250                                 << 32;
4251                 break;
4252         }
4253
4254         return systime_cycles;
4255 }
4256
4257 static uint64_t
4258 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4259 {
4260         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4261         uint64_t rx_tstamp_cycles;
4262
4263         switch (hw->mac.type) {
4264         case e1000_i210:
4265         case e1000_i211:
4266                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4267                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4268                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4269                                 * NSEC_PER_SEC;
4270                 break;
4271         case e1000_82580:
4272         case e1000_i350:
4273         case e1000_i354:
4274                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4275                 /* Only the 8 LSB are valid. */
4276                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4277                                 & 0xff) << 32;
4278                 break;
4279         default:
4280                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4281                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4282                                 << 32;
4283                 break;
4284         }
4285
4286         return rx_tstamp_cycles;
4287 }
4288
4289 static uint64_t
4290 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4291 {
4292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         uint64_t tx_tstamp_cycles;
4294
4295         switch (hw->mac.type) {
4296         case e1000_i210:
4297         case e1000_i211:
4298                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4299                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4300                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4301                                 * NSEC_PER_SEC;
4302                 break;
4303         case e1000_82580:
4304         case e1000_i350:
4305         case e1000_i354:
4306                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4307                 /* Only the 8 LSB are valid. */
4308                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4309                                 & 0xff) << 32;
4310                 break;
4311         default:
4312                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4313                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4314                                 << 32;
4315                 break;
4316         }
4317
4318         return tx_tstamp_cycles;
4319 }
4320
4321 static void
4322 igb_start_timecounters(struct rte_eth_dev *dev)
4323 {
4324         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325         struct e1000_adapter *adapter =
4326                 (struct e1000_adapter *)dev->data->dev_private;
4327         uint32_t incval = 1;
4328         uint32_t shift = 0;
4329         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4330
4331         switch (hw->mac.type) {
4332         case e1000_82580:
4333         case e1000_i350:
4334         case e1000_i354:
4335                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4336                 mask = (1ULL << 40) - 1;
4337                 /* fall-through */
4338         case e1000_i210:
4339         case e1000_i211:
4340                 /*
4341                  * Start incrementing the register
4342                  * used to timestamp PTP packets.
4343                  */
4344                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4345                 break;
4346         case e1000_82576:
4347                 incval = E1000_INCVALUE_82576;
4348                 shift = IGB_82576_TSYNC_SHIFT;
4349                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4350                                 E1000_INCPERIOD_82576 | incval);
4351                 break;
4352         default:
4353                 /* Not supported */
4354                 return;
4355         }
4356
4357         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4358         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4359         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4360
4361         adapter->systime_tc.cc_mask = mask;
4362         adapter->systime_tc.cc_shift = shift;
4363         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4364
4365         adapter->rx_tstamp_tc.cc_mask = mask;
4366         adapter->rx_tstamp_tc.cc_shift = shift;
4367         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4368
4369         adapter->tx_tstamp_tc.cc_mask = mask;
4370         adapter->tx_tstamp_tc.cc_shift = shift;
4371         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4372 }
4373
4374 static int
4375 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4376 {
4377         struct e1000_adapter *adapter =
4378                         (struct e1000_adapter *)dev->data->dev_private;
4379
4380         adapter->systime_tc.nsec += delta;
4381         adapter->rx_tstamp_tc.nsec += delta;
4382         adapter->tx_tstamp_tc.nsec += delta;
4383
4384         return 0;
4385 }
4386
4387 static int
4388 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4389 {
4390         uint64_t ns;
4391         struct e1000_adapter *adapter =
4392                         (struct e1000_adapter *)dev->data->dev_private;
4393
4394         ns = rte_timespec_to_ns(ts);
4395
4396         /* Set the timecounters to a new value. */
4397         adapter->systime_tc.nsec = ns;
4398         adapter->rx_tstamp_tc.nsec = ns;
4399         adapter->tx_tstamp_tc.nsec = ns;
4400
4401         return 0;
4402 }
4403
4404 static int
4405 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4406 {
4407         uint64_t ns, systime_cycles;
4408         struct e1000_adapter *adapter =
4409                         (struct e1000_adapter *)dev->data->dev_private;
4410
4411         systime_cycles = igb_read_systime_cyclecounter(dev);
4412         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4413         *ts = rte_ns_to_timespec(ns);
4414
4415         return 0;
4416 }
4417
4418 static int
4419 igb_timesync_enable(struct rte_eth_dev *dev)
4420 {
4421         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4422         uint32_t tsync_ctl;
4423         uint32_t tsauxc;
4424
4425         /* Stop the timesync system time. */
4426         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4427         /* Reset the timesync system time value. */
4428         switch (hw->mac.type) {
4429         case e1000_82580:
4430         case e1000_i350:
4431         case e1000_i354:
4432         case e1000_i210:
4433         case e1000_i211:
4434                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4435                 /* fall-through */
4436         case e1000_82576:
4437                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4438                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4439                 break;
4440         default:
4441                 /* Not supported. */
4442                 return -ENOTSUP;
4443         }
4444
4445         /* Enable system time for it isn't on by default. */
4446         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4447         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4448         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4449
4450         igb_start_timecounters(dev);
4451
4452         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4453         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4454                         (ETHER_TYPE_1588 |
4455                          E1000_ETQF_FILTER_ENABLE |
4456                          E1000_ETQF_1588));
4457
4458         /* Enable timestamping of received PTP packets. */
4459         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4460         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4461         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4462
4463         /* Enable Timestamping of transmitted PTP packets. */
4464         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4465         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4466         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4467
4468         return 0;
4469 }
4470
4471 static int
4472 igb_timesync_disable(struct rte_eth_dev *dev)
4473 {
4474         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         uint32_t tsync_ctl;
4476
4477         /* Disable timestamping of transmitted PTP packets. */
4478         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4479         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4480         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4481
4482         /* Disable timestamping of received PTP packets. */
4483         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4484         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4485         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4486
4487         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4488         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4489
4490         /* Stop incrementating the System Time registers. */
4491         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4492
4493         return 0;
4494 }
4495
4496 static int
4497 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4498                                struct timespec *timestamp,
4499                                uint32_t flags __rte_unused)
4500 {
4501         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4502         struct e1000_adapter *adapter =
4503                         (struct e1000_adapter *)dev->data->dev_private;
4504         uint32_t tsync_rxctl;
4505         uint64_t rx_tstamp_cycles;
4506         uint64_t ns;
4507
4508         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4509         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4510                 return -EINVAL;
4511
4512         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4513         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4514         *timestamp = rte_ns_to_timespec(ns);
4515
4516         return  0;
4517 }
4518
4519 static int
4520 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4521                                struct timespec *timestamp)
4522 {
4523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         struct e1000_adapter *adapter =
4525                         (struct e1000_adapter *)dev->data->dev_private;
4526         uint32_t tsync_txctl;
4527         uint64_t tx_tstamp_cycles;
4528         uint64_t ns;
4529
4530         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4531         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4532                 return -EINVAL;
4533
4534         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4535         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4536         *timestamp = rte_ns_to_timespec(ns);
4537
4538         return  0;
4539 }
4540
4541 static int
4542 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4543 {
4544         int count = 0;
4545         int g_ind = 0;
4546         const struct reg_info *reg_group;
4547
4548         while ((reg_group = igb_regs[g_ind++]))
4549                 count += igb_reg_group_count(reg_group);
4550
4551         return count;
4552 }
4553
4554 static int
4555 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4556 {
4557         int count = 0;
4558         int g_ind = 0;
4559         const struct reg_info *reg_group;
4560
4561         while ((reg_group = igbvf_regs[g_ind++]))
4562                 count += igb_reg_group_count(reg_group);
4563
4564         return count;
4565 }
4566
4567 static int
4568 eth_igb_get_regs(struct rte_eth_dev *dev,
4569         struct rte_dev_reg_info *regs)
4570 {
4571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4572         uint32_t *data = regs->data;
4573         int g_ind = 0;
4574         int count = 0;
4575         const struct reg_info *reg_group;
4576
4577         /* Support only full register dump */
4578         if ((regs->length == 0) ||
4579             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4580                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4581                         hw->device_id;
4582                 while ((reg_group = igb_regs[g_ind++]))
4583                         count += igb_read_regs_group(dev, &data[count],
4584                                                         reg_group);
4585                 return 0;
4586         }
4587
4588         return -ENOTSUP;
4589 }
4590
4591 static int
4592 igbvf_get_regs(struct rte_eth_dev *dev,
4593         struct rte_dev_reg_info *regs)
4594 {
4595         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596         uint32_t *data = regs->data;
4597         int g_ind = 0;
4598         int count = 0;
4599         const struct reg_info *reg_group;
4600
4601         /* Support only full register dump */
4602         if ((regs->length == 0) ||
4603             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4604                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4605                         hw->device_id;
4606                 while ((reg_group = igbvf_regs[g_ind++]))
4607                         count += igb_read_regs_group(dev, &data[count],
4608                                                         reg_group);
4609                 return 0;
4610         }
4611
4612         return -ENOTSUP;
4613 }
4614
4615 static int
4616 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4617 {
4618         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4619
4620         /* Return unit is byte count */
4621         return hw->nvm.word_size * 2;
4622 }
4623
4624 static int
4625 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4626         struct rte_dev_eeprom_info *in_eeprom)
4627 {
4628         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         struct e1000_nvm_info *nvm = &hw->nvm;
4630         uint16_t *data = in_eeprom->data;
4631         int first, length;
4632
4633         first = in_eeprom->offset >> 1;
4634         length = in_eeprom->length >> 1;
4635         if ((first >= hw->nvm.word_size) ||
4636             ((first + length) >= hw->nvm.word_size))
4637                 return -EINVAL;
4638
4639         in_eeprom->magic = hw->vendor_id |
4640                 ((uint32_t)hw->device_id << 16);
4641
4642         if ((nvm->ops.read) == NULL)
4643                 return -ENOTSUP;
4644
4645         return nvm->ops.read(hw, first, length, data);
4646 }
4647
4648 static int
4649 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4650         struct rte_dev_eeprom_info *in_eeprom)
4651 {
4652         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653         struct e1000_nvm_info *nvm = &hw->nvm;
4654         uint16_t *data = in_eeprom->data;
4655         int first, length;
4656
4657         first = in_eeprom->offset >> 1;
4658         length = in_eeprom->length >> 1;
4659         if ((first >= hw->nvm.word_size) ||
4660             ((first + length) >= hw->nvm.word_size))
4661                 return -EINVAL;
4662
4663         in_eeprom->magic = (uint32_t)hw->vendor_id |
4664                 ((uint32_t)hw->device_id << 16);
4665
4666         if ((nvm->ops.write) == NULL)
4667                 return -ENOTSUP;
4668         return nvm->ops.write(hw,  first, length, data);
4669 }
4670
4671 static struct rte_driver pmd_igb_drv = {
4672         .type = PMD_PDEV,
4673         .init = rte_igb_pmd_init,
4674 };
4675
4676 static struct rte_driver pmd_igbvf_drv = {
4677         .type = PMD_PDEV,
4678         .init = rte_igbvf_pmd_init,
4679 };
4680
4681 static int
4682 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4683 {
4684         struct e1000_hw *hw =
4685                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686         uint32_t mask = 1 << queue_id;
4687
4688         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4689         E1000_WRITE_FLUSH(hw);
4690
4691         return 0;
4692 }
4693
4694 static int
4695 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4696 {
4697         struct e1000_hw *hw =
4698                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699         uint32_t mask = 1 << queue_id;
4700         uint32_t regval;
4701
4702         regval = E1000_READ_REG(hw, E1000_EIMS);
4703         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4704         E1000_WRITE_FLUSH(hw);
4705
4706         rte_intr_enable(&dev->pci_dev->intr_handle);
4707
4708         return 0;
4709 }
4710
4711 static void
4712 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4713                    uint8_t index, uint8_t offset)
4714 {
4715         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4716
4717         /* clear bits */
4718         val &= ~((uint32_t)0xFF << offset);
4719
4720         /* write vector and valid bit */
4721         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4722
4723         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4724 }
4725
4726 static void
4727 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4728                            uint8_t queue, uint8_t msix_vector)
4729 {
4730         uint32_t tmp = 0;
4731
4732         if (hw->mac.type == e1000_82575) {
4733                 if (direction == 0)
4734                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4735                 else if (direction == 1)
4736                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4737                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4738         } else if (hw->mac.type == e1000_82576) {
4739                 if ((direction == 0) || (direction == 1))
4740                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4741                                            ((queue & 0x8) << 1) +
4742                                            8 * direction);
4743         } else if ((hw->mac.type == e1000_82580) ||
4744                         (hw->mac.type == e1000_i350) ||
4745                         (hw->mac.type == e1000_i354) ||
4746                         (hw->mac.type == e1000_i210) ||
4747                         (hw->mac.type == e1000_i211)) {
4748                 if ((direction == 0) || (direction == 1))
4749                         eth_igb_write_ivar(hw, msix_vector,
4750                                            queue >> 1,
4751                                            ((queue & 0x1) << 4) +
4752                                            8 * direction);
4753         }
4754 }
4755
4756 /* Sets up the hardware to generate MSI-X interrupts properly
4757  * @hw
4758  *  board private structure
4759  */
4760 static void
4761 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4762 {
4763         int queue_id;
4764         uint32_t tmpval, regval, intr_mask;
4765         struct e1000_hw *hw =
4766                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767         uint32_t vec = E1000_MISC_VEC_ID;
4768         uint32_t base = E1000_MISC_VEC_ID;
4769         uint32_t misc_shift = 0;
4770
4771         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4772
4773         /* won't configure msix register if no mapping is done
4774          * between intr vector and event fd
4775          */
4776         if (!rte_intr_dp_is_en(intr_handle))
4777                 return;
4778
4779         if (rte_intr_allow_others(intr_handle)) {
4780                 vec = base = E1000_RX_VEC_START;
4781                 misc_shift = 1;
4782         }
4783
4784         /* set interrupt vector for other causes */
4785         if (hw->mac.type == e1000_82575) {
4786                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4787                 /* enable MSI-X PBA support */
4788                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4789
4790                 /* Auto-Mask interrupts upon ICR read */
4791                 tmpval |= E1000_CTRL_EXT_EIAME;
4792                 tmpval |= E1000_CTRL_EXT_IRCA;
4793
4794                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4795
4796                 /* enable msix_other interrupt */
4797                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4798                 regval = E1000_READ_REG(hw, E1000_EIAC);
4799                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4800                 regval = E1000_READ_REG(hw, E1000_EIAM);
4801                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4802         } else if ((hw->mac.type == e1000_82576) ||
4803                         (hw->mac.type == e1000_82580) ||
4804                         (hw->mac.type == e1000_i350) ||
4805                         (hw->mac.type == e1000_i354) ||
4806                         (hw->mac.type == e1000_i210) ||
4807                         (hw->mac.type == e1000_i211)) {
4808                 /* turn on MSI-X capability first */
4809                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4810                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4811                                         E1000_GPIE_NSICR);
4812                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4813                         misc_shift;
4814                 regval = E1000_READ_REG(hw, E1000_EIAC);
4815                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4816
4817                 /* enable msix_other interrupt */
4818                 regval = E1000_READ_REG(hw, E1000_EIMS);
4819                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4820                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4821                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4822         }
4823
4824         /* use EIAM to auto-mask when MSI-X interrupt
4825          * is asserted, this saves a register write for every interrupt
4826          */
4827         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4828                 misc_shift;
4829         regval = E1000_READ_REG(hw, E1000_EIAM);
4830         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4831
4832         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4833                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4834                 intr_handle->intr_vec[queue_id] = vec;
4835                 if (vec < base + intr_handle->nb_efd - 1)
4836                         vec++;
4837         }
4838
4839         E1000_WRITE_FLUSH(hw);
4840 }
4841
4842 PMD_REGISTER_DRIVER(pmd_igb_drv);
4843 PMD_REGISTER_DRIVER(pmd_igbvf_drv);