1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_atomic.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 #define IGB_HKEY_MAX_INDEX 10
47 /* Bit shift and mask */
48 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
49 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
50 #define IGB_8_BIT_WIDTH CHAR_BIT
51 #define IGB_8_BIT_MASK UINT8_MAX
53 /* Additional timesync values. */
54 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
55 #define E1000_ETQF_FILTER_1588 3
56 #define IGB_82576_TSYNC_SHIFT 16
57 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
58 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
59 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
61 #define E1000_VTIVAR_MISC 0x01740
62 #define E1000_VTIVAR_MISC_MASK 0xFF
63 #define E1000_VTIVAR_VALID 0x80
64 #define E1000_VTIVAR_MISC_MAILBOX 0
65 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
67 /* External VLAN Enable bit mask */
68 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
70 /* External VLAN Ether Type bit mask and shift */
71 #define E1000_VET_VET_EXT 0xFFFF0000
72 #define E1000_VET_VET_EXT_SHIFT 16
74 static int eth_igb_configure(struct rte_eth_dev *dev);
75 static int eth_igb_start(struct rte_eth_dev *dev);
76 static void eth_igb_stop(struct rte_eth_dev *dev);
77 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
79 static void eth_igb_close(struct rte_eth_dev *dev);
80 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
81 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
82 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
83 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
84 static int eth_igb_link_update(struct rte_eth_dev *dev,
85 int wait_to_complete);
86 static int eth_igb_stats_get(struct rte_eth_dev *dev,
87 struct rte_eth_stats *rte_stats);
88 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
89 struct rte_eth_xstat *xstats, unsigned n);
90 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
92 uint64_t *values, unsigned int n);
93 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
94 struct rte_eth_xstat_name *xstats_names,
96 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
97 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
99 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
100 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
101 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
102 char *fw_version, size_t fw_size);
103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
104 struct rte_eth_dev_info *dev_info);
105 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
107 struct rte_eth_dev_info *dev_info);
108 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
109 struct rte_eth_fc_conf *fc_conf);
110 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
116 struct rte_intr_handle *handle);
117 static void eth_igb_interrupt_handler(void *param);
118 static int igb_hardware_init(struct e1000_hw *hw);
119 static void igb_hw_control_acquire(struct e1000_hw *hw);
120 static void igb_hw_control_release(struct e1000_hw *hw);
121 static void igb_init_manageability(struct e1000_hw *hw);
122 static void igb_release_manageability(struct e1000_hw *hw);
124 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
127 uint16_t vlan_id, int on);
128 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
129 enum rte_vlan_type vlan_type,
131 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
133 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
140 static int eth_igb_led_on(struct rte_eth_dev *dev);
141 static int eth_igb_led_off(struct rte_eth_dev *dev);
143 static void igb_intr_disable(struct e1000_hw *hw);
144 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
145 static int eth_igb_rar_set(struct rte_eth_dev *dev,
146 struct ether_addr *mac_addr,
147 uint32_t index, uint32_t pool);
148 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
149 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
150 struct ether_addr *addr);
152 static void igbvf_intr_disable(struct e1000_hw *hw);
153 static int igbvf_dev_configure(struct rte_eth_dev *dev);
154 static int igbvf_dev_start(struct rte_eth_dev *dev);
155 static void igbvf_dev_stop(struct rte_eth_dev *dev);
156 static void igbvf_dev_close(struct rte_eth_dev *dev);
157 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
158 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
159 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
160 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
161 static int eth_igbvf_link_update(struct e1000_hw *hw);
162 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
163 struct rte_eth_stats *rte_stats);
164 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
165 struct rte_eth_xstat *xstats, unsigned n);
166 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
169 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
170 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
171 uint16_t vlan_id, int on);
172 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
173 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
174 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
175 struct ether_addr *addr);
176 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
177 static int igbvf_get_regs(struct rte_eth_dev *dev,
178 struct rte_dev_reg_info *regs);
180 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
181 struct rte_eth_rss_reta_entry64 *reta_conf,
183 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
184 struct rte_eth_rss_reta_entry64 *reta_conf,
187 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
188 struct rte_eth_syn_filter *filter);
189 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
190 enum rte_filter_op filter_op,
192 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
193 struct rte_eth_ntuple_filter *ntuple_filter);
194 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
197 struct rte_eth_flex_filter *filter);
198 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
199 enum rte_filter_op filter_op,
201 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
202 struct rte_eth_ntuple_filter *ntuple_filter);
203 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *filter);
207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
208 enum rte_filter_op filter_op,
210 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
211 enum rte_filter_op filter_op,
213 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
214 struct rte_eth_ethertype_filter *filter);
215 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
216 enum rte_filter_type filter_type,
217 enum rte_filter_op filter_op,
219 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
220 static int eth_igb_get_regs(struct rte_eth_dev *dev,
221 struct rte_dev_reg_info *regs);
222 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
223 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
224 struct rte_dev_eeprom_info *eeprom);
225 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
228 struct ether_addr *mc_addr_set,
229 uint32_t nb_mc_addr);
230 static int igb_timesync_enable(struct rte_eth_dev *dev);
231 static int igb_timesync_disable(struct rte_eth_dev *dev);
232 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
233 struct timespec *timestamp,
235 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
236 struct timespec *timestamp);
237 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
238 static int igb_timesync_read_time(struct rte_eth_dev *dev,
239 struct timespec *timestamp);
240 static int igb_timesync_write_time(struct rte_eth_dev *dev,
241 const struct timespec *timestamp);
242 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
244 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
246 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
247 uint8_t queue, uint8_t msix_vector);
248 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
249 uint8_t index, uint8_t offset);
250 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
251 static void eth_igbvf_interrupt_handler(void *param);
252 static void igbvf_mbx_process(struct rte_eth_dev *dev);
253 static int igb_filter_restore(struct rte_eth_dev *dev);
256 * Define VF Stats MACRO for Non "cleared on read" register
258 #define UPDATE_VF_STAT(reg, last, cur) \
260 u32 latest = E1000_READ_REG(hw, reg); \
261 cur += (latest - last) & UINT_MAX; \
265 #define IGB_FC_PAUSE_TIME 0x0680
266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
269 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
274 * The set of PCI devices this driver supports
276 static const struct rte_pci_id pci_id_igb_map[] = {
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
318 { .vendor_id = 0, /* sentinel */ },
322 * The set of PCI devices this driver supports (for 82576&I350 VF)
324 static const struct rte_pci_id pci_id_igbvf_map[] = {
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
329 { .vendor_id = 0, /* sentinel */ },
332 static const struct rte_eth_desc_lim rx_desc_lim = {
333 .nb_max = E1000_MAX_RING_DESC,
334 .nb_min = E1000_MIN_RING_DESC,
335 .nb_align = IGB_RXD_ALIGN,
338 static const struct rte_eth_desc_lim tx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
342 .nb_seg_max = IGB_TX_MAX_SEG,
343 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
346 static const struct eth_dev_ops eth_igb_ops = {
347 .dev_configure = eth_igb_configure,
348 .dev_start = eth_igb_start,
349 .dev_stop = eth_igb_stop,
350 .dev_set_link_up = eth_igb_dev_set_link_up,
351 .dev_set_link_down = eth_igb_dev_set_link_down,
352 .dev_close = eth_igb_close,
353 .promiscuous_enable = eth_igb_promiscuous_enable,
354 .promiscuous_disable = eth_igb_promiscuous_disable,
355 .allmulticast_enable = eth_igb_allmulticast_enable,
356 .allmulticast_disable = eth_igb_allmulticast_disable,
357 .link_update = eth_igb_link_update,
358 .stats_get = eth_igb_stats_get,
359 .xstats_get = eth_igb_xstats_get,
360 .xstats_get_by_id = eth_igb_xstats_get_by_id,
361 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
362 .xstats_get_names = eth_igb_xstats_get_names,
363 .stats_reset = eth_igb_stats_reset,
364 .xstats_reset = eth_igb_xstats_reset,
365 .fw_version_get = eth_igb_fw_version_get,
366 .dev_infos_get = eth_igb_infos_get,
367 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
368 .mtu_set = eth_igb_mtu_set,
369 .vlan_filter_set = eth_igb_vlan_filter_set,
370 .vlan_tpid_set = eth_igb_vlan_tpid_set,
371 .vlan_offload_set = eth_igb_vlan_offload_set,
372 .rx_queue_setup = eth_igb_rx_queue_setup,
373 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
374 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
375 .rx_queue_release = eth_igb_rx_queue_release,
376 .rx_queue_count = eth_igb_rx_queue_count,
377 .rx_descriptor_done = eth_igb_rx_descriptor_done,
378 .rx_descriptor_status = eth_igb_rx_descriptor_status,
379 .tx_descriptor_status = eth_igb_tx_descriptor_status,
380 .tx_queue_setup = eth_igb_tx_queue_setup,
381 .tx_queue_release = eth_igb_tx_queue_release,
382 .tx_done_cleanup = eth_igb_tx_done_cleanup,
383 .dev_led_on = eth_igb_led_on,
384 .dev_led_off = eth_igb_led_off,
385 .flow_ctrl_get = eth_igb_flow_ctrl_get,
386 .flow_ctrl_set = eth_igb_flow_ctrl_set,
387 .mac_addr_add = eth_igb_rar_set,
388 .mac_addr_remove = eth_igb_rar_clear,
389 .mac_addr_set = eth_igb_default_mac_addr_set,
390 .reta_update = eth_igb_rss_reta_update,
391 .reta_query = eth_igb_rss_reta_query,
392 .rss_hash_update = eth_igb_rss_hash_update,
393 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
394 .filter_ctrl = eth_igb_filter_ctrl,
395 .set_mc_addr_list = eth_igb_set_mc_addr_list,
396 .rxq_info_get = igb_rxq_info_get,
397 .txq_info_get = igb_txq_info_get,
398 .timesync_enable = igb_timesync_enable,
399 .timesync_disable = igb_timesync_disable,
400 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
401 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
402 .get_reg = eth_igb_get_regs,
403 .get_eeprom_length = eth_igb_get_eeprom_length,
404 .get_eeprom = eth_igb_get_eeprom,
405 .set_eeprom = eth_igb_set_eeprom,
406 .timesync_adjust_time = igb_timesync_adjust_time,
407 .timesync_read_time = igb_timesync_read_time,
408 .timesync_write_time = igb_timesync_write_time,
412 * dev_ops for virtual function, bare necessities for basic vf
413 * operation have been implemented
415 static const struct eth_dev_ops igbvf_eth_dev_ops = {
416 .dev_configure = igbvf_dev_configure,
417 .dev_start = igbvf_dev_start,
418 .dev_stop = igbvf_dev_stop,
419 .dev_close = igbvf_dev_close,
420 .promiscuous_enable = igbvf_promiscuous_enable,
421 .promiscuous_disable = igbvf_promiscuous_disable,
422 .allmulticast_enable = igbvf_allmulticast_enable,
423 .allmulticast_disable = igbvf_allmulticast_disable,
424 .link_update = eth_igb_link_update,
425 .stats_get = eth_igbvf_stats_get,
426 .xstats_get = eth_igbvf_xstats_get,
427 .xstats_get_names = eth_igbvf_xstats_get_names,
428 .stats_reset = eth_igbvf_stats_reset,
429 .xstats_reset = eth_igbvf_stats_reset,
430 .vlan_filter_set = igbvf_vlan_filter_set,
431 .dev_infos_get = eth_igbvf_infos_get,
432 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
433 .rx_queue_setup = eth_igb_rx_queue_setup,
434 .rx_queue_release = eth_igb_rx_queue_release,
435 .tx_queue_setup = eth_igb_tx_queue_setup,
436 .tx_queue_release = eth_igb_tx_queue_release,
437 .set_mc_addr_list = eth_igb_set_mc_addr_list,
438 .rxq_info_get = igb_rxq_info_get,
439 .txq_info_get = igb_txq_info_get,
440 .mac_addr_set = igbvf_default_mac_addr_set,
441 .get_reg = igbvf_get_regs,
444 /* store statistics names and its offset in stats structure */
445 struct rte_igb_xstats_name_off {
446 char name[RTE_ETH_XSTATS_NAME_SIZE];
450 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
451 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
452 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
453 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
454 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
455 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
456 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
457 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
459 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
460 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
461 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
462 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
463 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
464 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
465 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
466 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
467 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
468 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
469 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
471 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
472 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
473 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
474 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
475 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
477 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
479 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
480 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
481 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
482 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
483 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
484 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
485 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
486 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
487 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
488 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
489 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
490 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
491 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
492 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
493 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
494 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
495 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
496 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
498 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
500 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
501 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
502 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
503 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
504 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
505 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
506 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
508 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
511 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
512 sizeof(rte_igb_stats_strings[0]))
514 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
515 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
516 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
517 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
518 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
519 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
522 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
523 sizeof(rte_igbvf_stats_strings[0]))
526 * Atomically reads the link status information from global
527 * structure rte_eth_dev.
530 * - Pointer to the structure rte_eth_dev to read from.
531 * - Pointer to the buffer to be saved with the link status.
534 * - On success, zero.
535 * - On failure, negative value.
538 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
539 struct rte_eth_link *link)
541 struct rte_eth_link *dst = link;
542 struct rte_eth_link *src = &(dev->data->dev_link);
544 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
545 *(uint64_t *)src) == 0)
552 * Atomically writes the link status information into global
553 * structure rte_eth_dev.
556 * - Pointer to the structure rte_eth_dev to read from.
557 * - Pointer to the buffer to be saved with the link status.
560 * - On success, zero.
561 * - On failure, negative value.
564 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
565 struct rte_eth_link *link)
567 struct rte_eth_link *dst = &(dev->data->dev_link);
568 struct rte_eth_link *src = link;
570 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
571 *(uint64_t *)src) == 0)
578 igb_intr_enable(struct rte_eth_dev *dev)
580 struct e1000_interrupt *intr =
581 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
582 struct e1000_hw *hw =
583 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
585 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
586 E1000_WRITE_FLUSH(hw);
590 igb_intr_disable(struct e1000_hw *hw)
592 E1000_WRITE_REG(hw, E1000_IMC, ~0);
593 E1000_WRITE_FLUSH(hw);
597 igbvf_intr_enable(struct rte_eth_dev *dev)
599 struct e1000_hw *hw =
600 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
602 /* only for mailbox */
603 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
604 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
605 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
606 E1000_WRITE_FLUSH(hw);
609 /* only for mailbox now. If RX/TX needed, should extend this function. */
611 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
616 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
617 tmp |= E1000_VTIVAR_VALID;
618 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
622 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
624 struct e1000_hw *hw =
625 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 /* Configure VF other cause ivar */
628 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
631 static inline int32_t
632 igb_pf_reset_hw(struct e1000_hw *hw)
637 status = e1000_reset_hw(hw);
639 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
640 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
641 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
642 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
643 E1000_WRITE_FLUSH(hw);
649 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
651 struct e1000_hw *hw =
652 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
655 hw->vendor_id = pci_dev->id.vendor_id;
656 hw->device_id = pci_dev->id.device_id;
657 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
658 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
660 e1000_set_mac_type(hw);
662 /* need to check if it is a vf device below */
666 igb_reset_swfw_lock(struct e1000_hw *hw)
671 * Do mac ops initialization manually here, since we will need
672 * some function pointers set by this call.
674 ret_val = e1000_init_mac_params(hw);
679 * SMBI lock should not fail in this early stage. If this is the case,
680 * it is due to an improper exit of the application.
681 * So force the release of the faulty lock.
683 if (e1000_get_hw_semaphore_generic(hw) < 0) {
684 PMD_DRV_LOG(DEBUG, "SMBI lock released");
686 e1000_put_hw_semaphore_generic(hw);
688 if (hw->mac.ops.acquire_swfw_sync != NULL) {
692 * Phy lock should not fail in this early stage. If this is the case,
693 * it is due to an improper exit of the application.
694 * So force the release of the faulty lock.
696 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
697 if (hw->bus.func > E1000_FUNC_1)
699 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
700 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
703 hw->mac.ops.release_swfw_sync(hw, mask);
706 * This one is more tricky since it is common to all ports; but
707 * swfw_sync retries last long enough (1s) to be almost sure that if
708 * lock can not be taken it is due to an improper lock of the
711 mask = E1000_SWFW_EEP_SM;
712 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
713 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
715 hw->mac.ops.release_swfw_sync(hw, mask);
718 return E1000_SUCCESS;
721 /* Remove all ntuple filters of the device */
722 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
724 struct e1000_filter_info *filter_info =
725 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
726 struct e1000_5tuple_filter *p_5tuple;
727 struct e1000_2tuple_filter *p_2tuple;
729 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
730 TAILQ_REMOVE(&filter_info->fivetuple_list,
734 filter_info->fivetuple_mask = 0;
735 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
736 TAILQ_REMOVE(&filter_info->twotuple_list,
740 filter_info->twotuple_mask = 0;
745 /* Remove all flex filters of the device */
746 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_flex_filter *p_flex;
752 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
753 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
756 filter_info->flex_mask = 0;
762 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
766 struct e1000_hw *hw =
767 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
768 struct e1000_vfta * shadow_vfta =
769 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
770 struct e1000_filter_info *filter_info =
771 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
772 struct e1000_adapter *adapter =
773 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
777 eth_dev->dev_ops = ð_igb_ops;
778 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
779 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
780 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
782 /* for secondary processes, we don't initialise any further as primary
783 * has already done this work. Only check we don't need a different
785 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
786 if (eth_dev->data->scattered_rx)
787 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
791 rte_eth_copy_pci_info(eth_dev, pci_dev);
793 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
795 igb_identify_hardware(eth_dev, pci_dev);
796 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
801 e1000_get_bus_info(hw);
803 /* Reset any pending lock */
804 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
809 /* Finish initialization */
810 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
816 hw->phy.autoneg_wait_to_complete = 0;
817 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
820 if (hw->phy.media_type == e1000_media_type_copper) {
821 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
822 hw->phy.disable_polarity_correction = 0;
823 hw->phy.ms_type = e1000_ms_hw_default;
827 * Start from a known state, this is important in reading the nvm
832 /* Make sure we have a good EEPROM before we read from it */
833 if (e1000_validate_nvm_checksum(hw) < 0) {
835 * Some PCI-E parts fail the first check due to
836 * the link being in sleep state, call it again,
837 * if it fails a second time its a real issue.
839 if (e1000_validate_nvm_checksum(hw) < 0) {
840 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
846 /* Read the permanent MAC address out of the EEPROM */
847 if (e1000_read_mac_addr(hw) != 0) {
848 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
853 /* Allocate memory for storing MAC addresses */
854 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
855 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
856 if (eth_dev->data->mac_addrs == NULL) {
857 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
858 "store MAC addresses",
859 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
864 /* Copy the permanent MAC address */
865 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
867 /* initialize the vfta */
868 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
870 /* Now initialize the hardware */
871 if (igb_hardware_init(hw) != 0) {
872 PMD_INIT_LOG(ERR, "Hardware initialization failed");
873 rte_free(eth_dev->data->mac_addrs);
874 eth_dev->data->mac_addrs = NULL;
878 hw->mac.get_link_status = 1;
879 adapter->stopped = 0;
881 /* Indicate SOL/IDER usage */
882 if (e1000_check_reset_block(hw) < 0) {
883 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
887 /* initialize PF if max_vfs not zero */
888 igb_pf_host_init(eth_dev);
890 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
893 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
894 E1000_WRITE_FLUSH(hw);
896 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
897 eth_dev->data->port_id, pci_dev->id.vendor_id,
898 pci_dev->id.device_id);
900 rte_intr_callback_register(&pci_dev->intr_handle,
901 eth_igb_interrupt_handler,
904 /* enable uio/vfio intr/eventfd mapping */
905 rte_intr_enable(&pci_dev->intr_handle);
907 /* enable support intr */
908 igb_intr_enable(eth_dev);
910 /* initialize filter info */
911 memset(filter_info, 0,
912 sizeof(struct e1000_filter_info));
914 TAILQ_INIT(&filter_info->flex_list);
915 TAILQ_INIT(&filter_info->twotuple_list);
916 TAILQ_INIT(&filter_info->fivetuple_list);
918 TAILQ_INIT(&igb_filter_ntuple_list);
919 TAILQ_INIT(&igb_filter_ethertype_list);
920 TAILQ_INIT(&igb_filter_syn_list);
921 TAILQ_INIT(&igb_filter_flex_list);
922 TAILQ_INIT(&igb_flow_list);
927 igb_hw_control_release(hw);
933 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
935 struct rte_pci_device *pci_dev;
936 struct rte_intr_handle *intr_handle;
938 struct e1000_adapter *adapter =
939 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
940 struct e1000_filter_info *filter_info =
941 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
943 PMD_INIT_FUNC_TRACE();
945 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
948 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
949 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
950 intr_handle = &pci_dev->intr_handle;
952 if (adapter->stopped == 0)
953 eth_igb_close(eth_dev);
955 eth_dev->dev_ops = NULL;
956 eth_dev->rx_pkt_burst = NULL;
957 eth_dev->tx_pkt_burst = NULL;
959 /* Reset any pending lock */
960 igb_reset_swfw_lock(hw);
962 rte_free(eth_dev->data->mac_addrs);
963 eth_dev->data->mac_addrs = NULL;
965 /* uninitialize PF if max_vfs not zero */
966 igb_pf_host_uninit(eth_dev);
968 /* disable uio intr before callback unregister */
969 rte_intr_disable(intr_handle);
970 rte_intr_callback_unregister(intr_handle,
971 eth_igb_interrupt_handler, eth_dev);
973 /* clear the SYN filter info */
974 filter_info->syn_info = 0;
976 /* clear the ethertype filters info */
977 filter_info->ethertype_mask = 0;
978 memset(filter_info->ethertype_filters, 0,
979 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
981 /* remove all ntuple filters of the device */
982 igb_ntuple_filter_uninit(eth_dev);
984 /* remove all flex filters of the device */
985 igb_flex_filter_uninit(eth_dev);
987 /* clear all the filters list */
988 igb_filterlist_flush(eth_dev);
994 * Virtual Function device init
997 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
999 struct rte_pci_device *pci_dev;
1000 struct rte_intr_handle *intr_handle;
1001 struct e1000_adapter *adapter =
1002 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1003 struct e1000_hw *hw =
1004 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1006 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1008 PMD_INIT_FUNC_TRACE();
1010 eth_dev->dev_ops = &igbvf_eth_dev_ops;
1011 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
1012 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
1013 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
1015 /* for secondary processes, we don't initialise any further as primary
1016 * has already done this work. Only check we don't need a different
1018 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1019 if (eth_dev->data->scattered_rx)
1020 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1024 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1025 rte_eth_copy_pci_info(eth_dev, pci_dev);
1027 hw->device_id = pci_dev->id.device_id;
1028 hw->vendor_id = pci_dev->id.vendor_id;
1029 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1030 adapter->stopped = 0;
1032 /* Initialize the shared code (base driver) */
1033 diag = e1000_setup_init_funcs(hw, TRUE);
1035 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1040 /* init_mailbox_params */
1041 hw->mbx.ops.init_params(hw);
1043 /* Disable the interrupts for VF */
1044 igbvf_intr_disable(hw);
1046 diag = hw->mac.ops.reset_hw(hw);
1048 /* Allocate memory for storing MAC addresses */
1049 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1050 hw->mac.rar_entry_count, 0);
1051 if (eth_dev->data->mac_addrs == NULL) {
1053 "Failed to allocate %d bytes needed to store MAC "
1055 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1059 /* Generate a random MAC address, if none was assigned by PF. */
1060 if (is_zero_ether_addr(perm_addr)) {
1061 eth_random_addr(perm_addr->addr_bytes);
1062 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1063 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1064 "%02x:%02x:%02x:%02x:%02x:%02x",
1065 perm_addr->addr_bytes[0],
1066 perm_addr->addr_bytes[1],
1067 perm_addr->addr_bytes[2],
1068 perm_addr->addr_bytes[3],
1069 perm_addr->addr_bytes[4],
1070 perm_addr->addr_bytes[5]);
1073 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1075 rte_free(eth_dev->data->mac_addrs);
1076 eth_dev->data->mac_addrs = NULL;
1079 /* Copy the permanent MAC address */
1080 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1081 ð_dev->data->mac_addrs[0]);
1083 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1085 eth_dev->data->port_id, pci_dev->id.vendor_id,
1086 pci_dev->id.device_id, "igb_mac_82576_vf");
1088 intr_handle = &pci_dev->intr_handle;
1089 rte_intr_callback_register(intr_handle,
1090 eth_igbvf_interrupt_handler, eth_dev);
1096 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1098 struct e1000_adapter *adapter =
1099 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1100 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102 PMD_INIT_FUNC_TRACE();
1104 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1107 if (adapter->stopped == 0)
1108 igbvf_dev_close(eth_dev);
1110 eth_dev->dev_ops = NULL;
1111 eth_dev->rx_pkt_burst = NULL;
1112 eth_dev->tx_pkt_burst = NULL;
1114 rte_free(eth_dev->data->mac_addrs);
1115 eth_dev->data->mac_addrs = NULL;
1117 /* disable uio intr before callback unregister */
1118 rte_intr_disable(&pci_dev->intr_handle);
1119 rte_intr_callback_unregister(&pci_dev->intr_handle,
1120 eth_igbvf_interrupt_handler,
1126 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1127 struct rte_pci_device *pci_dev)
1129 return rte_eth_dev_pci_generic_probe(pci_dev,
1130 sizeof(struct e1000_adapter), eth_igb_dev_init);
1133 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1135 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1138 static struct rte_pci_driver rte_igb_pmd = {
1139 .id_table = pci_id_igb_map,
1140 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1141 RTE_PCI_DRV_IOVA_AS_VA,
1142 .probe = eth_igb_pci_probe,
1143 .remove = eth_igb_pci_remove,
1147 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1148 struct rte_pci_device *pci_dev)
1150 return rte_eth_dev_pci_generic_probe(pci_dev,
1151 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1154 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1156 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1160 * virtual function driver struct
1162 static struct rte_pci_driver rte_igbvf_pmd = {
1163 .id_table = pci_id_igbvf_map,
1164 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1165 .probe = eth_igbvf_pci_probe,
1166 .remove = eth_igbvf_pci_remove,
1170 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1172 struct e1000_hw *hw =
1173 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1175 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1176 rctl |= E1000_RCTL_VFE;
1177 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1181 igb_check_mq_mode(struct rte_eth_dev *dev)
1183 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1184 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1185 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1186 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1188 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1189 tx_mq_mode == ETH_MQ_TX_DCB ||
1190 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1191 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1194 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1195 /* Check multi-queue mode.
1196 * To no break software we accept ETH_MQ_RX_NONE as this might
1197 * be used to turn off VLAN filter.
1200 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1201 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1202 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1203 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1205 /* Only support one queue on VFs.
1206 * RSS together with SRIOV is not supported.
1208 PMD_INIT_LOG(ERR, "SRIOV is active,"
1209 " wrong mq_mode rx %d.",
1213 /* TX mode is not used here, so mode might be ignored.*/
1214 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1215 /* SRIOV only works in VMDq enable mode */
1216 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1217 " TX mode %d is not supported. "
1218 " Driver will behave as %d mode.",
1219 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1222 /* check valid queue number */
1223 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1224 PMD_INIT_LOG(ERR, "SRIOV is active,"
1225 " only support one queue on VFs.");
1229 /* To no break software that set invalid mode, only display
1230 * warning if invalid mode is used.
1232 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1233 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1234 rx_mq_mode != ETH_MQ_RX_RSS) {
1235 /* RSS together with VMDq not supported*/
1236 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1241 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1242 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1243 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1244 " Due to txmode is meaningless in this"
1245 " driver, just ignore.",
1253 eth_igb_configure(struct rte_eth_dev *dev)
1255 struct e1000_interrupt *intr =
1256 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1259 PMD_INIT_FUNC_TRACE();
1261 /* multipe queue mode checking */
1262 ret = igb_check_mq_mode(dev);
1264 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1269 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1270 PMD_INIT_FUNC_TRACE();
1276 eth_igb_start(struct rte_eth_dev *dev)
1278 struct e1000_hw *hw =
1279 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280 struct e1000_adapter *adapter =
1281 E1000_DEV_PRIVATE(dev->data->dev_private);
1282 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1283 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1285 uint32_t intr_vector = 0;
1291 PMD_INIT_FUNC_TRACE();
1293 /* disable uio/vfio intr/eventfd mapping */
1294 rte_intr_disable(intr_handle);
1296 /* Power up the phy. Needed to make the link go Up */
1297 eth_igb_dev_set_link_up(dev);
1300 * Packet Buffer Allocation (PBA)
1301 * Writing PBA sets the receive portion of the buffer
1302 * the remainder is used for the transmit buffer.
1304 if (hw->mac.type == e1000_82575) {
1307 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1308 E1000_WRITE_REG(hw, E1000_PBA, pba);
1311 /* Put the address into the Receive Address Array */
1312 e1000_rar_set(hw, hw->mac.addr, 0);
1314 /* Initialize the hardware */
1315 if (igb_hardware_init(hw)) {
1316 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1319 adapter->stopped = 0;
1321 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1323 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1324 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1325 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1326 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1327 E1000_WRITE_FLUSH(hw);
1329 /* configure PF module if SRIOV enabled */
1330 igb_pf_host_configure(dev);
1332 /* check and configure queue intr-vector mapping */
1333 if ((rte_intr_cap_multiple(intr_handle) ||
1334 !RTE_ETH_DEV_SRIOV(dev).active) &&
1335 dev->data->dev_conf.intr_conf.rxq != 0) {
1336 intr_vector = dev->data->nb_rx_queues;
1337 if (rte_intr_efd_enable(intr_handle, intr_vector))
1341 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1342 intr_handle->intr_vec =
1343 rte_zmalloc("intr_vec",
1344 dev->data->nb_rx_queues * sizeof(int), 0);
1345 if (intr_handle->intr_vec == NULL) {
1346 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1347 " intr_vec", dev->data->nb_rx_queues);
1352 /* confiugre msix for rx interrupt */
1353 eth_igb_configure_msix_intr(dev);
1355 /* Configure for OS presence */
1356 igb_init_manageability(hw);
1358 eth_igb_tx_init(dev);
1360 /* This can fail when allocating mbufs for descriptor rings */
1361 ret = eth_igb_rx_init(dev);
1363 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1364 igb_dev_clear_queues(dev);
1368 e1000_clear_hw_cntrs_base_generic(hw);
1371 * VLAN Offload Settings
1373 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1374 ETH_VLAN_EXTEND_MASK;
1375 ret = eth_igb_vlan_offload_set(dev, mask);
1377 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1378 igb_dev_clear_queues(dev);
1382 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1383 /* Enable VLAN filter since VMDq always use VLAN filter */
1384 igb_vmdq_vlan_hw_filter_enable(dev);
1387 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1388 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1389 (hw->mac.type == e1000_i211)) {
1390 /* Configure EITR with the maximum possible value (0xFFFF) */
1391 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1394 /* Setup link speed and duplex */
1395 speeds = &dev->data->dev_conf.link_speeds;
1396 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1397 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1398 hw->mac.autoneg = 1;
1401 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1404 hw->phy.autoneg_advertised = 0;
1406 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1407 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1408 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1410 goto error_invalid_config;
1412 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1413 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1416 if (*speeds & ETH_LINK_SPEED_10M) {
1417 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1420 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1421 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1424 if (*speeds & ETH_LINK_SPEED_100M) {
1425 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1428 if (*speeds & ETH_LINK_SPEED_1G) {
1429 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1432 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1433 goto error_invalid_config;
1435 /* Set/reset the mac.autoneg based on the link speed,
1439 hw->mac.autoneg = 0;
1440 hw->mac.forced_speed_duplex =
1441 hw->phy.autoneg_advertised;
1443 hw->mac.autoneg = 1;
1447 e1000_setup_link(hw);
1449 if (rte_intr_allow_others(intr_handle)) {
1450 /* check if lsc interrupt is enabled */
1451 if (dev->data->dev_conf.intr_conf.lsc != 0)
1452 eth_igb_lsc_interrupt_setup(dev, TRUE);
1454 eth_igb_lsc_interrupt_setup(dev, FALSE);
1456 rte_intr_callback_unregister(intr_handle,
1457 eth_igb_interrupt_handler,
1459 if (dev->data->dev_conf.intr_conf.lsc != 0)
1460 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1461 " no intr multiplex");
1464 /* check if rxq interrupt is enabled */
1465 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1466 rte_intr_dp_is_en(intr_handle))
1467 eth_igb_rxq_interrupt_setup(dev);
1469 /* enable uio/vfio intr/eventfd mapping */
1470 rte_intr_enable(intr_handle);
1472 /* resume enabled intr since hw reset */
1473 igb_intr_enable(dev);
1475 /* restore all types filter */
1476 igb_filter_restore(dev);
1478 PMD_INIT_LOG(DEBUG, "<<");
1482 error_invalid_config:
1483 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1484 dev->data->dev_conf.link_speeds, dev->data->port_id);
1485 igb_dev_clear_queues(dev);
1489 /*********************************************************************
1491 * This routine disables all traffic on the adapter by issuing a
1492 * global reset on the MAC.
1494 **********************************************************************/
1496 eth_igb_stop(struct rte_eth_dev *dev)
1498 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1500 struct rte_eth_link link;
1501 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1503 igb_intr_disable(hw);
1505 /* disable intr eventfd mapping */
1506 rte_intr_disable(intr_handle);
1508 igb_pf_reset_hw(hw);
1509 E1000_WRITE_REG(hw, E1000_WUC, 0);
1511 /* Set bit for Go Link disconnect */
1512 if (hw->mac.type >= e1000_82580) {
1515 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1516 phpm_reg |= E1000_82580_PM_GO_LINKD;
1517 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1520 /* Power down the phy. Needed to make the link go Down */
1521 eth_igb_dev_set_link_down(dev);
1523 igb_dev_clear_queues(dev);
1525 /* clear the recorded link status */
1526 memset(&link, 0, sizeof(link));
1527 rte_igb_dev_atomic_write_link_status(dev, &link);
1529 if (!rte_intr_allow_others(intr_handle))
1530 /* resume to the default handler */
1531 rte_intr_callback_register(intr_handle,
1532 eth_igb_interrupt_handler,
1535 /* Clean datapath event and queue/vec mapping */
1536 rte_intr_efd_disable(intr_handle);
1537 if (intr_handle->intr_vec != NULL) {
1538 rte_free(intr_handle->intr_vec);
1539 intr_handle->intr_vec = NULL;
1544 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1546 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548 if (hw->phy.media_type == e1000_media_type_copper)
1549 e1000_power_up_phy(hw);
1551 e1000_power_up_fiber_serdes_link(hw);
1557 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1559 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561 if (hw->phy.media_type == e1000_media_type_copper)
1562 e1000_power_down_phy(hw);
1564 e1000_shutdown_fiber_serdes_link(hw);
1570 eth_igb_close(struct rte_eth_dev *dev)
1572 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 struct e1000_adapter *adapter =
1574 E1000_DEV_PRIVATE(dev->data->dev_private);
1575 struct rte_eth_link link;
1576 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1577 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1580 adapter->stopped = 1;
1582 e1000_phy_hw_reset(hw);
1583 igb_release_manageability(hw);
1584 igb_hw_control_release(hw);
1586 /* Clear bit for Go Link disconnect */
1587 if (hw->mac.type >= e1000_82580) {
1590 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1591 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1592 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1595 igb_dev_free_queues(dev);
1597 if (intr_handle->intr_vec) {
1598 rte_free(intr_handle->intr_vec);
1599 intr_handle->intr_vec = NULL;
1602 memset(&link, 0, sizeof(link));
1603 rte_igb_dev_atomic_write_link_status(dev, &link);
1607 igb_get_rx_buffer_size(struct e1000_hw *hw)
1609 uint32_t rx_buf_size;
1610 if (hw->mac.type == e1000_82576) {
1611 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1612 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1613 /* PBS needs to be translated according to a lookup table */
1614 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1615 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1616 rx_buf_size = (rx_buf_size << 10);
1617 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1618 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1620 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1626 /*********************************************************************
1628 * Initialize the hardware
1630 **********************************************************************/
1632 igb_hardware_init(struct e1000_hw *hw)
1634 uint32_t rx_buf_size;
1637 /* Let the firmware know the OS is in control */
1638 igb_hw_control_acquire(hw);
1641 * These parameters control the automatic generation (Tx) and
1642 * response (Rx) to Ethernet PAUSE frames.
1643 * - High water mark should allow for at least two standard size (1518)
1644 * frames to be received after sending an XOFF.
1645 * - Low water mark works best when it is very near the high water mark.
1646 * This allows the receiver to restart by sending XON when it has
1647 * drained a bit. Here we use an arbitrary value of 1500 which will
1648 * restart after one full frame is pulled from the buffer. There
1649 * could be several smaller frames in the buffer and if so they will
1650 * not trigger the XON until their total number reduces the buffer
1652 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1654 rx_buf_size = igb_get_rx_buffer_size(hw);
1656 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1657 hw->fc.low_water = hw->fc.high_water - 1500;
1658 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1659 hw->fc.send_xon = 1;
1661 /* Set Flow control, use the tunable location if sane */
1662 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1663 hw->fc.requested_mode = igb_fc_setting;
1665 hw->fc.requested_mode = e1000_fc_none;
1667 /* Issue a global reset */
1668 igb_pf_reset_hw(hw);
1669 E1000_WRITE_REG(hw, E1000_WUC, 0);
1671 diag = e1000_init_hw(hw);
1675 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1676 e1000_get_phy_info(hw);
1677 e1000_check_for_link(hw);
1682 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1684 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1688 uint64_t old_gprc = stats->gprc;
1689 uint64_t old_gptc = stats->gptc;
1690 uint64_t old_tpr = stats->tpr;
1691 uint64_t old_tpt = stats->tpt;
1692 uint64_t old_rpthc = stats->rpthc;
1693 uint64_t old_hgptc = stats->hgptc;
1695 if(hw->phy.media_type == e1000_media_type_copper ||
1696 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1698 E1000_READ_REG(hw,E1000_SYMERRS);
1699 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1702 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1703 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1704 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1705 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1707 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1708 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1709 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1710 stats->dc += E1000_READ_REG(hw, E1000_DC);
1711 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1712 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1713 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1715 ** For watchdog management we need to know if we have been
1716 ** paused during the last interval, so capture that here.
1718 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1719 stats->xoffrxc += pause_frames;
1720 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1721 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1722 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1723 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1724 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1725 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1726 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1727 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1728 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1729 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1730 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1731 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1733 /* For the 64-bit byte counters the low dword must be read first. */
1734 /* Both registers clear on the read of the high dword */
1736 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1737 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1738 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1739 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1740 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1741 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1742 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1744 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1745 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1746 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1747 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1748 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1750 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1751 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1753 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1754 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1755 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1756 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1757 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1758 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1760 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1761 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1762 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1763 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1764 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1765 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1766 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1767 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1769 /* Interrupt Counts */
1771 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1772 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1773 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1774 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1775 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1776 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1777 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1778 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1779 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1781 /* Host to Card Statistics */
1783 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1784 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1785 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1786 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1787 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1788 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1789 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1790 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1791 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1792 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1793 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1794 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1795 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1796 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1797 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1798 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1800 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1801 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1802 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1803 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1804 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1805 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1809 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1811 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812 struct e1000_hw_stats *stats =
1813 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1815 igb_read_stats_registers(hw, stats);
1817 if (rte_stats == NULL)
1821 rte_stats->imissed = stats->mpc;
1822 rte_stats->ierrors = stats->crcerrs +
1823 stats->rlec + stats->ruc + stats->roc +
1824 stats->rxerrc + stats->algnerrc + stats->cexterr;
1827 rte_stats->oerrors = stats->ecol + stats->latecol;
1829 rte_stats->ipackets = stats->gprc;
1830 rte_stats->opackets = stats->gptc;
1831 rte_stats->ibytes = stats->gorc;
1832 rte_stats->obytes = stats->gotc;
1837 eth_igb_stats_reset(struct rte_eth_dev *dev)
1839 struct e1000_hw_stats *hw_stats =
1840 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842 /* HW registers are cleared on read */
1843 eth_igb_stats_get(dev, NULL);
1845 /* Reset software totals */
1846 memset(hw_stats, 0, sizeof(*hw_stats));
1850 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1852 struct e1000_hw_stats *stats =
1853 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1855 /* HW registers are cleared on read */
1856 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1858 /* Reset software totals */
1859 memset(stats, 0, sizeof(*stats));
1862 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1863 struct rte_eth_xstat_name *xstats_names,
1864 __rte_unused unsigned int size)
1868 if (xstats_names == NULL)
1869 return IGB_NB_XSTATS;
1871 /* Note: limit checked in rte_eth_xstats_names() */
1873 for (i = 0; i < IGB_NB_XSTATS; i++) {
1874 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1875 "%s", rte_igb_stats_strings[i].name);
1878 return IGB_NB_XSTATS;
1881 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1882 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1888 if (xstats_names == NULL)
1889 return IGB_NB_XSTATS;
1891 for (i = 0; i < IGB_NB_XSTATS; i++)
1892 snprintf(xstats_names[i].name,
1893 sizeof(xstats_names[i].name),
1894 "%s", rte_igb_stats_strings[i].name);
1896 return IGB_NB_XSTATS;
1899 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1901 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1904 for (i = 0; i < limit; i++) {
1905 if (ids[i] >= IGB_NB_XSTATS) {
1906 PMD_INIT_LOG(ERR, "id value isn't valid");
1909 strcpy(xstats_names[i].name,
1910 xstats_names_copy[ids[i]].name);
1917 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1920 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 struct e1000_hw_stats *hw_stats =
1922 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1925 if (n < IGB_NB_XSTATS)
1926 return IGB_NB_XSTATS;
1928 igb_read_stats_registers(hw, hw_stats);
1930 /* If this is a reset xstats is NULL, and we have cleared the
1931 * registers by reading them.
1936 /* Extended stats */
1937 for (i = 0; i < IGB_NB_XSTATS; i++) {
1939 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1940 rte_igb_stats_strings[i].offset);
1943 return IGB_NB_XSTATS;
1947 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1948 uint64_t *values, unsigned int n)
1953 struct e1000_hw *hw =
1954 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955 struct e1000_hw_stats *hw_stats =
1956 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1958 if (n < IGB_NB_XSTATS)
1959 return IGB_NB_XSTATS;
1961 igb_read_stats_registers(hw, hw_stats);
1963 /* If this is a reset xstats is NULL, and we have cleared the
1964 * registers by reading them.
1969 /* Extended stats */
1970 for (i = 0; i < IGB_NB_XSTATS; i++)
1971 values[i] = *(uint64_t *)(((char *)hw_stats) +
1972 rte_igb_stats_strings[i].offset);
1974 return IGB_NB_XSTATS;
1977 uint64_t values_copy[IGB_NB_XSTATS];
1979 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1982 for (i = 0; i < n; i++) {
1983 if (ids[i] >= IGB_NB_XSTATS) {
1984 PMD_INIT_LOG(ERR, "id value isn't valid");
1987 values[i] = values_copy[ids[i]];
1994 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1996 /* Good Rx packets, include VF loopback */
1997 UPDATE_VF_STAT(E1000_VFGPRC,
1998 hw_stats->last_gprc, hw_stats->gprc);
2000 /* Good Rx octets, include VF loopback */
2001 UPDATE_VF_STAT(E1000_VFGORC,
2002 hw_stats->last_gorc, hw_stats->gorc);
2004 /* Good Tx packets, include VF loopback */
2005 UPDATE_VF_STAT(E1000_VFGPTC,
2006 hw_stats->last_gptc, hw_stats->gptc);
2008 /* Good Tx octets, include VF loopback */
2009 UPDATE_VF_STAT(E1000_VFGOTC,
2010 hw_stats->last_gotc, hw_stats->gotc);
2012 /* Rx Multicst packets */
2013 UPDATE_VF_STAT(E1000_VFMPRC,
2014 hw_stats->last_mprc, hw_stats->mprc);
2016 /* Good Rx loopback packets */
2017 UPDATE_VF_STAT(E1000_VFGPRLBC,
2018 hw_stats->last_gprlbc, hw_stats->gprlbc);
2020 /* Good Rx loopback octets */
2021 UPDATE_VF_STAT(E1000_VFGORLBC,
2022 hw_stats->last_gorlbc, hw_stats->gorlbc);
2024 /* Good Tx loopback packets */
2025 UPDATE_VF_STAT(E1000_VFGPTLBC,
2026 hw_stats->last_gptlbc, hw_stats->gptlbc);
2028 /* Good Tx loopback octets */
2029 UPDATE_VF_STAT(E1000_VFGOTLBC,
2030 hw_stats->last_gotlbc, hw_stats->gotlbc);
2033 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2034 struct rte_eth_xstat_name *xstats_names,
2035 __rte_unused unsigned limit)
2039 if (xstats_names != NULL)
2040 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2041 snprintf(xstats_names[i].name,
2042 sizeof(xstats_names[i].name), "%s",
2043 rte_igbvf_stats_strings[i].name);
2045 return IGBVF_NB_XSTATS;
2049 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2052 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2054 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2057 if (n < IGBVF_NB_XSTATS)
2058 return IGBVF_NB_XSTATS;
2060 igbvf_read_stats_registers(hw, hw_stats);
2065 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2067 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2068 rte_igbvf_stats_strings[i].offset);
2071 return IGBVF_NB_XSTATS;
2075 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2077 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2079 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081 igbvf_read_stats_registers(hw, hw_stats);
2083 if (rte_stats == NULL)
2086 rte_stats->ipackets = hw_stats->gprc;
2087 rte_stats->ibytes = hw_stats->gorc;
2088 rte_stats->opackets = hw_stats->gptc;
2089 rte_stats->obytes = hw_stats->gotc;
2094 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2096 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2097 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2099 /* Sync HW register to the last stats */
2100 eth_igbvf_stats_get(dev, NULL);
2102 /* reset HW current stats*/
2103 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2104 offsetof(struct e1000_vf_stats, gprc));
2108 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2111 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 struct e1000_fw_version fw;
2115 e1000_get_fw_version(hw, &fw);
2117 switch (hw->mac.type) {
2120 if (!(e1000_get_flash_presence_i210(hw))) {
2121 ret = snprintf(fw_version, fw_size,
2123 fw.invm_major, fw.invm_minor,
2129 /* if option rom is valid, display its version too */
2131 ret = snprintf(fw_version, fw_size,
2132 "%d.%d, 0x%08x, %d.%d.%d",
2133 fw.eep_major, fw.eep_minor, fw.etrack_id,
2134 fw.or_major, fw.or_build, fw.or_patch);
2137 if (fw.etrack_id != 0X0000) {
2138 ret = snprintf(fw_version, fw_size,
2140 fw.eep_major, fw.eep_minor,
2143 ret = snprintf(fw_version, fw_size,
2145 fw.eep_major, fw.eep_minor,
2152 ret += 1; /* add the size of '\0' */
2153 if (fw_size < (u32)ret)
2160 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2162 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2165 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2166 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2167 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2168 dev_info->rx_offload_capa =
2169 DEV_RX_OFFLOAD_VLAN_STRIP |
2170 DEV_RX_OFFLOAD_IPV4_CKSUM |
2171 DEV_RX_OFFLOAD_UDP_CKSUM |
2172 DEV_RX_OFFLOAD_TCP_CKSUM;
2173 dev_info->tx_offload_capa =
2174 DEV_TX_OFFLOAD_VLAN_INSERT |
2175 DEV_TX_OFFLOAD_IPV4_CKSUM |
2176 DEV_TX_OFFLOAD_UDP_CKSUM |
2177 DEV_TX_OFFLOAD_TCP_CKSUM |
2178 DEV_TX_OFFLOAD_SCTP_CKSUM |
2179 DEV_TX_OFFLOAD_TCP_TSO;
2181 switch (hw->mac.type) {
2183 dev_info->max_rx_queues = 4;
2184 dev_info->max_tx_queues = 4;
2185 dev_info->max_vmdq_pools = 0;
2189 dev_info->max_rx_queues = 16;
2190 dev_info->max_tx_queues = 16;
2191 dev_info->max_vmdq_pools = ETH_8_POOLS;
2192 dev_info->vmdq_queue_num = 16;
2196 dev_info->max_rx_queues = 8;
2197 dev_info->max_tx_queues = 8;
2198 dev_info->max_vmdq_pools = ETH_8_POOLS;
2199 dev_info->vmdq_queue_num = 8;
2203 dev_info->max_rx_queues = 8;
2204 dev_info->max_tx_queues = 8;
2205 dev_info->max_vmdq_pools = ETH_8_POOLS;
2206 dev_info->vmdq_queue_num = 8;
2210 dev_info->max_rx_queues = 8;
2211 dev_info->max_tx_queues = 8;
2215 dev_info->max_rx_queues = 4;
2216 dev_info->max_tx_queues = 4;
2217 dev_info->max_vmdq_pools = 0;
2221 dev_info->max_rx_queues = 2;
2222 dev_info->max_tx_queues = 2;
2223 dev_info->max_vmdq_pools = 0;
2227 /* Should not happen */
2230 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2231 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2232 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2234 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2236 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2237 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2238 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2240 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2244 dev_info->default_txconf = (struct rte_eth_txconf) {
2246 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2247 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2248 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2253 dev_info->rx_desc_lim = rx_desc_lim;
2254 dev_info->tx_desc_lim = tx_desc_lim;
2256 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2257 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2261 static const uint32_t *
2262 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2264 static const uint32_t ptypes[] = {
2265 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2268 RTE_PTYPE_L3_IPV4_EXT,
2270 RTE_PTYPE_L3_IPV6_EXT,
2274 RTE_PTYPE_TUNNEL_IP,
2275 RTE_PTYPE_INNER_L3_IPV6,
2276 RTE_PTYPE_INNER_L3_IPV6_EXT,
2277 RTE_PTYPE_INNER_L4_TCP,
2278 RTE_PTYPE_INNER_L4_UDP,
2282 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2283 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2289 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2291 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2294 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2295 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2296 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2297 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2298 DEV_RX_OFFLOAD_IPV4_CKSUM |
2299 DEV_RX_OFFLOAD_UDP_CKSUM |
2300 DEV_RX_OFFLOAD_TCP_CKSUM;
2301 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2302 DEV_TX_OFFLOAD_IPV4_CKSUM |
2303 DEV_TX_OFFLOAD_UDP_CKSUM |
2304 DEV_TX_OFFLOAD_TCP_CKSUM |
2305 DEV_TX_OFFLOAD_SCTP_CKSUM |
2306 DEV_TX_OFFLOAD_TCP_TSO;
2307 switch (hw->mac.type) {
2309 dev_info->max_rx_queues = 2;
2310 dev_info->max_tx_queues = 2;
2312 case e1000_vfadapt_i350:
2313 dev_info->max_rx_queues = 1;
2314 dev_info->max_tx_queues = 1;
2317 /* Should not happen */
2321 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2323 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2324 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2325 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2327 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2331 dev_info->default_txconf = (struct rte_eth_txconf) {
2333 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2334 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2335 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2340 dev_info->rx_desc_lim = rx_desc_lim;
2341 dev_info->tx_desc_lim = tx_desc_lim;
2344 /* return 0 means link status changed, -1 means not changed */
2346 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2348 struct e1000_hw *hw =
2349 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2350 struct rte_eth_link link, old;
2351 int link_check, count;
2354 hw->mac.get_link_status = 1;
2356 /* possible wait-to-complete in up to 9 seconds */
2357 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2358 /* Read the real link status */
2359 switch (hw->phy.media_type) {
2360 case e1000_media_type_copper:
2361 /* Do the work to read phy */
2362 e1000_check_for_link(hw);
2363 link_check = !hw->mac.get_link_status;
2366 case e1000_media_type_fiber:
2367 e1000_check_for_link(hw);
2368 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2372 case e1000_media_type_internal_serdes:
2373 e1000_check_for_link(hw);
2374 link_check = hw->mac.serdes_has_link;
2377 /* VF device is type_unknown */
2378 case e1000_media_type_unknown:
2379 eth_igbvf_link_update(hw);
2380 link_check = !hw->mac.get_link_status;
2386 if (link_check || wait_to_complete == 0)
2388 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2390 memset(&link, 0, sizeof(link));
2391 rte_igb_dev_atomic_read_link_status(dev, &link);
2394 /* Now we check if a transition has happened */
2396 uint16_t duplex, speed;
2397 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2398 link.link_duplex = (duplex == FULL_DUPLEX) ?
2399 ETH_LINK_FULL_DUPLEX :
2400 ETH_LINK_HALF_DUPLEX;
2401 link.link_speed = speed;
2402 link.link_status = ETH_LINK_UP;
2403 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2404 ETH_LINK_SPEED_FIXED);
2405 } else if (!link_check) {
2406 link.link_speed = 0;
2407 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2408 link.link_status = ETH_LINK_DOWN;
2409 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2411 rte_igb_dev_atomic_write_link_status(dev, &link);
2414 if (old.link_status == link.link_status)
2422 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2423 * For ASF and Pass Through versions of f/w this means
2424 * that the driver is loaded.
2427 igb_hw_control_acquire(struct e1000_hw *hw)
2431 /* Let firmware know the driver has taken over */
2432 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2433 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2437 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2438 * For ASF and Pass Through versions of f/w this means that the
2439 * driver is no longer loaded.
2442 igb_hw_control_release(struct e1000_hw *hw)
2446 /* Let firmware taken over control of h/w */
2447 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2448 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2449 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2453 * Bit of a misnomer, what this really means is
2454 * to enable OS management of the system... aka
2455 * to disable special hardware management features.
2458 igb_init_manageability(struct e1000_hw *hw)
2460 if (e1000_enable_mng_pass_thru(hw)) {
2461 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2462 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2464 /* disable hardware interception of ARP */
2465 manc &= ~(E1000_MANC_ARP_EN);
2467 /* enable receiving management packets to the host */
2468 manc |= E1000_MANC_EN_MNG2HOST;
2469 manc2h |= 1 << 5; /* Mng Port 623 */
2470 manc2h |= 1 << 6; /* Mng Port 664 */
2471 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2472 E1000_WRITE_REG(hw, E1000_MANC, manc);
2477 igb_release_manageability(struct e1000_hw *hw)
2479 if (e1000_enable_mng_pass_thru(hw)) {
2480 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2482 manc |= E1000_MANC_ARP_EN;
2483 manc &= ~E1000_MANC_EN_MNG2HOST;
2485 E1000_WRITE_REG(hw, E1000_MANC, manc);
2490 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2492 struct e1000_hw *hw =
2493 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 rctl = E1000_READ_REG(hw, E1000_RCTL);
2497 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2498 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2502 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2504 struct e1000_hw *hw =
2505 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2508 rctl = E1000_READ_REG(hw, E1000_RCTL);
2509 rctl &= (~E1000_RCTL_UPE);
2510 if (dev->data->all_multicast == 1)
2511 rctl |= E1000_RCTL_MPE;
2513 rctl &= (~E1000_RCTL_MPE);
2514 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2518 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2520 struct e1000_hw *hw =
2521 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524 rctl = E1000_READ_REG(hw, E1000_RCTL);
2525 rctl |= E1000_RCTL_MPE;
2526 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2530 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2532 struct e1000_hw *hw =
2533 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 if (dev->data->promiscuous == 1)
2537 return; /* must remain in all_multicast mode */
2538 rctl = E1000_READ_REG(hw, E1000_RCTL);
2539 rctl &= (~E1000_RCTL_MPE);
2540 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2544 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2546 struct e1000_hw *hw =
2547 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548 struct e1000_vfta * shadow_vfta =
2549 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2554 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2555 E1000_VFTA_ENTRY_MASK);
2556 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2557 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2562 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2564 /* update local VFTA copy */
2565 shadow_vfta->vfta[vid_idx] = vfta;
2571 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2572 enum rte_vlan_type vlan_type,
2575 struct e1000_hw *hw =
2576 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2580 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2582 /* only outer TPID of double VLAN can be configured*/
2583 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2584 reg = E1000_READ_REG(hw, E1000_VET);
2585 reg = (reg & (~E1000_VET_VET_EXT)) |
2586 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2587 E1000_WRITE_REG(hw, E1000_VET, reg);
2592 /* all other TPID values are read-only*/
2593 PMD_DRV_LOG(ERR, "Not supported");
2599 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2601 struct e1000_hw *hw =
2602 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605 /* Filter Table Disable */
2606 reg = E1000_READ_REG(hw, E1000_RCTL);
2607 reg &= ~E1000_RCTL_CFIEN;
2608 reg &= ~E1000_RCTL_VFE;
2609 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2613 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2615 struct e1000_hw *hw =
2616 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617 struct e1000_vfta * shadow_vfta =
2618 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2622 /* Filter Table Enable, CFI not used for packet acceptance */
2623 reg = E1000_READ_REG(hw, E1000_RCTL);
2624 reg &= ~E1000_RCTL_CFIEN;
2625 reg |= E1000_RCTL_VFE;
2626 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2628 /* restore VFTA table */
2629 for (i = 0; i < IGB_VFTA_SIZE; i++)
2630 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2634 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2636 struct e1000_hw *hw =
2637 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 /* VLAN Mode Disable */
2641 reg = E1000_READ_REG(hw, E1000_CTRL);
2642 reg &= ~E1000_CTRL_VME;
2643 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2647 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2649 struct e1000_hw *hw =
2650 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2653 /* VLAN Mode Enable */
2654 reg = E1000_READ_REG(hw, E1000_CTRL);
2655 reg |= E1000_CTRL_VME;
2656 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2660 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2662 struct e1000_hw *hw =
2663 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666 /* CTRL_EXT: Extended VLAN */
2667 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2668 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2669 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2671 /* Update maximum packet length */
2672 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2673 E1000_WRITE_REG(hw, E1000_RLPML,
2674 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2679 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2681 struct e1000_hw *hw =
2682 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685 /* CTRL_EXT: Extended VLAN */
2686 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2687 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2688 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2690 /* Update maximum packet length */
2691 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2692 E1000_WRITE_REG(hw, E1000_RLPML,
2693 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2698 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2700 if(mask & ETH_VLAN_STRIP_MASK){
2701 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2702 igb_vlan_hw_strip_enable(dev);
2704 igb_vlan_hw_strip_disable(dev);
2707 if(mask & ETH_VLAN_FILTER_MASK){
2708 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2709 igb_vlan_hw_filter_enable(dev);
2711 igb_vlan_hw_filter_disable(dev);
2714 if(mask & ETH_VLAN_EXTEND_MASK){
2715 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2716 igb_vlan_hw_extend_enable(dev);
2718 igb_vlan_hw_extend_disable(dev);
2726 * It enables the interrupt mask and then enable the interrupt.
2729 * Pointer to struct rte_eth_dev.
2734 * - On success, zero.
2735 * - On failure, a negative value.
2738 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2740 struct e1000_interrupt *intr =
2741 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2744 intr->mask |= E1000_ICR_LSC;
2746 intr->mask &= ~E1000_ICR_LSC;
2751 /* It clears the interrupt causes and enables the interrupt.
2752 * It will be called once only during nic initialized.
2755 * Pointer to struct rte_eth_dev.
2758 * - On success, zero.
2759 * - On failure, a negative value.
2761 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2763 uint32_t mask, regval;
2764 struct e1000_hw *hw =
2765 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766 struct rte_eth_dev_info dev_info;
2768 memset(&dev_info, 0, sizeof(dev_info));
2769 eth_igb_infos_get(dev, &dev_info);
2771 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2772 regval = E1000_READ_REG(hw, E1000_EIMS);
2773 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2779 * It reads ICR and gets interrupt causes, check it and set a bit flag
2780 * to update link status.
2783 * Pointer to struct rte_eth_dev.
2786 * - On success, zero.
2787 * - On failure, a negative value.
2790 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2793 struct e1000_hw *hw =
2794 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 struct e1000_interrupt *intr =
2796 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2798 igb_intr_disable(hw);
2800 /* read-on-clear nic registers here */
2801 icr = E1000_READ_REG(hw, E1000_ICR);
2804 if (icr & E1000_ICR_LSC) {
2805 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2808 if (icr & E1000_ICR_VMMB)
2809 intr->flags |= E1000_FLAG_MAILBOX;
2815 * It executes link_update after knowing an interrupt is prsent.
2818 * Pointer to struct rte_eth_dev.
2821 * - On success, zero.
2822 * - On failure, a negative value.
2825 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2826 struct rte_intr_handle *intr_handle)
2828 struct e1000_hw *hw =
2829 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830 struct e1000_interrupt *intr =
2831 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2833 uint32_t tctl, rctl;
2834 struct rte_eth_link link;
2837 if (intr->flags & E1000_FLAG_MAILBOX) {
2838 igb_pf_mbx_process(dev);
2839 intr->flags &= ~E1000_FLAG_MAILBOX;
2842 igb_intr_enable(dev);
2843 rte_intr_enable(intr_handle);
2845 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2846 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2848 /* set get_link_status to check register later */
2849 hw->mac.get_link_status = 1;
2850 ret = eth_igb_link_update(dev, 0);
2852 /* check if link has changed */
2856 memset(&link, 0, sizeof(link));
2857 rte_igb_dev_atomic_read_link_status(dev, &link);
2858 if (link.link_status) {
2860 " Port %d: Link Up - speed %u Mbps - %s",
2862 (unsigned)link.link_speed,
2863 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2864 "full-duplex" : "half-duplex");
2866 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2867 dev->data->port_id);
2870 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2871 pci_dev->addr.domain,
2873 pci_dev->addr.devid,
2874 pci_dev->addr.function);
2875 tctl = E1000_READ_REG(hw, E1000_TCTL);
2876 rctl = E1000_READ_REG(hw, E1000_RCTL);
2877 if (link.link_status) {
2879 tctl |= E1000_TCTL_EN;
2880 rctl |= E1000_RCTL_EN;
2883 tctl &= ~E1000_TCTL_EN;
2884 rctl &= ~E1000_RCTL_EN;
2886 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2887 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2888 E1000_WRITE_FLUSH(hw);
2889 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2897 * Interrupt handler which shall be registered at first.
2900 * Pointer to interrupt handle.
2902 * The address of parameter (struct rte_eth_dev *) regsitered before.
2908 eth_igb_interrupt_handler(void *param)
2910 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2912 eth_igb_interrupt_get_status(dev);
2913 eth_igb_interrupt_action(dev, dev->intr_handle);
2917 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2920 struct e1000_hw *hw =
2921 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922 struct e1000_interrupt *intr =
2923 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2925 igbvf_intr_disable(hw);
2927 /* read-on-clear nic registers here */
2928 eicr = E1000_READ_REG(hw, E1000_EICR);
2931 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2932 intr->flags |= E1000_FLAG_MAILBOX;
2937 void igbvf_mbx_process(struct rte_eth_dev *dev)
2939 struct e1000_hw *hw =
2940 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941 struct e1000_mbx_info *mbx = &hw->mbx;
2944 if (mbx->ops.read(hw, &in_msg, 1, 0))
2947 /* PF reset VF event */
2948 if (in_msg == E1000_PF_CONTROL_MSG)
2949 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2954 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2956 struct e1000_interrupt *intr =
2957 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2959 if (intr->flags & E1000_FLAG_MAILBOX) {
2960 igbvf_mbx_process(dev);
2961 intr->flags &= ~E1000_FLAG_MAILBOX;
2964 igbvf_intr_enable(dev);
2965 rte_intr_enable(intr_handle);
2971 eth_igbvf_interrupt_handler(void *param)
2973 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2975 eth_igbvf_interrupt_get_status(dev);
2976 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2980 eth_igb_led_on(struct rte_eth_dev *dev)
2982 struct e1000_hw *hw;
2984 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2985 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2989 eth_igb_led_off(struct rte_eth_dev *dev)
2991 struct e1000_hw *hw;
2993 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2998 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3000 struct e1000_hw *hw;
3005 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006 fc_conf->pause_time = hw->fc.pause_time;
3007 fc_conf->high_water = hw->fc.high_water;
3008 fc_conf->low_water = hw->fc.low_water;
3009 fc_conf->send_xon = hw->fc.send_xon;
3010 fc_conf->autoneg = hw->mac.autoneg;
3013 * Return rx_pause and tx_pause status according to actual setting of
3014 * the TFCE and RFCE bits in the CTRL register.
3016 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3017 if (ctrl & E1000_CTRL_TFCE)
3022 if (ctrl & E1000_CTRL_RFCE)
3027 if (rx_pause && tx_pause)
3028 fc_conf->mode = RTE_FC_FULL;
3030 fc_conf->mode = RTE_FC_RX_PAUSE;
3032 fc_conf->mode = RTE_FC_TX_PAUSE;
3034 fc_conf->mode = RTE_FC_NONE;
3040 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3042 struct e1000_hw *hw;
3044 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3050 uint32_t rx_buf_size;
3051 uint32_t max_high_water;
3054 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055 if (fc_conf->autoneg != hw->mac.autoneg)
3057 rx_buf_size = igb_get_rx_buffer_size(hw);
3058 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3060 /* At least reserve one Ethernet frame for watermark */
3061 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3062 if ((fc_conf->high_water > max_high_water) ||
3063 (fc_conf->high_water < fc_conf->low_water)) {
3064 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3065 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3069 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3070 hw->fc.pause_time = fc_conf->pause_time;
3071 hw->fc.high_water = fc_conf->high_water;
3072 hw->fc.low_water = fc_conf->low_water;
3073 hw->fc.send_xon = fc_conf->send_xon;
3075 err = e1000_setup_link_generic(hw);
3076 if (err == E1000_SUCCESS) {
3078 /* check if we want to forward MAC frames - driver doesn't have native
3079 * capability to do that, so we'll write the registers ourselves */
3081 rctl = E1000_READ_REG(hw, E1000_RCTL);
3083 /* set or clear MFLCN.PMCF bit depending on configuration */
3084 if (fc_conf->mac_ctrl_frame_fwd != 0)
3085 rctl |= E1000_RCTL_PMCF;
3087 rctl &= ~E1000_RCTL_PMCF;
3089 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3090 E1000_WRITE_FLUSH(hw);
3095 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3099 #define E1000_RAH_POOLSEL_SHIFT (18)
3101 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3102 uint32_t index, uint32_t pool)
3104 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3108 rah = E1000_READ_REG(hw, E1000_RAH(index));
3109 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3110 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3115 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3117 uint8_t addr[ETHER_ADDR_LEN];
3118 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120 memset(addr, 0, sizeof(addr));
3122 e1000_rar_set(hw, addr, index);
3126 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3127 struct ether_addr *addr)
3129 eth_igb_rar_clear(dev, 0);
3131 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3134 * Virtual Function operations
3137 igbvf_intr_disable(struct e1000_hw *hw)
3139 PMD_INIT_FUNC_TRACE();
3141 /* Clear interrupt mask to stop from interrupts being generated */
3142 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3144 E1000_WRITE_FLUSH(hw);
3148 igbvf_stop_adapter(struct rte_eth_dev *dev)
3152 struct rte_eth_dev_info dev_info;
3153 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155 memset(&dev_info, 0, sizeof(dev_info));
3156 eth_igbvf_infos_get(dev, &dev_info);
3158 /* Clear interrupt mask to stop from interrupts being generated */
3159 igbvf_intr_disable(hw);
3161 /* Clear any pending interrupts, flush previous writes */
3162 E1000_READ_REG(hw, E1000_EICR);
3164 /* Disable the transmit unit. Each queue must be disabled. */
3165 for (i = 0; i < dev_info.max_tx_queues; i++)
3166 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3168 /* Disable the receive unit by stopping each queue */
3169 for (i = 0; i < dev_info.max_rx_queues; i++) {
3170 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3171 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3172 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3173 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3177 /* flush all queues disables */
3178 E1000_WRITE_FLUSH(hw);
3182 static int eth_igbvf_link_update(struct e1000_hw *hw)
3184 struct e1000_mbx_info *mbx = &hw->mbx;
3185 struct e1000_mac_info *mac = &hw->mac;
3186 int ret_val = E1000_SUCCESS;
3188 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3191 * We only want to run this if there has been a rst asserted.
3192 * in this case that could mean a link change, device reset,
3193 * or a virtual function reset
3196 /* If we were hit with a reset or timeout drop the link */
3197 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3198 mac->get_link_status = TRUE;
3200 if (!mac->get_link_status)
3203 /* if link status is down no point in checking to see if pf is up */
3204 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3207 /* if we passed all the tests above then the link is up and we no
3208 * longer need to check for link */
3209 mac->get_link_status = FALSE;
3217 igbvf_dev_configure(struct rte_eth_dev *dev)
3219 struct rte_eth_conf* conf = &dev->data->dev_conf;
3221 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3222 dev->data->port_id);
3225 * VF has no ability to enable/disable HW CRC
3226 * Keep the persistent behavior the same as Host PF
3228 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3229 if (!conf->rxmode.hw_strip_crc) {
3230 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3231 conf->rxmode.hw_strip_crc = 1;
3234 if (conf->rxmode.hw_strip_crc) {
3235 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3236 conf->rxmode.hw_strip_crc = 0;
3244 igbvf_dev_start(struct rte_eth_dev *dev)
3246 struct e1000_hw *hw =
3247 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3248 struct e1000_adapter *adapter =
3249 E1000_DEV_PRIVATE(dev->data->dev_private);
3250 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3251 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3253 uint32_t intr_vector = 0;
3255 PMD_INIT_FUNC_TRACE();
3257 hw->mac.ops.reset_hw(hw);
3258 adapter->stopped = 0;
3261 igbvf_set_vfta_all(dev,1);
3263 eth_igbvf_tx_init(dev);
3265 /* This can fail when allocating mbufs for descriptor rings */
3266 ret = eth_igbvf_rx_init(dev);
3268 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3269 igb_dev_clear_queues(dev);
3273 /* check and configure queue intr-vector mapping */
3274 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3275 intr_vector = dev->data->nb_rx_queues;
3276 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3281 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3282 intr_handle->intr_vec =
3283 rte_zmalloc("intr_vec",
3284 dev->data->nb_rx_queues * sizeof(int), 0);
3285 if (!intr_handle->intr_vec) {
3286 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3287 " intr_vec", dev->data->nb_rx_queues);
3292 eth_igbvf_configure_msix_intr(dev);
3294 /* enable uio/vfio intr/eventfd mapping */
3295 rte_intr_enable(intr_handle);
3297 /* resume enabled intr since hw reset */
3298 igbvf_intr_enable(dev);
3304 igbvf_dev_stop(struct rte_eth_dev *dev)
3306 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3307 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3309 PMD_INIT_FUNC_TRACE();
3311 igbvf_stop_adapter(dev);
3314 * Clear what we set, but we still keep shadow_vfta to
3315 * restore after device starts
3317 igbvf_set_vfta_all(dev,0);
3319 igb_dev_clear_queues(dev);
3321 /* disable intr eventfd mapping */
3322 rte_intr_disable(intr_handle);
3324 /* Clean datapath event and queue/vec mapping */
3325 rte_intr_efd_disable(intr_handle);
3326 if (intr_handle->intr_vec) {
3327 rte_free(intr_handle->intr_vec);
3328 intr_handle->intr_vec = NULL;
3333 igbvf_dev_close(struct rte_eth_dev *dev)
3335 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336 struct e1000_adapter *adapter =
3337 E1000_DEV_PRIVATE(dev->data->dev_private);
3338 struct ether_addr addr;
3340 PMD_INIT_FUNC_TRACE();
3344 igbvf_dev_stop(dev);
3345 adapter->stopped = 1;
3346 igb_dev_free_queues(dev);
3349 * reprogram the RAR with a zero mac address,
3350 * to ensure that the VF traffic goes to the PF
3351 * after stop, close and detach of the VF.
3354 memset(&addr, 0, sizeof(addr));
3355 igbvf_default_mac_addr_set(dev, &addr);
3359 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3361 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363 /* Set both unicast and multicast promisc */
3364 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3368 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3370 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3372 /* If in allmulticast mode leave multicast promisc */
3373 if (dev->data->all_multicast == 1)
3374 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3376 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3380 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3382 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384 /* In promiscuous mode multicast promisc already set */
3385 if (dev->data->promiscuous == 0)
3386 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3390 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3392 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394 /* In promiscuous mode leave multicast promisc enabled */
3395 if (dev->data->promiscuous == 0)
3396 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3399 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3401 struct e1000_mbx_info *mbx = &hw->mbx;
3405 /* After set vlan, vlan strip will also be enabled in igb driver*/
3406 msgbuf[0] = E1000_VF_SET_VLAN;
3408 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3410 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3412 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3416 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3420 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3421 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3428 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3430 struct e1000_hw *hw =
3431 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432 struct e1000_vfta * shadow_vfta =
3433 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3434 int i = 0, j = 0, vfta = 0, mask = 1;
3436 for (i = 0; i < IGB_VFTA_SIZE; i++){
3437 vfta = shadow_vfta->vfta[i];
3440 for (j = 0; j < 32; j++){
3443 (uint16_t)((i<<5)+j), on);
3452 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3454 struct e1000_hw *hw =
3455 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456 struct e1000_vfta * shadow_vfta =
3457 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3458 uint32_t vid_idx = 0;
3459 uint32_t vid_bit = 0;
3462 PMD_INIT_FUNC_TRACE();
3464 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3465 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3467 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3470 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3471 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3473 /*Save what we set and retore it after device reset*/
3475 shadow_vfta->vfta[vid_idx] |= vid_bit;
3477 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3483 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3485 struct e1000_hw *hw =
3486 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3488 /* index is not used by rar_set() */
3489 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3494 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3495 struct rte_eth_rss_reta_entry64 *reta_conf,
3500 uint16_t idx, shift;
3501 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3503 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3504 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3505 "(%d) doesn't match the number hardware can supported "
3506 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3510 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3511 idx = i / RTE_RETA_GROUP_SIZE;
3512 shift = i % RTE_RETA_GROUP_SIZE;
3513 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3517 if (mask == IGB_4_BIT_MASK)
3520 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3521 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3522 if (mask & (0x1 << j))
3523 reta |= reta_conf[idx].reta[shift + j] <<
3526 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3528 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3535 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3536 struct rte_eth_rss_reta_entry64 *reta_conf,
3541 uint16_t idx, shift;
3542 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3545 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3546 "(%d) doesn't match the number hardware can supported "
3547 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3551 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3552 idx = i / RTE_RETA_GROUP_SIZE;
3553 shift = i % RTE_RETA_GROUP_SIZE;
3554 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3558 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3559 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3560 if (mask & (0x1 << j))
3561 reta_conf[idx].reta[shift + j] =
3562 ((reta >> (CHAR_BIT * j)) &
3571 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3572 struct rte_eth_syn_filter *filter,
3575 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576 struct e1000_filter_info *filter_info =
3577 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3578 uint32_t synqf, rfctl;
3580 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3583 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3586 if (synqf & E1000_SYN_FILTER_ENABLE)
3589 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3590 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3592 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3593 if (filter->hig_pri)
3594 rfctl |= E1000_RFCTL_SYNQFP;
3596 rfctl &= ~E1000_RFCTL_SYNQFP;
3598 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3600 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3605 filter_info->syn_info = synqf;
3606 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3607 E1000_WRITE_FLUSH(hw);
3612 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3613 struct rte_eth_syn_filter *filter)
3615 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3616 uint32_t synqf, rfctl;
3618 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3619 if (synqf & E1000_SYN_FILTER_ENABLE) {
3620 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3621 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3622 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3623 E1000_SYN_FILTER_QUEUE_SHIFT);
3631 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3632 enum rte_filter_op filter_op,
3635 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638 MAC_TYPE_FILTER_SUP(hw->mac.type);
3640 if (filter_op == RTE_ETH_FILTER_NOP)
3644 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3649 switch (filter_op) {
3650 case RTE_ETH_FILTER_ADD:
3651 ret = eth_igb_syn_filter_set(dev,
3652 (struct rte_eth_syn_filter *)arg,
3655 case RTE_ETH_FILTER_DELETE:
3656 ret = eth_igb_syn_filter_set(dev,
3657 (struct rte_eth_syn_filter *)arg,
3660 case RTE_ETH_FILTER_GET:
3661 ret = eth_igb_syn_filter_get(dev,
3662 (struct rte_eth_syn_filter *)arg);
3665 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3673 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3675 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3676 struct e1000_2tuple_filter_info *filter_info)
3678 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3680 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3681 return -EINVAL; /* filter index is out of range. */
3682 if (filter->tcp_flags > TCP_FLAG_ALL)
3683 return -EINVAL; /* flags is invalid. */
3685 switch (filter->dst_port_mask) {
3687 filter_info->dst_port_mask = 0;
3688 filter_info->dst_port = filter->dst_port;
3691 filter_info->dst_port_mask = 1;
3694 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3698 switch (filter->proto_mask) {
3700 filter_info->proto_mask = 0;
3701 filter_info->proto = filter->proto;
3704 filter_info->proto_mask = 1;
3707 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3711 filter_info->priority = (uint8_t)filter->priority;
3712 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3713 filter_info->tcp_flags = filter->tcp_flags;
3715 filter_info->tcp_flags = 0;
3720 static inline struct e1000_2tuple_filter *
3721 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3722 struct e1000_2tuple_filter_info *key)
3724 struct e1000_2tuple_filter *it;
3726 TAILQ_FOREACH(it, filter_list, entries) {
3727 if (memcmp(key, &it->filter_info,
3728 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3735 /* inject a igb 2tuple filter to HW */
3737 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3738 struct e1000_2tuple_filter *filter)
3740 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3742 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3746 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3747 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3748 imir |= E1000_IMIR_PORT_BP;
3750 imir &= ~E1000_IMIR_PORT_BP;
3752 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3754 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3755 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3756 ttqf |= (uint32_t)(filter->filter_info.proto &
3757 E1000_TTQF_PROTOCOL_MASK);
3758 if (filter->filter_info.proto_mask == 0)
3759 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3761 /* tcp flags bits setting. */
3762 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3763 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3764 imir_ext |= E1000_IMIREXT_CTRL_URG;
3765 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3766 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3767 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3768 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3769 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3770 imir_ext |= E1000_IMIREXT_CTRL_RST;
3771 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3772 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3773 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3774 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3776 imir_ext |= E1000_IMIREXT_CTRL_BP;
3778 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3779 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3780 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3784 * igb_add_2tuple_filter - add a 2tuple filter
3787 * dev: Pointer to struct rte_eth_dev.
3788 * ntuple_filter: ponter to the filter that will be added.
3791 * - On success, zero.
3792 * - On failure, a negative value.
3795 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3796 struct rte_eth_ntuple_filter *ntuple_filter)
3798 struct e1000_filter_info *filter_info =
3799 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3800 struct e1000_2tuple_filter *filter;
3803 filter = rte_zmalloc("e1000_2tuple_filter",
3804 sizeof(struct e1000_2tuple_filter), 0);
3808 ret = ntuple_filter_to_2tuple(ntuple_filter,
3809 &filter->filter_info);
3814 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3815 &filter->filter_info) != NULL) {
3816 PMD_DRV_LOG(ERR, "filter exists.");
3820 filter->queue = ntuple_filter->queue;
3823 * look for an unused 2tuple filter index,
3824 * and insert the filter to list.
3826 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3827 if (!(filter_info->twotuple_mask & (1 << i))) {
3828 filter_info->twotuple_mask |= 1 << i;
3830 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3836 if (i >= E1000_MAX_TTQF_FILTERS) {
3837 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3842 igb_inject_2uple_filter(dev, filter);
3847 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3848 struct e1000_2tuple_filter *filter)
3850 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851 struct e1000_filter_info *filter_info =
3852 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3854 filter_info->twotuple_mask &= ~(1 << filter->index);
3855 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3858 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3859 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3860 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3865 * igb_remove_2tuple_filter - remove a 2tuple filter
3868 * dev: Pointer to struct rte_eth_dev.
3869 * ntuple_filter: ponter to the filter that will be removed.
3872 * - On success, zero.
3873 * - On failure, a negative value.
3876 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3877 struct rte_eth_ntuple_filter *ntuple_filter)
3879 struct e1000_filter_info *filter_info =
3880 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3881 struct e1000_2tuple_filter_info filter_2tuple;
3882 struct e1000_2tuple_filter *filter;
3885 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3886 ret = ntuple_filter_to_2tuple(ntuple_filter,
3891 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3893 if (filter == NULL) {
3894 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3898 igb_delete_2tuple_filter(dev, filter);
3903 /* inject a igb flex filter to HW */
3905 igb_inject_flex_filter(struct rte_eth_dev *dev,
3906 struct e1000_flex_filter *filter)
3908 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3909 uint32_t wufc, queueing;
3913 wufc = E1000_READ_REG(hw, E1000_WUFC);
3914 if (filter->index < E1000_MAX_FHFT)
3915 reg_off = E1000_FHFT(filter->index);
3917 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3919 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3920 (E1000_WUFC_FLX0 << filter->index));
3921 queueing = filter->filter_info.len |
3922 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3923 (filter->filter_info.priority <<
3924 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3925 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3928 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3929 E1000_WRITE_REG(hw, reg_off,
3930 filter->filter_info.dwords[j]);
3931 reg_off += sizeof(uint32_t);
3932 E1000_WRITE_REG(hw, reg_off,
3933 filter->filter_info.dwords[++j]);
3934 reg_off += sizeof(uint32_t);
3935 E1000_WRITE_REG(hw, reg_off,
3936 (uint32_t)filter->filter_info.mask[i]);
3937 reg_off += sizeof(uint32_t) * 2;
3942 static inline struct e1000_flex_filter *
3943 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3944 struct e1000_flex_filter_info *key)
3946 struct e1000_flex_filter *it;
3948 TAILQ_FOREACH(it, filter_list, entries) {
3949 if (memcmp(key, &it->filter_info,
3950 sizeof(struct e1000_flex_filter_info)) == 0)
3957 /* remove a flex byte filter
3959 * dev: Pointer to struct rte_eth_dev.
3960 * filter: the pointer of the filter will be removed.
3963 igb_remove_flex_filter(struct rte_eth_dev *dev,
3964 struct e1000_flex_filter *filter)
3966 struct e1000_filter_info *filter_info =
3967 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3972 wufc = E1000_READ_REG(hw, E1000_WUFC);
3973 if (filter->index < E1000_MAX_FHFT)
3974 reg_off = E1000_FHFT(filter->index);
3976 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3978 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3979 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3981 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3982 (~(E1000_WUFC_FLX0 << filter->index)));
3984 filter_info->flex_mask &= ~(1 << filter->index);
3985 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3990 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3991 struct rte_eth_flex_filter *filter,
3994 struct e1000_filter_info *filter_info =
3995 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3996 struct e1000_flex_filter *flex_filter, *it;
4000 flex_filter = rte_zmalloc("e1000_flex_filter",
4001 sizeof(struct e1000_flex_filter), 0);
4002 if (flex_filter == NULL)
4005 flex_filter->filter_info.len = filter->len;
4006 flex_filter->filter_info.priority = filter->priority;
4007 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4008 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4010 /* reverse bits in flex filter's mask*/
4011 for (shift = 0; shift < CHAR_BIT; shift++) {
4012 if (filter->mask[i] & (0x01 << shift))
4013 mask |= (0x80 >> shift);
4015 flex_filter->filter_info.mask[i] = mask;
4018 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4019 &flex_filter->filter_info);
4020 if (it == NULL && !add) {
4021 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4022 rte_free(flex_filter);
4025 if (it != NULL && add) {
4026 PMD_DRV_LOG(ERR, "filter exists.");
4027 rte_free(flex_filter);
4032 flex_filter->queue = filter->queue;
4034 * look for an unused flex filter index
4035 * and insert the filter into the list.
4037 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4038 if (!(filter_info->flex_mask & (1 << i))) {
4039 filter_info->flex_mask |= 1 << i;
4040 flex_filter->index = i;
4041 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4047 if (i >= E1000_MAX_FLEX_FILTERS) {
4048 PMD_DRV_LOG(ERR, "flex filters are full.");
4049 rte_free(flex_filter);
4053 igb_inject_flex_filter(dev, flex_filter);
4056 igb_remove_flex_filter(dev, it);
4057 rte_free(flex_filter);
4064 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4065 struct rte_eth_flex_filter *filter)
4067 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4068 struct e1000_filter_info *filter_info =
4069 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4070 struct e1000_flex_filter flex_filter, *it;
4071 uint32_t wufc, queueing, wufc_en = 0;
4073 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4074 flex_filter.filter_info.len = filter->len;
4075 flex_filter.filter_info.priority = filter->priority;
4076 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4077 memcpy(flex_filter.filter_info.mask, filter->mask,
4078 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4080 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4081 &flex_filter.filter_info);
4083 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4087 wufc = E1000_READ_REG(hw, E1000_WUFC);
4088 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4090 if ((wufc & wufc_en) == wufc_en) {
4091 uint32_t reg_off = 0;
4092 if (it->index < E1000_MAX_FHFT)
4093 reg_off = E1000_FHFT(it->index);
4095 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4097 queueing = E1000_READ_REG(hw,
4098 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4099 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4100 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4101 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4102 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4103 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4110 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4111 enum rte_filter_op filter_op,
4114 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115 struct rte_eth_flex_filter *filter;
4118 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4120 if (filter_op == RTE_ETH_FILTER_NOP)
4124 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4129 filter = (struct rte_eth_flex_filter *)arg;
4130 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4131 || filter->len % sizeof(uint64_t) != 0) {
4132 PMD_DRV_LOG(ERR, "filter's length is out of range");
4135 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4136 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4140 switch (filter_op) {
4141 case RTE_ETH_FILTER_ADD:
4142 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4144 case RTE_ETH_FILTER_DELETE:
4145 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4147 case RTE_ETH_FILTER_GET:
4148 ret = eth_igb_get_flex_filter(dev, filter);
4151 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4159 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4161 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4162 struct e1000_5tuple_filter_info *filter_info)
4164 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4166 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4167 return -EINVAL; /* filter index is out of range. */
4168 if (filter->tcp_flags > TCP_FLAG_ALL)
4169 return -EINVAL; /* flags is invalid. */
4171 switch (filter->dst_ip_mask) {
4173 filter_info->dst_ip_mask = 0;
4174 filter_info->dst_ip = filter->dst_ip;
4177 filter_info->dst_ip_mask = 1;
4180 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4184 switch (filter->src_ip_mask) {
4186 filter_info->src_ip_mask = 0;
4187 filter_info->src_ip = filter->src_ip;
4190 filter_info->src_ip_mask = 1;
4193 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4197 switch (filter->dst_port_mask) {
4199 filter_info->dst_port_mask = 0;
4200 filter_info->dst_port = filter->dst_port;
4203 filter_info->dst_port_mask = 1;
4206 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4210 switch (filter->src_port_mask) {
4212 filter_info->src_port_mask = 0;
4213 filter_info->src_port = filter->src_port;
4216 filter_info->src_port_mask = 1;
4219 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4223 switch (filter->proto_mask) {
4225 filter_info->proto_mask = 0;
4226 filter_info->proto = filter->proto;
4229 filter_info->proto_mask = 1;
4232 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4236 filter_info->priority = (uint8_t)filter->priority;
4237 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4238 filter_info->tcp_flags = filter->tcp_flags;
4240 filter_info->tcp_flags = 0;
4245 static inline struct e1000_5tuple_filter *
4246 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4247 struct e1000_5tuple_filter_info *key)
4249 struct e1000_5tuple_filter *it;
4251 TAILQ_FOREACH(it, filter_list, entries) {
4252 if (memcmp(key, &it->filter_info,
4253 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4260 /* inject a igb 5-tuple filter to HW */
4262 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4263 struct e1000_5tuple_filter *filter)
4265 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4266 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4267 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4271 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4272 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4273 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4274 if (filter->filter_info.dst_ip_mask == 0)
4275 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4276 if (filter->filter_info.src_port_mask == 0)
4277 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4278 if (filter->filter_info.proto_mask == 0)
4279 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4280 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4281 E1000_FTQF_QUEUE_MASK;
4282 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4283 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4284 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4285 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4287 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4288 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4290 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4291 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4292 imir |= E1000_IMIR_PORT_BP;
4294 imir &= ~E1000_IMIR_PORT_BP;
4295 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4297 /* tcp flags bits setting. */
4298 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4299 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4300 imir_ext |= E1000_IMIREXT_CTRL_URG;
4301 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4302 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4303 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4304 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4305 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4306 imir_ext |= E1000_IMIREXT_CTRL_RST;
4307 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4308 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4309 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4310 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4312 imir_ext |= E1000_IMIREXT_CTRL_BP;
4314 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4315 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4319 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4322 * dev: Pointer to struct rte_eth_dev.
4323 * ntuple_filter: ponter to the filter that will be added.
4326 * - On success, zero.
4327 * - On failure, a negative value.
4330 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4331 struct rte_eth_ntuple_filter *ntuple_filter)
4333 struct e1000_filter_info *filter_info =
4334 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4335 struct e1000_5tuple_filter *filter;
4339 filter = rte_zmalloc("e1000_5tuple_filter",
4340 sizeof(struct e1000_5tuple_filter), 0);
4344 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4345 &filter->filter_info);
4351 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4352 &filter->filter_info) != NULL) {
4353 PMD_DRV_LOG(ERR, "filter exists.");
4357 filter->queue = ntuple_filter->queue;
4360 * look for an unused 5tuple filter index,
4361 * and insert the filter to list.
4363 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4364 if (!(filter_info->fivetuple_mask & (1 << i))) {
4365 filter_info->fivetuple_mask |= 1 << i;
4367 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4373 if (i >= E1000_MAX_FTQF_FILTERS) {
4374 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4379 igb_inject_5tuple_filter_82576(dev, filter);
4384 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4385 struct e1000_5tuple_filter *filter)
4387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4388 struct e1000_filter_info *filter_info =
4389 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4391 filter_info->fivetuple_mask &= ~(1 << filter->index);
4392 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4395 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4396 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4397 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4398 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4399 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4400 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4401 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4406 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4409 * dev: Pointer to struct rte_eth_dev.
4410 * ntuple_filter: ponter to the filter that will be removed.
4413 * - On success, zero.
4414 * - On failure, a negative value.
4417 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4418 struct rte_eth_ntuple_filter *ntuple_filter)
4420 struct e1000_filter_info *filter_info =
4421 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4422 struct e1000_5tuple_filter_info filter_5tuple;
4423 struct e1000_5tuple_filter *filter;
4426 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4427 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4432 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4434 if (filter == NULL) {
4435 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4439 igb_delete_5tuple_filter_82576(dev, filter);
4445 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4448 struct e1000_hw *hw;
4449 struct rte_eth_dev_info dev_info;
4450 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4453 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455 #ifdef RTE_LIBRTE_82571_SUPPORT
4456 /* XXX: not bigger than max_rx_pktlen */
4457 if (hw->mac.type == e1000_82571)
4460 eth_igb_infos_get(dev, &dev_info);
4462 /* check that mtu is within the allowed range */
4463 if ((mtu < ETHER_MIN_MTU) ||
4464 (frame_size > dev_info.max_rx_pktlen))
4467 /* refuse mtu that requires the support of scattered packets when this
4468 * feature has not been enabled before. */
4469 if (!dev->data->scattered_rx &&
4470 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4473 rctl = E1000_READ_REG(hw, E1000_RCTL);
4475 /* switch to jumbo mode if needed */
4476 if (frame_size > ETHER_MAX_LEN) {
4477 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4478 rctl |= E1000_RCTL_LPE;
4480 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4481 rctl &= ~E1000_RCTL_LPE;
4483 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4485 /* update max frame size */
4486 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4488 E1000_WRITE_REG(hw, E1000_RLPML,
4489 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4495 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4498 * dev: Pointer to struct rte_eth_dev.
4499 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4500 * add: if true, add filter, if false, remove filter
4503 * - On success, zero.
4504 * - On failure, a negative value.
4507 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4508 struct rte_eth_ntuple_filter *ntuple_filter,
4511 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4514 switch (ntuple_filter->flags) {
4515 case RTE_5TUPLE_FLAGS:
4516 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4517 if (hw->mac.type != e1000_82576)
4520 ret = igb_add_5tuple_filter_82576(dev,
4523 ret = igb_remove_5tuple_filter_82576(dev,
4526 case RTE_2TUPLE_FLAGS:
4527 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4528 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4529 hw->mac.type != e1000_i210 &&
4530 hw->mac.type != e1000_i211)
4533 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4535 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4546 * igb_get_ntuple_filter - get a ntuple filter
4549 * dev: Pointer to struct rte_eth_dev.
4550 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4553 * - On success, zero.
4554 * - On failure, a negative value.
4557 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4558 struct rte_eth_ntuple_filter *ntuple_filter)
4560 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561 struct e1000_filter_info *filter_info =
4562 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4563 struct e1000_5tuple_filter_info filter_5tuple;
4564 struct e1000_2tuple_filter_info filter_2tuple;
4565 struct e1000_5tuple_filter *p_5tuple_filter;
4566 struct e1000_2tuple_filter *p_2tuple_filter;
4569 switch (ntuple_filter->flags) {
4570 case RTE_5TUPLE_FLAGS:
4571 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4572 if (hw->mac.type != e1000_82576)
4574 memset(&filter_5tuple,
4576 sizeof(struct e1000_5tuple_filter_info));
4577 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4581 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4582 &filter_info->fivetuple_list,
4584 if (p_5tuple_filter == NULL) {
4585 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4588 ntuple_filter->queue = p_5tuple_filter->queue;
4590 case RTE_2TUPLE_FLAGS:
4591 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4592 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4594 memset(&filter_2tuple,
4596 sizeof(struct e1000_2tuple_filter_info));
4597 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4600 p_2tuple_filter = igb_2tuple_filter_lookup(
4601 &filter_info->twotuple_list,
4603 if (p_2tuple_filter == NULL) {
4604 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4607 ntuple_filter->queue = p_2tuple_filter->queue;
4618 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4619 * @dev: pointer to rte_eth_dev structure
4620 * @filter_op:operation will be taken.
4621 * @arg: a pointer to specific structure corresponding to the filter_op
4624 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4625 enum rte_filter_op filter_op,
4628 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631 MAC_TYPE_FILTER_SUP(hw->mac.type);
4633 if (filter_op == RTE_ETH_FILTER_NOP)
4637 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4642 switch (filter_op) {
4643 case RTE_ETH_FILTER_ADD:
4644 ret = igb_add_del_ntuple_filter(dev,
4645 (struct rte_eth_ntuple_filter *)arg,
4648 case RTE_ETH_FILTER_DELETE:
4649 ret = igb_add_del_ntuple_filter(dev,
4650 (struct rte_eth_ntuple_filter *)arg,
4653 case RTE_ETH_FILTER_GET:
4654 ret = igb_get_ntuple_filter(dev,
4655 (struct rte_eth_ntuple_filter *)arg);
4658 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4666 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4671 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4672 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4673 (filter_info->ethertype_mask & (1 << i)))
4680 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4681 uint16_t ethertype, uint32_t etqf)
4685 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4686 if (!(filter_info->ethertype_mask & (1 << i))) {
4687 filter_info->ethertype_mask |= 1 << i;
4688 filter_info->ethertype_filters[i].ethertype = ethertype;
4689 filter_info->ethertype_filters[i].etqf = etqf;
4697 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4700 if (idx >= E1000_MAX_ETQF_FILTERS)
4702 filter_info->ethertype_mask &= ~(1 << idx);
4703 filter_info->ethertype_filters[idx].ethertype = 0;
4704 filter_info->ethertype_filters[idx].etqf = 0;
4710 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4711 struct rte_eth_ethertype_filter *filter,
4714 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4715 struct e1000_filter_info *filter_info =
4716 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4720 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4721 filter->ether_type == ETHER_TYPE_IPv6) {
4722 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4723 " ethertype filter.", filter->ether_type);
4727 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4728 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4731 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4732 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4736 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4737 if (ret >= 0 && add) {
4738 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4739 filter->ether_type);
4742 if (ret < 0 && !add) {
4743 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4744 filter->ether_type);
4749 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4750 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4751 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4752 ret = igb_ethertype_filter_insert(filter_info,
4753 filter->ether_type, etqf);
4755 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4759 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4763 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4764 E1000_WRITE_FLUSH(hw);
4770 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4771 struct rte_eth_ethertype_filter *filter)
4773 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774 struct e1000_filter_info *filter_info =
4775 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4779 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4781 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4782 filter->ether_type);
4786 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4787 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4788 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4790 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4791 E1000_ETQF_QUEUE_SHIFT;
4799 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4800 * @dev: pointer to rte_eth_dev structure
4801 * @filter_op:operation will be taken.
4802 * @arg: a pointer to specific structure corresponding to the filter_op
4805 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4806 enum rte_filter_op filter_op,
4809 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4812 MAC_TYPE_FILTER_SUP(hw->mac.type);
4814 if (filter_op == RTE_ETH_FILTER_NOP)
4818 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4823 switch (filter_op) {
4824 case RTE_ETH_FILTER_ADD:
4825 ret = igb_add_del_ethertype_filter(dev,
4826 (struct rte_eth_ethertype_filter *)arg,
4829 case RTE_ETH_FILTER_DELETE:
4830 ret = igb_add_del_ethertype_filter(dev,
4831 (struct rte_eth_ethertype_filter *)arg,
4834 case RTE_ETH_FILTER_GET:
4835 ret = igb_get_ethertype_filter(dev,
4836 (struct rte_eth_ethertype_filter *)arg);
4839 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4847 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4848 enum rte_filter_type filter_type,
4849 enum rte_filter_op filter_op,
4854 switch (filter_type) {
4855 case RTE_ETH_FILTER_NTUPLE:
4856 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4858 case RTE_ETH_FILTER_ETHERTYPE:
4859 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4861 case RTE_ETH_FILTER_SYN:
4862 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4864 case RTE_ETH_FILTER_FLEXIBLE:
4865 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4867 case RTE_ETH_FILTER_GENERIC:
4868 if (filter_op != RTE_ETH_FILTER_GET)
4870 *(const void **)arg = &igb_flow_ops;
4873 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4882 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4883 struct ether_addr *mc_addr_set,
4884 uint32_t nb_mc_addr)
4886 struct e1000_hw *hw;
4888 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4894 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4896 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897 uint64_t systime_cycles;
4899 switch (hw->mac.type) {
4903 * Need to read System Time Residue Register to be able
4904 * to read the other two registers.
4906 E1000_READ_REG(hw, E1000_SYSTIMR);
4907 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4908 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4909 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4916 * Need to read System Time Residue Register to be able
4917 * to read the other two registers.
4919 E1000_READ_REG(hw, E1000_SYSTIMR);
4920 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4921 /* Only the 8 LSB are valid. */
4922 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4926 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4927 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4932 return systime_cycles;
4936 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4938 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939 uint64_t rx_tstamp_cycles;
4941 switch (hw->mac.type) {
4944 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4945 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4946 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4952 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4953 /* Only the 8 LSB are valid. */
4954 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4958 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4959 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4964 return rx_tstamp_cycles;
4968 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4970 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971 uint64_t tx_tstamp_cycles;
4973 switch (hw->mac.type) {
4976 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4977 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4978 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4984 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4985 /* Only the 8 LSB are valid. */
4986 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4990 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4991 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4996 return tx_tstamp_cycles;
5000 igb_start_timecounters(struct rte_eth_dev *dev)
5002 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5003 struct e1000_adapter *adapter =
5004 (struct e1000_adapter *)dev->data->dev_private;
5005 uint32_t incval = 1;
5007 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5009 switch (hw->mac.type) {
5013 /* 32 LSB bits + 8 MSB bits = 40 bits */
5014 mask = (1ULL << 40) - 1;
5019 * Start incrementing the register
5020 * used to timestamp PTP packets.
5022 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5025 incval = E1000_INCVALUE_82576;
5026 shift = IGB_82576_TSYNC_SHIFT;
5027 E1000_WRITE_REG(hw, E1000_TIMINCA,
5028 E1000_INCPERIOD_82576 | incval);
5035 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5036 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5037 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5039 adapter->systime_tc.cc_mask = mask;
5040 adapter->systime_tc.cc_shift = shift;
5041 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5043 adapter->rx_tstamp_tc.cc_mask = mask;
5044 adapter->rx_tstamp_tc.cc_shift = shift;
5045 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5047 adapter->tx_tstamp_tc.cc_mask = mask;
5048 adapter->tx_tstamp_tc.cc_shift = shift;
5049 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5053 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5055 struct e1000_adapter *adapter =
5056 (struct e1000_adapter *)dev->data->dev_private;
5058 adapter->systime_tc.nsec += delta;
5059 adapter->rx_tstamp_tc.nsec += delta;
5060 adapter->tx_tstamp_tc.nsec += delta;
5066 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5069 struct e1000_adapter *adapter =
5070 (struct e1000_adapter *)dev->data->dev_private;
5072 ns = rte_timespec_to_ns(ts);
5074 /* Set the timecounters to a new value. */
5075 adapter->systime_tc.nsec = ns;
5076 adapter->rx_tstamp_tc.nsec = ns;
5077 adapter->tx_tstamp_tc.nsec = ns;
5083 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5085 uint64_t ns, systime_cycles;
5086 struct e1000_adapter *adapter =
5087 (struct e1000_adapter *)dev->data->dev_private;
5089 systime_cycles = igb_read_systime_cyclecounter(dev);
5090 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5091 *ts = rte_ns_to_timespec(ns);
5097 igb_timesync_enable(struct rte_eth_dev *dev)
5099 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103 /* Stop the timesync system time. */
5104 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5105 /* Reset the timesync system time value. */
5106 switch (hw->mac.type) {
5112 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5115 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5116 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5119 /* Not supported. */
5123 /* Enable system time for it isn't on by default. */
5124 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5125 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5126 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5128 igb_start_timecounters(dev);
5130 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5131 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5133 E1000_ETQF_FILTER_ENABLE |
5136 /* Enable timestamping of received PTP packets. */
5137 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5138 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5139 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5141 /* Enable Timestamping of transmitted PTP packets. */
5142 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5143 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5144 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5150 igb_timesync_disable(struct rte_eth_dev *dev)
5152 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155 /* Disable timestamping of transmitted PTP packets. */
5156 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5157 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5158 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5160 /* Disable timestamping of received PTP packets. */
5161 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5162 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5163 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5165 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5166 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5168 /* Stop incrementating the System Time registers. */
5169 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5175 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5176 struct timespec *timestamp,
5177 uint32_t flags __rte_unused)
5179 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180 struct e1000_adapter *adapter =
5181 (struct e1000_adapter *)dev->data->dev_private;
5182 uint32_t tsync_rxctl;
5183 uint64_t rx_tstamp_cycles;
5186 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5187 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5190 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5191 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5192 *timestamp = rte_ns_to_timespec(ns);
5198 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5199 struct timespec *timestamp)
5201 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202 struct e1000_adapter *adapter =
5203 (struct e1000_adapter *)dev->data->dev_private;
5204 uint32_t tsync_txctl;
5205 uint64_t tx_tstamp_cycles;
5208 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5209 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5212 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5213 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5214 *timestamp = rte_ns_to_timespec(ns);
5220 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5224 const struct reg_info *reg_group;
5226 while ((reg_group = igb_regs[g_ind++]))
5227 count += igb_reg_group_count(reg_group);
5233 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5237 const struct reg_info *reg_group;
5239 while ((reg_group = igbvf_regs[g_ind++]))
5240 count += igb_reg_group_count(reg_group);
5246 eth_igb_get_regs(struct rte_eth_dev *dev,
5247 struct rte_dev_reg_info *regs)
5249 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250 uint32_t *data = regs->data;
5253 const struct reg_info *reg_group;
5256 regs->length = eth_igb_get_reg_length(dev);
5257 regs->width = sizeof(uint32_t);
5261 /* Support only full register dump */
5262 if ((regs->length == 0) ||
5263 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5264 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5266 while ((reg_group = igb_regs[g_ind++]))
5267 count += igb_read_regs_group(dev, &data[count],
5276 igbvf_get_regs(struct rte_eth_dev *dev,
5277 struct rte_dev_reg_info *regs)
5279 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5280 uint32_t *data = regs->data;
5283 const struct reg_info *reg_group;
5286 regs->length = igbvf_get_reg_length(dev);
5287 regs->width = sizeof(uint32_t);
5291 /* Support only full register dump */
5292 if ((regs->length == 0) ||
5293 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5294 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5296 while ((reg_group = igbvf_regs[g_ind++]))
5297 count += igb_read_regs_group(dev, &data[count],
5306 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5308 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5310 /* Return unit is byte count */
5311 return hw->nvm.word_size * 2;
5315 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5316 struct rte_dev_eeprom_info *in_eeprom)
5318 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5319 struct e1000_nvm_info *nvm = &hw->nvm;
5320 uint16_t *data = in_eeprom->data;
5323 first = in_eeprom->offset >> 1;
5324 length = in_eeprom->length >> 1;
5325 if ((first >= hw->nvm.word_size) ||
5326 ((first + length) >= hw->nvm.word_size))
5329 in_eeprom->magic = hw->vendor_id |
5330 ((uint32_t)hw->device_id << 16);
5332 if ((nvm->ops.read) == NULL)
5335 return nvm->ops.read(hw, first, length, data);
5339 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5340 struct rte_dev_eeprom_info *in_eeprom)
5342 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5343 struct e1000_nvm_info *nvm = &hw->nvm;
5344 uint16_t *data = in_eeprom->data;
5347 first = in_eeprom->offset >> 1;
5348 length = in_eeprom->length >> 1;
5349 if ((first >= hw->nvm.word_size) ||
5350 ((first + length) >= hw->nvm.word_size))
5353 in_eeprom->magic = (uint32_t)hw->vendor_id |
5354 ((uint32_t)hw->device_id << 16);
5356 if ((nvm->ops.write) == NULL)
5358 return nvm->ops.write(hw, first, length, data);
5362 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5364 struct e1000_hw *hw =
5365 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5366 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5367 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5368 uint32_t vec = E1000_MISC_VEC_ID;
5370 if (rte_intr_allow_others(intr_handle))
5371 vec = E1000_RX_VEC_START;
5373 uint32_t mask = 1 << (queue_id + vec);
5375 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5376 E1000_WRITE_FLUSH(hw);
5382 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5384 struct e1000_hw *hw =
5385 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5386 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5388 uint32_t vec = E1000_MISC_VEC_ID;
5390 if (rte_intr_allow_others(intr_handle))
5391 vec = E1000_RX_VEC_START;
5393 uint32_t mask = 1 << (queue_id + vec);
5396 regval = E1000_READ_REG(hw, E1000_EIMS);
5397 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5398 E1000_WRITE_FLUSH(hw);
5400 rte_intr_enable(intr_handle);
5406 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5407 uint8_t index, uint8_t offset)
5409 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5412 val &= ~((uint32_t)0xFF << offset);
5414 /* write vector and valid bit */
5415 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5417 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5421 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5422 uint8_t queue, uint8_t msix_vector)
5426 if (hw->mac.type == e1000_82575) {
5428 tmp = E1000_EICR_RX_QUEUE0 << queue;
5429 else if (direction == 1)
5430 tmp = E1000_EICR_TX_QUEUE0 << queue;
5431 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5432 } else if (hw->mac.type == e1000_82576) {
5433 if ((direction == 0) || (direction == 1))
5434 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5435 ((queue & 0x8) << 1) +
5437 } else if ((hw->mac.type == e1000_82580) ||
5438 (hw->mac.type == e1000_i350) ||
5439 (hw->mac.type == e1000_i354) ||
5440 (hw->mac.type == e1000_i210) ||
5441 (hw->mac.type == e1000_i211)) {
5442 if ((direction == 0) || (direction == 1))
5443 eth_igb_write_ivar(hw, msix_vector,
5445 ((queue & 0x1) << 4) +
5450 /* Sets up the hardware to generate MSI-X interrupts properly
5452 * board private structure
5455 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5458 uint32_t tmpval, regval, intr_mask;
5459 struct e1000_hw *hw =
5460 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5461 uint32_t vec = E1000_MISC_VEC_ID;
5462 uint32_t base = E1000_MISC_VEC_ID;
5463 uint32_t misc_shift = 0;
5464 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5465 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5467 /* won't configure msix register if no mapping is done
5468 * between intr vector and event fd
5470 if (!rte_intr_dp_is_en(intr_handle))
5473 if (rte_intr_allow_others(intr_handle)) {
5474 vec = base = E1000_RX_VEC_START;
5478 /* set interrupt vector for other causes */
5479 if (hw->mac.type == e1000_82575) {
5480 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5481 /* enable MSI-X PBA support */
5482 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5484 /* Auto-Mask interrupts upon ICR read */
5485 tmpval |= E1000_CTRL_EXT_EIAME;
5486 tmpval |= E1000_CTRL_EXT_IRCA;
5488 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5490 /* enable msix_other interrupt */
5491 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5492 regval = E1000_READ_REG(hw, E1000_EIAC);
5493 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5494 regval = E1000_READ_REG(hw, E1000_EIAM);
5495 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5496 } else if ((hw->mac.type == e1000_82576) ||
5497 (hw->mac.type == e1000_82580) ||
5498 (hw->mac.type == e1000_i350) ||
5499 (hw->mac.type == e1000_i354) ||
5500 (hw->mac.type == e1000_i210) ||
5501 (hw->mac.type == e1000_i211)) {
5502 /* turn on MSI-X capability first */
5503 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5504 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5506 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5508 regval = E1000_READ_REG(hw, E1000_EIAC);
5509 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5511 /* enable msix_other interrupt */
5512 regval = E1000_READ_REG(hw, E1000_EIMS);
5513 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5514 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5515 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5518 /* use EIAM to auto-mask when MSI-X interrupt
5519 * is asserted, this saves a register write for every interrupt
5521 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5523 regval = E1000_READ_REG(hw, E1000_EIAM);
5524 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5526 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5527 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5528 intr_handle->intr_vec[queue_id] = vec;
5529 if (vec < base + intr_handle->nb_efd - 1)
5533 E1000_WRITE_FLUSH(hw);
5536 /* restore n-tuple filter */
5538 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5540 struct e1000_filter_info *filter_info =
5541 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5542 struct e1000_5tuple_filter *p_5tuple;
5543 struct e1000_2tuple_filter *p_2tuple;
5545 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5546 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5549 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5550 igb_inject_2uple_filter(dev, p_2tuple);
5554 /* restore SYN filter */
5556 igb_syn_filter_restore(struct rte_eth_dev *dev)
5558 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5559 struct e1000_filter_info *filter_info =
5560 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5563 synqf = filter_info->syn_info;
5565 if (synqf & E1000_SYN_FILTER_ENABLE) {
5566 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5567 E1000_WRITE_FLUSH(hw);
5571 /* restore ethernet type filter */
5573 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5575 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5576 struct e1000_filter_info *filter_info =
5577 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5580 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5581 if (filter_info->ethertype_mask & (1 << i)) {
5582 E1000_WRITE_REG(hw, E1000_ETQF(i),
5583 filter_info->ethertype_filters[i].etqf);
5584 E1000_WRITE_FLUSH(hw);
5589 /* restore flex byte filter */
5591 igb_flex_filter_restore(struct rte_eth_dev *dev)
5593 struct e1000_filter_info *filter_info =
5594 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5595 struct e1000_flex_filter *flex_filter;
5597 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5598 igb_inject_flex_filter(dev, flex_filter);
5602 /* restore all types filter */
5604 igb_filter_restore(struct rte_eth_dev *dev)
5606 igb_ntuple_filter_restore(dev);
5607 igb_ethertype_filter_restore(dev);
5608 igb_syn_filter_restore(dev);
5609 igb_flex_filter_restore(dev);
5614 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5615 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5616 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5617 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5618 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5619 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");