drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  86
  87 static int  eth_igb_configure(struct rte_eth_dev *dev);
  88 static int  eth_igb_start(struct rte_eth_dev *dev);
  89 static void eth_igb_stop(struct rte_eth_dev *dev);
  90 static void eth_igb_close(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  95 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  96                                 int wait_to_complete);
  97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  98                                 struct rte_eth_stats *rte_stats);
  99 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 100                               struct rte_eth_xstats *xstats, unsigned n);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 104                               struct rte_eth_dev_info *dev_info);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 115 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 116                                                         void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129
 130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 136
 137 static int eth_igb_led_on(struct rte_eth_dev *dev);
 138 static int eth_igb_led_off(struct rte_eth_dev *dev);
 139
 140 static void igb_intr_disable(struct e1000_hw *hw);
 141 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 142 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 143                 struct ether_addr *mac_addr,
 144                 uint32_t index, uint32_t pool);
 145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 146 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 147                 struct ether_addr *addr);
 148
 149 static void igbvf_intr_disable(struct e1000_hw *hw);
 150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 151 static int igbvf_dev_start(struct rte_eth_dev *dev);
 152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 153 static void igbvf_dev_close(struct rte_eth_dev *dev);
 154 static int eth_igbvf_link_update(struct e1000_hw *hw);
 155 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *rte_stats);
 157 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstats *xstats, unsigned n);
 159 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 160 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 161                 uint16_t vlan_id, int on);
 162 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 163 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 164 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 165                 struct ether_addr *addr);
 166 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 167 static int igbvf_get_regs(struct rte_eth_dev *dev,
 168                 struct rte_dev_reg_info *regs);
 169
 170 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 171                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 172                                    uint16_t reta_size);
 173 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 174                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 175                                   uint16_t reta_size);
 176
 177 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 178                         struct rte_eth_syn_filter *filter,
 179                         bool add);
 180 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 181                         struct rte_eth_syn_filter *filter);
 182 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 183                         enum rte_filter_op filter_op,
 184                         void *arg);
 185 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 186                         struct rte_eth_ntuple_filter *ntuple_filter);
 187 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 188                         struct rte_eth_ntuple_filter *ntuple_filter);
 189 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_flex_filter *filter,
 191                         bool add);
 192 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_flex_filter *filter);
 194 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 195                         enum rte_filter_op filter_op,
 196                         void *arg);
 197 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 198                         struct rte_eth_ntuple_filter *ntuple_filter);
 199 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 200                         struct rte_eth_ntuple_filter *ntuple_filter);
 201 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_ntuple_filter *filter,
 203                         bool add);
 204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *filter);
 206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 210                         struct rte_eth_ethertype_filter *filter,
 211                         bool add);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 230                                     struct ether_addr *mc_addr_set,
 231                                     uint32_t nb_mc_addr);
 232 static int igb_timesync_enable(struct rte_eth_dev *dev);
 233 static int igb_timesync_disable(struct rte_eth_dev *dev);
 234 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp,
 236                                           uint32_t flags);
 237 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 238                                           struct timespec *timestamp);
 239 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 240                                         uint16_t queue_id);
 241 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 242                                          uint16_t queue_id);
 243 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 244                                        uint8_t queue, uint8_t msix_vector);
 245 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 246                                uint8_t index, uint8_t offset);
 247 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 248
 249 /*
 250  * Define VF Stats MACRO for Non "cleared on read" register
 251  */
 252 #define UPDATE_VF_STAT(reg, last, cur)            \
 253 {                                                 \
 254         u32 latest = E1000_READ_REG(hw, reg);     \
 255         cur += (latest - last) & UINT_MAX;        \
 256         last = latest;                            \
 257 }
 258
 259 #define IGB_FC_PAUSE_TIME 0x0680
 260 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 261 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 262
 263 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 264
 265 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 266
 267 /*
 268  * The set of PCI devices this driver supports
 269  */
 270 static const struct rte_pci_id pci_id_igb_map[] = {
 271
 272 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 273 #include "rte_pci_dev_ids.h"
 274
 275 {0},
 276 };
 277
 278 /*
 279  * The set of PCI devices this driver supports (for 82576&I350 VF)
 280  */
 281 static const struct rte_pci_id pci_id_igbvf_map[] = {
 282
 283 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 284 #include "rte_pci_dev_ids.h"
 285
 286 {0},
 287 };
 288
 289 static const struct rte_eth_desc_lim rx_desc_lim = {
 290         .nb_max = E1000_MAX_RING_DESC,
 291         .nb_min = E1000_MIN_RING_DESC,
 292         .nb_align = IGB_RXD_ALIGN,
 293 };
 294
 295 static const struct rte_eth_desc_lim tx_desc_lim = {
 296         .nb_max = E1000_MAX_RING_DESC,
 297         .nb_min = E1000_MIN_RING_DESC,
 298         .nb_align = IGB_RXD_ALIGN,
 299 };
 300
 301 static const struct eth_dev_ops eth_igb_ops = {
 302         .dev_configure        = eth_igb_configure,
 303         .dev_start            = eth_igb_start,
 304         .dev_stop             = eth_igb_stop,
 305         .dev_close            = eth_igb_close,
 306         .promiscuous_enable   = eth_igb_promiscuous_enable,
 307         .promiscuous_disable  = eth_igb_promiscuous_disable,
 308         .allmulticast_enable  = eth_igb_allmulticast_enable,
 309         .allmulticast_disable = eth_igb_allmulticast_disable,
 310         .link_update          = eth_igb_link_update,
 311         .stats_get            = eth_igb_stats_get,
 312         .xstats_get           = eth_igb_xstats_get,
 313         .stats_reset          = eth_igb_stats_reset,
 314         .xstats_reset         = eth_igb_xstats_reset,
 315         .dev_infos_get        = eth_igb_infos_get,
 316         .mtu_set              = eth_igb_mtu_set,
 317         .vlan_filter_set      = eth_igb_vlan_filter_set,
 318         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 319         .vlan_offload_set     = eth_igb_vlan_offload_set,
 320         .rx_queue_setup       = eth_igb_rx_queue_setup,
 321         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 322         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 323         .rx_queue_release     = eth_igb_rx_queue_release,
 324         .rx_queue_count       = eth_igb_rx_queue_count,
 325         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 326         .tx_queue_setup       = eth_igb_tx_queue_setup,
 327         .tx_queue_release     = eth_igb_tx_queue_release,
 328         .dev_led_on           = eth_igb_led_on,
 329         .dev_led_off          = eth_igb_led_off,
 330         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 331         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 332         .mac_addr_add         = eth_igb_rar_set,
 333         .mac_addr_remove      = eth_igb_rar_clear,
 334         .mac_addr_set         = eth_igb_default_mac_addr_set,
 335         .reta_update          = eth_igb_rss_reta_update,
 336         .reta_query           = eth_igb_rss_reta_query,
 337         .rss_hash_update      = eth_igb_rss_hash_update,
 338         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 339         .filter_ctrl          = eth_igb_filter_ctrl,
 340         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 341         .rxq_info_get         = igb_rxq_info_get,
 342         .txq_info_get         = igb_txq_info_get,
 343         .timesync_enable      = igb_timesync_enable,
 344         .timesync_disable     = igb_timesync_disable,
 345         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 346         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 347         .get_reg_length       = eth_igb_get_reg_length,
 348         .get_reg              = eth_igb_get_regs,
 349         .get_eeprom_length    = eth_igb_get_eeprom_length,
 350         .get_eeprom           = eth_igb_get_eeprom,
 351         .set_eeprom           = eth_igb_set_eeprom,
 352 };
 353
 354 /*
 355  * dev_ops for virtual function, bare necessities for basic vf
 356  * operation have been implemented
 357  */
 358 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 359         .dev_configure        = igbvf_dev_configure,
 360         .dev_start            = igbvf_dev_start,
 361         .dev_stop             = igbvf_dev_stop,
 362         .dev_close            = igbvf_dev_close,
 363         .link_update          = eth_igb_link_update,
 364         .stats_get            = eth_igbvf_stats_get,
 365         .xstats_get           = eth_igbvf_xstats_get,
 366         .stats_reset          = eth_igbvf_stats_reset,
 367         .xstats_reset         = eth_igbvf_stats_reset,
 368         .vlan_filter_set      = igbvf_vlan_filter_set,
 369         .dev_infos_get        = eth_igbvf_infos_get,
 370         .rx_queue_setup       = eth_igb_rx_queue_setup,
 371         .rx_queue_release     = eth_igb_rx_queue_release,
 372         .tx_queue_setup       = eth_igb_tx_queue_setup,
 373         .tx_queue_release     = eth_igb_tx_queue_release,
 374         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 375         .rxq_info_get         = igb_rxq_info_get,
 376         .txq_info_get         = igb_txq_info_get,
 377         .mac_addr_set         = igbvf_default_mac_addr_set,
 378         .get_reg_length       = igbvf_get_reg_length,
 379         .get_reg              = igbvf_get_regs,
 380 };
 381
 382 /* store statistics names and its offset in stats structure */
 383 struct rte_igb_xstats_name_off {
 384         char name[RTE_ETH_XSTATS_NAME_SIZE];
 385         unsigned offset;
 386 };
 387
 388 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 389         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 390         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 391         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 392         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 393         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 394         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 395         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 396                 ecol)},
 397         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 398         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 399         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 400         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 401         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 402         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 403         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 404         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 405         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 406         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 407         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 408                 fcruc)},
 409         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 410         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 411         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 412         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 413         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 414                 prc1023)},
 415         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 416                 prc1522)},
 417         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 418         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 419         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 420         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 421         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 422         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 423         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 424         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 425         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 426         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 427         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 428         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 429         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 430         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 431         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 432         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 433         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 434         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 435                 ptc1023)},
 436         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 437                 ptc1522)},
 438         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 439         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 440         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 441         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 442         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 443         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 444         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 445
 446         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 447 };
 448
 449 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 450                 sizeof(rte_igb_stats_strings[0]))
 451
 452 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 453         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 454         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 455         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 456         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 457         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 458 };
 459
 460 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 461                 sizeof(rte_igbvf_stats_strings[0]))
 462
 463 /**
 464  * Atomically reads the link status information from global
 465  * structure rte_eth_dev.
 466  *
 467  * @param dev
 468  *   - Pointer to the structure rte_eth_dev to read from.
 469  *   - Pointer to the buffer to be saved with the link status.
 470  *
 471  * @return
 472  *   - On success, zero.
 473  *   - On failure, negative value.
 474  */
 475 static inline int
 476 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 477                                 struct rte_eth_link *link)
 478 {
 479         struct rte_eth_link *dst = link;
 480         struct rte_eth_link *src = &(dev->data->dev_link);
 481
 482         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 483                                         *(uint64_t *)src) == 0)
 484                 return -1;
 485
 486         return 0;
 487 }
 488
 489 /**
 490  * Atomically writes the link status information into global
 491  * structure rte_eth_dev.
 492  *
 493  * @param dev
 494  *   - Pointer to the structure rte_eth_dev to read from.
 495  *   - Pointer to the buffer to be saved with the link status.
 496  *
 497  * @return
 498  *   - On success, zero.
 499  *   - On failure, negative value.
 500  */
 501 static inline int
 502 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 503                                 struct rte_eth_link *link)
 504 {
 505         struct rte_eth_link *dst = &(dev->data->dev_link);
 506         struct rte_eth_link *src = link;
 507
 508         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 509                                         *(uint64_t *)src) == 0)
 510                 return -1;
 511
 512         return 0;
 513 }
 514
 515 static inline void
 516 igb_intr_enable(struct rte_eth_dev *dev)
 517 {
 518         struct e1000_interrupt *intr =
 519                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 520         struct e1000_hw *hw =
 521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 522
 523         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 524         E1000_WRITE_FLUSH(hw);
 525 }
 526
 527 static void
 528 igb_intr_disable(struct e1000_hw *hw)
 529 {
 530         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 531         E1000_WRITE_FLUSH(hw);
 532 }
 533
 534 static inline int32_t
 535 igb_pf_reset_hw(struct e1000_hw *hw)
 536 {
 537         uint32_t ctrl_ext;
 538         int32_t status;
 539
 540         status = e1000_reset_hw(hw);
 541
 542         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 543         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 544         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 545         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 546         E1000_WRITE_FLUSH(hw);
 547
 548         return status;
 549 }
 550
 551 static void
 552 igb_identify_hardware(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556
 557         hw->vendor_id = dev->pci_dev->id.vendor_id;
 558         hw->device_id = dev->pci_dev->id.device_id;
 559         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 560         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 561
 562         e1000_set_mac_type(hw);
 563
 564         /* need to check if it is a vf device below */
 565 }
 566
 567 static int
 568 igb_reset_swfw_lock(struct e1000_hw *hw)
 569 {
 570         int ret_val;
 571
 572         /*
 573          * Do mac ops initialization manually here, since we will need
 574          * some function pointers set by this call.
 575          */
 576         ret_val = e1000_init_mac_params(hw);
 577         if (ret_val)
 578                 return ret_val;
 579
 580         /*
 581          * SMBI lock should not fail in this early stage. If this is the case,
 582          * it is due to an improper exit of the application.
 583          * So force the release of the faulty lock.
 584          */
 585         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 586                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 587         }
 588         e1000_put_hw_semaphore_generic(hw);
 589
 590         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 591                 uint16_t mask;
 592
 593                 /*
 594                  * Phy lock should not fail in this early stage. If this is the case,
 595                  * it is due to an improper exit of the application.
 596                  * So force the release of the faulty lock.
 597                  */
 598                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 599                 if (hw->bus.func > E1000_FUNC_1)
 600                         mask <<= 2;
 601                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 602                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 603                                     hw->bus.func);
 604                 }
 605                 hw->mac.ops.release_swfw_sync(hw, mask);
 606
 607                 /*
 608                  * This one is more tricky since it is common to all ports; but
 609                  * swfw_sync retries last long enough (1s) to be almost sure that if
 610                  * lock can not be taken it is due to an improper lock of the
 611                  * semaphore.
 612                  */
 613                 mask = E1000_SWFW_EEP_SM;
 614                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 615                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 616                 }
 617                 hw->mac.ops.release_swfw_sync(hw, mask);
 618         }
 619
 620         return E1000_SUCCESS;
 621 }
 622
 623 static int
 624 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 625 {
 626         int error = 0;
 627         struct rte_pci_device *pci_dev;
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 630         struct e1000_vfta * shadow_vfta =
 631                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 632         struct e1000_filter_info *filter_info =
 633                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 634         struct e1000_adapter *adapter =
 635                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 636
 637         uint32_t ctrl_ext;
 638
 639         pci_dev = eth_dev->pci_dev;
 640
 641         rte_eth_copy_pci_info(eth_dev, pci_dev);
 642
 643         eth_dev->dev_ops = &eth_igb_ops;
 644         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 645         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 646
 647         /* for secondary processes, we don't initialise any further as primary
 648          * has already done this work. Only check we don't need a different
 649          * RX function */
 650         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 651                 if (eth_dev->data->scattered_rx)
 652                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 653                 return 0;
 654         }
 655
 656         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 657
 658         igb_identify_hardware(eth_dev);
 659         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 660                 error = -EIO;
 661                 goto err_late;
 662         }
 663
 664         e1000_get_bus_info(hw);
 665
 666         /* Reset any pending lock */
 667         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 668                 error = -EIO;
 669                 goto err_late;
 670         }
 671
 672         /* Finish initialization */
 673         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 674                 error = -EIO;
 675                 goto err_late;
 676         }
 677
 678         hw->mac.autoneg = 1;
 679         hw->phy.autoneg_wait_to_complete = 0;
 680         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 681
 682         /* Copper options */
 683         if (hw->phy.media_type == e1000_media_type_copper) {
 684                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 685                 hw->phy.disable_polarity_correction = 0;
 686                 hw->phy.ms_type = e1000_ms_hw_default;
 687         }
 688
 689         /*
 690          * Start from a known state, this is important in reading the nvm
 691          * and mac from that.
 692          */
 693         igb_pf_reset_hw(hw);
 694
 695         /* Make sure we have a good EEPROM before we read from it */
 696         if (e1000_validate_nvm_checksum(hw) < 0) {
 697                 /*
 698                  * Some PCI-E parts fail the first check due to
 699                  * the link being in sleep state, call it again,
 700                  * if it fails a second time its a real issue.
 701                  */
 702                 if (e1000_validate_nvm_checksum(hw) < 0) {
 703                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 704                         error = -EIO;
 705                         goto err_late;
 706                 }
 707         }
 708
 709         /* Read the permanent MAC address out of the EEPROM */
 710         if (e1000_read_mac_addr(hw) != 0) {
 711                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 712                 error = -EIO;
 713                 goto err_late;
 714         }
 715
 716         /* Allocate memory for storing MAC addresses */
 717         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 718                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 719         if (eth_dev->data->mac_addrs == NULL) {
 720                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 721                                                 "store MAC addresses",
 722                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 723                 error = -ENOMEM;
 724                 goto err_late;
 725         }
 726
 727         /* Copy the permanent MAC address */
 728         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 729
 730         /* initialize the vfta */
 731         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 732
 733         /* Now initialize the hardware */
 734         if (igb_hardware_init(hw) != 0) {
 735                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 736                 rte_free(eth_dev->data->mac_addrs);
 737                 eth_dev->data->mac_addrs = NULL;
 738                 error = -ENODEV;
 739                 goto err_late;
 740         }
 741         hw->mac.get_link_status = 1;
 742         adapter->stopped = 0;
 743
 744         /* Indicate SOL/IDER usage */
 745         if (e1000_check_reset_block(hw) < 0) {
 746                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 747                                         "SOL/IDER session");
 748         }
 749
 750         /* initialize PF if max_vfs not zero */
 751         igb_pf_host_init(eth_dev);
 752
 753         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 754         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 755         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 756         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 757         E1000_WRITE_FLUSH(hw);
 758
 759         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 760                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 761                      pci_dev->id.device_id);
 762
 763         rte_intr_callback_register(&pci_dev->intr_handle,
 764                                    eth_igb_interrupt_handler,
 765                                    (void *)eth_dev);
 766
 767         /* enable uio/vfio intr/eventfd mapping */
 768         rte_intr_enable(&pci_dev->intr_handle);
 769
 770         /* enable support intr */
 771         igb_intr_enable(eth_dev);
 772
 773         TAILQ_INIT(&filter_info->flex_list);
 774         filter_info->flex_mask = 0;
 775         TAILQ_INIT(&filter_info->twotuple_list);
 776         filter_info->twotuple_mask = 0;
 777         TAILQ_INIT(&filter_info->fivetuple_list);
 778         filter_info->fivetuple_mask = 0;
 779
 780         return 0;
 781
 782 err_late:
 783         igb_hw_control_release(hw);
 784
 785         return (error);
 786 }
 787
 788 static int
 789 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 790 {
 791         struct rte_pci_device *pci_dev;
 792         struct e1000_hw *hw;
 793         struct e1000_adapter *adapter =
 794                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 795
 796         PMD_INIT_FUNC_TRACE();
 797
 798         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 799                 return -EPERM;
 800
 801         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 802         pci_dev = eth_dev->pci_dev;
 803
 804         if (adapter->stopped == 0)
 805                 eth_igb_close(eth_dev);
 806
 807         eth_dev->dev_ops = NULL;
 808         eth_dev->rx_pkt_burst = NULL;
 809         eth_dev->tx_pkt_burst = NULL;
 810
 811         /* Reset any pending lock */
 812         igb_reset_swfw_lock(hw);
 813
 814         rte_free(eth_dev->data->mac_addrs);
 815         eth_dev->data->mac_addrs = NULL;
 816
 817         /* uninitialize PF if max_vfs not zero */
 818         igb_pf_host_uninit(eth_dev);
 819
 820         /* disable uio intr before callback unregister */
 821         rte_intr_disable(&(pci_dev->intr_handle));
 822         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 823                 eth_igb_interrupt_handler, (void *)eth_dev);
 824
 825         return 0;
 826 }
 827
 828 /*
 829  * Virtual Function device init
 830  */
 831 static int
 832 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 833 {
 834         struct rte_pci_device *pci_dev;
 835         struct e1000_adapter *adapter =
 836                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 837         struct e1000_hw *hw =
 838                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 839         int diag;
 840
 841         PMD_INIT_FUNC_TRACE();
 842
 843         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 844         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 845         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 846
 847         /* for secondary processes, we don't initialise any further as primary
 848          * has already done this work. Only check we don't need a different
 849          * RX function */
 850         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 851                 if (eth_dev->data->scattered_rx)
 852                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 853                 return 0;
 854         }
 855
 856         pci_dev = eth_dev->pci_dev;
 857
 858         rte_eth_copy_pci_info(eth_dev, pci_dev);
 859
 860         hw->device_id = pci_dev->id.device_id;
 861         hw->vendor_id = pci_dev->id.vendor_id;
 862         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 863         adapter->stopped = 0;
 864
 865         /* Initialize the shared code (base driver) */
 866         diag = e1000_setup_init_funcs(hw, TRUE);
 867         if (diag != 0) {
 868                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 869                         diag);
 870                 return -EIO;
 871         }
 872
 873         /* init_mailbox_params */
 874         hw->mbx.ops.init_params(hw);
 875
 876         /* Disable the interrupts for VF */
 877         igbvf_intr_disable(hw);
 878
 879         diag = hw->mac.ops.reset_hw(hw);
 880
 881         /* Allocate memory for storing MAC addresses */
 882         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 883                 hw->mac.rar_entry_count, 0);
 884         if (eth_dev->data->mac_addrs == NULL) {
 885                 PMD_INIT_LOG(ERR,
 886                         "Failed to allocate %d bytes needed to store MAC "
 887                         "addresses",
 888                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 889                 return -ENOMEM;
 890         }
 891
 892         /* Copy the permanent MAC address */
 893         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 894                         &eth_dev->data->mac_addrs[0]);
 895
 896         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 897                      "mac.type=%s",
 898                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 899                      pci_dev->id.device_id, "igb_mac_82576_vf");
 900
 901         return 0;
 902 }
 903
 904 static int
 905 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 906 {
 907         struct e1000_adapter *adapter =
 908                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 909
 910         PMD_INIT_FUNC_TRACE();
 911
 912         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 913                 return -EPERM;
 914
 915         if (adapter->stopped == 0)
 916                 igbvf_dev_close(eth_dev);
 917
 918         eth_dev->dev_ops = NULL;
 919         eth_dev->rx_pkt_burst = NULL;
 920         eth_dev->tx_pkt_burst = NULL;
 921
 922         rte_free(eth_dev->data->mac_addrs);
 923         eth_dev->data->mac_addrs = NULL;
 924
 925         return 0;
 926 }
 927
 928 static struct eth_driver rte_igb_pmd = {
 929         .pci_drv = {
 930                 .name = "rte_igb_pmd",
 931                 .id_table = pci_id_igb_map,
 932                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 933                         RTE_PCI_DRV_DETACHABLE,
 934         },
 935         .eth_dev_init = eth_igb_dev_init,
 936         .eth_dev_uninit = eth_igb_dev_uninit,
 937         .dev_private_size = sizeof(struct e1000_adapter),
 938 };
 939
 940 /*
 941  * virtual function driver struct
 942  */
 943 static struct eth_driver rte_igbvf_pmd = {
 944         .pci_drv = {
 945                 .name = "rte_igbvf_pmd",
 946                 .id_table = pci_id_igbvf_map,
 947                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 948         },
 949         .eth_dev_init = eth_igbvf_dev_init,
 950         .eth_dev_uninit = eth_igbvf_dev_uninit,
 951         .dev_private_size = sizeof(struct e1000_adapter),
 952 };
 953
 954 static int
 955 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 956 {
 957         rte_eth_driver_register(&rte_igb_pmd);
 958         return 0;
 959 }
 960
 961 static void
 962 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 963 {
 964         struct e1000_hw *hw =
 965                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 967         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 968         rctl |= E1000_RCTL_VFE;
 969         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 970 }
 971
 972 /*
 973  * VF Driver initialization routine.
 974  * Invoked one at EAL init time.
 975  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 976  */
 977 static int
 978 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 979 {
 980         PMD_INIT_FUNC_TRACE();
 981
 982         rte_eth_driver_register(&rte_igbvf_pmd);
 983         return (0);
 984 }
 985
 986 static int
 987 igb_check_mq_mode(struct rte_eth_dev *dev)
 988 {
 989         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 990         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 991         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 992         uint16_t nb_tx_q = dev->data->nb_rx_queues;
 993
 994         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
 995             tx_mq_mode == ETH_MQ_TX_DCB ||
 996             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
 997                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 998                 return -EINVAL;
 999         }
1000         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1001                 /* Check multi-queue mode.
1002                  * To no break software we accept ETH_MQ_RX_NONE as this might
1003                  * be used to turn off VLAN filter.
1004                  */
1005
1006                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1007                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1008                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1009                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1010                 } else {
1011                         /* Only support one queue on VFs.
1012                          * RSS together with SRIOV is not supported.
1013                          */
1014                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1015                                         " wrong mq_mode rx %d.",
1016                                         rx_mq_mode);
1017                         return -EINVAL;
1018                 }
1019                 /* TX mode is not used here, so mode might be ignored.*/
1020                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1021                         /* SRIOV only works in VMDq enable mode */
1022                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1023                                         " TX mode %d is not supported. "
1024                                         " Driver will behave as %d mode.",
1025                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1026                 }
1027
1028                 /* check valid queue number */
1029                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1030                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1031                                         " only support one queue on VFs.");
1032                         return -EINVAL;
1033                 }
1034         } else {
1035                 /* To no break software that set invalid mode, only display
1036                  * warning if invalid mode is used.
1037                  */
1038                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1039                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1040                     rx_mq_mode != ETH_MQ_RX_RSS) {
1041                         /* RSS together with VMDq not supported*/
1042                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1043                                      rx_mq_mode);
1044                         return -EINVAL;
1045                 }
1046
1047                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1048                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1049                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1050                                         " Due to txmode is meaningless in this"
1051                                         " driver, just ignore.",
1052                                         tx_mq_mode);
1053                 }
1054         }
1055         return 0;
1056 }
1057
1058 static int
1059 eth_igb_configure(struct rte_eth_dev *dev)
1060 {
1061         struct e1000_interrupt *intr =
1062                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1063         int ret;
1064
1065         PMD_INIT_FUNC_TRACE();
1066
1067         /* multipe queue mode checking */
1068         ret  = igb_check_mq_mode(dev);
1069         if (ret != 0) {
1070                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1071                             ret);
1072                 return ret;
1073         }
1074
1075         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1076         PMD_INIT_FUNC_TRACE();
1077
1078         return 0;
1079 }
1080
1081 static int
1082 eth_igb_start(struct rte_eth_dev *dev)
1083 {
1084         struct e1000_hw *hw =
1085                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086         struct e1000_adapter *adapter =
1087                 E1000_DEV_PRIVATE(dev->data->dev_private);
1088         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1089         int ret, mask;
1090         uint32_t intr_vector = 0;
1091         uint32_t ctrl_ext;
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         /* Power up the phy. Needed to make the link go Up */
1096         e1000_power_up_phy(hw);
1097
1098         /*
1099          * Packet Buffer Allocation (PBA)
1100          * Writing PBA sets the receive portion of the buffer
1101          * the remainder is used for the transmit buffer.
1102          */
1103         if (hw->mac.type == e1000_82575) {
1104                 uint32_t pba;
1105
1106                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1107                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1108         }
1109
1110         /* Put the address into the Receive Address Array */
1111         e1000_rar_set(hw, hw->mac.addr, 0);
1112
1113         /* Initialize the hardware */
1114         if (igb_hardware_init(hw)) {
1115                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1116                 return (-EIO);
1117         }
1118         adapter->stopped = 0;
1119
1120         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1121
1122         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1123         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1124         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1125         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1126         E1000_WRITE_FLUSH(hw);
1127
1128         /* configure PF module if SRIOV enabled */
1129         igb_pf_host_configure(dev);
1130
1131         /* check and configure queue intr-vector mapping */
1132         if ((rte_intr_cap_multiple(intr_handle) ||
1133              !RTE_ETH_DEV_SRIOV(dev).active) &&
1134             dev->data->dev_conf.intr_conf.rxq != 0) {
1135                 intr_vector = dev->data->nb_rx_queues;
1136                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1137                         return -1;
1138         }
1139
1140         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1141                 intr_handle->intr_vec =
1142                         rte_zmalloc("intr_vec",
1143                                     dev->data->nb_rx_queues * sizeof(int), 0);
1144                 if (intr_handle->intr_vec == NULL) {
1145                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1146                                      " intr_vec\n", dev->data->nb_rx_queues);
1147                         return -ENOMEM;
1148                 }
1149         }
1150
1151         /* confiugre msix for rx interrupt */
1152         eth_igb_configure_msix_intr(dev);
1153
1154         /* Configure for OS presence */
1155         igb_init_manageability(hw);
1156
1157         eth_igb_tx_init(dev);
1158
1159         /* This can fail when allocating mbufs for descriptor rings */
1160         ret = eth_igb_rx_init(dev);
1161         if (ret) {
1162                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1163                 igb_dev_clear_queues(dev);
1164                 return ret;
1165         }
1166
1167         e1000_clear_hw_cntrs_base_generic(hw);
1168
1169         /*
1170          * VLAN Offload Settings
1171          */
1172         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1173                         ETH_VLAN_EXTEND_MASK;
1174         eth_igb_vlan_offload_set(dev, mask);
1175
1176         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1177                 /* Enable VLAN filter since VMDq always use VLAN filter */
1178                 igb_vmdq_vlan_hw_filter_enable(dev);
1179         }
1180
1181         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1182                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1183                 (hw->mac.type == e1000_i211)) {
1184                 /* Configure EITR with the maximum possible value (0xFFFF) */
1185                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1186         }
1187
1188         /* Setup link speed and duplex */
1189         switch (dev->data->dev_conf.link_speed) {
1190         case ETH_LINK_SPEED_AUTONEG:
1191                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1192                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1193                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1194                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1195                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1196                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1197                 else
1198                         goto error_invalid_config;
1199                 break;
1200         case ETH_LINK_SPEED_10:
1201                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1202                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1203                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1204                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1205                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1206                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1207                 else
1208                         goto error_invalid_config;
1209                 break;
1210         case ETH_LINK_SPEED_100:
1211                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1212                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1213                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1214                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1215                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1216                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1217                 else
1218                         goto error_invalid_config;
1219                 break;
1220         case ETH_LINK_SPEED_1000:
1221                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1222                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1223                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1224                 else
1225                         goto error_invalid_config;
1226                 break;
1227         case ETH_LINK_SPEED_10000:
1228         default:
1229                 goto error_invalid_config;
1230         }
1231         e1000_setup_link(hw);
1232
1233         if (rte_intr_allow_others(intr_handle)) {
1234                 /* check if lsc interrupt is enabled */
1235                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1236                         eth_igb_lsc_interrupt_setup(dev);
1237         } else {
1238                 rte_intr_callback_unregister(intr_handle,
1239                                              eth_igb_interrupt_handler,
1240                                              (void *)dev);
1241                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1242                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1243                                      " no intr multiplex\n");
1244         }
1245
1246         /* check if rxq interrupt is enabled */
1247         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1248             rte_intr_dp_is_en(intr_handle))
1249                 eth_igb_rxq_interrupt_setup(dev);
1250
1251         /* enable uio/vfio intr/eventfd mapping */
1252         rte_intr_enable(intr_handle);
1253
1254         /* resume enabled intr since hw reset */
1255         igb_intr_enable(dev);
1256
1257         PMD_INIT_LOG(DEBUG, "<<");
1258
1259         return (0);
1260
1261 error_invalid_config:
1262         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1263                      dev->data->dev_conf.link_speed,
1264                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1265         igb_dev_clear_queues(dev);
1266         return (-EINVAL);
1267 }
1268
1269 /*********************************************************************
1270  *
1271  *  This routine disables all traffic on the adapter by issuing a
1272  *  global reset on the MAC.
1273  *
1274  **********************************************************************/
1275 static void
1276 eth_igb_stop(struct rte_eth_dev *dev)
1277 {
1278         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279         struct e1000_filter_info *filter_info =
1280                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1281         struct rte_eth_link link;
1282         struct e1000_flex_filter *p_flex;
1283         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1284         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1285         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1286
1287         igb_intr_disable(hw);
1288
1289         /* disable intr eventfd mapping */
1290         rte_intr_disable(intr_handle);
1291
1292         igb_pf_reset_hw(hw);
1293         E1000_WRITE_REG(hw, E1000_WUC, 0);
1294
1295         /* Set bit for Go Link disconnect */
1296         if (hw->mac.type >= e1000_82580) {
1297                 uint32_t phpm_reg;
1298
1299                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1300                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1301                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1302         }
1303
1304         /* Power down the phy. Needed to make the link go Down */
1305         if (hw->phy.media_type == e1000_media_type_copper)
1306                 e1000_power_down_phy(hw);
1307         else
1308                 e1000_shutdown_fiber_serdes_link(hw);
1309
1310         igb_dev_clear_queues(dev);
1311
1312         /* clear the recorded link status */
1313         memset(&link, 0, sizeof(link));
1314         rte_igb_dev_atomic_write_link_status(dev, &link);
1315
1316         /* Remove all flex filters of the device */
1317         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1318                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1319                 rte_free(p_flex);
1320         }
1321         filter_info->flex_mask = 0;
1322
1323         /* Remove all ntuple filters of the device */
1324         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1325              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1326                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1327                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1328                              p_5tuple, entries);
1329                 rte_free(p_5tuple);
1330         }
1331         filter_info->fivetuple_mask = 0;
1332         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1333              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1334                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1335                 TAILQ_REMOVE(&filter_info->twotuple_list,
1336                              p_2tuple, entries);
1337                 rte_free(p_2tuple);
1338         }
1339         filter_info->twotuple_mask = 0;
1340
1341         if (!rte_intr_allow_others(intr_handle))
1342                 /* resume to the default handler */
1343                 rte_intr_callback_register(intr_handle,
1344                                            eth_igb_interrupt_handler,
1345                                            (void *)dev);
1346
1347         /* Clean datapath event and queue/vec mapping */
1348         rte_intr_efd_disable(intr_handle);
1349         if (intr_handle->intr_vec != NULL) {
1350                 rte_free(intr_handle->intr_vec);
1351                 intr_handle->intr_vec = NULL;
1352         }
1353 }
1354
1355 static void
1356 eth_igb_close(struct rte_eth_dev *dev)
1357 {
1358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         struct e1000_adapter *adapter =
1360                 E1000_DEV_PRIVATE(dev->data->dev_private);
1361         struct rte_eth_link link;
1362         struct rte_pci_device *pci_dev;
1363
1364         eth_igb_stop(dev);
1365         adapter->stopped = 1;
1366
1367         e1000_phy_hw_reset(hw);
1368         igb_release_manageability(hw);
1369         igb_hw_control_release(hw);
1370
1371         /* Clear bit for Go Link disconnect */
1372         if (hw->mac.type >= e1000_82580) {
1373                 uint32_t phpm_reg;
1374
1375                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1376                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1377                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1378         }
1379
1380         igb_dev_free_queues(dev);
1381
1382         pci_dev = dev->pci_dev;
1383         if (pci_dev->intr_handle.intr_vec) {
1384                 rte_free(pci_dev->intr_handle.intr_vec);
1385                 pci_dev->intr_handle.intr_vec = NULL;
1386         }
1387
1388         memset(&link, 0, sizeof(link));
1389         rte_igb_dev_atomic_write_link_status(dev, &link);
1390 }
1391
1392 static int
1393 igb_get_rx_buffer_size(struct e1000_hw *hw)
1394 {
1395         uint32_t rx_buf_size;
1396         if (hw->mac.type == e1000_82576) {
1397                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1398         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1399                 /* PBS needs to be translated according to a lookup table */
1400                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1401                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1402                 rx_buf_size = (rx_buf_size << 10);
1403         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1404                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1405         } else {
1406                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1407         }
1408
1409         return rx_buf_size;
1410 }
1411
1412 /*********************************************************************
1413  *
1414  *  Initialize the hardware
1415  *
1416  **********************************************************************/
1417 static int
1418 igb_hardware_init(struct e1000_hw *hw)
1419 {
1420         uint32_t rx_buf_size;
1421         int diag;
1422
1423         /* Let the firmware know the OS is in control */
1424         igb_hw_control_acquire(hw);
1425
1426         /*
1427          * These parameters control the automatic generation (Tx) and
1428          * response (Rx) to Ethernet PAUSE frames.
1429          * - High water mark should allow for at least two standard size (1518)
1430          *   frames to be received after sending an XOFF.
1431          * - Low water mark works best when it is very near the high water mark.
1432          *   This allows the receiver to restart by sending XON when it has
1433          *   drained a bit. Here we use an arbitrary value of 1500 which will
1434          *   restart after one full frame is pulled from the buffer. There
1435          *   could be several smaller frames in the buffer and if so they will
1436          *   not trigger the XON until their total number reduces the buffer
1437          *   by 1500.
1438          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1439          */
1440         rx_buf_size = igb_get_rx_buffer_size(hw);
1441
1442         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1443         hw->fc.low_water = hw->fc.high_water - 1500;
1444         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1445         hw->fc.send_xon = 1;
1446
1447         /* Set Flow control, use the tunable location if sane */
1448         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1449                 hw->fc.requested_mode = igb_fc_setting;
1450         else
1451                 hw->fc.requested_mode = e1000_fc_none;
1452
1453         /* Issue a global reset */
1454         igb_pf_reset_hw(hw);
1455         E1000_WRITE_REG(hw, E1000_WUC, 0);
1456
1457         diag = e1000_init_hw(hw);
1458         if (diag < 0)
1459                 return (diag);
1460
1461         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1462         e1000_get_phy_info(hw);
1463         e1000_check_for_link(hw);
1464
1465         return (0);
1466 }
1467
1468 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1469 static void
1470 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1471 {
1472         int pause_frames;
1473
1474         if(hw->phy.media_type == e1000_media_type_copper ||
1475             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1476                 stats->symerrs +=
1477                     E1000_READ_REG(hw,E1000_SYMERRS);
1478                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1479         }
1480
1481         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1482         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1483         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1484         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1485
1486         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1487         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1488         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1489         stats->dc += E1000_READ_REG(hw, E1000_DC);
1490         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1491         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1492         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1493         /*
1494         ** For watchdog management we need to know if we have been
1495         ** paused during the last interval, so capture that here.
1496         */
1497         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1498         stats->xoffrxc += pause_frames;
1499         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1500         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1501         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1502         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1503         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1504         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1505         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1506         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1507         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1508         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1509         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1510         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1511
1512         /* For the 64-bit byte counters the low dword must be read first. */
1513         /* Both registers clear on the read of the high dword */
1514
1515         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1516         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1517         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1518         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1519
1520         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1521         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1522         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1523         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1524         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1525
1526         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1527         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1528         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1529         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1530
1531         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1532         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1533         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1534         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1535         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1536         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1537         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1538         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1539         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1540         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1541
1542         /* Interrupt Counts */
1543
1544         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1545         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1546         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1547         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1548         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1549         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1550         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1551         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1552         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1553
1554         /* Host to Card Statistics */
1555
1556         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1557         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1558         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1559         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1560         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1561         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1562         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1563         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1564         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1565         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1566         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1567         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1568         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1569         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1570
1571         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1572         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1573         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1574         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1575         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1576         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1577 }
1578
1579 static void
1580 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1581 {
1582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583         struct e1000_hw_stats *stats =
1584                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1585
1586         igb_read_stats_registers(hw, stats);
1587
1588         if (rte_stats == NULL)
1589                 return;
1590
1591         /* Rx Errors */
1592         rte_stats->imissed = stats->mpc;
1593         rte_stats->ierrors = stats->crcerrs +
1594                              stats->rlec + stats->ruc + stats->roc +
1595                              rte_stats->imissed +
1596                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1597
1598         /* Tx Errors */
1599         rte_stats->oerrors = stats->ecol + stats->latecol;
1600
1601         rte_stats->ipackets = stats->gprc;
1602         rte_stats->opackets = stats->gptc;
1603         rte_stats->ibytes   = stats->gorc;
1604         rte_stats->obytes   = stats->gotc;
1605 }
1606
1607 static void
1608 eth_igb_stats_reset(struct rte_eth_dev *dev)
1609 {
1610         struct e1000_hw_stats *hw_stats =
1611                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1612
1613         /* HW registers are cleared on read */
1614         eth_igb_stats_get(dev, NULL);
1615
1616         /* Reset software totals */
1617         memset(hw_stats, 0, sizeof(*hw_stats));
1618 }
1619
1620 static void
1621 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1622 {
1623         struct e1000_hw_stats *stats =
1624                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1625
1626         /* HW registers are cleared on read */
1627         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1628
1629         /* Reset software totals */
1630         memset(stats, 0, sizeof(*stats));
1631 }
1632
1633 static int
1634 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1635                    unsigned n)
1636 {
1637         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         struct e1000_hw_stats *hw_stats =
1639                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1640         unsigned i;
1641
1642         if (n < IGB_NB_XSTATS)
1643                 return IGB_NB_XSTATS;
1644
1645         igb_read_stats_registers(hw, hw_stats);
1646
1647         /* If this is a reset xstats is NULL, and we have cleared the
1648          * registers by reading them.
1649          */
1650         if (!xstats)
1651                 return 0;
1652
1653         /* Extended stats */
1654         for (i = 0; i < IGB_NB_XSTATS; i++) {
1655                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1656                          "%s", rte_igb_stats_strings[i].name);
1657                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1658                         rte_igb_stats_strings[i].offset);
1659         }
1660
1661         return IGB_NB_XSTATS;
1662 }
1663
1664 static void
1665 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1666 {
1667         /* Good Rx packets, include VF loopback */
1668         UPDATE_VF_STAT(E1000_VFGPRC,
1669             hw_stats->last_gprc, hw_stats->gprc);
1670
1671         /* Good Rx octets, include VF loopback */
1672         UPDATE_VF_STAT(E1000_VFGORC,
1673             hw_stats->last_gorc, hw_stats->gorc);
1674
1675         /* Good Tx packets, include VF loopback */
1676         UPDATE_VF_STAT(E1000_VFGPTC,
1677             hw_stats->last_gptc, hw_stats->gptc);
1678
1679         /* Good Tx octets, include VF loopback */
1680         UPDATE_VF_STAT(E1000_VFGOTC,
1681             hw_stats->last_gotc, hw_stats->gotc);
1682
1683         /* Rx Multicst packets */
1684         UPDATE_VF_STAT(E1000_VFMPRC,
1685             hw_stats->last_mprc, hw_stats->mprc);
1686
1687         /* Good Rx loopback packets */
1688         UPDATE_VF_STAT(E1000_VFGPRLBC,
1689             hw_stats->last_gprlbc, hw_stats->gprlbc);
1690
1691         /* Good Rx loopback octets */
1692         UPDATE_VF_STAT(E1000_VFGORLBC,
1693             hw_stats->last_gorlbc, hw_stats->gorlbc);
1694
1695         /* Good Tx loopback packets */
1696         UPDATE_VF_STAT(E1000_VFGPTLBC,
1697             hw_stats->last_gptlbc, hw_stats->gptlbc);
1698
1699         /* Good Tx loopback octets */
1700         UPDATE_VF_STAT(E1000_VFGOTLBC,
1701             hw_stats->last_gotlbc, hw_stats->gotlbc);
1702 }
1703
1704 static int
1705 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1706                      unsigned n)
1707 {
1708         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1710                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1711         unsigned i;
1712
1713         if (n < IGBVF_NB_XSTATS)
1714                 return IGBVF_NB_XSTATS;
1715
1716         igbvf_read_stats_registers(hw, hw_stats);
1717
1718         if (!xstats)
1719                 return 0;
1720
1721         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1722                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1723                          rte_igbvf_stats_strings[i].name);
1724                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1725                         rte_igbvf_stats_strings[i].offset);
1726         }
1727
1728         return IGBVF_NB_XSTATS;
1729 }
1730
1731 static void
1732 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1733 {
1734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1736                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1737
1738         igbvf_read_stats_registers(hw, hw_stats);
1739
1740         if (rte_stats == NULL)
1741                 return;
1742
1743         rte_stats->ipackets = hw_stats->gprc;
1744         rte_stats->ibytes = hw_stats->gorc;
1745         rte_stats->opackets = hw_stats->gptc;
1746         rte_stats->obytes = hw_stats->gotc;
1747         rte_stats->imcasts = hw_stats->mprc;
1748         rte_stats->ilbpackets = hw_stats->gprlbc;
1749         rte_stats->ilbbytes = hw_stats->gorlbc;
1750         rte_stats->olbpackets = hw_stats->gptlbc;
1751         rte_stats->olbbytes = hw_stats->gotlbc;
1752 }
1753
1754 static void
1755 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1756 {
1757         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1758                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1759
1760         /* Sync HW register to the last stats */
1761         eth_igbvf_stats_get(dev, NULL);
1762
1763         /* reset HW current stats*/
1764         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1765                offsetof(struct e1000_vf_stats, gprc));
1766 }
1767
1768 static void
1769 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1770 {
1771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772
1773         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1774         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1775         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1776         dev_info->rx_offload_capa =
1777                 DEV_RX_OFFLOAD_VLAN_STRIP |
1778                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1779                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1780                 DEV_RX_OFFLOAD_TCP_CKSUM;
1781         dev_info->tx_offload_capa =
1782                 DEV_TX_OFFLOAD_VLAN_INSERT |
1783                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1784                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1785                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1786                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1787                 DEV_TX_OFFLOAD_TCP_TSO;
1788
1789         switch (hw->mac.type) {
1790         case e1000_82575:
1791                 dev_info->max_rx_queues = 4;
1792                 dev_info->max_tx_queues = 4;
1793                 dev_info->max_vmdq_pools = 0;
1794                 break;
1795
1796         case e1000_82576:
1797                 dev_info->max_rx_queues = 16;
1798                 dev_info->max_tx_queues = 16;
1799                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1800                 dev_info->vmdq_queue_num = 16;
1801                 break;
1802
1803         case e1000_82580:
1804                 dev_info->max_rx_queues = 8;
1805                 dev_info->max_tx_queues = 8;
1806                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1807                 dev_info->vmdq_queue_num = 8;
1808                 break;
1809
1810         case e1000_i350:
1811                 dev_info->max_rx_queues = 8;
1812                 dev_info->max_tx_queues = 8;
1813                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1814                 dev_info->vmdq_queue_num = 8;
1815                 break;
1816
1817         case e1000_i354:
1818                 dev_info->max_rx_queues = 8;
1819                 dev_info->max_tx_queues = 8;
1820                 break;
1821
1822         case e1000_i210:
1823                 dev_info->max_rx_queues = 4;
1824                 dev_info->max_tx_queues = 4;
1825                 dev_info->max_vmdq_pools = 0;
1826                 break;
1827
1828         case e1000_i211:
1829                 dev_info->max_rx_queues = 2;
1830                 dev_info->max_tx_queues = 2;
1831                 dev_info->max_vmdq_pools = 0;
1832                 break;
1833
1834         default:
1835                 /* Should not happen */
1836                 break;
1837         }
1838         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1839         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1840         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1841
1842         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1843                 .rx_thresh = {
1844                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1845                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1846                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1847                 },
1848                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1849                 .rx_drop_en = 0,
1850         };
1851
1852         dev_info->default_txconf = (struct rte_eth_txconf) {
1853                 .tx_thresh = {
1854                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1855                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1856                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1857                 },
1858                 .txq_flags = 0,
1859         };
1860
1861         dev_info->rx_desc_lim = rx_desc_lim;
1862         dev_info->tx_desc_lim = tx_desc_lim;
1863 }
1864
1865 static void
1866 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1867 {
1868         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869
1870         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1871         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1872         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1873         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1874                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1875                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1876                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1877         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1878                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1879                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1880                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1881                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1882                                 DEV_TX_OFFLOAD_TCP_TSO;
1883         switch (hw->mac.type) {
1884         case e1000_vfadapt:
1885                 dev_info->max_rx_queues = 2;
1886                 dev_info->max_tx_queues = 2;
1887                 break;
1888         case e1000_vfadapt_i350:
1889                 dev_info->max_rx_queues = 1;
1890                 dev_info->max_tx_queues = 1;
1891                 break;
1892         default:
1893                 /* Should not happen */
1894                 break;
1895         }
1896
1897         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1898                 .rx_thresh = {
1899                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1900                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1901                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1902                 },
1903                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1904                 .rx_drop_en = 0,
1905         };
1906
1907         dev_info->default_txconf = (struct rte_eth_txconf) {
1908                 .tx_thresh = {
1909                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1910                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1911                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1912                 },
1913                 .txq_flags = 0,
1914         };
1915
1916         dev_info->rx_desc_lim = rx_desc_lim;
1917         dev_info->tx_desc_lim = tx_desc_lim;
1918 }
1919
1920 /* return 0 means link status changed, -1 means not changed */
1921 static int
1922 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1923 {
1924         struct e1000_hw *hw =
1925                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct rte_eth_link link, old;
1927         int link_check, count;
1928
1929         link_check = 0;
1930         hw->mac.get_link_status = 1;
1931
1932         /* possible wait-to-complete in up to 9 seconds */
1933         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1934                 /* Read the real link status */
1935                 switch (hw->phy.media_type) {
1936                 case e1000_media_type_copper:
1937                         /* Do the work to read phy */
1938                         e1000_check_for_link(hw);
1939                         link_check = !hw->mac.get_link_status;
1940                         break;
1941
1942                 case e1000_media_type_fiber:
1943                         e1000_check_for_link(hw);
1944                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1945                                       E1000_STATUS_LU);
1946                         break;
1947
1948                 case e1000_media_type_internal_serdes:
1949                         e1000_check_for_link(hw);
1950                         link_check = hw->mac.serdes_has_link;
1951                         break;
1952
1953                 /* VF device is type_unknown */
1954                 case e1000_media_type_unknown:
1955                         eth_igbvf_link_update(hw);
1956                         link_check = !hw->mac.get_link_status;
1957                         break;
1958
1959                 default:
1960                         break;
1961                 }
1962                 if (link_check || wait_to_complete == 0)
1963                         break;
1964                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1965         }
1966         memset(&link, 0, sizeof(link));
1967         rte_igb_dev_atomic_read_link_status(dev, &link);
1968         old = link;
1969
1970         /* Now we check if a transition has happened */
1971         if (link_check) {
1972                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1973                                           &link.link_duplex);
1974                 link.link_status = 1;
1975         } else if (!link_check) {
1976                 link.link_speed = 0;
1977                 link.link_duplex = 0;
1978                 link.link_status = 0;
1979         }
1980         rte_igb_dev_atomic_write_link_status(dev, &link);
1981
1982         /* not changed */
1983         if (old.link_status == link.link_status)
1984                 return -1;
1985
1986         /* changed */
1987         return 0;
1988 }
1989
1990 /*
1991  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1992  * For ASF and Pass Through versions of f/w this means
1993  * that the driver is loaded.
1994  */
1995 static void
1996 igb_hw_control_acquire(struct e1000_hw *hw)
1997 {
1998         uint32_t ctrl_ext;
1999
2000         /* Let firmware know the driver has taken over */
2001         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2002         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2003 }
2004
2005 /*
2006  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2007  * For ASF and Pass Through versions of f/w this means that the
2008  * driver is no longer loaded.
2009  */
2010 static void
2011 igb_hw_control_release(struct e1000_hw *hw)
2012 {
2013         uint32_t ctrl_ext;
2014
2015         /* Let firmware taken over control of h/w */
2016         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2017         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2018                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2019 }
2020
2021 /*
2022  * Bit of a misnomer, what this really means is
2023  * to enable OS management of the system... aka
2024  * to disable special hardware management features.
2025  */
2026 static void
2027 igb_init_manageability(struct e1000_hw *hw)
2028 {
2029         if (e1000_enable_mng_pass_thru(hw)) {
2030                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2031                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2032
2033                 /* disable hardware interception of ARP */
2034                 manc &= ~(E1000_MANC_ARP_EN);
2035
2036                 /* enable receiving management packets to the host */
2037                 manc |= E1000_MANC_EN_MNG2HOST;
2038                 manc2h |= 1 << 5;  /* Mng Port 623 */
2039                 manc2h |= 1 << 6;  /* Mng Port 664 */
2040                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2041                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2042         }
2043 }
2044
2045 static void
2046 igb_release_manageability(struct e1000_hw *hw)
2047 {
2048         if (e1000_enable_mng_pass_thru(hw)) {
2049                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2050
2051                 manc |= E1000_MANC_ARP_EN;
2052                 manc &= ~E1000_MANC_EN_MNG2HOST;
2053
2054                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2055         }
2056 }
2057
2058 static void
2059 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2060 {
2061         struct e1000_hw *hw =
2062                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t rctl;
2064
2065         rctl = E1000_READ_REG(hw, E1000_RCTL);
2066         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2067         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2068 }
2069
2070 static void
2071 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2072 {
2073         struct e1000_hw *hw =
2074                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075         uint32_t rctl;
2076
2077         rctl = E1000_READ_REG(hw, E1000_RCTL);
2078         rctl &= (~E1000_RCTL_UPE);
2079         if (dev->data->all_multicast == 1)
2080                 rctl |= E1000_RCTL_MPE;
2081         else
2082                 rctl &= (~E1000_RCTL_MPE);
2083         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2084 }
2085
2086 static void
2087 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2088 {
2089         struct e1000_hw *hw =
2090                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         uint32_t rctl;
2092
2093         rctl = E1000_READ_REG(hw, E1000_RCTL);
2094         rctl |= E1000_RCTL_MPE;
2095         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2096 }
2097
2098 static void
2099 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2100 {
2101         struct e1000_hw *hw =
2102                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         uint32_t rctl;
2104
2105         if (dev->data->promiscuous == 1)
2106                 return; /* must remain in all_multicast mode */
2107         rctl = E1000_READ_REG(hw, E1000_RCTL);
2108         rctl &= (~E1000_RCTL_MPE);
2109         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2110 }
2111
2112 static int
2113 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2114 {
2115         struct e1000_hw *hw =
2116                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct e1000_vfta * shadow_vfta =
2118                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2119         uint32_t vfta;
2120         uint32_t vid_idx;
2121         uint32_t vid_bit;
2122
2123         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2124                               E1000_VFTA_ENTRY_MASK);
2125         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2126         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2127         if (on)
2128                 vfta |= vid_bit;
2129         else
2130                 vfta &= ~vid_bit;
2131         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2132
2133         /* update local VFTA copy */
2134         shadow_vfta->vfta[vid_idx] = vfta;
2135
2136         return 0;
2137 }
2138
2139 static void
2140 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2141 {
2142         struct e1000_hw *hw =
2143                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         uint32_t reg = ETHER_TYPE_VLAN ;
2145
2146         reg |= (tpid << 16);
2147         E1000_WRITE_REG(hw, E1000_VET, reg);
2148 }
2149
2150 static void
2151 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2152 {
2153         struct e1000_hw *hw =
2154                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         uint32_t reg;
2156
2157         /* Filter Table Disable */
2158         reg = E1000_READ_REG(hw, E1000_RCTL);
2159         reg &= ~E1000_RCTL_CFIEN;
2160         reg &= ~E1000_RCTL_VFE;
2161         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2162 }
2163
2164 static void
2165 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2166 {
2167         struct e1000_hw *hw =
2168                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct e1000_vfta * shadow_vfta =
2170                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2171         uint32_t reg;
2172         int i;
2173
2174         /* Filter Table Enable, CFI not used for packet acceptance */
2175         reg = E1000_READ_REG(hw, E1000_RCTL);
2176         reg &= ~E1000_RCTL_CFIEN;
2177         reg |= E1000_RCTL_VFE;
2178         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2179
2180         /* restore VFTA table */
2181         for (i = 0; i < IGB_VFTA_SIZE; i++)
2182                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2183 }
2184
2185 static void
2186 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2187 {
2188         struct e1000_hw *hw =
2189                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190         uint32_t reg;
2191
2192         /* VLAN Mode Disable */
2193         reg = E1000_READ_REG(hw, E1000_CTRL);
2194         reg &= ~E1000_CTRL_VME;
2195         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2196 }
2197
2198 static void
2199 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2200 {
2201         struct e1000_hw *hw =
2202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint32_t reg;
2204
2205         /* VLAN Mode Enable */
2206         reg = E1000_READ_REG(hw, E1000_CTRL);
2207         reg |= E1000_CTRL_VME;
2208         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2209 }
2210
2211 static void
2212 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2213 {
2214         struct e1000_hw *hw =
2215                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         uint32_t reg;
2217
2218         /* CTRL_EXT: Extended VLAN */
2219         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2220         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2221         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2222
2223         /* Update maximum packet length */
2224         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2225                 E1000_WRITE_REG(hw, E1000_RLPML,
2226                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2227                                                 VLAN_TAG_SIZE);
2228 }
2229
2230 static void
2231 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2232 {
2233         struct e1000_hw *hw =
2234                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         uint32_t reg;
2236
2237         /* CTRL_EXT: Extended VLAN */
2238         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2239         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2240         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2241
2242         /* Update maximum packet length */
2243         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2244                 E1000_WRITE_REG(hw, E1000_RLPML,
2245                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2246                                                 2 * VLAN_TAG_SIZE);
2247 }
2248
2249 static void
2250 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2251 {
2252         if(mask & ETH_VLAN_STRIP_MASK){
2253                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2254                         igb_vlan_hw_strip_enable(dev);
2255                 else
2256                         igb_vlan_hw_strip_disable(dev);
2257         }
2258
2259         if(mask & ETH_VLAN_FILTER_MASK){
2260                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2261                         igb_vlan_hw_filter_enable(dev);
2262                 else
2263                         igb_vlan_hw_filter_disable(dev);
2264         }
2265
2266         if(mask & ETH_VLAN_EXTEND_MASK){
2267                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2268                         igb_vlan_hw_extend_enable(dev);
2269                 else
2270                         igb_vlan_hw_extend_disable(dev);
2271         }
2272 }
2273
2274
2275 /**
2276  * It enables the interrupt mask and then enable the interrupt.
2277  *
2278  * @param dev
2279  *  Pointer to struct rte_eth_dev.
2280  *
2281  * @return
2282  *  - On success, zero.
2283  *  - On failure, a negative value.
2284  */
2285 static int
2286 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2287 {
2288         struct e1000_interrupt *intr =
2289                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2290
2291         intr->mask |= E1000_ICR_LSC;
2292
2293         return 0;
2294 }
2295
2296 /* It clears the interrupt causes and enables the interrupt.
2297  * It will be called once only during nic initialized.
2298  *
2299  * @param dev
2300  *  Pointer to struct rte_eth_dev.
2301  *
2302  * @return
2303  *  - On success, zero.
2304  *  - On failure, a negative value.
2305  */
2306 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2307 {
2308         uint32_t mask, regval;
2309         struct e1000_hw *hw =
2310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2311         struct rte_eth_dev_info dev_info;
2312
2313         memset(&dev_info, 0, sizeof(dev_info));
2314         eth_igb_infos_get(dev, &dev_info);
2315
2316         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2317         regval = E1000_READ_REG(hw, E1000_EIMS);
2318         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2319
2320         return 0;
2321 }
2322
2323 /*
2324  * It reads ICR and gets interrupt causes, check it and set a bit flag
2325  * to update link status.
2326  *
2327  * @param dev
2328  *  Pointer to struct rte_eth_dev.
2329  *
2330  * @return
2331  *  - On success, zero.
2332  *  - On failure, a negative value.
2333  */
2334 static int
2335 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2336 {
2337         uint32_t icr;
2338         struct e1000_hw *hw =
2339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         struct e1000_interrupt *intr =
2341                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2342
2343         igb_intr_disable(hw);
2344
2345         /* read-on-clear nic registers here */
2346         icr = E1000_READ_REG(hw, E1000_ICR);
2347
2348         intr->flags = 0;
2349         if (icr & E1000_ICR_LSC) {
2350                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2351         }
2352
2353         if (icr & E1000_ICR_VMMB)
2354                 intr->flags |= E1000_FLAG_MAILBOX;
2355
2356         return 0;
2357 }
2358
2359 /*
2360  * It executes link_update after knowing an interrupt is prsent.
2361  *
2362  * @param dev
2363  *  Pointer to struct rte_eth_dev.
2364  *
2365  * @return
2366  *  - On success, zero.
2367  *  - On failure, a negative value.
2368  */
2369 static int
2370 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2371 {
2372         struct e1000_hw *hw =
2373                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         struct e1000_interrupt *intr =
2375                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2376         uint32_t tctl, rctl;
2377         struct rte_eth_link link;
2378         int ret;
2379
2380         if (intr->flags & E1000_FLAG_MAILBOX) {
2381                 igb_pf_mbx_process(dev);
2382                 intr->flags &= ~E1000_FLAG_MAILBOX;
2383         }
2384
2385         igb_intr_enable(dev);
2386         rte_intr_enable(&(dev->pci_dev->intr_handle));
2387
2388         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2389                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2390
2391                 /* set get_link_status to check register later */
2392                 hw->mac.get_link_status = 1;
2393                 ret = eth_igb_link_update(dev, 0);
2394
2395                 /* check if link has changed */
2396                 if (ret < 0)
2397                         return 0;
2398
2399                 memset(&link, 0, sizeof(link));
2400                 rte_igb_dev_atomic_read_link_status(dev, &link);
2401                 if (link.link_status) {
2402                         PMD_INIT_LOG(INFO,
2403                                      " Port %d: Link Up - speed %u Mbps - %s",
2404                                      dev->data->port_id,
2405                                      (unsigned)link.link_speed,
2406                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2407                                      "full-duplex" : "half-duplex");
2408                 } else {
2409                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2410                                      dev->data->port_id);
2411                 }
2412
2413                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2414                              dev->pci_dev->addr.domain,
2415                              dev->pci_dev->addr.bus,
2416                              dev->pci_dev->addr.devid,
2417                              dev->pci_dev->addr.function);
2418                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2419                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2420                 if (link.link_status) {
2421                         /* enable Tx/Rx */
2422                         tctl |= E1000_TCTL_EN;
2423                         rctl |= E1000_RCTL_EN;
2424                 } else {
2425                         /* disable Tx/Rx */
2426                         tctl &= ~E1000_TCTL_EN;
2427                         rctl &= ~E1000_RCTL_EN;
2428                 }
2429                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2430                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2431                 E1000_WRITE_FLUSH(hw);
2432                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2433         }
2434
2435         return 0;
2436 }
2437
2438 /**
2439  * Interrupt handler which shall be registered at first.
2440  *
2441  * @param handle
2442  *  Pointer to interrupt handle.
2443  * @param param
2444  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2445  *
2446  * @return
2447  *  void
2448  */
2449 static void
2450 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2451                                                         void *param)
2452 {
2453         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2454
2455         eth_igb_interrupt_get_status(dev);
2456         eth_igb_interrupt_action(dev);
2457 }
2458
2459 static int
2460 eth_igb_led_on(struct rte_eth_dev *dev)
2461 {
2462         struct e1000_hw *hw;
2463
2464         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2466 }
2467
2468 static int
2469 eth_igb_led_off(struct rte_eth_dev *dev)
2470 {
2471         struct e1000_hw *hw;
2472
2473         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2475 }
2476
2477 static int
2478 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2479 {
2480         struct e1000_hw *hw;
2481         uint32_t ctrl;
2482         int tx_pause;
2483         int rx_pause;
2484
2485         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         fc_conf->pause_time = hw->fc.pause_time;
2487         fc_conf->high_water = hw->fc.high_water;
2488         fc_conf->low_water = hw->fc.low_water;
2489         fc_conf->send_xon = hw->fc.send_xon;
2490         fc_conf->autoneg = hw->mac.autoneg;
2491
2492         /*
2493          * Return rx_pause and tx_pause status according to actual setting of
2494          * the TFCE and RFCE bits in the CTRL register.
2495          */
2496         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2497         if (ctrl & E1000_CTRL_TFCE)
2498                 tx_pause = 1;
2499         else
2500                 tx_pause = 0;
2501
2502         if (ctrl & E1000_CTRL_RFCE)
2503                 rx_pause = 1;
2504         else
2505                 rx_pause = 0;
2506
2507         if (rx_pause && tx_pause)
2508                 fc_conf->mode = RTE_FC_FULL;
2509         else if (rx_pause)
2510                 fc_conf->mode = RTE_FC_RX_PAUSE;
2511         else if (tx_pause)
2512                 fc_conf->mode = RTE_FC_TX_PAUSE;
2513         else
2514                 fc_conf->mode = RTE_FC_NONE;
2515
2516         return 0;
2517 }
2518
2519 static int
2520 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2521 {
2522         struct e1000_hw *hw;
2523         int err;
2524         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2525                 e1000_fc_none,
2526                 e1000_fc_rx_pause,
2527                 e1000_fc_tx_pause,
2528                 e1000_fc_full
2529         };
2530         uint32_t rx_buf_size;
2531         uint32_t max_high_water;
2532         uint32_t rctl;
2533
2534         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         if (fc_conf->autoneg != hw->mac.autoneg)
2536                 return -ENOTSUP;
2537         rx_buf_size = igb_get_rx_buffer_size(hw);
2538         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2539
2540         /* At least reserve one Ethernet frame for watermark */
2541         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2542         if ((fc_conf->high_water > max_high_water) ||
2543             (fc_conf->high_water < fc_conf->low_water)) {
2544                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2545                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2546                 return (-EINVAL);
2547         }
2548
2549         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2550         hw->fc.pause_time     = fc_conf->pause_time;
2551         hw->fc.high_water     = fc_conf->high_water;
2552         hw->fc.low_water      = fc_conf->low_water;
2553         hw->fc.send_xon       = fc_conf->send_xon;
2554
2555         err = e1000_setup_link_generic(hw);
2556         if (err == E1000_SUCCESS) {
2557
2558                 /* check if we want to forward MAC frames - driver doesn't have native
2559                  * capability to do that, so we'll write the registers ourselves */
2560
2561                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2562
2563                 /* set or clear MFLCN.PMCF bit depending on configuration */
2564                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2565                         rctl |= E1000_RCTL_PMCF;
2566                 else
2567                         rctl &= ~E1000_RCTL_PMCF;
2568
2569                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2570                 E1000_WRITE_FLUSH(hw);
2571
2572                 return 0;
2573         }
2574
2575         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2576         return (-EIO);
2577 }
2578
2579 #define E1000_RAH_POOLSEL_SHIFT      (18)
2580 static void
2581 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2582                 uint32_t index, __rte_unused uint32_t pool)
2583 {
2584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         uint32_t rah;
2586
2587         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2588         rah = E1000_READ_REG(hw, E1000_RAH(index));
2589         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2590         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2591 }
2592
2593 static void
2594 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2595 {
2596         uint8_t addr[ETHER_ADDR_LEN];
2597         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598
2599         memset(addr, 0, sizeof(addr));
2600
2601         e1000_rar_set(hw, addr, index);
2602 }
2603
2604 static void
2605 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2606                                 struct ether_addr *addr)
2607 {
2608         eth_igb_rar_clear(dev, 0);
2609
2610         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2611 }
2612 /*
2613  * Virtual Function operations
2614  */
2615 static void
2616 igbvf_intr_disable(struct e1000_hw *hw)
2617 {
2618         PMD_INIT_FUNC_TRACE();
2619
2620         /* Clear interrupt mask to stop from interrupts being generated */
2621         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2622
2623         E1000_WRITE_FLUSH(hw);
2624 }
2625
2626 static void
2627 igbvf_stop_adapter(struct rte_eth_dev *dev)
2628 {
2629         u32 reg_val;
2630         u16 i;
2631         struct rte_eth_dev_info dev_info;
2632         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633
2634         memset(&dev_info, 0, sizeof(dev_info));
2635         eth_igbvf_infos_get(dev, &dev_info);
2636
2637         /* Clear interrupt mask to stop from interrupts being generated */
2638         igbvf_intr_disable(hw);
2639
2640         /* Clear any pending interrupts, flush previous writes */
2641         E1000_READ_REG(hw, E1000_EICR);
2642
2643         /* Disable the transmit unit.  Each queue must be disabled. */
2644         for (i = 0; i < dev_info.max_tx_queues; i++)
2645                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2646
2647         /* Disable the receive unit by stopping each queue */
2648         for (i = 0; i < dev_info.max_rx_queues; i++) {
2649                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2650                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2651                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2652                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2653                         ;
2654         }
2655
2656         /* flush all queues disables */
2657         E1000_WRITE_FLUSH(hw);
2658         msec_delay(2);
2659 }
2660
2661 static int eth_igbvf_link_update(struct e1000_hw *hw)
2662 {
2663         struct e1000_mbx_info *mbx = &hw->mbx;
2664         struct e1000_mac_info *mac = &hw->mac;
2665         int ret_val = E1000_SUCCESS;
2666
2667         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2668
2669         /*
2670          * We only want to run this if there has been a rst asserted.
2671          * in this case that could mean a link change, device reset,
2672          * or a virtual function reset
2673          */
2674
2675         /* If we were hit with a reset or timeout drop the link */
2676         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2677                 mac->get_link_status = TRUE;
2678
2679         if (!mac->get_link_status)
2680                 goto out;
2681
2682         /* if link status is down no point in checking to see if pf is up */
2683         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2684                 goto out;
2685
2686         /* if we passed all the tests above then the link is up and we no
2687          * longer need to check for link */
2688         mac->get_link_status = FALSE;
2689
2690 out:
2691         return ret_val;
2692 }
2693
2694
2695 static int
2696 igbvf_dev_configure(struct rte_eth_dev *dev)
2697 {
2698         struct rte_eth_conf* conf = &dev->data->dev_conf;
2699
2700         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2701                      dev->data->port_id);
2702
2703         /*
2704          * VF has no ability to enable/disable HW CRC
2705          * Keep the persistent behavior the same as Host PF
2706          */
2707 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2708         if (!conf->rxmode.hw_strip_crc) {
2709                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2710                 conf->rxmode.hw_strip_crc = 1;
2711         }
2712 #else
2713         if (conf->rxmode.hw_strip_crc) {
2714                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2715                 conf->rxmode.hw_strip_crc = 0;
2716         }
2717 #endif
2718
2719         return 0;
2720 }
2721
2722 static int
2723 igbvf_dev_start(struct rte_eth_dev *dev)
2724 {
2725         struct e1000_hw *hw =
2726                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727         struct e1000_adapter *adapter =
2728                 E1000_DEV_PRIVATE(dev->data->dev_private);
2729         int ret;
2730
2731         PMD_INIT_FUNC_TRACE();
2732
2733         hw->mac.ops.reset_hw(hw);
2734         adapter->stopped = 0;
2735
2736         /* Set all vfta */
2737         igbvf_set_vfta_all(dev,1);
2738
2739         eth_igbvf_tx_init(dev);
2740
2741         /* This can fail when allocating mbufs for descriptor rings */
2742         ret = eth_igbvf_rx_init(dev);
2743         if (ret) {
2744                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2745                 igb_dev_clear_queues(dev);
2746                 return ret;
2747         }
2748
2749         return 0;
2750 }
2751
2752 static void
2753 igbvf_dev_stop(struct rte_eth_dev *dev)
2754 {
2755         PMD_INIT_FUNC_TRACE();
2756
2757         igbvf_stop_adapter(dev);
2758
2759         /*
2760           * Clear what we set, but we still keep shadow_vfta to
2761           * restore after device starts
2762           */
2763         igbvf_set_vfta_all(dev,0);
2764
2765         igb_dev_clear_queues(dev);
2766 }
2767
2768 static void
2769 igbvf_dev_close(struct rte_eth_dev *dev)
2770 {
2771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772         struct e1000_adapter *adapter =
2773                 E1000_DEV_PRIVATE(dev->data->dev_private);
2774
2775         PMD_INIT_FUNC_TRACE();
2776
2777         e1000_reset_hw(hw);
2778
2779         igbvf_dev_stop(dev);
2780         adapter->stopped = 1;
2781         igb_dev_free_queues(dev);
2782 }
2783
2784 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2785 {
2786         struct e1000_mbx_info *mbx = &hw->mbx;
2787         uint32_t msgbuf[2];
2788         s32 err;
2789
2790         /* After set vlan, vlan strip will also be enabled in igb driver*/
2791         msgbuf[0] = E1000_VF_SET_VLAN;
2792         msgbuf[1] = vid;
2793         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2794         if (on)
2795                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2796
2797         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2798         if (err)
2799                 goto mbx_err;
2800
2801         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2802         if (err)
2803                 goto mbx_err;
2804
2805         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2806         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2807                 err = -EINVAL;
2808
2809 mbx_err:
2810         return err;
2811 }
2812
2813 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2814 {
2815         struct e1000_hw *hw =
2816                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         struct e1000_vfta * shadow_vfta =
2818                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2819         int i = 0, j = 0, vfta = 0, mask = 1;
2820
2821         for (i = 0; i < IGB_VFTA_SIZE; i++){
2822                 vfta = shadow_vfta->vfta[i];
2823                 if(vfta){
2824                         mask = 1;
2825                         for (j = 0; j < 32; j++){
2826                                 if(vfta & mask)
2827                                         igbvf_set_vfta(hw,
2828                                                 (uint16_t)((i<<5)+j), on);
2829                                 mask<<=1;
2830                         }
2831                 }
2832         }
2833
2834 }
2835
2836 static int
2837 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2838 {
2839         struct e1000_hw *hw =
2840                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         struct e1000_vfta * shadow_vfta =
2842                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2843         uint32_t vid_idx = 0;
2844         uint32_t vid_bit = 0;
2845         int ret = 0;
2846
2847         PMD_INIT_FUNC_TRACE();
2848
2849         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2850         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2851         if(ret){
2852                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2853                 return ret;
2854         }
2855         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2856         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2857
2858         /*Save what we set and retore it after device reset*/
2859         if (on)
2860                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2861         else
2862                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2863
2864         return 0;
2865 }
2866
2867 static void
2868 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2869 {
2870         struct e1000_hw *hw =
2871                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872
2873         /* index is not used by rar_set() */
2874         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2875 }
2876
2877
2878 static int
2879 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2880                         struct rte_eth_rss_reta_entry64 *reta_conf,
2881                         uint16_t reta_size)
2882 {
2883         uint8_t i, j, mask;
2884         uint32_t reta, r;
2885         uint16_t idx, shift;
2886         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887
2888         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2889                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2890                         "(%d) doesn't match the number hardware can supported "
2891                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2892                 return -EINVAL;
2893         }
2894
2895         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2896                 idx = i / RTE_RETA_GROUP_SIZE;
2897                 shift = i % RTE_RETA_GROUP_SIZE;
2898                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2899                                                 IGB_4_BIT_MASK);
2900                 if (!mask)
2901                         continue;
2902                 if (mask == IGB_4_BIT_MASK)
2903                         r = 0;
2904                 else
2905                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2906                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2907                         if (mask & (0x1 << j))
2908                                 reta |= reta_conf[idx].reta[shift + j] <<
2909                                                         (CHAR_BIT * j);
2910                         else
2911                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2912                 }
2913                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2914         }
2915
2916         return 0;
2917 }
2918
2919 static int
2920 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2921                        struct rte_eth_rss_reta_entry64 *reta_conf,
2922                        uint16_t reta_size)
2923 {
2924         uint8_t i, j, mask;
2925         uint32_t reta;
2926         uint16_t idx, shift;
2927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928
2929         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2930                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2931                         "(%d) doesn't match the number hardware can supported "
2932                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2933                 return -EINVAL;
2934         }
2935
2936         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2937                 idx = i / RTE_RETA_GROUP_SIZE;
2938                 shift = i % RTE_RETA_GROUP_SIZE;
2939                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2940                                                 IGB_4_BIT_MASK);
2941                 if (!mask)
2942                         continue;
2943                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2944                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2945                         if (mask & (0x1 << j))
2946                                 reta_conf[idx].reta[shift + j] =
2947                                         ((reta >> (CHAR_BIT * j)) &
2948                                                 IGB_8_BIT_MASK);
2949                 }
2950         }
2951
2952         return 0;
2953 }
2954
2955 #define MAC_TYPE_FILTER_SUP(type)    do {\
2956         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2957                 (type) != e1000_82576)\
2958                 return -ENOTSUP;\
2959 } while (0)
2960
2961 static int
2962 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2963                         struct rte_eth_syn_filter *filter,
2964                         bool add)
2965 {
2966         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         uint32_t synqf, rfctl;
2968
2969         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2970                 return -EINVAL;
2971
2972         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2973
2974         if (add) {
2975                 if (synqf & E1000_SYN_FILTER_ENABLE)
2976                         return -EINVAL;
2977
2978                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2979                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2980
2981                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2982                 if (filter->hig_pri)
2983                         rfctl |= E1000_RFCTL_SYNQFP;
2984                 else
2985                         rfctl &= ~E1000_RFCTL_SYNQFP;
2986
2987                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2988         } else {
2989                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2990                         return -ENOENT;
2991                 synqf = 0;
2992         }
2993
2994         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2995         E1000_WRITE_FLUSH(hw);
2996         return 0;
2997 }
2998
2999 static int
3000 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3001                         struct rte_eth_syn_filter *filter)
3002 {
3003         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         uint32_t synqf, rfctl;
3005
3006         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3007         if (synqf & E1000_SYN_FILTER_ENABLE) {
3008                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3009                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3010                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3011                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3012                 return 0;
3013         }
3014
3015         return -ENOENT;
3016 }
3017
3018 static int
3019 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3020                         enum rte_filter_op filter_op,
3021                         void *arg)
3022 {
3023         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024         int ret;
3025
3026         MAC_TYPE_FILTER_SUP(hw->mac.type);
3027
3028         if (filter_op == RTE_ETH_FILTER_NOP)
3029                 return 0;
3030
3031         if (arg == NULL) {
3032                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3033                             filter_op);
3034                 return -EINVAL;
3035         }
3036
3037         switch (filter_op) {
3038         case RTE_ETH_FILTER_ADD:
3039                 ret = eth_igb_syn_filter_set(dev,
3040                                 (struct rte_eth_syn_filter *)arg,
3041                                 TRUE);
3042                 break;
3043         case RTE_ETH_FILTER_DELETE:
3044                 ret = eth_igb_syn_filter_set(dev,
3045                                 (struct rte_eth_syn_filter *)arg,
3046                                 FALSE);
3047                 break;
3048         case RTE_ETH_FILTER_GET:
3049                 ret = eth_igb_syn_filter_get(dev,
3050                                 (struct rte_eth_syn_filter *)arg);
3051                 break;
3052         default:
3053                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3054                 ret = -EINVAL;
3055                 break;
3056         }
3057
3058         return ret;
3059 }
3060
3061 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3062         if ((type) != e1000_82580 && (type) != e1000_i350)\
3063                 return -ENOSYS; \
3064 } while (0)
3065
3066 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3067 static inline int
3068 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3069                         struct e1000_2tuple_filter_info *filter_info)
3070 {
3071         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3072                 return -EINVAL;
3073         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3074                 return -EINVAL;  /* filter index is out of range. */
3075         if (filter->tcp_flags > TCP_FLAG_ALL)
3076                 return -EINVAL;  /* flags is invalid. */
3077
3078         switch (filter->dst_port_mask) {
3079         case UINT16_MAX:
3080                 filter_info->dst_port_mask = 0;
3081                 filter_info->dst_port = filter->dst_port;
3082                 break;
3083         case 0:
3084                 filter_info->dst_port_mask = 1;
3085                 break;
3086         default:
3087                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3088                 return -EINVAL;
3089         }
3090
3091         switch (filter->proto_mask) {
3092         case UINT8_MAX:
3093                 filter_info->proto_mask = 0;
3094                 filter_info->proto = filter->proto;
3095                 break;
3096         case 0:
3097                 filter_info->proto_mask = 1;
3098                 break;
3099         default:
3100                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3101                 return -EINVAL;
3102         }
3103
3104         filter_info->priority = (uint8_t)filter->priority;
3105         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3106                 filter_info->tcp_flags = filter->tcp_flags;
3107         else
3108                 filter_info->tcp_flags = 0;
3109
3110         return 0;
3111 }
3112
3113 static inline struct e1000_2tuple_filter *
3114 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3115                         struct e1000_2tuple_filter_info *key)
3116 {
3117         struct e1000_2tuple_filter *it;
3118
3119         TAILQ_FOREACH(it, filter_list, entries) {
3120                 if (memcmp(key, &it->filter_info,
3121                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3122                         return it;
3123                 }
3124         }
3125         return NULL;
3126 }
3127
3128 /*
3129  * igb_add_2tuple_filter - add a 2tuple filter
3130  *
3131  * @param
3132  * dev: Pointer to struct rte_eth_dev.
3133  * ntuple_filter: ponter to the filter that will be added.
3134  *
3135  * @return
3136  *    - On success, zero.
3137  *    - On failure, a negative value.
3138  */
3139 static int
3140 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3141                         struct rte_eth_ntuple_filter *ntuple_filter)
3142 {
3143         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144         struct e1000_filter_info *filter_info =
3145                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3146         struct e1000_2tuple_filter *filter;
3147         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3148         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3149         int i, ret;
3150
3151         filter = rte_zmalloc("e1000_2tuple_filter",
3152                         sizeof(struct e1000_2tuple_filter), 0);
3153         if (filter == NULL)
3154                 return -ENOMEM;
3155
3156         ret = ntuple_filter_to_2tuple(ntuple_filter,
3157                                       &filter->filter_info);
3158         if (ret < 0) {
3159                 rte_free(filter);
3160                 return ret;
3161         }
3162         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3163                                          &filter->filter_info) != NULL) {
3164                 PMD_DRV_LOG(ERR, "filter exists.");
3165                 rte_free(filter);
3166                 return -EEXIST;
3167         }
3168         filter->queue = ntuple_filter->queue;
3169
3170         /*
3171          * look for an unused 2tuple filter index,
3172          * and insert the filter to list.
3173          */
3174         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3175                 if (!(filter_info->twotuple_mask & (1 << i))) {
3176                         filter_info->twotuple_mask |= 1 << i;
3177                         filter->index = i;
3178                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3179                                           filter,
3180                                           entries);
3181                         break;
3182                 }
3183         }
3184         if (i >= E1000_MAX_TTQF_FILTERS) {
3185                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3186                 rte_free(filter);
3187                 return -ENOSYS;
3188         }
3189
3190         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3191         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3192                 imir |= E1000_IMIR_PORT_BP;
3193         else
3194                 imir &= ~E1000_IMIR_PORT_BP;
3195
3196         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3197
3198         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3199         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3200         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3201         if (filter->filter_info.proto_mask == 0)
3202                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3203
3204         /* tcp flags bits setting. */
3205         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3206                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3207                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3208                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3209                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3210                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3211                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3212                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3213                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3214                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3215                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3216                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3217                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3218         } else
3219                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3220         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3221         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3222         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3223         return 0;
3224 }
3225
3226 /*
3227  * igb_remove_2tuple_filter - remove a 2tuple filter
3228  *
3229  * @param
3230  * dev: Pointer to struct rte_eth_dev.
3231  * ntuple_filter: ponter to the filter that will be removed.
3232  *
3233  * @return
3234  *    - On success, zero.
3235  *    - On failure, a negative value.
3236  */
3237 static int
3238 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3239                         struct rte_eth_ntuple_filter *ntuple_filter)
3240 {
3241         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242         struct e1000_filter_info *filter_info =
3243                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3244         struct e1000_2tuple_filter_info filter_2tuple;
3245         struct e1000_2tuple_filter *filter;
3246         int ret;
3247
3248         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3249         ret = ntuple_filter_to_2tuple(ntuple_filter,
3250                                       &filter_2tuple);
3251         if (ret < 0)
3252                 return ret;
3253
3254         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3255                                          &filter_2tuple);
3256         if (filter == NULL) {
3257                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3258                 return -ENOENT;
3259         }
3260
3261         filter_info->twotuple_mask &= ~(1 << filter->index);
3262         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3263         rte_free(filter);
3264
3265         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3266         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3267         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3268         return 0;
3269 }
3270
3271 static inline struct e1000_flex_filter *
3272 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3273                         struct e1000_flex_filter_info *key)
3274 {
3275         struct e1000_flex_filter *it;
3276
3277         TAILQ_FOREACH(it, filter_list, entries) {
3278                 if (memcmp(key, &it->filter_info,
3279                         sizeof(struct e1000_flex_filter_info)) == 0)
3280                         return it;
3281         }
3282
3283         return NULL;
3284 }
3285
3286 static int
3287 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3288                         struct rte_eth_flex_filter *filter,
3289                         bool add)
3290 {
3291         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292         struct e1000_filter_info *filter_info =
3293                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3294         struct e1000_flex_filter *flex_filter, *it;
3295         uint32_t wufc, queueing, mask;
3296         uint32_t reg_off;
3297         uint8_t shift, i, j = 0;
3298
3299         flex_filter = rte_zmalloc("e1000_flex_filter",
3300                         sizeof(struct e1000_flex_filter), 0);
3301         if (flex_filter == NULL)
3302                 return -ENOMEM;
3303
3304         flex_filter->filter_info.len = filter->len;
3305         flex_filter->filter_info.priority = filter->priority;
3306         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3307         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3308                 mask = 0;
3309                 /* reverse bits in flex filter's mask*/
3310                 for (shift = 0; shift < CHAR_BIT; shift++) {
3311                         if (filter->mask[i] & (0x01 << shift))
3312                                 mask |= (0x80 >> shift);
3313                 }
3314                 flex_filter->filter_info.mask[i] = mask;
3315         }
3316
3317         wufc = E1000_READ_REG(hw, E1000_WUFC);
3318         if (flex_filter->index < E1000_MAX_FHFT)
3319                 reg_off = E1000_FHFT(flex_filter->index);
3320         else
3321                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3322
3323         if (add) {
3324                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3325                                 &flex_filter->filter_info) != NULL) {
3326                         PMD_DRV_LOG(ERR, "filter exists.");
3327                         rte_free(flex_filter);
3328                         return -EEXIST;
3329                 }
3330                 flex_filter->queue = filter->queue;
3331                 /*
3332                  * look for an unused flex filter index
3333                  * and insert the filter into the list.
3334                  */
3335                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3336                         if (!(filter_info->flex_mask & (1 << i))) {
3337                                 filter_info->flex_mask |= 1 << i;
3338                                 flex_filter->index = i;
3339                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3340                                         flex_filter,
3341                                         entries);
3342                                 break;
3343                         }
3344                 }
3345                 if (i >= E1000_MAX_FLEX_FILTERS) {
3346                         PMD_DRV_LOG(ERR, "flex filters are full.");
3347                         rte_free(flex_filter);
3348                         return -ENOSYS;
3349                 }
3350
3351                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3352                                 (E1000_WUFC_FLX0 << flex_filter->index));
3353                 queueing = filter->len |
3354                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3355                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3356                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3357                                 queueing);
3358                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3359                         E1000_WRITE_REG(hw, reg_off,
3360                                         flex_filter->filter_info.dwords[j]);
3361                         reg_off += sizeof(uint32_t);
3362                         E1000_WRITE_REG(hw, reg_off,
3363                                         flex_filter->filter_info.dwords[++j]);
3364                         reg_off += sizeof(uint32_t);
3365                         E1000_WRITE_REG(hw, reg_off,
3366                                 (uint32_t)flex_filter->filter_info.mask[i]);
3367                         reg_off += sizeof(uint32_t) * 2;
3368                         ++j;
3369                 }
3370         } else {
3371                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3372                                 &flex_filter->filter_info);
3373                 if (it == NULL) {
3374                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3375                         rte_free(flex_filter);
3376                         return -ENOENT;
3377                 }
3378
3379                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3380                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3381                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3382                         (~(E1000_WUFC_FLX0 << it->index)));
3383
3384                 filter_info->flex_mask &= ~(1 << it->index);
3385                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3386                 rte_free(it);
3387                 rte_free(flex_filter);
3388         }
3389
3390         return 0;
3391 }
3392
3393 static int
3394 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3395                         struct rte_eth_flex_filter *filter)
3396 {
3397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398         struct e1000_filter_info *filter_info =
3399                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3400         struct e1000_flex_filter flex_filter, *it;
3401         uint32_t wufc, queueing, wufc_en = 0;
3402
3403         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3404         flex_filter.filter_info.len = filter->len;
3405         flex_filter.filter_info.priority = filter->priority;
3406         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3407         memcpy(flex_filter.filter_info.mask, filter->mask,
3408                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3409
3410         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3411                                 &flex_filter.filter_info);
3412         if (it == NULL) {
3413                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3414                 return -ENOENT;
3415         }
3416
3417         wufc = E1000_READ_REG(hw, E1000_WUFC);
3418         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3419
3420         if ((wufc & wufc_en) == wufc_en) {
3421                 uint32_t reg_off = 0;
3422                 if (it->index < E1000_MAX_FHFT)
3423                         reg_off = E1000_FHFT(it->index);
3424                 else
3425                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3426
3427                 queueing = E1000_READ_REG(hw,
3428                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3429                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3430                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3431                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3432                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3433                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3434                 return 0;
3435         }
3436         return -ENOENT;
3437 }
3438
3439 static int
3440 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3441                         enum rte_filter_op filter_op,
3442                         void *arg)
3443 {
3444         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct rte_eth_flex_filter *filter;
3446         int ret = 0;
3447
3448         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3449
3450         if (filter_op == RTE_ETH_FILTER_NOP)
3451                 return ret;
3452
3453         if (arg == NULL) {
3454                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3455                             filter_op);
3456                 return -EINVAL;
3457         }
3458
3459         filter = (struct rte_eth_flex_filter *)arg;
3460         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3461             || filter->len % sizeof(uint64_t) != 0) {
3462                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3463                 return -EINVAL;
3464         }
3465         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3466                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3467                 return -EINVAL;
3468         }
3469
3470         switch (filter_op) {
3471         case RTE_ETH_FILTER_ADD:
3472                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3473                 break;
3474         case RTE_ETH_FILTER_DELETE:
3475                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3476                 break;
3477         case RTE_ETH_FILTER_GET:
3478                 ret = eth_igb_get_flex_filter(dev, filter);
3479                 break;
3480         default:
3481                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3482                 ret = -EINVAL;
3483                 break;
3484         }
3485
3486         return ret;
3487 }
3488
3489 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3490 static inline int
3491 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3492                         struct e1000_5tuple_filter_info *filter_info)
3493 {
3494         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3495                 return -EINVAL;
3496         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3497                 return -EINVAL;  /* filter index is out of range. */
3498         if (filter->tcp_flags > TCP_FLAG_ALL)
3499                 return -EINVAL;  /* flags is invalid. */
3500
3501         switch (filter->dst_ip_mask) {
3502         case UINT32_MAX:
3503                 filter_info->dst_ip_mask = 0;
3504                 filter_info->dst_ip = filter->dst_ip;
3505                 break;
3506         case 0:
3507                 filter_info->dst_ip_mask = 1;
3508                 break;
3509         default:
3510                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3511                 return -EINVAL;
3512         }
3513
3514         switch (filter->src_ip_mask) {
3515         case UINT32_MAX:
3516                 filter_info->src_ip_mask = 0;
3517                 filter_info->src_ip = filter->src_ip;
3518                 break;
3519         case 0:
3520                 filter_info->src_ip_mask = 1;
3521                 break;
3522         default:
3523                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3524                 return -EINVAL;
3525         }
3526
3527         switch (filter->dst_port_mask) {
3528         case UINT16_MAX:
3529                 filter_info->dst_port_mask = 0;
3530                 filter_info->dst_port = filter->dst_port;
3531                 break;
3532         case 0:
3533                 filter_info->dst_port_mask = 1;
3534                 break;
3535         default:
3536                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3537                 return -EINVAL;
3538         }
3539
3540         switch (filter->src_port_mask) {
3541         case UINT16_MAX:
3542                 filter_info->src_port_mask = 0;
3543                 filter_info->src_port = filter->src_port;
3544                 break;
3545         case 0:
3546                 filter_info->src_port_mask = 1;
3547                 break;
3548         default:
3549                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3550                 return -EINVAL;
3551         }
3552
3553         switch (filter->proto_mask) {
3554         case UINT8_MAX:
3555                 filter_info->proto_mask = 0;
3556                 filter_info->proto = filter->proto;
3557                 break;
3558         case 0:
3559                 filter_info->proto_mask = 1;
3560                 break;
3561         default:
3562                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3563                 return -EINVAL;
3564         }
3565
3566         filter_info->priority = (uint8_t)filter->priority;
3567         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3568                 filter_info->tcp_flags = filter->tcp_flags;
3569         else
3570                 filter_info->tcp_flags = 0;
3571
3572         return 0;
3573 }
3574
3575 static inline struct e1000_5tuple_filter *
3576 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3577                         struct e1000_5tuple_filter_info *key)
3578 {
3579         struct e1000_5tuple_filter *it;
3580
3581         TAILQ_FOREACH(it, filter_list, entries) {
3582                 if (memcmp(key, &it->filter_info,
3583                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3584                         return it;
3585                 }
3586         }
3587         return NULL;
3588 }
3589
3590 /*
3591  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3592  *
3593  * @param
3594  * dev: Pointer to struct rte_eth_dev.
3595  * ntuple_filter: ponter to the filter that will be added.
3596  *
3597  * @return
3598  *    - On success, zero.
3599  *    - On failure, a negative value.
3600  */
3601 static int
3602 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3603                         struct rte_eth_ntuple_filter *ntuple_filter)
3604 {
3605         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606         struct e1000_filter_info *filter_info =
3607                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3608         struct e1000_5tuple_filter *filter;
3609         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3610         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3611         uint8_t i;
3612         int ret;
3613
3614         filter = rte_zmalloc("e1000_5tuple_filter",
3615                         sizeof(struct e1000_5tuple_filter), 0);
3616         if (filter == NULL)
3617                 return -ENOMEM;
3618
3619         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3620                                             &filter->filter_info);
3621         if (ret < 0) {
3622                 rte_free(filter);
3623                 return ret;
3624         }
3625
3626         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3627                                          &filter->filter_info) != NULL) {
3628                 PMD_DRV_LOG(ERR, "filter exists.");
3629                 rte_free(filter);
3630                 return -EEXIST;
3631         }
3632         filter->queue = ntuple_filter->queue;
3633
3634         /*
3635          * look for an unused 5tuple filter index,
3636          * and insert the filter to list.
3637          */
3638         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3639                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3640                         filter_info->fivetuple_mask |= 1 << i;
3641                         filter->index = i;
3642                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3643                                           filter,
3644                                           entries);
3645                         break;
3646                 }
3647         }
3648         if (i >= E1000_MAX_FTQF_FILTERS) {
3649                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3650                 rte_free(filter);
3651                 return -ENOSYS;
3652         }
3653
3654         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3655         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3656                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3657         if (filter->filter_info.dst_ip_mask == 0)
3658                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3659         if (filter->filter_info.src_port_mask == 0)
3660                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3661         if (filter->filter_info.proto_mask == 0)
3662                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3663         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3664                 E1000_FTQF_QUEUE_MASK;
3665         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3666         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3667         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3668         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3669
3670         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3671         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3672
3673         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3674         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3675                 imir |= E1000_IMIR_PORT_BP;
3676         else
3677                 imir &= ~E1000_IMIR_PORT_BP;
3678         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3679
3680         /* tcp flags bits setting. */
3681         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3682                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3683                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3684                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3685                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3686                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3687                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3688                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3689                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3690                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3691                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3692                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3693                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3694         } else
3695                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3696         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3697         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3698         return 0;
3699 }
3700
3701 /*
3702  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3703  *
3704  * @param
3705  * dev: Pointer to struct rte_eth_dev.
3706  * ntuple_filter: ponter to the filter that will be removed.
3707  *
3708  * @return
3709  *    - On success, zero.
3710  *    - On failure, a negative value.
3711  */
3712 static int
3713 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3714                                 struct rte_eth_ntuple_filter *ntuple_filter)
3715 {
3716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717         struct e1000_filter_info *filter_info =
3718                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3719         struct e1000_5tuple_filter_info filter_5tuple;
3720         struct e1000_5tuple_filter *filter;
3721         int ret;
3722
3723         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3724         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3725                                             &filter_5tuple);
3726         if (ret < 0)
3727                 return ret;
3728
3729         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3730                                          &filter_5tuple);
3731         if (filter == NULL) {
3732                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3733                 return -ENOENT;
3734         }
3735
3736         filter_info->fivetuple_mask &= ~(1 << filter->index);
3737         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3738         rte_free(filter);
3739
3740         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3741                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3742         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3743         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3744         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3745         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3746         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3747         return 0;
3748 }
3749
3750 static int
3751 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3752 {
3753         uint32_t rctl;
3754         struct e1000_hw *hw;
3755         struct rte_eth_dev_info dev_info;
3756         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3757                                      VLAN_TAG_SIZE);
3758
3759         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3760
3761 #ifdef RTE_LIBRTE_82571_SUPPORT
3762         /* XXX: not bigger than max_rx_pktlen */
3763         if (hw->mac.type == e1000_82571)
3764                 return -ENOTSUP;
3765 #endif
3766         eth_igb_infos_get(dev, &dev_info);
3767
3768         /* check that mtu is within the allowed range */
3769         if ((mtu < ETHER_MIN_MTU) ||
3770             (frame_size > dev_info.max_rx_pktlen))
3771                 return -EINVAL;
3772
3773         /* refuse mtu that requires the support of scattered packets when this
3774          * feature has not been enabled before. */
3775         if (!dev->data->scattered_rx &&
3776             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3777                 return -EINVAL;
3778
3779         rctl = E1000_READ_REG(hw, E1000_RCTL);
3780
3781         /* switch to jumbo mode if needed */
3782         if (frame_size > ETHER_MAX_LEN) {
3783                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3784                 rctl |= E1000_RCTL_LPE;
3785         } else {
3786                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3787                 rctl &= ~E1000_RCTL_LPE;
3788         }
3789         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3790
3791         /* update max frame size */
3792         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3793
3794         E1000_WRITE_REG(hw, E1000_RLPML,
3795                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3796
3797         return 0;
3798 }
3799
3800 /*
3801  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3802  *
3803  * @param
3804  * dev: Pointer to struct rte_eth_dev.
3805  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3806  * add: if true, add filter, if false, remove filter
3807  *
3808  * @return
3809  *    - On success, zero.
3810  *    - On failure, a negative value.
3811  */
3812 static int
3813 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3814                         struct rte_eth_ntuple_filter *ntuple_filter,
3815                         bool add)
3816 {
3817         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818         int ret;
3819
3820         switch (ntuple_filter->flags) {
3821         case RTE_5TUPLE_FLAGS:
3822         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3823                 if (hw->mac.type != e1000_82576)
3824                         return -ENOTSUP;
3825                 if (add)
3826                         ret = igb_add_5tuple_filter_82576(dev,
3827                                                           ntuple_filter);
3828                 else
3829                         ret = igb_remove_5tuple_filter_82576(dev,
3830                                                              ntuple_filter);
3831                 break;
3832         case RTE_2TUPLE_FLAGS:
3833         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3834                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3835                         return -ENOTSUP;
3836                 if (add)
3837                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3838                 else
3839                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3840                 break;
3841         default:
3842                 ret = -EINVAL;
3843                 break;
3844         }
3845
3846         return ret;
3847 }
3848
3849 /*
3850  * igb_get_ntuple_filter - get a ntuple filter
3851  *
3852  * @param
3853  * dev: Pointer to struct rte_eth_dev.
3854  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3855  *
3856  * @return
3857  *    - On success, zero.
3858  *    - On failure, a negative value.
3859  */
3860 static int
3861 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3862                         struct rte_eth_ntuple_filter *ntuple_filter)
3863 {
3864         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3865         struct e1000_filter_info *filter_info =
3866                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3867         struct e1000_5tuple_filter_info filter_5tuple;
3868         struct e1000_2tuple_filter_info filter_2tuple;
3869         struct e1000_5tuple_filter *p_5tuple_filter;
3870         struct e1000_2tuple_filter *p_2tuple_filter;
3871         int ret;
3872
3873         switch (ntuple_filter->flags) {
3874         case RTE_5TUPLE_FLAGS:
3875         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3876                 if (hw->mac.type != e1000_82576)
3877                         return -ENOTSUP;
3878                 memset(&filter_5tuple,
3879                         0,
3880                         sizeof(struct e1000_5tuple_filter_info));
3881                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3882                                                     &filter_5tuple);
3883                 if (ret < 0)
3884                         return ret;
3885                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3886                                         &filter_info->fivetuple_list,
3887                                         &filter_5tuple);
3888                 if (p_5tuple_filter == NULL) {
3889                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3890                         return -ENOENT;
3891                 }
3892                 ntuple_filter->queue = p_5tuple_filter->queue;
3893                 break;
3894         case RTE_2TUPLE_FLAGS:
3895         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3896                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3897                         return -ENOTSUP;
3898                 memset(&filter_2tuple,
3899                         0,
3900                         sizeof(struct e1000_2tuple_filter_info));
3901                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3902                 if (ret < 0)
3903                         return ret;
3904                 p_2tuple_filter = igb_2tuple_filter_lookup(
3905                                         &filter_info->twotuple_list,
3906                                         &filter_2tuple);
3907                 if (p_2tuple_filter == NULL) {
3908                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3909                         return -ENOENT;
3910                 }
3911                 ntuple_filter->queue = p_2tuple_filter->queue;
3912                 break;
3913         default:
3914                 ret = -EINVAL;
3915                 break;
3916         }
3917
3918         return 0;
3919 }
3920
3921 /*
3922  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3923  * @dev: pointer to rte_eth_dev structure
3924  * @filter_op:operation will be taken.
3925  * @arg: a pointer to specific structure corresponding to the filter_op
3926  */
3927 static int
3928 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3929                                 enum rte_filter_op filter_op,
3930                                 void *arg)
3931 {
3932         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         int ret;
3934
3935         MAC_TYPE_FILTER_SUP(hw->mac.type);
3936
3937         if (filter_op == RTE_ETH_FILTER_NOP)
3938                 return 0;
3939
3940         if (arg == NULL) {
3941                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3942                             filter_op);
3943                 return -EINVAL;
3944         }
3945
3946         switch (filter_op) {
3947         case RTE_ETH_FILTER_ADD:
3948                 ret = igb_add_del_ntuple_filter(dev,
3949                         (struct rte_eth_ntuple_filter *)arg,
3950                         TRUE);
3951                 break;
3952         case RTE_ETH_FILTER_DELETE:
3953                 ret = igb_add_del_ntuple_filter(dev,
3954                         (struct rte_eth_ntuple_filter *)arg,
3955                         FALSE);
3956                 break;
3957         case RTE_ETH_FILTER_GET:
3958                 ret = igb_get_ntuple_filter(dev,
3959                         (struct rte_eth_ntuple_filter *)arg);
3960                 break;
3961         default:
3962                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3963                 ret = -EINVAL;
3964                 break;
3965         }
3966         return ret;
3967 }
3968
3969 static inline int
3970 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3971                         uint16_t ethertype)
3972 {
3973         int i;
3974
3975         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3976                 if (filter_info->ethertype_filters[i] == ethertype &&
3977                     (filter_info->ethertype_mask & (1 << i)))
3978                         return i;
3979         }
3980         return -1;
3981 }
3982
3983 static inline int
3984 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3985                         uint16_t ethertype)
3986 {
3987         int i;
3988
3989         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3990                 if (!(filter_info->ethertype_mask & (1 << i))) {
3991                         filter_info->ethertype_mask |= 1 << i;
3992                         filter_info->ethertype_filters[i] = ethertype;
3993                         return i;
3994                 }
3995         }
3996         return -1;
3997 }
3998
3999 static inline int
4000 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4001                         uint8_t idx)
4002 {
4003         if (idx >= E1000_MAX_ETQF_FILTERS)
4004                 return -1;
4005         filter_info->ethertype_mask &= ~(1 << idx);
4006         filter_info->ethertype_filters[idx] = 0;
4007         return idx;
4008 }
4009
4010
4011 static int
4012 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4013                         struct rte_eth_ethertype_filter *filter,
4014                         bool add)
4015 {
4016         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017         struct e1000_filter_info *filter_info =
4018                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4019         uint32_t etqf = 0;
4020         int ret;
4021
4022         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4023                 filter->ether_type == ETHER_TYPE_IPv6) {
4024                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4025                         " ethertype filter.", filter->ether_type);
4026                 return -EINVAL;
4027         }
4028
4029         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4030                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4031                 return -EINVAL;
4032         }
4033         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4034                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4035                 return -EINVAL;
4036         }
4037
4038         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4039         if (ret >= 0 && add) {
4040                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4041                             filter->ether_type);
4042                 return -EEXIST;
4043         }
4044         if (ret < 0 && !add) {
4045                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4046                             filter->ether_type);
4047                 return -ENOENT;
4048         }
4049
4050         if (add) {
4051                 ret = igb_ethertype_filter_insert(filter_info,
4052                         filter->ether_type);
4053                 if (ret < 0) {
4054                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4055                         return -ENOSYS;
4056                 }
4057
4058                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4059                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4060                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4061         } else {
4062                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4063                 if (ret < 0)
4064                         return -ENOSYS;
4065         }
4066         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4067         E1000_WRITE_FLUSH(hw);
4068
4069         return 0;
4070 }
4071
4072 static int
4073 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4074                         struct rte_eth_ethertype_filter *filter)
4075 {
4076         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         struct e1000_filter_info *filter_info =
4078                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4079         uint32_t etqf;
4080         int ret;
4081
4082         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4083         if (ret < 0) {
4084                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4085                             filter->ether_type);
4086                 return -ENOENT;
4087         }
4088
4089         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4090         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4091                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4092                 filter->flags = 0;
4093                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4094                                 E1000_ETQF_QUEUE_SHIFT;
4095                 return 0;
4096         }
4097
4098         return -ENOENT;
4099 }
4100
4101 /*
4102  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4103  * @dev: pointer to rte_eth_dev structure
4104  * @filter_op:operation will be taken.
4105  * @arg: a pointer to specific structure corresponding to the filter_op
4106  */
4107 static int
4108 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4109                                 enum rte_filter_op filter_op,
4110                                 void *arg)
4111 {
4112         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113         int ret;
4114
4115         MAC_TYPE_FILTER_SUP(hw->mac.type);
4116
4117         if (filter_op == RTE_ETH_FILTER_NOP)
4118                 return 0;
4119
4120         if (arg == NULL) {
4121                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4122                             filter_op);
4123                 return -EINVAL;
4124         }
4125
4126         switch (filter_op) {
4127         case RTE_ETH_FILTER_ADD:
4128                 ret = igb_add_del_ethertype_filter(dev,
4129                         (struct rte_eth_ethertype_filter *)arg,
4130                         TRUE);
4131                 break;
4132         case RTE_ETH_FILTER_DELETE:
4133                 ret = igb_add_del_ethertype_filter(dev,
4134                         (struct rte_eth_ethertype_filter *)arg,
4135                         FALSE);
4136                 break;
4137         case RTE_ETH_FILTER_GET:
4138                 ret = igb_get_ethertype_filter(dev,
4139                         (struct rte_eth_ethertype_filter *)arg);
4140                 break;
4141         default:
4142                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4143                 ret = -EINVAL;
4144                 break;
4145         }
4146         return ret;
4147 }
4148
4149 static int
4150 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4151                      enum rte_filter_type filter_type,
4152                      enum rte_filter_op filter_op,
4153                      void *arg)
4154 {
4155         int ret = -EINVAL;
4156
4157         switch (filter_type) {
4158         case RTE_ETH_FILTER_NTUPLE:
4159                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4160                 break;
4161         case RTE_ETH_FILTER_ETHERTYPE:
4162                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4163                 break;
4164         case RTE_ETH_FILTER_SYN:
4165                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4166                 break;
4167         case RTE_ETH_FILTER_FLEXIBLE:
4168                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4169                 break;
4170         default:
4171                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4172                                                         filter_type);
4173                 break;
4174         }
4175
4176         return ret;
4177 }
4178
4179 static int
4180 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4181                          struct ether_addr *mc_addr_set,
4182                          uint32_t nb_mc_addr)
4183 {
4184         struct e1000_hw *hw;
4185
4186         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4188         return 0;
4189 }
4190
4191 static int
4192 igb_timesync_enable(struct rte_eth_dev *dev)
4193 {
4194         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4195         uint32_t tsync_ctl;
4196         uint32_t tsauxc;
4197
4198         /* Enable system time for it isn't on by default. */
4199         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4200         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4201         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4202
4203         /* Start incrementing the register used to timestamp PTP packets. */
4204         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
4205
4206         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4207         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4208                         (ETHER_TYPE_1588 |
4209                          E1000_ETQF_FILTER_ENABLE |
4210                          E1000_ETQF_1588));
4211
4212         /* Enable timestamping of received PTP packets. */
4213         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4214         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4215         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4216
4217         /* Enable Timestamping of transmitted PTP packets. */
4218         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4219         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4220         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4221
4222         return 0;
4223 }
4224
4225 static int
4226 igb_timesync_disable(struct rte_eth_dev *dev)
4227 {
4228         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229         uint32_t tsync_ctl;
4230
4231         /* Disable timestamping of transmitted PTP packets. */
4232         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4233         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4234         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4235
4236         /* Disable timestamping of received PTP packets. */
4237         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4238         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4239         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4240
4241         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4242         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4243
4244         /* Stop incrementating the System Time registers. */
4245         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4246
4247         return 0;
4248 }
4249
4250 static int
4251 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4252                                struct timespec *timestamp,
4253                                uint32_t flags __rte_unused)
4254 {
4255         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256         uint32_t tsync_rxctl;
4257         uint32_t rx_stmpl;
4258         uint32_t rx_stmph;
4259
4260         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4261         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4262                 return -EINVAL;
4263
4264         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
4265         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
4266
4267         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4268         timestamp->tv_nsec = 0;
4269
4270         return  0;
4271 }
4272
4273 static int
4274 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4275                                struct timespec *timestamp)
4276 {
4277         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278         uint32_t tsync_txctl;
4279         uint32_t tx_stmpl;
4280         uint32_t tx_stmph;
4281
4282         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4283         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4284                 return -EINVAL;
4285
4286         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
4287         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
4288
4289         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4290         timestamp->tv_nsec = 0;
4291
4292         return  0;
4293 }
4294
4295 static int
4296 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4297 {
4298         int count = 0;
4299         int g_ind = 0;
4300         const struct reg_info *reg_group;
4301
4302         while ((reg_group = igb_regs[g_ind++]))
4303                 count += igb_reg_group_count(reg_group);
4304
4305         return count;
4306 }
4307
4308 static int
4309 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4310 {
4311         int count = 0;
4312         int g_ind = 0;
4313         const struct reg_info *reg_group;
4314
4315         while ((reg_group = igbvf_regs[g_ind++]))
4316                 count += igb_reg_group_count(reg_group);
4317
4318         return count;
4319 }
4320
4321 static int
4322 eth_igb_get_regs(struct rte_eth_dev *dev,
4323         struct rte_dev_reg_info *regs)
4324 {
4325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326         uint32_t *data = regs->data;
4327         int g_ind = 0;
4328         int count = 0;
4329         const struct reg_info *reg_group;
4330
4331         /* Support only full register dump */
4332         if ((regs->length == 0) ||
4333             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4334                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4335                         hw->device_id;
4336                 while ((reg_group = igb_regs[g_ind++]))
4337                         count += igb_read_regs_group(dev, &data[count],
4338                                                         reg_group);
4339                 return 0;
4340         }
4341
4342         return -ENOTSUP;
4343 }
4344
4345 static int
4346 igbvf_get_regs(struct rte_eth_dev *dev,
4347         struct rte_dev_reg_info *regs)
4348 {
4349         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350         uint32_t *data = regs->data;
4351         int g_ind = 0;
4352         int count = 0;
4353         const struct reg_info *reg_group;
4354
4355         /* Support only full register dump */
4356         if ((regs->length == 0) ||
4357             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4358                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4359                         hw->device_id;
4360                 while ((reg_group = igbvf_regs[g_ind++]))
4361                         count += igb_read_regs_group(dev, &data[count],
4362                                                         reg_group);
4363                 return 0;
4364         }
4365
4366         return -ENOTSUP;
4367 }
4368
4369 static int
4370 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4371 {
4372         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373
4374         /* Return unit is byte count */
4375         return hw->nvm.word_size * 2;
4376 }
4377
4378 static int
4379 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4380         struct rte_dev_eeprom_info *in_eeprom)
4381 {
4382         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4383         struct e1000_nvm_info *nvm = &hw->nvm;
4384         uint16_t *data = in_eeprom->data;
4385         int first, length;
4386
4387         first = in_eeprom->offset >> 1;
4388         length = in_eeprom->length >> 1;
4389         if ((first >= hw->nvm.word_size) ||
4390             ((first + length) >= hw->nvm.word_size))
4391                 return -EINVAL;
4392
4393         in_eeprom->magic = hw->vendor_id |
4394                 ((uint32_t)hw->device_id << 16);
4395
4396         if ((nvm->ops.read) == NULL)
4397                 return -ENOTSUP;
4398
4399         return nvm->ops.read(hw, first, length, data);
4400 }
4401
4402 static int
4403 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4404         struct rte_dev_eeprom_info *in_eeprom)
4405 {
4406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         struct e1000_nvm_info *nvm = &hw->nvm;
4408         uint16_t *data = in_eeprom->data;
4409         int first, length;
4410
4411         first = in_eeprom->offset >> 1;
4412         length = in_eeprom->length >> 1;
4413         if ((first >= hw->nvm.word_size) ||
4414             ((first + length) >= hw->nvm.word_size))
4415                 return -EINVAL;
4416
4417         in_eeprom->magic = (uint32_t)hw->vendor_id |
4418                 ((uint32_t)hw->device_id << 16);
4419
4420         if ((nvm->ops.write) == NULL)
4421                 return -ENOTSUP;
4422         return nvm->ops.write(hw,  first, length, data);
4423 }
4424
4425 static struct rte_driver pmd_igb_drv = {
4426         .type = PMD_PDEV,
4427         .init = rte_igb_pmd_init,
4428 };
4429
4430 static struct rte_driver pmd_igbvf_drv = {
4431         .type = PMD_PDEV,
4432         .init = rte_igbvf_pmd_init,
4433 };
4434
4435 static int
4436 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4437 {
4438         struct e1000_hw *hw =
4439                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440         uint32_t mask = 1 << queue_id;
4441
4442         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4443         E1000_WRITE_FLUSH(hw);
4444
4445         return 0;
4446 }
4447
4448 static int
4449 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4450 {
4451         struct e1000_hw *hw =
4452                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4453         uint32_t mask = 1 << queue_id;
4454         uint32_t regval;
4455
4456         regval = E1000_READ_REG(hw, E1000_EIMS);
4457         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4458         E1000_WRITE_FLUSH(hw);
4459
4460         rte_intr_enable(&dev->pci_dev->intr_handle);
4461
4462         return 0;
4463 }
4464
4465 static void
4466 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4467                    uint8_t index, uint8_t offset)
4468 {
4469         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4470
4471         /* clear bits */
4472         val &= ~((uint32_t)0xFF << offset);
4473
4474         /* write vector and valid bit */
4475         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4476
4477         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4478 }
4479
4480 static void
4481 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4482                            uint8_t queue, uint8_t msix_vector)
4483 {
4484         uint32_t tmp = 0;
4485
4486         if (hw->mac.type == e1000_82575) {
4487                 if (direction == 0)
4488                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4489                 else if (direction == 1)
4490                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4491                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4492         } else if (hw->mac.type == e1000_82576) {
4493                 if ((direction == 0) || (direction == 1))
4494                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4495                                            ((queue & 0x8) << 1) +
4496                                            8 * direction);
4497         } else if ((hw->mac.type == e1000_82580) ||
4498                         (hw->mac.type == e1000_i350) ||
4499                         (hw->mac.type == e1000_i354) ||
4500                         (hw->mac.type == e1000_i210) ||
4501                         (hw->mac.type == e1000_i211)) {
4502                 if ((direction == 0) || (direction == 1))
4503                         eth_igb_write_ivar(hw, msix_vector,
4504                                            queue >> 1,
4505                                            ((queue & 0x1) << 4) +
4506                                            8 * direction);
4507         }
4508 }
4509
4510 /* Sets up the hardware to generate MSI-X interrupts properly
4511  * @hw
4512  *  board private structure
4513  */
4514 static void
4515 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4516 {
4517         int queue_id;
4518         uint32_t tmpval, regval, intr_mask;
4519         struct e1000_hw *hw =
4520                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521         uint32_t vec = E1000_MISC_VEC_ID;
4522         uint32_t base = E1000_MISC_VEC_ID;
4523         uint32_t misc_shift = 0;
4524
4525         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4526
4527         /* won't configure msix register if no mapping is done
4528          * between intr vector and event fd
4529          */
4530         if (!rte_intr_dp_is_en(intr_handle))
4531                 return;
4532
4533         if (rte_intr_allow_others(intr_handle)) {
4534                 vec = base = E1000_RX_VEC_START;
4535                 misc_shift = 1;
4536         }
4537
4538         /* set interrupt vector for other causes */
4539         if (hw->mac.type == e1000_82575) {
4540                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4541                 /* enable MSI-X PBA support */
4542                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4543
4544                 /* Auto-Mask interrupts upon ICR read */
4545                 tmpval |= E1000_CTRL_EXT_EIAME;
4546                 tmpval |= E1000_CTRL_EXT_IRCA;
4547
4548                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4549
4550                 /* enable msix_other interrupt */
4551                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4552                 regval = E1000_READ_REG(hw, E1000_EIAC);
4553                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4554                 regval = E1000_READ_REG(hw, E1000_EIAM);
4555                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4556         } else if ((hw->mac.type == e1000_82576) ||
4557                         (hw->mac.type == e1000_82580) ||
4558                         (hw->mac.type == e1000_i350) ||
4559                         (hw->mac.type == e1000_i354) ||
4560                         (hw->mac.type == e1000_i210) ||
4561                         (hw->mac.type == e1000_i211)) {
4562                 /* turn on MSI-X capability first */
4563                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4564                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4565                                         E1000_GPIE_NSICR);
4566                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4567                         misc_shift;
4568                 regval = E1000_READ_REG(hw, E1000_EIAC);
4569                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4570
4571                 /* enable msix_other interrupt */
4572                 regval = E1000_READ_REG(hw, E1000_EIMS);
4573                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4574                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4575                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4576         }
4577
4578         /* use EIAM to auto-mask when MSI-X interrupt
4579          * is asserted, this saves a register write for every interrupt
4580          */
4581         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4582                 misc_shift;
4583         regval = E1000_READ_REG(hw, E1000_EIAM);
4584         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4585
4586         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4587                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4588                 intr_handle->intr_vec[queue_id] = vec;
4589                 if (vec < base + intr_handle->nb_efd - 1)
4590                         vec++;
4591         }
4592
4593         E1000_WRITE_FLUSH(hw);
4594 }
4595
4596 PMD_REGISTER_DRIVER(pmd_igb_drv);
4597 PMD_REGISTER_DRIVER(pmd_igbvf_drv);