drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 /*
  60  * Default values for port configuration
  61  */
  62 #define IGB_DEFAULT_RX_FREE_THRESH  32
  63 #define IGB_DEFAULT_RX_PTHRESH      8
  64 #define IGB_DEFAULT_RX_HTHRESH      8
  65 #define IGB_DEFAULT_RX_WTHRESH      0
  66
  67 #define IGB_DEFAULT_TX_PTHRESH      32
  68 #define IGB_DEFAULT_TX_HTHRESH      0
  69 #define IGB_DEFAULT_TX_WTHRESH      0
  70
  71 #define IGB_HKEY_MAX_INDEX 10
  72
  73 /* Bit shift and mask */
  74 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  75 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  76 #define IGB_8_BIT_WIDTH  CHAR_BIT
  77 #define IGB_8_BIT_MASK   UINT8_MAX
  78
  79 /* Additional timesync values. */
  80 #define E1000_ETQF_FILTER_1588 3
  81 #define E1000_TIMINCA_INCVALUE 16000000
  82 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  83                                 | E1000_TIMINCA_INCVALUE)
  84
  85 static int  eth_igb_configure(struct rte_eth_dev *dev);
  86 static int  eth_igb_start(struct rte_eth_dev *dev);
  87 static void eth_igb_stop(struct rte_eth_dev *dev);
  88 static void eth_igb_close(struct rte_eth_dev *dev);
  89 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  90 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  91 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  93 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  94                                 int wait_to_complete);
  95 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  96                                 struct rte_eth_stats *rte_stats);
  97 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  98 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  99                               struct rte_eth_dev_info *dev_info);
 100 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 101                                 struct rte_eth_dev_info *dev_info);
 102 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 103                                 struct rte_eth_fc_conf *fc_conf);
 104 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 105                                 struct rte_eth_fc_conf *fc_conf);
 106 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 107 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 108 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 109 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 110                                                         void *param);
 111 static int  igb_hardware_init(struct e1000_hw *hw);
 112 static void igb_hw_control_acquire(struct e1000_hw *hw);
 113 static void igb_hw_control_release(struct e1000_hw *hw);
 114 static void igb_init_manageability(struct e1000_hw *hw);
 115 static void igb_release_manageability(struct e1000_hw *hw);
 116
 117 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 118
 119 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 120                 uint16_t vlan_id, int on);
 121 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 122 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123
 124 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 125 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 126 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 127 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 128 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 129 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 130
 131 static int eth_igb_led_on(struct rte_eth_dev *dev);
 132 static int eth_igb_led_off(struct rte_eth_dev *dev);
 133
 134 static void igb_intr_disable(struct e1000_hw *hw);
 135 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 136 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 137                 struct ether_addr *mac_addr,
 138                 uint32_t index, uint32_t pool);
 139 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 140
 141 static void igbvf_intr_disable(struct e1000_hw *hw);
 142 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 143 static int igbvf_dev_start(struct rte_eth_dev *dev);
 144 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 145 static void igbvf_dev_close(struct rte_eth_dev *dev);
 146 static int eth_igbvf_link_update(struct e1000_hw *hw);
 147 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 148 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 149 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 150                 uint16_t vlan_id, int on);
 151 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 152 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 153 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 154                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 155                                    uint16_t reta_size);
 156 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 157                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 158                                   uint16_t reta_size);
 159
 160 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 161                         struct rte_eth_syn_filter *filter,
 162                         bool add);
 163 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 164                         struct rte_eth_syn_filter *filter);
 165 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 166                         enum rte_filter_op filter_op,
 167                         void *arg);
 168 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 169                         struct rte_eth_ntuple_filter *ntuple_filter);
 170 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 171                         struct rte_eth_ntuple_filter *ntuple_filter);
 172 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 173                         struct rte_eth_flex_filter *filter,
 174                         bool add);
 175 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 176                         struct rte_eth_flex_filter *filter);
 177 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 178                         enum rte_filter_op filter_op,
 179                         void *arg);
 180 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 181                         struct rte_eth_ntuple_filter *ntuple_filter);
 182 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 183                         struct rte_eth_ntuple_filter *ntuple_filter);
 184 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 185                         struct rte_eth_ntuple_filter *filter,
 186                         bool add);
 187 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 188                         struct rte_eth_ntuple_filter *filter);
 189 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 190                                 enum rte_filter_op filter_op,
 191                                 void *arg);
 192 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_ethertype_filter *filter,
 194                         bool add);
 195 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 196                                 enum rte_filter_op filter_op,
 197                                 void *arg);
 198 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_ethertype_filter *filter);
 200 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 201                      enum rte_filter_type filter_type,
 202                      enum rte_filter_op filter_op,
 203                      void *arg);
 204
 205 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 206                                     struct ether_addr *mc_addr_set,
 207                                     uint32_t nb_mc_addr);
 208 static int igb_timesync_enable(struct rte_eth_dev *dev);
 209 static int igb_timesync_disable(struct rte_eth_dev *dev);
 210 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 211                                           struct timespec *timestamp,
 212                                           uint32_t flags);
 213 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 214                                           struct timespec *timestamp);
 215
 216 /*
 217  * Define VF Stats MACRO for Non "cleared on read" register
 218  */
 219 #define UPDATE_VF_STAT(reg, last, cur)            \
 220 {                                                 \
 221         u32 latest = E1000_READ_REG(hw, reg);     \
 222         cur += latest - last;                     \
 223         last = latest;                            \
 224 }
 225
 226
 227 #define IGB_FC_PAUSE_TIME 0x0680
 228 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 229 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 230
 231 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 232
 233 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 234
 235 /*
 236  * The set of PCI devices this driver supports
 237  */
 238 static const struct rte_pci_id pci_id_igb_map[] = {
 239
 240 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 241 #include "rte_pci_dev_ids.h"
 242
 243 {0},
 244 };
 245
 246 /*
 247  * The set of PCI devices this driver supports (for 82576&I350 VF)
 248  */
 249 static const struct rte_pci_id pci_id_igbvf_map[] = {
 250
 251 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 252 #include "rte_pci_dev_ids.h"
 253
 254 {0},
 255 };
 256
 257 static const struct eth_dev_ops eth_igb_ops = {
 258         .dev_configure        = eth_igb_configure,
 259         .dev_start            = eth_igb_start,
 260         .dev_stop             = eth_igb_stop,
 261         .dev_close            = eth_igb_close,
 262         .promiscuous_enable   = eth_igb_promiscuous_enable,
 263         .promiscuous_disable  = eth_igb_promiscuous_disable,
 264         .allmulticast_enable  = eth_igb_allmulticast_enable,
 265         .allmulticast_disable = eth_igb_allmulticast_disable,
 266         .link_update          = eth_igb_link_update,
 267         .stats_get            = eth_igb_stats_get,
 268         .stats_reset          = eth_igb_stats_reset,
 269         .dev_infos_get        = eth_igb_infos_get,
 270         .mtu_set              = eth_igb_mtu_set,
 271         .vlan_filter_set      = eth_igb_vlan_filter_set,
 272         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 273         .vlan_offload_set     = eth_igb_vlan_offload_set,
 274         .rx_queue_setup       = eth_igb_rx_queue_setup,
 275         .rx_queue_release     = eth_igb_rx_queue_release,
 276         .rx_queue_count       = eth_igb_rx_queue_count,
 277         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 278         .tx_queue_setup       = eth_igb_tx_queue_setup,
 279         .tx_queue_release     = eth_igb_tx_queue_release,
 280         .dev_led_on           = eth_igb_led_on,
 281         .dev_led_off          = eth_igb_led_off,
 282         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 283         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 284         .mac_addr_add         = eth_igb_rar_set,
 285         .mac_addr_remove      = eth_igb_rar_clear,
 286         .reta_update          = eth_igb_rss_reta_update,
 287         .reta_query           = eth_igb_rss_reta_query,
 288         .rss_hash_update      = eth_igb_rss_hash_update,
 289         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 290         .filter_ctrl          = eth_igb_filter_ctrl,
 291         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 292         .timesync_enable      = igb_timesync_enable,
 293         .timesync_disable     = igb_timesync_disable,
 294         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 295         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 296 };
 297
 298 /*
 299  * dev_ops for virtual function, bare necessities for basic vf
 300  * operation have been implemented
 301  */
 302 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 303         .dev_configure        = igbvf_dev_configure,
 304         .dev_start            = igbvf_dev_start,
 305         .dev_stop             = igbvf_dev_stop,
 306         .dev_close            = igbvf_dev_close,
 307         .link_update          = eth_igb_link_update,
 308         .stats_get            = eth_igbvf_stats_get,
 309         .stats_reset          = eth_igbvf_stats_reset,
 310         .vlan_filter_set      = igbvf_vlan_filter_set,
 311         .dev_infos_get        = eth_igbvf_infos_get,
 312         .rx_queue_setup       = eth_igb_rx_queue_setup,
 313         .rx_queue_release     = eth_igb_rx_queue_release,
 314         .tx_queue_setup       = eth_igb_tx_queue_setup,
 315         .tx_queue_release     = eth_igb_tx_queue_release,
 316         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 317 };
 318
 319 /**
 320  * Atomically reads the link status information from global
 321  * structure rte_eth_dev.
 322  *
 323  * @param dev
 324  *   - Pointer to the structure rte_eth_dev to read from.
 325  *   - Pointer to the buffer to be saved with the link status.
 326  *
 327  * @return
 328  *   - On success, zero.
 329  *   - On failure, negative value.
 330  */
 331 static inline int
 332 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 333                                 struct rte_eth_link *link)
 334 {
 335         struct rte_eth_link *dst = link;
 336         struct rte_eth_link *src = &(dev->data->dev_link);
 337
 338         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 339                                         *(uint64_t *)src) == 0)
 340                 return -1;
 341
 342         return 0;
 343 }
 344
 345 /**
 346  * Atomically writes the link status information into global
 347  * structure rte_eth_dev.
 348  *
 349  * @param dev
 350  *   - Pointer to the structure rte_eth_dev to read from.
 351  *   - Pointer to the buffer to be saved with the link status.
 352  *
 353  * @return
 354  *   - On success, zero.
 355  *   - On failure, negative value.
 356  */
 357 static inline int
 358 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 359                                 struct rte_eth_link *link)
 360 {
 361         struct rte_eth_link *dst = &(dev->data->dev_link);
 362         struct rte_eth_link *src = link;
 363
 364         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 365                                         *(uint64_t *)src) == 0)
 366                 return -1;
 367
 368         return 0;
 369 }
 370
 371 static inline void
 372 igb_intr_enable(struct rte_eth_dev *dev)
 373 {
 374         struct e1000_interrupt *intr =
 375                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 376         struct e1000_hw *hw =
 377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 378
 379         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 380         E1000_WRITE_FLUSH(hw);
 381 }
 382
 383 static void
 384 igb_intr_disable(struct e1000_hw *hw)
 385 {
 386         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 387         E1000_WRITE_FLUSH(hw);
 388 }
 389
 390 static inline int32_t
 391 igb_pf_reset_hw(struct e1000_hw *hw)
 392 {
 393         uint32_t ctrl_ext;
 394         int32_t status;
 395
 396         status = e1000_reset_hw(hw);
 397
 398         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 399         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 400         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 401         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 402         E1000_WRITE_FLUSH(hw);
 403
 404         return status;
 405 }
 406
 407 static void
 408 igb_identify_hardware(struct rte_eth_dev *dev)
 409 {
 410         struct e1000_hw *hw =
 411                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 412
 413         hw->vendor_id = dev->pci_dev->id.vendor_id;
 414         hw->device_id = dev->pci_dev->id.device_id;
 415         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 416         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 417
 418         e1000_set_mac_type(hw);
 419
 420         /* need to check if it is a vf device below */
 421 }
 422
 423 static int
 424 igb_reset_swfw_lock(struct e1000_hw *hw)
 425 {
 426         int ret_val;
 427
 428         /*
 429          * Do mac ops initialization manually here, since we will need
 430          * some function pointers set by this call.
 431          */
 432         ret_val = e1000_init_mac_params(hw);
 433         if (ret_val)
 434                 return ret_val;
 435
 436         /*
 437          * SMBI lock should not fail in this early stage. If this is the case,
 438          * it is due to an improper exit of the application.
 439          * So force the release of the faulty lock.
 440          */
 441         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 442                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 443         }
 444         e1000_put_hw_semaphore_generic(hw);
 445
 446         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 447                 uint16_t mask;
 448
 449                 /*
 450                  * Phy lock should not fail in this early stage. If this is the case,
 451                  * it is due to an improper exit of the application.
 452                  * So force the release of the faulty lock.
 453                  */
 454                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 455                 if (hw->bus.func > E1000_FUNC_1)
 456                         mask <<= 2;
 457                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 458                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 459                                     hw->bus.func);
 460                 }
 461                 hw->mac.ops.release_swfw_sync(hw, mask);
 462
 463                 /*
 464                  * This one is more tricky since it is common to all ports; but
 465                  * swfw_sync retries last long enough (1s) to be almost sure that if
 466                  * lock can not be taken it is due to an improper lock of the
 467                  * semaphore.
 468                  */
 469                 mask = E1000_SWFW_EEP_SM;
 470                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 471                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 472                 }
 473                 hw->mac.ops.release_swfw_sync(hw, mask);
 474         }
 475
 476         return E1000_SUCCESS;
 477 }
 478
 479 static int
 480 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 481 {
 482         int error = 0;
 483         struct rte_pci_device *pci_dev;
 484         struct e1000_hw *hw =
 485                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 486         struct e1000_vfta * shadow_vfta =
 487                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 488         struct e1000_filter_info *filter_info =
 489                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 490         uint32_t ctrl_ext;
 491
 492         pci_dev = eth_dev->pci_dev;
 493         eth_dev->dev_ops = &eth_igb_ops;
 494         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 495         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 496
 497         /* for secondary processes, we don't initialise any further as primary
 498          * has already done this work. Only check we don't need a different
 499          * RX function */
 500         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 501                 if (eth_dev->data->scattered_rx)
 502                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 503                 return 0;
 504         }
 505
 506         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 507
 508         igb_identify_hardware(eth_dev);
 509         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 510                 error = -EIO;
 511                 goto err_late;
 512         }
 513
 514         e1000_get_bus_info(hw);
 515
 516         /* Reset any pending lock */
 517         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 518                 error = -EIO;
 519                 goto err_late;
 520         }
 521
 522         /* Finish initialization */
 523         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 524                 error = -EIO;
 525                 goto err_late;
 526         }
 527
 528         hw->mac.autoneg = 1;
 529         hw->phy.autoneg_wait_to_complete = 0;
 530         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 531
 532         /* Copper options */
 533         if (hw->phy.media_type == e1000_media_type_copper) {
 534                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 535                 hw->phy.disable_polarity_correction = 0;
 536                 hw->phy.ms_type = e1000_ms_hw_default;
 537         }
 538
 539         /*
 540          * Start from a known state, this is important in reading the nvm
 541          * and mac from that.
 542          */
 543         igb_pf_reset_hw(hw);
 544
 545         /* Make sure we have a good EEPROM before we read from it */
 546         if (e1000_validate_nvm_checksum(hw) < 0) {
 547                 /*
 548                  * Some PCI-E parts fail the first check due to
 549                  * the link being in sleep state, call it again,
 550                  * if it fails a second time its a real issue.
 551                  */
 552                 if (e1000_validate_nvm_checksum(hw) < 0) {
 553                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 554                         error = -EIO;
 555                         goto err_late;
 556                 }
 557         }
 558
 559         /* Read the permanent MAC address out of the EEPROM */
 560         if (e1000_read_mac_addr(hw) != 0) {
 561                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 562                 error = -EIO;
 563                 goto err_late;
 564         }
 565
 566         /* Allocate memory for storing MAC addresses */
 567         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 568                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 569         if (eth_dev->data->mac_addrs == NULL) {
 570                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 571                                                 "store MAC addresses",
 572                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 573                 error = -ENOMEM;
 574                 goto err_late;
 575         }
 576
 577         /* Copy the permanent MAC address */
 578         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 579
 580         /* initialize the vfta */
 581         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 582
 583         /* Now initialize the hardware */
 584         if (igb_hardware_init(hw) != 0) {
 585                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 586                 rte_free(eth_dev->data->mac_addrs);
 587                 eth_dev->data->mac_addrs = NULL;
 588                 error = -ENODEV;
 589                 goto err_late;
 590         }
 591         hw->mac.get_link_status = 1;
 592
 593         /* Indicate SOL/IDER usage */
 594         if (e1000_check_reset_block(hw) < 0) {
 595                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 596                                         "SOL/IDER session");
 597         }
 598
 599         /* initialize PF if max_vfs not zero */
 600         igb_pf_host_init(eth_dev);
 601
 602         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 603         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 604         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 605         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 606         E1000_WRITE_FLUSH(hw);
 607
 608         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 609                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 610                      pci_dev->id.device_id);
 611
 612         rte_intr_callback_register(&(pci_dev->intr_handle),
 613                 eth_igb_interrupt_handler, (void *)eth_dev);
 614
 615         /* enable uio intr after callback register */
 616         rte_intr_enable(&(pci_dev->intr_handle));
 617
 618         /* enable support intr */
 619         igb_intr_enable(eth_dev);
 620
 621         TAILQ_INIT(&filter_info->flex_list);
 622         filter_info->flex_mask = 0;
 623         TAILQ_INIT(&filter_info->twotuple_list);
 624         filter_info->twotuple_mask = 0;
 625         TAILQ_INIT(&filter_info->fivetuple_list);
 626         filter_info->fivetuple_mask = 0;
 627
 628         return 0;
 629
 630 err_late:
 631         igb_hw_control_release(hw);
 632
 633         return (error);
 634 }
 635
 636 /*
 637  * Virtual Function device init
 638  */
 639 static int
 640 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 641 {
 642         struct rte_pci_device *pci_dev;
 643         struct e1000_hw *hw =
 644                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 645         int diag;
 646
 647         PMD_INIT_FUNC_TRACE();
 648
 649         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 650         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 651         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 652
 653         /* for secondary processes, we don't initialise any further as primary
 654          * has already done this work. Only check we don't need a different
 655          * RX function */
 656         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 657                 if (eth_dev->data->scattered_rx)
 658                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 659                 return 0;
 660         }
 661
 662         pci_dev = eth_dev->pci_dev;
 663
 664         hw->device_id = pci_dev->id.device_id;
 665         hw->vendor_id = pci_dev->id.vendor_id;
 666         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 667
 668         /* Initialize the shared code (base driver) */
 669         diag = e1000_setup_init_funcs(hw, TRUE);
 670         if (diag != 0) {
 671                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 672                         diag);
 673                 return -EIO;
 674         }
 675
 676         /* init_mailbox_params */
 677         hw->mbx.ops.init_params(hw);
 678
 679         /* Disable the interrupts for VF */
 680         igbvf_intr_disable(hw);
 681
 682         diag = hw->mac.ops.reset_hw(hw);
 683
 684         /* Allocate memory for storing MAC addresses */
 685         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 686                 hw->mac.rar_entry_count, 0);
 687         if (eth_dev->data->mac_addrs == NULL) {
 688                 PMD_INIT_LOG(ERR,
 689                         "Failed to allocate %d bytes needed to store MAC "
 690                         "addresses",
 691                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 692                 return -ENOMEM;
 693         }
 694
 695         /* Copy the permanent MAC address */
 696         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 697                         &eth_dev->data->mac_addrs[0]);
 698
 699         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 700                      "mac.type=%s",
 701                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 702                      pci_dev->id.device_id, "igb_mac_82576_vf");
 703
 704         return 0;
 705 }
 706
 707 static struct eth_driver rte_igb_pmd = {
 708         .pci_drv = {
 709                 .name = "rte_igb_pmd",
 710                 .id_table = pci_id_igb_map,
 711                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 712         },
 713         .eth_dev_init = eth_igb_dev_init,
 714         .dev_private_size = sizeof(struct e1000_adapter),
 715 };
 716
 717 /*
 718  * virtual function driver struct
 719  */
 720 static struct eth_driver rte_igbvf_pmd = {
 721         .pci_drv = {
 722                 .name = "rte_igbvf_pmd",
 723                 .id_table = pci_id_igbvf_map,
 724                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 725         },
 726         .eth_dev_init = eth_igbvf_dev_init,
 727         .dev_private_size = sizeof(struct e1000_adapter),
 728 };
 729
 730 static int
 731 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 732 {
 733         rte_eth_driver_register(&rte_igb_pmd);
 734         return 0;
 735 }
 736
 737 static void
 738 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 739 {
 740         struct e1000_hw *hw =
 741                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 742         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 743         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 744         rctl |= E1000_RCTL_VFE;
 745         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 746 }
 747
 748 /*
 749  * VF Driver initialization routine.
 750  * Invoked one at EAL init time.
 751  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 752  */
 753 static int
 754 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 755 {
 756         PMD_INIT_FUNC_TRACE();
 757
 758         rte_eth_driver_register(&rte_igbvf_pmd);
 759         return (0);
 760 }
 761
 762 static int
 763 eth_igb_configure(struct rte_eth_dev *dev)
 764 {
 765         struct e1000_interrupt *intr =
 766                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 767
 768         PMD_INIT_FUNC_TRACE();
 769         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 770         PMD_INIT_FUNC_TRACE();
 771
 772         return (0);
 773 }
 774
 775 static int
 776 eth_igb_start(struct rte_eth_dev *dev)
 777 {
 778         struct e1000_hw *hw =
 779                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 780         int ret, i, mask;
 781         uint32_t ctrl_ext;
 782
 783         PMD_INIT_FUNC_TRACE();
 784
 785         /* Power up the phy. Needed to make the link go Up */
 786         e1000_power_up_phy(hw);
 787
 788         /*
 789          * Packet Buffer Allocation (PBA)
 790          * Writing PBA sets the receive portion of the buffer
 791          * the remainder is used for the transmit buffer.
 792          */
 793         if (hw->mac.type == e1000_82575) {
 794                 uint32_t pba;
 795
 796                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 797                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 798         }
 799
 800         /* Put the address into the Receive Address Array */
 801         e1000_rar_set(hw, hw->mac.addr, 0);
 802
 803         /* Initialize the hardware */
 804         if (igb_hardware_init(hw)) {
 805                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 806                 return (-EIO);
 807         }
 808
 809         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 810
 811         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 812         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 813         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 814         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 815         E1000_WRITE_FLUSH(hw);
 816
 817         /* configure PF module if SRIOV enabled */
 818         igb_pf_host_configure(dev);
 819
 820         /* Configure for OS presence */
 821         igb_init_manageability(hw);
 822
 823         eth_igb_tx_init(dev);
 824
 825         /* This can fail when allocating mbufs for descriptor rings */
 826         ret = eth_igb_rx_init(dev);
 827         if (ret) {
 828                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 829                 igb_dev_clear_queues(dev);
 830                 return ret;
 831         }
 832
 833         e1000_clear_hw_cntrs_base_generic(hw);
 834
 835         /*
 836          * VLAN Offload Settings
 837          */
 838         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 839                         ETH_VLAN_EXTEND_MASK;
 840         eth_igb_vlan_offload_set(dev, mask);
 841
 842         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 843                 /* Enable VLAN filter since VMDq always use VLAN filter */
 844                 igb_vmdq_vlan_hw_filter_enable(dev);
 845         }
 846
 847         /*
 848          * Configure the Interrupt Moderation register (EITR) with the maximum
 849          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 850          * spurious [DMA] memory updates of RX and TX ring descriptors.
 851          *
 852          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 853          * spurious memory updates per second should be expected.
 854          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 855          *
 856          * Because interrupts are not used at all, the MSI-X is not activated
 857          * and interrupt moderation is controlled by EITR[0].
 858          *
 859          * Note that having [almost] disabled memory updates of RX and TX ring
 860          * descriptors through the Interrupt Moderation mechanism, memory
 861          * updates of ring descriptors are now moderated by the configurable
 862          * value of Write-Back Threshold registers.
 863          */
 864         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 865                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 866                 (hw->mac.type == e1000_i211)) {
 867                 uint32_t ivar;
 868
 869                 /* Enable all RX & TX queues in the IVAR registers */
 870                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 871                 for (i = 0; i < 8; i++)
 872                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 873
 874                 /* Configure EITR with the maximum possible value (0xFFFF) */
 875                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 876         }
 877
 878         /* Setup link speed and duplex */
 879         switch (dev->data->dev_conf.link_speed) {
 880         case ETH_LINK_SPEED_AUTONEG:
 881                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 882                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 883                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 884                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 885                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 886                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 887                 else
 888                         goto error_invalid_config;
 889                 break;
 890         case ETH_LINK_SPEED_10:
 891                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 892                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 893                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 894                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 895                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 896                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 897                 else
 898                         goto error_invalid_config;
 899                 break;
 900         case ETH_LINK_SPEED_100:
 901                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 902                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 903                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 904                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 905                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 906                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 907                 else
 908                         goto error_invalid_config;
 909                 break;
 910         case ETH_LINK_SPEED_1000:
 911                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 912                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 913                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 914                 else
 915                         goto error_invalid_config;
 916                 break;
 917         case ETH_LINK_SPEED_10000:
 918         default:
 919                 goto error_invalid_config;
 920         }
 921         e1000_setup_link(hw);
 922
 923         /* check if lsc interrupt feature is enabled */
 924         if (dev->data->dev_conf.intr_conf.lsc != 0)
 925                 ret = eth_igb_lsc_interrupt_setup(dev);
 926
 927         /* resume enabled intr since hw reset */
 928         igb_intr_enable(dev);
 929
 930         PMD_INIT_LOG(DEBUG, "<<");
 931
 932         return (0);
 933
 934 error_invalid_config:
 935         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 936                      dev->data->dev_conf.link_speed,
 937                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 938         igb_dev_clear_queues(dev);
 939         return (-EINVAL);
 940 }
 941
 942 /*********************************************************************
 943  *
 944  *  This routine disables all traffic on the adapter by issuing a
 945  *  global reset on the MAC.
 946  *
 947  **********************************************************************/
 948 static void
 949 eth_igb_stop(struct rte_eth_dev *dev)
 950 {
 951         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 952         struct e1000_filter_info *filter_info =
 953                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
 954         struct rte_eth_link link;
 955         struct e1000_flex_filter *p_flex;
 956         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
 957         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
 958
 959         igb_intr_disable(hw);
 960         igb_pf_reset_hw(hw);
 961         E1000_WRITE_REG(hw, E1000_WUC, 0);
 962
 963         /* Set bit for Go Link disconnect */
 964         if (hw->mac.type >= e1000_82580) {
 965                 uint32_t phpm_reg;
 966
 967                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 968                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 969                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 970         }
 971
 972         /* Power down the phy. Needed to make the link go Down */
 973         if (hw->phy.media_type == e1000_media_type_copper)
 974                 e1000_power_down_phy(hw);
 975         else
 976                 e1000_shutdown_fiber_serdes_link(hw);
 977
 978         igb_dev_clear_queues(dev);
 979
 980         /* clear the recorded link status */
 981         memset(&link, 0, sizeof(link));
 982         rte_igb_dev_atomic_write_link_status(dev, &link);
 983
 984         /* Remove all flex filters of the device */
 985         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 986                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 987                 rte_free(p_flex);
 988         }
 989         filter_info->flex_mask = 0;
 990
 991         /* Remove all ntuple filters of the device */
 992         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
 993              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
 994                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
 995                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 996                              p_5tuple, entries);
 997                 rte_free(p_5tuple);
 998         }
 999         filter_info->fivetuple_mask = 0;
1000         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1001              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1002                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1003                 TAILQ_REMOVE(&filter_info->twotuple_list,
1004                              p_2tuple, entries);
1005                 rte_free(p_2tuple);
1006         }
1007         filter_info->twotuple_mask = 0;
1008 }
1009
1010 static void
1011 eth_igb_close(struct rte_eth_dev *dev)
1012 {
1013         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014         struct rte_eth_link link;
1015
1016         eth_igb_stop(dev);
1017         e1000_phy_hw_reset(hw);
1018         igb_release_manageability(hw);
1019         igb_hw_control_release(hw);
1020
1021         /* Clear bit for Go Link disconnect */
1022         if (hw->mac.type >= e1000_82580) {
1023                 uint32_t phpm_reg;
1024
1025                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1026                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1027                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1028         }
1029
1030         igb_dev_clear_queues(dev);
1031
1032         memset(&link, 0, sizeof(link));
1033         rte_igb_dev_atomic_write_link_status(dev, &link);
1034 }
1035
1036 static int
1037 igb_get_rx_buffer_size(struct e1000_hw *hw)
1038 {
1039         uint32_t rx_buf_size;
1040         if (hw->mac.type == e1000_82576) {
1041                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1042         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1043                 /* PBS needs to be translated according to a lookup table */
1044                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1045                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1046                 rx_buf_size = (rx_buf_size << 10);
1047         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1048                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1049         } else {
1050                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1051         }
1052
1053         return rx_buf_size;
1054 }
1055
1056 /*********************************************************************
1057  *
1058  *  Initialize the hardware
1059  *
1060  **********************************************************************/
1061 static int
1062 igb_hardware_init(struct e1000_hw *hw)
1063 {
1064         uint32_t rx_buf_size;
1065         int diag;
1066
1067         /* Let the firmware know the OS is in control */
1068         igb_hw_control_acquire(hw);
1069
1070         /*
1071          * These parameters control the automatic generation (Tx) and
1072          * response (Rx) to Ethernet PAUSE frames.
1073          * - High water mark should allow for at least two standard size (1518)
1074          *   frames to be received after sending an XOFF.
1075          * - Low water mark works best when it is very near the high water mark.
1076          *   This allows the receiver to restart by sending XON when it has
1077          *   drained a bit. Here we use an arbitrary value of 1500 which will
1078          *   restart after one full frame is pulled from the buffer. There
1079          *   could be several smaller frames in the buffer and if so they will
1080          *   not trigger the XON until their total number reduces the buffer
1081          *   by 1500.
1082          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1083          */
1084         rx_buf_size = igb_get_rx_buffer_size(hw);
1085
1086         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1087         hw->fc.low_water = hw->fc.high_water - 1500;
1088         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1089         hw->fc.send_xon = 1;
1090
1091         /* Set Flow control, use the tunable location if sane */
1092         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1093                 hw->fc.requested_mode = igb_fc_setting;
1094         else
1095                 hw->fc.requested_mode = e1000_fc_none;
1096
1097         /* Issue a global reset */
1098         igb_pf_reset_hw(hw);
1099         E1000_WRITE_REG(hw, E1000_WUC, 0);
1100
1101         diag = e1000_init_hw(hw);
1102         if (diag < 0)
1103                 return (diag);
1104
1105         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1106         e1000_get_phy_info(hw);
1107         e1000_check_for_link(hw);
1108
1109         return (0);
1110 }
1111
1112 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1113 static void
1114 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1115 {
1116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117         struct e1000_hw_stats *stats =
1118                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1119         int pause_frames;
1120
1121         if(hw->phy.media_type == e1000_media_type_copper ||
1122             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1123                 stats->symerrs +=
1124                     E1000_READ_REG(hw,E1000_SYMERRS);
1125                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1126         }
1127
1128         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1129         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1130         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1131         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1132
1133         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1134         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1135         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1136         stats->dc += E1000_READ_REG(hw, E1000_DC);
1137         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1138         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1139         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1140         /*
1141         ** For watchdog management we need to know if we have been
1142         ** paused during the last interval, so capture that here.
1143         */
1144         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1145         stats->xoffrxc += pause_frames;
1146         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1147         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1148         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1149         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1150         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1151         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1152         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1153         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1154         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1155         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1156         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1157         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1158
1159         /* For the 64-bit byte counters the low dword must be read first. */
1160         /* Both registers clear on the read of the high dword */
1161
1162         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1163         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1164         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1165         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1166
1167         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1168         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1169         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1170         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1171         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1172
1173         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1174         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1175
1176         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1177         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1178         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1179         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1180         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1181         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1182         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1183         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1184         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1185         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1186
1187         /* Interrupt Counts */
1188
1189         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1190         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1191         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1192         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1193         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1194         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1195         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1196         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1197         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1198
1199         /* Host to Card Statistics */
1200
1201         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1202         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1203         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1204         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1205         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1206         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1207         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1208         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1209         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1210         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1211         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1212         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1213         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1214         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1215
1216         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1217         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1218         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1219         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1220         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1221         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1222
1223         if (rte_stats == NULL)
1224                 return;
1225
1226         /* Rx Errors */
1227         rte_stats->ibadcrc = stats->crcerrs;
1228         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1229         rte_stats->imissed = stats->mpc;
1230         rte_stats->ierrors = rte_stats->ibadcrc +
1231                              rte_stats->ibadlen +
1232                              rte_stats->imissed +
1233                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1234
1235         /* Tx Errors */
1236         rte_stats->oerrors = stats->ecol + stats->latecol;
1237
1238         /* XON/XOFF pause frames */
1239         rte_stats->tx_pause_xon  = stats->xontxc;
1240         rte_stats->rx_pause_xon  = stats->xonrxc;
1241         rte_stats->tx_pause_xoff = stats->xofftxc;
1242         rte_stats->rx_pause_xoff = stats->xoffrxc;
1243
1244         rte_stats->ipackets = stats->gprc;
1245         rte_stats->opackets = stats->gptc;
1246         rte_stats->ibytes   = stats->gorc;
1247         rte_stats->obytes   = stats->gotc;
1248 }
1249
1250 static void
1251 eth_igb_stats_reset(struct rte_eth_dev *dev)
1252 {
1253         struct e1000_hw_stats *hw_stats =
1254                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1255
1256         /* HW registers are cleared on read */
1257         eth_igb_stats_get(dev, NULL);
1258
1259         /* Reset software totals */
1260         memset(hw_stats, 0, sizeof(*hw_stats));
1261 }
1262
1263 static void
1264 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1265 {
1266         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1267         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1268                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1269
1270         /* Good Rx packets, include VF loopback */
1271         UPDATE_VF_STAT(E1000_VFGPRC,
1272             hw_stats->last_gprc, hw_stats->gprc);
1273
1274         /* Good Rx octets, include VF loopback */
1275         UPDATE_VF_STAT(E1000_VFGORC,
1276             hw_stats->last_gorc, hw_stats->gorc);
1277
1278         /* Good Tx packets, include VF loopback */
1279         UPDATE_VF_STAT(E1000_VFGPTC,
1280             hw_stats->last_gptc, hw_stats->gptc);
1281
1282         /* Good Tx octets, include VF loopback */
1283         UPDATE_VF_STAT(E1000_VFGOTC,
1284             hw_stats->last_gotc, hw_stats->gotc);
1285
1286         /* Rx Multicst packets */
1287         UPDATE_VF_STAT(E1000_VFMPRC,
1288             hw_stats->last_mprc, hw_stats->mprc);
1289
1290         /* Good Rx loopback packets */
1291         UPDATE_VF_STAT(E1000_VFGPRLBC,
1292             hw_stats->last_gprlbc, hw_stats->gprlbc);
1293
1294         /* Good Rx loopback octets */
1295         UPDATE_VF_STAT(E1000_VFGORLBC,
1296             hw_stats->last_gorlbc, hw_stats->gorlbc);
1297
1298         /* Good Tx loopback packets */
1299         UPDATE_VF_STAT(E1000_VFGPTLBC,
1300             hw_stats->last_gptlbc, hw_stats->gptlbc);
1301
1302         /* Good Tx loopback octets */
1303         UPDATE_VF_STAT(E1000_VFGOTLBC,
1304             hw_stats->last_gotlbc, hw_stats->gotlbc);
1305
1306         if (rte_stats == NULL)
1307                 return;
1308
1309         rte_stats->ipackets = hw_stats->gprc;
1310         rte_stats->ibytes = hw_stats->gorc;
1311         rte_stats->opackets = hw_stats->gptc;
1312         rte_stats->obytes = hw_stats->gotc;
1313         rte_stats->imcasts = hw_stats->mprc;
1314         rte_stats->ilbpackets = hw_stats->gprlbc;
1315         rte_stats->ilbbytes = hw_stats->gorlbc;
1316         rte_stats->olbpackets = hw_stats->gptlbc;
1317         rte_stats->olbbytes = hw_stats->gotlbc;
1318
1319 }
1320
1321 static void
1322 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1323 {
1324         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1325                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1326
1327         /* Sync HW register to the last stats */
1328         eth_igbvf_stats_get(dev, NULL);
1329
1330         /* reset HW current stats*/
1331         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1332                offsetof(struct e1000_vf_stats, gprc));
1333
1334 }
1335
1336 static void
1337 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1338 {
1339         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340
1341         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1342         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1343         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1344         dev_info->rx_offload_capa =
1345                 DEV_RX_OFFLOAD_VLAN_STRIP |
1346                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1347                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1348                 DEV_RX_OFFLOAD_TCP_CKSUM;
1349         dev_info->tx_offload_capa =
1350                 DEV_TX_OFFLOAD_VLAN_INSERT |
1351                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1352                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1353                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1354                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1355
1356         switch (hw->mac.type) {
1357         case e1000_82575:
1358                 dev_info->max_rx_queues = 4;
1359                 dev_info->max_tx_queues = 4;
1360                 dev_info->max_vmdq_pools = 0;
1361                 break;
1362
1363         case e1000_82576:
1364                 dev_info->max_rx_queues = 16;
1365                 dev_info->max_tx_queues = 16;
1366                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1367                 dev_info->vmdq_queue_num = 16;
1368                 break;
1369
1370         case e1000_82580:
1371                 dev_info->max_rx_queues = 8;
1372                 dev_info->max_tx_queues = 8;
1373                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1374                 dev_info->vmdq_queue_num = 8;
1375                 break;
1376
1377         case e1000_i350:
1378                 dev_info->max_rx_queues = 8;
1379                 dev_info->max_tx_queues = 8;
1380                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1381                 dev_info->vmdq_queue_num = 8;
1382                 break;
1383
1384         case e1000_i354:
1385                 dev_info->max_rx_queues = 8;
1386                 dev_info->max_tx_queues = 8;
1387                 break;
1388
1389         case e1000_i210:
1390                 dev_info->max_rx_queues = 4;
1391                 dev_info->max_tx_queues = 4;
1392                 dev_info->max_vmdq_pools = 0;
1393                 break;
1394
1395         case e1000_i211:
1396                 dev_info->max_rx_queues = 2;
1397                 dev_info->max_tx_queues = 2;
1398                 dev_info->max_vmdq_pools = 0;
1399                 break;
1400
1401         default:
1402                 /* Should not happen */
1403                 break;
1404         }
1405         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1406         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1407         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1408
1409         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1410                 .rx_thresh = {
1411                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1412                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1413                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1414                 },
1415                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1416                 .rx_drop_en = 0,
1417         };
1418
1419         dev_info->default_txconf = (struct rte_eth_txconf) {
1420                 .tx_thresh = {
1421                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1422                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1423                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1424                 },
1425                 .txq_flags = 0,
1426         };
1427 }
1428
1429 static void
1430 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1431 {
1432         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433
1434         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1435         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1436         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1437         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1438                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1439                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1440                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1441         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1442                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1443                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1444                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1445                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1446         switch (hw->mac.type) {
1447         case e1000_vfadapt:
1448                 dev_info->max_rx_queues = 2;
1449                 dev_info->max_tx_queues = 2;
1450                 break;
1451         case e1000_vfadapt_i350:
1452                 dev_info->max_rx_queues = 1;
1453                 dev_info->max_tx_queues = 1;
1454                 break;
1455         default:
1456                 /* Should not happen */
1457                 break;
1458         }
1459
1460         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1461                 .rx_thresh = {
1462                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1463                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1464                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1465                 },
1466                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1467                 .rx_drop_en = 0,
1468         };
1469
1470         dev_info->default_txconf = (struct rte_eth_txconf) {
1471                 .tx_thresh = {
1472                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1473                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1474                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1475                 },
1476                 .txq_flags = 0,
1477         };
1478 }
1479
1480 /* return 0 means link status changed, -1 means not changed */
1481 static int
1482 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1483 {
1484         struct e1000_hw *hw =
1485                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486         struct rte_eth_link link, old;
1487         int link_check, count;
1488
1489         link_check = 0;
1490         hw->mac.get_link_status = 1;
1491
1492         /* possible wait-to-complete in up to 9 seconds */
1493         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1494                 /* Read the real link status */
1495                 switch (hw->phy.media_type) {
1496                 case e1000_media_type_copper:
1497                         /* Do the work to read phy */
1498                         e1000_check_for_link(hw);
1499                         link_check = !hw->mac.get_link_status;
1500                         break;
1501
1502                 case e1000_media_type_fiber:
1503                         e1000_check_for_link(hw);
1504                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1505                                       E1000_STATUS_LU);
1506                         break;
1507
1508                 case e1000_media_type_internal_serdes:
1509                         e1000_check_for_link(hw);
1510                         link_check = hw->mac.serdes_has_link;
1511                         break;
1512
1513                 /* VF device is type_unknown */
1514                 case e1000_media_type_unknown:
1515                         eth_igbvf_link_update(hw);
1516                         link_check = !hw->mac.get_link_status;
1517                         break;
1518
1519                 default:
1520                         break;
1521                 }
1522                 if (link_check || wait_to_complete == 0)
1523                         break;
1524                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1525         }
1526         memset(&link, 0, sizeof(link));
1527         rte_igb_dev_atomic_read_link_status(dev, &link);
1528         old = link;
1529
1530         /* Now we check if a transition has happened */
1531         if (link_check) {
1532                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1533                                           &link.link_duplex);
1534                 link.link_status = 1;
1535         } else if (!link_check) {
1536                 link.link_speed = 0;
1537                 link.link_duplex = 0;
1538                 link.link_status = 0;
1539         }
1540         rte_igb_dev_atomic_write_link_status(dev, &link);
1541
1542         /* not changed */
1543         if (old.link_status == link.link_status)
1544                 return -1;
1545
1546         /* changed */
1547         return 0;
1548 }
1549
1550 /*
1551  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1552  * For ASF and Pass Through versions of f/w this means
1553  * that the driver is loaded.
1554  */
1555 static void
1556 igb_hw_control_acquire(struct e1000_hw *hw)
1557 {
1558         uint32_t ctrl_ext;
1559
1560         /* Let firmware know the driver has taken over */
1561         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1562         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1563 }
1564
1565 /*
1566  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1567  * For ASF and Pass Through versions of f/w this means that the
1568  * driver is no longer loaded.
1569  */
1570 static void
1571 igb_hw_control_release(struct e1000_hw *hw)
1572 {
1573         uint32_t ctrl_ext;
1574
1575         /* Let firmware taken over control of h/w */
1576         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1577         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1578                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1579 }
1580
1581 /*
1582  * Bit of a misnomer, what this really means is
1583  * to enable OS management of the system... aka
1584  * to disable special hardware management features.
1585  */
1586 static void
1587 igb_init_manageability(struct e1000_hw *hw)
1588 {
1589         if (e1000_enable_mng_pass_thru(hw)) {
1590                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1591                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1592
1593                 /* disable hardware interception of ARP */
1594                 manc &= ~(E1000_MANC_ARP_EN);
1595
1596                 /* enable receiving management packets to the host */
1597                 manc |= E1000_MANC_EN_MNG2HOST;
1598                 manc2h |= 1 << 5;  /* Mng Port 623 */
1599                 manc2h |= 1 << 6;  /* Mng Port 664 */
1600                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1601                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1602         }
1603 }
1604
1605 static void
1606 igb_release_manageability(struct e1000_hw *hw)
1607 {
1608         if (e1000_enable_mng_pass_thru(hw)) {
1609                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1610
1611                 manc |= E1000_MANC_ARP_EN;
1612                 manc &= ~E1000_MANC_EN_MNG2HOST;
1613
1614                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1615         }
1616 }
1617
1618 static void
1619 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1620 {
1621         struct e1000_hw *hw =
1622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         uint32_t rctl;
1624
1625         rctl = E1000_READ_REG(hw, E1000_RCTL);
1626         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1627         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1628 }
1629
1630 static void
1631 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1632 {
1633         struct e1000_hw *hw =
1634                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         uint32_t rctl;
1636
1637         rctl = E1000_READ_REG(hw, E1000_RCTL);
1638         rctl &= (~E1000_RCTL_UPE);
1639         if (dev->data->all_multicast == 1)
1640                 rctl |= E1000_RCTL_MPE;
1641         else
1642                 rctl &= (~E1000_RCTL_MPE);
1643         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1644 }
1645
1646 static void
1647 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1648 {
1649         struct e1000_hw *hw =
1650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651         uint32_t rctl;
1652
1653         rctl = E1000_READ_REG(hw, E1000_RCTL);
1654         rctl |= E1000_RCTL_MPE;
1655         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1656 }
1657
1658 static void
1659 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1660 {
1661         struct e1000_hw *hw =
1662                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         uint32_t rctl;
1664
1665         if (dev->data->promiscuous == 1)
1666                 return; /* must remain in all_multicast mode */
1667         rctl = E1000_READ_REG(hw, E1000_RCTL);
1668         rctl &= (~E1000_RCTL_MPE);
1669         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1670 }
1671
1672 static int
1673 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1674 {
1675         struct e1000_hw *hw =
1676                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         struct e1000_vfta * shadow_vfta =
1678                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1679         uint32_t vfta;
1680         uint32_t vid_idx;
1681         uint32_t vid_bit;
1682
1683         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1684                               E1000_VFTA_ENTRY_MASK);
1685         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1686         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1687         if (on)
1688                 vfta |= vid_bit;
1689         else
1690                 vfta &= ~vid_bit;
1691         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1692
1693         /* update local VFTA copy */
1694         shadow_vfta->vfta[vid_idx] = vfta;
1695
1696         return 0;
1697 }
1698
1699 static void
1700 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1701 {
1702         struct e1000_hw *hw =
1703                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704         uint32_t reg = ETHER_TYPE_VLAN ;
1705
1706         reg |= (tpid << 16);
1707         E1000_WRITE_REG(hw, E1000_VET, reg);
1708 }
1709
1710 static void
1711 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1712 {
1713         struct e1000_hw *hw =
1714                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715         uint32_t reg;
1716
1717         /* Filter Table Disable */
1718         reg = E1000_READ_REG(hw, E1000_RCTL);
1719         reg &= ~E1000_RCTL_CFIEN;
1720         reg &= ~E1000_RCTL_VFE;
1721         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1722 }
1723
1724 static void
1725 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1726 {
1727         struct e1000_hw *hw =
1728                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         struct e1000_vfta * shadow_vfta =
1730                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1731         uint32_t reg;
1732         int i;
1733
1734         /* Filter Table Enable, CFI not used for packet acceptance */
1735         reg = E1000_READ_REG(hw, E1000_RCTL);
1736         reg &= ~E1000_RCTL_CFIEN;
1737         reg |= E1000_RCTL_VFE;
1738         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1739
1740         /* restore VFTA table */
1741         for (i = 0; i < IGB_VFTA_SIZE; i++)
1742                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1743 }
1744
1745 static void
1746 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1747 {
1748         struct e1000_hw *hw =
1749                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         uint32_t reg;
1751
1752         /* VLAN Mode Disable */
1753         reg = E1000_READ_REG(hw, E1000_CTRL);
1754         reg &= ~E1000_CTRL_VME;
1755         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1756 }
1757
1758 static void
1759 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1760 {
1761         struct e1000_hw *hw =
1762                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763         uint32_t reg;
1764
1765         /* VLAN Mode Enable */
1766         reg = E1000_READ_REG(hw, E1000_CTRL);
1767         reg |= E1000_CTRL_VME;
1768         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1769 }
1770
1771 static void
1772 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1773 {
1774         struct e1000_hw *hw =
1775                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         uint32_t reg;
1777
1778         /* CTRL_EXT: Extended VLAN */
1779         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1780         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1781         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1782
1783         /* Update maximum packet length */
1784         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1785                 E1000_WRITE_REG(hw, E1000_RLPML,
1786                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1787                                                 VLAN_TAG_SIZE);
1788 }
1789
1790 static void
1791 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1792 {
1793         struct e1000_hw *hw =
1794                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795         uint32_t reg;
1796
1797         /* CTRL_EXT: Extended VLAN */
1798         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1799         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1800         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1801
1802         /* Update maximum packet length */
1803         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1804                 E1000_WRITE_REG(hw, E1000_RLPML,
1805                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1806                                                 2 * VLAN_TAG_SIZE);
1807 }
1808
1809 static void
1810 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1811 {
1812         if(mask & ETH_VLAN_STRIP_MASK){
1813                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1814                         igb_vlan_hw_strip_enable(dev);
1815                 else
1816                         igb_vlan_hw_strip_disable(dev);
1817         }
1818
1819         if(mask & ETH_VLAN_FILTER_MASK){
1820                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1821                         igb_vlan_hw_filter_enable(dev);
1822                 else
1823                         igb_vlan_hw_filter_disable(dev);
1824         }
1825
1826         if(mask & ETH_VLAN_EXTEND_MASK){
1827                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1828                         igb_vlan_hw_extend_enable(dev);
1829                 else
1830                         igb_vlan_hw_extend_disable(dev);
1831         }
1832 }
1833
1834
1835 /**
1836  * It enables the interrupt mask and then enable the interrupt.
1837  *
1838  * @param dev
1839  *  Pointer to struct rte_eth_dev.
1840  *
1841  * @return
1842  *  - On success, zero.
1843  *  - On failure, a negative value.
1844  */
1845 static int
1846 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1847 {
1848         struct e1000_interrupt *intr =
1849                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1850
1851         intr->mask |= E1000_ICR_LSC;
1852
1853         return 0;
1854 }
1855
1856 /*
1857  * It reads ICR and gets interrupt causes, check it and set a bit flag
1858  * to update link status.
1859  *
1860  * @param dev
1861  *  Pointer to struct rte_eth_dev.
1862  *
1863  * @return
1864  *  - On success, zero.
1865  *  - On failure, a negative value.
1866  */
1867 static int
1868 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1869 {
1870         uint32_t icr;
1871         struct e1000_hw *hw =
1872                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct e1000_interrupt *intr =
1874                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1875
1876         igb_intr_disable(hw);
1877
1878         /* read-on-clear nic registers here */
1879         icr = E1000_READ_REG(hw, E1000_ICR);
1880
1881         intr->flags = 0;
1882         if (icr & E1000_ICR_LSC) {
1883                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1884         }
1885
1886         if (icr & E1000_ICR_VMMB)
1887                 intr->flags |= E1000_FLAG_MAILBOX;
1888
1889         return 0;
1890 }
1891
1892 /*
1893  * It executes link_update after knowing an interrupt is prsent.
1894  *
1895  * @param dev
1896  *  Pointer to struct rte_eth_dev.
1897  *
1898  * @return
1899  *  - On success, zero.
1900  *  - On failure, a negative value.
1901  */
1902 static int
1903 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1904 {
1905         struct e1000_hw *hw =
1906                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         struct e1000_interrupt *intr =
1908                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1909         uint32_t tctl, rctl;
1910         struct rte_eth_link link;
1911         int ret;
1912
1913         if (intr->flags & E1000_FLAG_MAILBOX) {
1914                 igb_pf_mbx_process(dev);
1915                 intr->flags &= ~E1000_FLAG_MAILBOX;
1916         }
1917
1918         igb_intr_enable(dev);
1919         rte_intr_enable(&(dev->pci_dev->intr_handle));
1920
1921         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1922                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1923
1924                 /* set get_link_status to check register later */
1925                 hw->mac.get_link_status = 1;
1926                 ret = eth_igb_link_update(dev, 0);
1927
1928                 /* check if link has changed */
1929                 if (ret < 0)
1930                         return 0;
1931
1932                 memset(&link, 0, sizeof(link));
1933                 rte_igb_dev_atomic_read_link_status(dev, &link);
1934                 if (link.link_status) {
1935                         PMD_INIT_LOG(INFO,
1936                                      " Port %d: Link Up - speed %u Mbps - %s",
1937                                      dev->data->port_id,
1938                                      (unsigned)link.link_speed,
1939                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1940                                      "full-duplex" : "half-duplex");
1941                 } else {
1942                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1943                                      dev->data->port_id);
1944                 }
1945                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1946                              dev->pci_dev->addr.domain,
1947                              dev->pci_dev->addr.bus,
1948                              dev->pci_dev->addr.devid,
1949                              dev->pci_dev->addr.function);
1950                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1951                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1952                 if (link.link_status) {
1953                         /* enable Tx/Rx */
1954                         tctl |= E1000_TCTL_EN;
1955                         rctl |= E1000_RCTL_EN;
1956                 } else {
1957                         /* disable Tx/Rx */
1958                         tctl &= ~E1000_TCTL_EN;
1959                         rctl &= ~E1000_RCTL_EN;
1960                 }
1961                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1962                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1963                 E1000_WRITE_FLUSH(hw);
1964                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1965         }
1966
1967         return 0;
1968 }
1969
1970 /**
1971  * Interrupt handler which shall be registered at first.
1972  *
1973  * @param handle
1974  *  Pointer to interrupt handle.
1975  * @param param
1976  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1977  *
1978  * @return
1979  *  void
1980  */
1981 static void
1982 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1983                                                         void *param)
1984 {
1985         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1986
1987         eth_igb_interrupt_get_status(dev);
1988         eth_igb_interrupt_action(dev);
1989 }
1990
1991 static int
1992 eth_igb_led_on(struct rte_eth_dev *dev)
1993 {
1994         struct e1000_hw *hw;
1995
1996         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1998 }
1999
2000 static int
2001 eth_igb_led_off(struct rte_eth_dev *dev)
2002 {
2003         struct e1000_hw *hw;
2004
2005         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2007 }
2008
2009 static int
2010 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2011 {
2012         struct e1000_hw *hw;
2013         uint32_t ctrl;
2014         int tx_pause;
2015         int rx_pause;
2016
2017         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         fc_conf->pause_time = hw->fc.pause_time;
2019         fc_conf->high_water = hw->fc.high_water;
2020         fc_conf->low_water = hw->fc.low_water;
2021         fc_conf->send_xon = hw->fc.send_xon;
2022         fc_conf->autoneg = hw->mac.autoneg;
2023
2024         /*
2025          * Return rx_pause and tx_pause status according to actual setting of
2026          * the TFCE and RFCE bits in the CTRL register.
2027          */
2028         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2029         if (ctrl & E1000_CTRL_TFCE)
2030                 tx_pause = 1;
2031         else
2032                 tx_pause = 0;
2033
2034         if (ctrl & E1000_CTRL_RFCE)
2035                 rx_pause = 1;
2036         else
2037                 rx_pause = 0;
2038
2039         if (rx_pause && tx_pause)
2040                 fc_conf->mode = RTE_FC_FULL;
2041         else if (rx_pause)
2042                 fc_conf->mode = RTE_FC_RX_PAUSE;
2043         else if (tx_pause)
2044                 fc_conf->mode = RTE_FC_TX_PAUSE;
2045         else
2046                 fc_conf->mode = RTE_FC_NONE;
2047
2048         return 0;
2049 }
2050
2051 static int
2052 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2053 {
2054         struct e1000_hw *hw;
2055         int err;
2056         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2057                 e1000_fc_none,
2058                 e1000_fc_rx_pause,
2059                 e1000_fc_tx_pause,
2060                 e1000_fc_full
2061         };
2062         uint32_t rx_buf_size;
2063         uint32_t max_high_water;
2064         uint32_t rctl;
2065
2066         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         if (fc_conf->autoneg != hw->mac.autoneg)
2068                 return -ENOTSUP;
2069         rx_buf_size = igb_get_rx_buffer_size(hw);
2070         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2071
2072         /* At least reserve one Ethernet frame for watermark */
2073         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2074         if ((fc_conf->high_water > max_high_water) ||
2075             (fc_conf->high_water < fc_conf->low_water)) {
2076                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2077                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2078                 return (-EINVAL);
2079         }
2080
2081         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2082         hw->fc.pause_time     = fc_conf->pause_time;
2083         hw->fc.high_water     = fc_conf->high_water;
2084         hw->fc.low_water      = fc_conf->low_water;
2085         hw->fc.send_xon       = fc_conf->send_xon;
2086
2087         err = e1000_setup_link_generic(hw);
2088         if (err == E1000_SUCCESS) {
2089
2090                 /* check if we want to forward MAC frames - driver doesn't have native
2091                  * capability to do that, so we'll write the registers ourselves */
2092
2093                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2094
2095                 /* set or clear MFLCN.PMCF bit depending on configuration */
2096                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2097                         rctl |= E1000_RCTL_PMCF;
2098                 else
2099                         rctl &= ~E1000_RCTL_PMCF;
2100
2101                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2102                 E1000_WRITE_FLUSH(hw);
2103
2104                 return 0;
2105         }
2106
2107         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2108         return (-EIO);
2109 }
2110
2111 #define E1000_RAH_POOLSEL_SHIFT      (18)
2112 static void
2113 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2114                 uint32_t index, __rte_unused uint32_t pool)
2115 {
2116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         uint32_t rah;
2118
2119         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2120         rah = E1000_READ_REG(hw, E1000_RAH(index));
2121         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2122         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2123 }
2124
2125 static void
2126 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2127 {
2128         uint8_t addr[ETHER_ADDR_LEN];
2129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2130
2131         memset(addr, 0, sizeof(addr));
2132
2133         e1000_rar_set(hw, addr, index);
2134 }
2135
2136 /*
2137  * Virtual Function operations
2138  */
2139 static void
2140 igbvf_intr_disable(struct e1000_hw *hw)
2141 {
2142         PMD_INIT_FUNC_TRACE();
2143
2144         /* Clear interrupt mask to stop from interrupts being generated */
2145         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2146
2147         E1000_WRITE_FLUSH(hw);
2148 }
2149
2150 static void
2151 igbvf_stop_adapter(struct rte_eth_dev *dev)
2152 {
2153         u32 reg_val;
2154         u16 i;
2155         struct rte_eth_dev_info dev_info;
2156         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157
2158         memset(&dev_info, 0, sizeof(dev_info));
2159         eth_igbvf_infos_get(dev, &dev_info);
2160
2161         /* Clear interrupt mask to stop from interrupts being generated */
2162         igbvf_intr_disable(hw);
2163
2164         /* Clear any pending interrupts, flush previous writes */
2165         E1000_READ_REG(hw, E1000_EICR);
2166
2167         /* Disable the transmit unit.  Each queue must be disabled. */
2168         for (i = 0; i < dev_info.max_tx_queues; i++)
2169                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2170
2171         /* Disable the receive unit by stopping each queue */
2172         for (i = 0; i < dev_info.max_rx_queues; i++) {
2173                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2174                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2175                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2176                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2177                         ;
2178         }
2179
2180         /* flush all queues disables */
2181         E1000_WRITE_FLUSH(hw);
2182         msec_delay(2);
2183 }
2184
2185 static int eth_igbvf_link_update(struct e1000_hw *hw)
2186 {
2187         struct e1000_mbx_info *mbx = &hw->mbx;
2188         struct e1000_mac_info *mac = &hw->mac;
2189         int ret_val = E1000_SUCCESS;
2190
2191         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2192
2193         /*
2194          * We only want to run this if there has been a rst asserted.
2195          * in this case that could mean a link change, device reset,
2196          * or a virtual function reset
2197          */
2198
2199         /* If we were hit with a reset or timeout drop the link */
2200         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2201                 mac->get_link_status = TRUE;
2202
2203         if (!mac->get_link_status)
2204                 goto out;
2205
2206         /* if link status is down no point in checking to see if pf is up */
2207         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2208                 goto out;
2209
2210         /* if we passed all the tests above then the link is up and we no
2211          * longer need to check for link */
2212         mac->get_link_status = FALSE;
2213
2214 out:
2215         return ret_val;
2216 }
2217
2218
2219 static int
2220 igbvf_dev_configure(struct rte_eth_dev *dev)
2221 {
2222         struct rte_eth_conf* conf = &dev->data->dev_conf;
2223
2224         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2225                      dev->data->port_id);
2226
2227         /*
2228          * VF has no ability to enable/disable HW CRC
2229          * Keep the persistent behavior the same as Host PF
2230          */
2231 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2232         if (!conf->rxmode.hw_strip_crc) {
2233                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2234                 conf->rxmode.hw_strip_crc = 1;
2235         }
2236 #else
2237         if (conf->rxmode.hw_strip_crc) {
2238                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2239                 conf->rxmode.hw_strip_crc = 0;
2240         }
2241 #endif
2242
2243         return 0;
2244 }
2245
2246 static int
2247 igbvf_dev_start(struct rte_eth_dev *dev)
2248 {
2249         struct e1000_hw *hw =
2250                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         int ret;
2252
2253         PMD_INIT_FUNC_TRACE();
2254
2255         hw->mac.ops.reset_hw(hw);
2256
2257         /* Set all vfta */
2258         igbvf_set_vfta_all(dev,1);
2259
2260         eth_igbvf_tx_init(dev);
2261
2262         /* This can fail when allocating mbufs for descriptor rings */
2263         ret = eth_igbvf_rx_init(dev);
2264         if (ret) {
2265                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2266                 igb_dev_clear_queues(dev);
2267                 return ret;
2268         }
2269
2270         return 0;
2271 }
2272
2273 static void
2274 igbvf_dev_stop(struct rte_eth_dev *dev)
2275 {
2276         PMD_INIT_FUNC_TRACE();
2277
2278         igbvf_stop_adapter(dev);
2279
2280         /*
2281           * Clear what we set, but we still keep shadow_vfta to
2282           * restore after device starts
2283           */
2284         igbvf_set_vfta_all(dev,0);
2285
2286         igb_dev_clear_queues(dev);
2287 }
2288
2289 static void
2290 igbvf_dev_close(struct rte_eth_dev *dev)
2291 {
2292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293
2294         PMD_INIT_FUNC_TRACE();
2295
2296         e1000_reset_hw(hw);
2297
2298         igbvf_dev_stop(dev);
2299 }
2300
2301 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2302 {
2303         struct e1000_mbx_info *mbx = &hw->mbx;
2304         uint32_t msgbuf[2];
2305
2306         /* After set vlan, vlan strip will also be enabled in igb driver*/
2307         msgbuf[0] = E1000_VF_SET_VLAN;
2308         msgbuf[1] = vid;
2309         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2310         if (on)
2311                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2312
2313         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2314 }
2315
2316 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2317 {
2318         struct e1000_hw *hw =
2319                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         struct e1000_vfta * shadow_vfta =
2321                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2322         int i = 0, j = 0, vfta = 0, mask = 1;
2323
2324         for (i = 0; i < IGB_VFTA_SIZE; i++){
2325                 vfta = shadow_vfta->vfta[i];
2326                 if(vfta){
2327                         mask = 1;
2328                         for (j = 0; j < 32; j++){
2329                                 if(vfta & mask)
2330                                         igbvf_set_vfta(hw,
2331                                                 (uint16_t)((i<<5)+j), on);
2332                                 mask<<=1;
2333                         }
2334                 }
2335         }
2336
2337 }
2338
2339 static int
2340 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2341 {
2342         struct e1000_hw *hw =
2343                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344         struct e1000_vfta * shadow_vfta =
2345                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2346         uint32_t vid_idx = 0;
2347         uint32_t vid_bit = 0;
2348         int ret = 0;
2349
2350         PMD_INIT_FUNC_TRACE();
2351
2352         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2353         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2354         if(ret){
2355                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2356                 return ret;
2357         }
2358         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2359         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2360
2361         /*Save what we set and retore it after device reset*/
2362         if (on)
2363                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2364         else
2365                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2366
2367         return 0;
2368 }
2369
2370 static int
2371 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2372                         struct rte_eth_rss_reta_entry64 *reta_conf,
2373                         uint16_t reta_size)
2374 {
2375         uint8_t i, j, mask;
2376         uint32_t reta, r;
2377         uint16_t idx, shift;
2378         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379
2380         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2381                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2382                         "(%d) doesn't match the number hardware can supported "
2383                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2384                 return -EINVAL;
2385         }
2386
2387         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2388                 idx = i / RTE_RETA_GROUP_SIZE;
2389                 shift = i % RTE_RETA_GROUP_SIZE;
2390                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2391                                                 IGB_4_BIT_MASK);
2392                 if (!mask)
2393                         continue;
2394                 if (mask == IGB_4_BIT_MASK)
2395                         r = 0;
2396                 else
2397                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2398                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2399                         if (mask & (0x1 << j))
2400                                 reta |= reta_conf[idx].reta[shift + j] <<
2401                                                         (CHAR_BIT * j);
2402                         else
2403                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2404                 }
2405                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2406         }
2407
2408         return 0;
2409 }
2410
2411 static int
2412 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2413                        struct rte_eth_rss_reta_entry64 *reta_conf,
2414                        uint16_t reta_size)
2415 {
2416         uint8_t i, j, mask;
2417         uint32_t reta;
2418         uint16_t idx, shift;
2419         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420
2421         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2422                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2423                         "(%d) doesn't match the number hardware can supported "
2424                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2425                 return -EINVAL;
2426         }
2427
2428         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2429                 idx = i / RTE_RETA_GROUP_SIZE;
2430                 shift = i % RTE_RETA_GROUP_SIZE;
2431                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2432                                                 IGB_4_BIT_MASK);
2433                 if (!mask)
2434                         continue;
2435                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2436                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2437                         if (mask & (0x1 << j))
2438                                 reta_conf[idx].reta[shift + j] =
2439                                         ((reta >> (CHAR_BIT * j)) &
2440                                                 IGB_8_BIT_MASK);
2441                 }
2442         }
2443
2444         return 0;
2445 }
2446
2447 #define MAC_TYPE_FILTER_SUP(type)    do {\
2448         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2449                 (type) != e1000_82576)\
2450                 return -ENOTSUP;\
2451 } while (0)
2452
2453 static int
2454 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2455                         struct rte_eth_syn_filter *filter,
2456                         bool add)
2457 {
2458         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459         uint32_t synqf, rfctl;
2460
2461         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2462                 return -EINVAL;
2463
2464         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2465
2466         if (add) {
2467                 if (synqf & E1000_SYN_FILTER_ENABLE)
2468                         return -EINVAL;
2469
2470                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2471                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2472
2473                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2474                 if (filter->hig_pri)
2475                         rfctl |= E1000_RFCTL_SYNQFP;
2476                 else
2477                         rfctl &= ~E1000_RFCTL_SYNQFP;
2478
2479                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2480         } else {
2481                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2482                         return -ENOENT;
2483                 synqf = 0;
2484         }
2485
2486         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2487         E1000_WRITE_FLUSH(hw);
2488         return 0;
2489 }
2490
2491 static int
2492 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2493                         struct rte_eth_syn_filter *filter)
2494 {
2495         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         uint32_t synqf, rfctl;
2497
2498         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2499         if (synqf & E1000_SYN_FILTER_ENABLE) {
2500                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2501                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2502                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2503                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2504                 return 0;
2505         }
2506
2507         return -ENOENT;
2508 }
2509
2510 static int
2511 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2512                         enum rte_filter_op filter_op,
2513                         void *arg)
2514 {
2515         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516         int ret;
2517
2518         MAC_TYPE_FILTER_SUP(hw->mac.type);
2519
2520         if (filter_op == RTE_ETH_FILTER_NOP)
2521                 return 0;
2522
2523         if (arg == NULL) {
2524                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2525                             filter_op);
2526                 return -EINVAL;
2527         }
2528
2529         switch (filter_op) {
2530         case RTE_ETH_FILTER_ADD:
2531                 ret = eth_igb_syn_filter_set(dev,
2532                                 (struct rte_eth_syn_filter *)arg,
2533                                 TRUE);
2534                 break;
2535         case RTE_ETH_FILTER_DELETE:
2536                 ret = eth_igb_syn_filter_set(dev,
2537                                 (struct rte_eth_syn_filter *)arg,
2538                                 FALSE);
2539                 break;
2540         case RTE_ETH_FILTER_GET:
2541                 ret = eth_igb_syn_filter_get(dev,
2542                                 (struct rte_eth_syn_filter *)arg);
2543                 break;
2544         default:
2545                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2546                 ret = -EINVAL;
2547                 break;
2548         }
2549
2550         return ret;
2551 }
2552
2553 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2554         if ((type) != e1000_82580 && (type) != e1000_i350)\
2555                 return -ENOSYS; \
2556 } while (0)
2557
2558 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2559 static inline int
2560 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2561                         struct e1000_2tuple_filter_info *filter_info)
2562 {
2563         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2564                 return -EINVAL;
2565         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2566                 return -EINVAL;  /* filter index is out of range. */
2567         if (filter->tcp_flags > TCP_FLAG_ALL)
2568                 return -EINVAL;  /* flags is invalid. */
2569
2570         switch (filter->dst_port_mask) {
2571         case UINT16_MAX:
2572                 filter_info->dst_port_mask = 0;
2573                 filter_info->dst_port = filter->dst_port;
2574                 break;
2575         case 0:
2576                 filter_info->dst_port_mask = 1;
2577                 break;
2578         default:
2579                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2580                 return -EINVAL;
2581         }
2582
2583         switch (filter->proto_mask) {
2584         case UINT8_MAX:
2585                 filter_info->proto_mask = 0;
2586                 filter_info->proto = filter->proto;
2587                 break;
2588         case 0:
2589                 filter_info->proto_mask = 1;
2590                 break;
2591         default:
2592                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2593                 return -EINVAL;
2594         }
2595
2596         filter_info->priority = (uint8_t)filter->priority;
2597         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2598                 filter_info->tcp_flags = filter->tcp_flags;
2599         else
2600                 filter_info->tcp_flags = 0;
2601
2602         return 0;
2603 }
2604
2605 static inline struct e1000_2tuple_filter *
2606 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2607                         struct e1000_2tuple_filter_info *key)
2608 {
2609         struct e1000_2tuple_filter *it;
2610
2611         TAILQ_FOREACH(it, filter_list, entries) {
2612                 if (memcmp(key, &it->filter_info,
2613                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2614                         return it;
2615                 }
2616         }
2617         return NULL;
2618 }
2619
2620 /*
2621  * igb_add_2tuple_filter - add a 2tuple filter
2622  *
2623  * @param
2624  * dev: Pointer to struct rte_eth_dev.
2625  * ntuple_filter: ponter to the filter that will be added.
2626  *
2627  * @return
2628  *    - On success, zero.
2629  *    - On failure, a negative value.
2630  */
2631 static int
2632 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2633                         struct rte_eth_ntuple_filter *ntuple_filter)
2634 {
2635         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         struct e1000_filter_info *filter_info =
2637                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2638         struct e1000_2tuple_filter *filter;
2639         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2640         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2641         int i, ret;
2642
2643         filter = rte_zmalloc("e1000_2tuple_filter",
2644                         sizeof(struct e1000_2tuple_filter), 0);
2645         if (filter == NULL)
2646                 return -ENOMEM;
2647
2648         ret = ntuple_filter_to_2tuple(ntuple_filter,
2649                                       &filter->filter_info);
2650         if (ret < 0) {
2651                 rte_free(filter);
2652                 return ret;
2653         }
2654         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2655                                          &filter->filter_info) != NULL) {
2656                 PMD_DRV_LOG(ERR, "filter exists.");
2657                 rte_free(filter);
2658                 return -EEXIST;
2659         }
2660         filter->queue = ntuple_filter->queue;
2661
2662         /*
2663          * look for an unused 2tuple filter index,
2664          * and insert the filter to list.
2665          */
2666         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2667                 if (!(filter_info->twotuple_mask & (1 << i))) {
2668                         filter_info->twotuple_mask |= 1 << i;
2669                         filter->index = i;
2670                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2671                                           filter,
2672                                           entries);
2673                         break;
2674                 }
2675         }
2676         if (i >= E1000_MAX_TTQF_FILTERS) {
2677                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2678                 rte_free(filter);
2679                 return -ENOSYS;
2680         }
2681
2682         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2683         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2684                 imir |= E1000_IMIR_PORT_BP;
2685         else
2686                 imir &= ~E1000_IMIR_PORT_BP;
2687
2688         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2689
2690         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2691         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2692         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2693         if (filter->filter_info.proto_mask == 0)
2694                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2695
2696         /* tcp flags bits setting. */
2697         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2698                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2699                         imir_ext |= E1000_IMIREXT_CTRL_URG;
2700                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2701                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
2702                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2703                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
2704                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2705                         imir_ext |= E1000_IMIREXT_CTRL_RST;
2706                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2707                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
2708                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2709                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
2710         } else
2711                 imir_ext |= E1000_IMIREXT_CTRL_BP;
2712         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2713         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2714         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2715         return 0;
2716 }
2717
2718 /*
2719  * igb_remove_2tuple_filter - remove a 2tuple filter
2720  *
2721  * @param
2722  * dev: Pointer to struct rte_eth_dev.
2723  * ntuple_filter: ponter to the filter that will be removed.
2724  *
2725  * @return
2726  *    - On success, zero.
2727  *    - On failure, a negative value.
2728  */
2729 static int
2730 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2731                         struct rte_eth_ntuple_filter *ntuple_filter)
2732 {
2733         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734         struct e1000_filter_info *filter_info =
2735                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2736         struct e1000_2tuple_filter_info filter_2tuple;
2737         struct e1000_2tuple_filter *filter;
2738         int ret;
2739
2740         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2741         ret = ntuple_filter_to_2tuple(ntuple_filter,
2742                                       &filter_2tuple);
2743         if (ret < 0)
2744                 return ret;
2745
2746         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2747                                          &filter_2tuple);
2748         if (filter == NULL) {
2749                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2750                 return -ENOENT;
2751         }
2752
2753         filter_info->twotuple_mask &= ~(1 << filter->index);
2754         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2755         rte_free(filter);
2756
2757         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2758         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2759         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2760         return 0;
2761 }
2762
2763 static inline struct e1000_flex_filter *
2764 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2765                         struct e1000_flex_filter_info *key)
2766 {
2767         struct e1000_flex_filter *it;
2768
2769         TAILQ_FOREACH(it, filter_list, entries) {
2770                 if (memcmp(key, &it->filter_info,
2771                         sizeof(struct e1000_flex_filter_info)) == 0)
2772                         return it;
2773         }
2774
2775         return NULL;
2776 }
2777
2778 static int
2779 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2780                         struct rte_eth_flex_filter *filter,
2781                         bool add)
2782 {
2783         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         struct e1000_filter_info *filter_info =
2785                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2786         struct e1000_flex_filter *flex_filter, *it;
2787         uint32_t wufc, queueing, mask;
2788         uint32_t reg_off;
2789         uint8_t shift, i, j = 0;
2790
2791         flex_filter = rte_zmalloc("e1000_flex_filter",
2792                         sizeof(struct e1000_flex_filter), 0);
2793         if (flex_filter == NULL)
2794                 return -ENOMEM;
2795
2796         flex_filter->filter_info.len = filter->len;
2797         flex_filter->filter_info.priority = filter->priority;
2798         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2799         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2800                 mask = 0;
2801                 /* reverse bits in flex filter's mask*/
2802                 for (shift = 0; shift < CHAR_BIT; shift++) {
2803                         if (filter->mask[i] & (0x01 << shift))
2804                                 mask |= (0x80 >> shift);
2805                 }
2806                 flex_filter->filter_info.mask[i] = mask;
2807         }
2808
2809         wufc = E1000_READ_REG(hw, E1000_WUFC);
2810         if (flex_filter->index < E1000_MAX_FHFT)
2811                 reg_off = E1000_FHFT(flex_filter->index);
2812         else
2813                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2814
2815         if (add) {
2816                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2817                                 &flex_filter->filter_info) != NULL) {
2818                         PMD_DRV_LOG(ERR, "filter exists.");
2819                         rte_free(flex_filter);
2820                         return -EEXIST;
2821                 }
2822                 flex_filter->queue = filter->queue;
2823                 /*
2824                  * look for an unused flex filter index
2825                  * and insert the filter into the list.
2826                  */
2827                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2828                         if (!(filter_info->flex_mask & (1 << i))) {
2829                                 filter_info->flex_mask |= 1 << i;
2830                                 flex_filter->index = i;
2831                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2832                                         flex_filter,
2833                                         entries);
2834                                 break;
2835                         }
2836                 }
2837                 if (i >= E1000_MAX_FLEX_FILTERS) {
2838                         PMD_DRV_LOG(ERR, "flex filters are full.");
2839                         rte_free(flex_filter);
2840                         return -ENOSYS;
2841                 }
2842
2843                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2844                                 (E1000_WUFC_FLX0 << flex_filter->index));
2845                 queueing = filter->len |
2846                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2847                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2848                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2849                                 queueing);
2850                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2851                         E1000_WRITE_REG(hw, reg_off,
2852                                         flex_filter->filter_info.dwords[j]);
2853                         reg_off += sizeof(uint32_t);
2854                         E1000_WRITE_REG(hw, reg_off,
2855                                         flex_filter->filter_info.dwords[++j]);
2856                         reg_off += sizeof(uint32_t);
2857                         E1000_WRITE_REG(hw, reg_off,
2858                                 (uint32_t)flex_filter->filter_info.mask[i]);
2859                         reg_off += sizeof(uint32_t) * 2;
2860                         ++j;
2861                 }
2862         } else {
2863                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2864                                 &flex_filter->filter_info);
2865                 if (it == NULL) {
2866                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
2867                         rte_free(flex_filter);
2868                         return -ENOENT;
2869                 }
2870
2871                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2872                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2873                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2874                         (~(E1000_WUFC_FLX0 << it->index)));
2875
2876                 filter_info->flex_mask &= ~(1 << it->index);
2877                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2878                 rte_free(it);
2879                 rte_free(flex_filter);
2880         }
2881
2882         return 0;
2883 }
2884
2885 static int
2886 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2887                         struct rte_eth_flex_filter *filter)
2888 {
2889         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         struct e1000_filter_info *filter_info =
2891                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2892         struct e1000_flex_filter flex_filter, *it;
2893         uint32_t wufc, queueing, wufc_en = 0;
2894
2895         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2896         flex_filter.filter_info.len = filter->len;
2897         flex_filter.filter_info.priority = filter->priority;
2898         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2899         memcpy(flex_filter.filter_info.mask, filter->mask,
2900                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2901
2902         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2903                                 &flex_filter.filter_info);
2904         if (it == NULL) {
2905                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2906                 return -ENOENT;
2907         }
2908
2909         wufc = E1000_READ_REG(hw, E1000_WUFC);
2910         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2911
2912         if ((wufc & wufc_en) == wufc_en) {
2913                 uint32_t reg_off = 0;
2914                 if (it->index < E1000_MAX_FHFT)
2915                         reg_off = E1000_FHFT(it->index);
2916                 else
2917                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2918
2919                 queueing = E1000_READ_REG(hw,
2920                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2921                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2922                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2923                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2924                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2925                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2926                 return 0;
2927         }
2928         return -ENOENT;
2929 }
2930
2931 static int
2932 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2933                         enum rte_filter_op filter_op,
2934                         void *arg)
2935 {
2936         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937         struct rte_eth_flex_filter *filter;
2938         int ret = 0;
2939
2940         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2941
2942         if (filter_op == RTE_ETH_FILTER_NOP)
2943                 return ret;
2944
2945         if (arg == NULL) {
2946                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2947                             filter_op);
2948                 return -EINVAL;
2949         }
2950
2951         filter = (struct rte_eth_flex_filter *)arg;
2952         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2953             || filter->len % sizeof(uint64_t) != 0) {
2954                 PMD_DRV_LOG(ERR, "filter's length is out of range");
2955                 return -EINVAL;
2956         }
2957         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2958                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2959                 return -EINVAL;
2960         }
2961
2962         switch (filter_op) {
2963         case RTE_ETH_FILTER_ADD:
2964                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2965                 break;
2966         case RTE_ETH_FILTER_DELETE:
2967                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2968                 break;
2969         case RTE_ETH_FILTER_GET:
2970                 ret = eth_igb_get_flex_filter(dev, filter);
2971                 break;
2972         default:
2973                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2974                 ret = -EINVAL;
2975                 break;
2976         }
2977
2978         return ret;
2979 }
2980
2981 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
2982 static inline int
2983 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
2984                         struct e1000_5tuple_filter_info *filter_info)
2985 {
2986         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2987                 return -EINVAL;
2988         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2989                 return -EINVAL;  /* filter index is out of range. */
2990         if (filter->tcp_flags > TCP_FLAG_ALL)
2991                 return -EINVAL;  /* flags is invalid. */
2992
2993         switch (filter->dst_ip_mask) {
2994         case UINT32_MAX:
2995                 filter_info->dst_ip_mask = 0;
2996                 filter_info->dst_ip = filter->dst_ip;
2997                 break;
2998         case 0:
2999                 filter_info->dst_ip_mask = 1;
3000                 break;
3001         default:
3002                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3003                 return -EINVAL;
3004         }
3005
3006         switch (filter->src_ip_mask) {
3007         case UINT32_MAX:
3008                 filter_info->src_ip_mask = 0;
3009                 filter_info->src_ip = filter->src_ip;
3010                 break;
3011         case 0:
3012                 filter_info->src_ip_mask = 1;
3013                 break;
3014         default:
3015                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3016                 return -EINVAL;
3017         }
3018
3019         switch (filter->dst_port_mask) {
3020         case UINT16_MAX:
3021                 filter_info->dst_port_mask = 0;
3022                 filter_info->dst_port = filter->dst_port;
3023                 break;
3024         case 0:
3025                 filter_info->dst_port_mask = 1;
3026                 break;
3027         default:
3028                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3029                 return -EINVAL;
3030         }
3031
3032         switch (filter->src_port_mask) {
3033         case UINT16_MAX:
3034                 filter_info->src_port_mask = 0;
3035                 filter_info->src_port = filter->src_port;
3036                 break;
3037         case 0:
3038                 filter_info->src_port_mask = 1;
3039                 break;
3040         default:
3041                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3042                 return -EINVAL;
3043         }
3044
3045         switch (filter->proto_mask) {
3046         case UINT8_MAX:
3047                 filter_info->proto_mask = 0;
3048                 filter_info->proto = filter->proto;
3049                 break;
3050         case 0:
3051                 filter_info->proto_mask = 1;
3052                 break;
3053         default:
3054                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3055                 return -EINVAL;
3056         }
3057
3058         filter_info->priority = (uint8_t)filter->priority;
3059         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3060                 filter_info->tcp_flags = filter->tcp_flags;
3061         else
3062                 filter_info->tcp_flags = 0;
3063
3064         return 0;
3065 }
3066
3067 static inline struct e1000_5tuple_filter *
3068 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3069                         struct e1000_5tuple_filter_info *key)
3070 {
3071         struct e1000_5tuple_filter *it;
3072
3073         TAILQ_FOREACH(it, filter_list, entries) {
3074                 if (memcmp(key, &it->filter_info,
3075                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3076                         return it;
3077                 }
3078         }
3079         return NULL;
3080 }
3081
3082 /*
3083  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3084  *
3085  * @param
3086  * dev: Pointer to struct rte_eth_dev.
3087  * ntuple_filter: ponter to the filter that will be added.
3088  *
3089  * @return
3090  *    - On success, zero.
3091  *    - On failure, a negative value.
3092  */
3093 static int
3094 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3095                         struct rte_eth_ntuple_filter *ntuple_filter)
3096 {
3097         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098         struct e1000_filter_info *filter_info =
3099                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3100         struct e1000_5tuple_filter *filter;
3101         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3102         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3103         uint8_t i;
3104         int ret;
3105
3106         filter = rte_zmalloc("e1000_5tuple_filter",
3107                         sizeof(struct e1000_5tuple_filter), 0);
3108         if (filter == NULL)
3109                 return -ENOMEM;
3110
3111         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3112                                             &filter->filter_info);
3113         if (ret < 0) {
3114                 rte_free(filter);
3115                 return ret;
3116         }
3117
3118         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3119                                          &filter->filter_info) != NULL) {
3120                 PMD_DRV_LOG(ERR, "filter exists.");
3121                 rte_free(filter);
3122                 return -EEXIST;
3123         }
3124         filter->queue = ntuple_filter->queue;
3125
3126         /*
3127          * look for an unused 5tuple filter index,
3128          * and insert the filter to list.
3129          */
3130         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3131                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3132                         filter_info->fivetuple_mask |= 1 << i;
3133                         filter->index = i;
3134                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3135                                           filter,
3136                                           entries);
3137                         break;
3138                 }
3139         }
3140         if (i >= E1000_MAX_FTQF_FILTERS) {
3141                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3142                 rte_free(filter);
3143                 return -ENOSYS;
3144         }
3145
3146         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3147         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3148                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3149         if (filter->filter_info.dst_ip_mask == 0)
3150                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3151         if (filter->filter_info.src_port_mask == 0)
3152                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3153         if (filter->filter_info.proto_mask == 0)
3154                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3155         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3156                 E1000_FTQF_QUEUE_MASK;
3157         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3158         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3159         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3160         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3161
3162         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3163         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3164
3165         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3166         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3167                 imir |= E1000_IMIR_PORT_BP;
3168         else
3169                 imir &= ~E1000_IMIR_PORT_BP;
3170         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3171
3172         /* tcp flags bits setting. */
3173         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3174                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3175                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3176                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3177                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3178                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3179                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3180                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3181                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3182                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3183                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3184                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3185                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3186         } else
3187                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3188         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3189         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3190         return 0;
3191 }
3192
3193 /*
3194  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3195  *
3196  * @param
3197  * dev: Pointer to struct rte_eth_dev.
3198  * ntuple_filter: ponter to the filter that will be removed.
3199  *
3200  * @return
3201  *    - On success, zero.
3202  *    - On failure, a negative value.
3203  */
3204 static int
3205 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3206                                 struct rte_eth_ntuple_filter *ntuple_filter)
3207 {
3208         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209         struct e1000_filter_info *filter_info =
3210                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3211         struct e1000_5tuple_filter_info filter_5tuple;
3212         struct e1000_5tuple_filter *filter;
3213         int ret;
3214
3215         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3216         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3217                                             &filter_5tuple);
3218         if (ret < 0)
3219                 return ret;
3220
3221         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3222                                          &filter_5tuple);
3223         if (filter == NULL) {
3224                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3225                 return -ENOENT;
3226         }
3227
3228         filter_info->fivetuple_mask &= ~(1 << filter->index);
3229         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3230         rte_free(filter);
3231
3232         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3233                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3234         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3235         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3236         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3237         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3238         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3239         return 0;
3240 }
3241
3242 static int
3243 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3244 {
3245         uint32_t rctl;
3246         struct e1000_hw *hw;
3247         struct rte_eth_dev_info dev_info;
3248         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3249                                      VLAN_TAG_SIZE);
3250
3251         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3252
3253 #ifdef RTE_LIBRTE_82571_SUPPORT
3254         /* XXX: not bigger than max_rx_pktlen */
3255         if (hw->mac.type == e1000_82571)
3256                 return -ENOTSUP;
3257 #endif
3258         eth_igb_infos_get(dev, &dev_info);
3259
3260         /* check that mtu is within the allowed range */
3261         if ((mtu < ETHER_MIN_MTU) ||
3262             (frame_size > dev_info.max_rx_pktlen))
3263                 return -EINVAL;
3264
3265         /* refuse mtu that requires the support of scattered packets when this
3266          * feature has not been enabled before. */
3267         if (!dev->data->scattered_rx &&
3268             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3269                 return -EINVAL;
3270
3271         rctl = E1000_READ_REG(hw, E1000_RCTL);
3272
3273         /* switch to jumbo mode if needed */
3274         if (frame_size > ETHER_MAX_LEN) {
3275                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3276                 rctl |= E1000_RCTL_LPE;
3277         } else {
3278                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3279                 rctl &= ~E1000_RCTL_LPE;
3280         }
3281         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3282
3283         /* update max frame size */
3284         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3285
3286         E1000_WRITE_REG(hw, E1000_RLPML,
3287                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3288
3289         return 0;
3290 }
3291
3292 /*
3293  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3294  *
3295  * @param
3296  * dev: Pointer to struct rte_eth_dev.
3297  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3298  * add: if true, add filter, if false, remove filter
3299  *
3300  * @return
3301  *    - On success, zero.
3302  *    - On failure, a negative value.
3303  */
3304 static int
3305 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3306                         struct rte_eth_ntuple_filter *ntuple_filter,
3307                         bool add)
3308 {
3309         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3310         int ret;
3311
3312         switch (ntuple_filter->flags) {
3313         case RTE_5TUPLE_FLAGS:
3314         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3315                 if (hw->mac.type != e1000_82576)
3316                         return -ENOTSUP;
3317                 if (add)
3318                         ret = igb_add_5tuple_filter_82576(dev,
3319                                                           ntuple_filter);
3320                 else
3321                         ret = igb_remove_5tuple_filter_82576(dev,
3322                                                              ntuple_filter);
3323                 break;
3324         case RTE_2TUPLE_FLAGS:
3325         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3326                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3327                         return -ENOTSUP;
3328                 if (add)
3329                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3330                 else
3331                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3332                 break;
3333         default:
3334                 ret = -EINVAL;
3335                 break;
3336         }
3337
3338         return ret;
3339 }
3340
3341 /*
3342  * igb_get_ntuple_filter - get a ntuple filter
3343  *
3344  * @param
3345  * dev: Pointer to struct rte_eth_dev.
3346  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3347  *
3348  * @return
3349  *    - On success, zero.
3350  *    - On failure, a negative value.
3351  */
3352 static int
3353 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3354                         struct rte_eth_ntuple_filter *ntuple_filter)
3355 {
3356         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357         struct e1000_filter_info *filter_info =
3358                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3359         struct e1000_5tuple_filter_info filter_5tuple;
3360         struct e1000_2tuple_filter_info filter_2tuple;
3361         struct e1000_5tuple_filter *p_5tuple_filter;
3362         struct e1000_2tuple_filter *p_2tuple_filter;
3363         int ret;
3364
3365         switch (ntuple_filter->flags) {
3366         case RTE_5TUPLE_FLAGS:
3367         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3368                 if (hw->mac.type != e1000_82576)
3369                         return -ENOTSUP;
3370                 memset(&filter_5tuple,
3371                         0,
3372                         sizeof(struct e1000_5tuple_filter_info));
3373                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3374                                                     &filter_5tuple);
3375                 if (ret < 0)
3376                         return ret;
3377                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3378                                         &filter_info->fivetuple_list,
3379                                         &filter_5tuple);
3380                 if (p_5tuple_filter == NULL) {
3381                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3382                         return -ENOENT;
3383                 }
3384                 ntuple_filter->queue = p_5tuple_filter->queue;
3385                 break;
3386         case RTE_2TUPLE_FLAGS:
3387         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3388                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3389                         return -ENOTSUP;
3390                 memset(&filter_2tuple,
3391                         0,
3392                         sizeof(struct e1000_2tuple_filter_info));
3393                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3394                 if (ret < 0)
3395                         return ret;
3396                 p_2tuple_filter = igb_2tuple_filter_lookup(
3397                                         &filter_info->twotuple_list,
3398                                         &filter_2tuple);
3399                 if (p_2tuple_filter == NULL) {
3400                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3401                         return -ENOENT;
3402                 }
3403                 ntuple_filter->queue = p_2tuple_filter->queue;
3404                 break;
3405         default:
3406                 ret = -EINVAL;
3407                 break;
3408         }
3409
3410         return 0;
3411 }
3412
3413 /*
3414  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3415  * @dev: pointer to rte_eth_dev structure
3416  * @filter_op:operation will be taken.
3417  * @arg: a pointer to specific structure corresponding to the filter_op
3418  */
3419 static int
3420 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3421                                 enum rte_filter_op filter_op,
3422                                 void *arg)
3423 {
3424         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425         int ret;
3426
3427         MAC_TYPE_FILTER_SUP(hw->mac.type);
3428
3429         if (filter_op == RTE_ETH_FILTER_NOP)
3430                 return 0;
3431
3432         if (arg == NULL) {
3433                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3434                             filter_op);
3435                 return -EINVAL;
3436         }
3437
3438         switch (filter_op) {
3439         case RTE_ETH_FILTER_ADD:
3440                 ret = igb_add_del_ntuple_filter(dev,
3441                         (struct rte_eth_ntuple_filter *)arg,
3442                         TRUE);
3443                 break;
3444         case RTE_ETH_FILTER_DELETE:
3445                 ret = igb_add_del_ntuple_filter(dev,
3446                         (struct rte_eth_ntuple_filter *)arg,
3447                         FALSE);
3448                 break;
3449         case RTE_ETH_FILTER_GET:
3450                 ret = igb_get_ntuple_filter(dev,
3451                         (struct rte_eth_ntuple_filter *)arg);
3452                 break;
3453         default:
3454                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3455                 ret = -EINVAL;
3456                 break;
3457         }
3458         return ret;
3459 }
3460
3461 static inline int
3462 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3463                         uint16_t ethertype)
3464 {
3465         int i;
3466
3467         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3468                 if (filter_info->ethertype_filters[i] == ethertype &&
3469                     (filter_info->ethertype_mask & (1 << i)))
3470                         return i;
3471         }
3472         return -1;
3473 }
3474
3475 static inline int
3476 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3477                         uint16_t ethertype)
3478 {
3479         int i;
3480
3481         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3482                 if (!(filter_info->ethertype_mask & (1 << i))) {
3483                         filter_info->ethertype_mask |= 1 << i;
3484                         filter_info->ethertype_filters[i] = ethertype;
3485                         return i;
3486                 }
3487         }
3488         return -1;
3489 }
3490
3491 static inline int
3492 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3493                         uint8_t idx)
3494 {
3495         if (idx >= E1000_MAX_ETQF_FILTERS)
3496                 return -1;
3497         filter_info->ethertype_mask &= ~(1 << idx);
3498         filter_info->ethertype_filters[idx] = 0;
3499         return idx;
3500 }
3501
3502
3503 static int
3504 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3505                         struct rte_eth_ethertype_filter *filter,
3506                         bool add)
3507 {
3508         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509         struct e1000_filter_info *filter_info =
3510                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3511         uint32_t etqf = 0;
3512         int ret;
3513
3514         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3515                 filter->ether_type == ETHER_TYPE_IPv6) {
3516                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3517                         " ethertype filter.", filter->ether_type);
3518                 return -EINVAL;
3519         }
3520
3521         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3522                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3523                 return -EINVAL;
3524         }
3525         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3526                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3527                 return -EINVAL;
3528         }
3529
3530         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3531         if (ret >= 0 && add) {
3532                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3533                             filter->ether_type);
3534                 return -EEXIST;
3535         }
3536         if (ret < 0 && !add) {
3537                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3538                             filter->ether_type);
3539                 return -ENOENT;
3540         }
3541
3542         if (add) {
3543                 ret = igb_ethertype_filter_insert(filter_info,
3544                         filter->ether_type);
3545                 if (ret < 0) {
3546                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3547                         return -ENOSYS;
3548                 }
3549
3550                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3551                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3552                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3553         } else {
3554                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3555                 if (ret < 0)
3556                         return -ENOSYS;
3557         }
3558         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3559         E1000_WRITE_FLUSH(hw);
3560
3561         return 0;
3562 }
3563
3564 static int
3565 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3566                         struct rte_eth_ethertype_filter *filter)
3567 {
3568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569         struct e1000_filter_info *filter_info =
3570                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3571         uint32_t etqf;
3572         int ret;
3573
3574         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3575         if (ret < 0) {
3576                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3577                             filter->ether_type);
3578                 return -ENOENT;
3579         }
3580
3581         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3582         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3583                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3584                 filter->flags = 0;
3585                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3586                                 E1000_ETQF_QUEUE_SHIFT;
3587                 return 0;
3588         }
3589
3590         return -ENOENT;
3591 }
3592
3593 /*
3594  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3595  * @dev: pointer to rte_eth_dev structure
3596  * @filter_op:operation will be taken.
3597  * @arg: a pointer to specific structure corresponding to the filter_op
3598  */
3599 static int
3600 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3601                                 enum rte_filter_op filter_op,
3602                                 void *arg)
3603 {
3604         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605         int ret;
3606
3607         MAC_TYPE_FILTER_SUP(hw->mac.type);
3608
3609         if (filter_op == RTE_ETH_FILTER_NOP)
3610                 return 0;
3611
3612         if (arg == NULL) {
3613                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3614                             filter_op);
3615                 return -EINVAL;
3616         }
3617
3618         switch (filter_op) {
3619         case RTE_ETH_FILTER_ADD:
3620                 ret = igb_add_del_ethertype_filter(dev,
3621                         (struct rte_eth_ethertype_filter *)arg,
3622                         TRUE);
3623                 break;
3624         case RTE_ETH_FILTER_DELETE:
3625                 ret = igb_add_del_ethertype_filter(dev,
3626                         (struct rte_eth_ethertype_filter *)arg,
3627                         FALSE);
3628                 break;
3629         case RTE_ETH_FILTER_GET:
3630                 ret = igb_get_ethertype_filter(dev,
3631                         (struct rte_eth_ethertype_filter *)arg);
3632                 break;
3633         default:
3634                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3635                 ret = -EINVAL;
3636                 break;
3637         }
3638         return ret;
3639 }
3640
3641 static int
3642 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3643                      enum rte_filter_type filter_type,
3644                      enum rte_filter_op filter_op,
3645                      void *arg)
3646 {
3647         int ret = -EINVAL;
3648
3649         switch (filter_type) {
3650         case RTE_ETH_FILTER_NTUPLE:
3651                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3652                 break;
3653         case RTE_ETH_FILTER_ETHERTYPE:
3654                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3655                 break;
3656         case RTE_ETH_FILTER_SYN:
3657                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3658                 break;
3659         case RTE_ETH_FILTER_FLEXIBLE:
3660                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3661                 break;
3662         default:
3663                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3664                                                         filter_type);
3665                 break;
3666         }
3667
3668         return ret;
3669 }
3670
3671 static int
3672 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3673                          struct ether_addr *mc_addr_set,
3674                          uint32_t nb_mc_addr)
3675 {
3676         struct e1000_hw *hw;
3677
3678         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3680         return 0;
3681 }
3682
3683 static int
3684 igb_timesync_enable(struct rte_eth_dev *dev)
3685 {
3686         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3687         uint32_t tsync_ctl;
3688
3689         /* Start incrementing the register used to timestamp PTP packets. */
3690         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
3691
3692         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3693         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
3694                         (ETHER_TYPE_1588 |
3695                          E1000_ETQF_FILTER_ENABLE |
3696                          E1000_ETQF_1588));
3697
3698         /* Enable timestamping of received PTP packets. */
3699         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3700         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
3701         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3702
3703         /* Enable Timestamping of transmitted PTP packets. */
3704         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3705         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
3706         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3707
3708         return 0;
3709 }
3710
3711 static int
3712 igb_timesync_disable(struct rte_eth_dev *dev)
3713 {
3714         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715         uint32_t tsync_ctl;
3716
3717         /* Disable timestamping of transmitted PTP packets. */
3718         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3719         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
3720         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3721
3722         /* Disable timestamping of received PTP packets. */
3723         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3724         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
3725         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3726
3727         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3728         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
3729
3730         /* Stop incrementating the System Time registers. */
3731         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
3732
3733         return 0;
3734 }
3735
3736 static int
3737 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3738                                struct timespec *timestamp,
3739                                uint32_t flags __rte_unused)
3740 {
3741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742         uint32_t tsync_rxctl;
3743         uint32_t rx_stmpl;
3744         uint32_t rx_stmph;
3745
3746         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3747         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
3748                 return -EINVAL;
3749
3750         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
3751         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
3752
3753         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
3754         timestamp->tv_nsec = 0;
3755
3756         return  0;
3757 }
3758
3759 static int
3760 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3761                                struct timespec *timestamp)
3762 {
3763         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         uint32_t tsync_txctl;
3765         uint32_t tx_stmpl;
3766         uint32_t tx_stmph;
3767
3768         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3769         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
3770                 return -EINVAL;
3771
3772         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
3773         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
3774
3775         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
3776         timestamp->tv_nsec = 0;
3777
3778         return  0;
3779 }
3780
3781 static struct rte_driver pmd_igb_drv = {
3782         .type = PMD_PDEV,
3783         .init = rte_igb_pmd_init,
3784 };
3785
3786 static struct rte_driver pmd_igbvf_drv = {
3787         .type = PMD_PDEV,
3788         .init = rte_igbvf_pmd_init,
3789 };
3790
3791 PMD_REGISTER_DRIVER(pmd_igb_drv);
3792 PMD_REGISTER_DRIVER(pmd_igbvf_drv);