drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85
  86 static int  eth_igb_configure(struct rte_eth_dev *dev);
  87 static int  eth_igb_start(struct rte_eth_dev *dev);
  88 static void eth_igb_stop(struct rte_eth_dev *dev);
  89 static void eth_igb_close(struct rte_eth_dev *dev);
  90 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  92 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  94 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  95                                 int wait_to_complete);
  96 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  97                                 struct rte_eth_stats *rte_stats);
  98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  99 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 100                               struct rte_eth_dev_info *dev_info);
 101 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 102                                 struct rte_eth_dev_info *dev_info);
 103 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 104                                 struct rte_eth_fc_conf *fc_conf);
 105 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 106                                 struct rte_eth_fc_conf *fc_conf);
 107 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 108 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 109 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 110 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 111                                                         void *param);
 112 static int  igb_hardware_init(struct e1000_hw *hw);
 113 static void igb_hw_control_acquire(struct e1000_hw *hw);
 114 static void igb_hw_control_release(struct e1000_hw *hw);
 115 static void igb_init_manageability(struct e1000_hw *hw);
 116 static void igb_release_manageability(struct e1000_hw *hw);
 117
 118 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 119
 120 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 121                 uint16_t vlan_id, int on);
 122 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 123 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 124
 125 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 126 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 127 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 128 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 129 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 130 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 131
 132 static int eth_igb_led_on(struct rte_eth_dev *dev);
 133 static int eth_igb_led_off(struct rte_eth_dev *dev);
 134
 135 static void igb_intr_disable(struct e1000_hw *hw);
 136 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 137 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 138                 struct ether_addr *mac_addr,
 139                 uint32_t index, uint32_t pool);
 140 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 141 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 142                 struct ether_addr *addr);
 143
 144 static void igbvf_intr_disable(struct e1000_hw *hw);
 145 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 146 static int igbvf_dev_start(struct rte_eth_dev *dev);
 147 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 148 static void igbvf_dev_close(struct rte_eth_dev *dev);
 149 static int eth_igbvf_link_update(struct e1000_hw *hw);
 150 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 151 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 152 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 153                 uint16_t vlan_id, int on);
 154 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 155 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 156 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 157                 struct ether_addr *addr);
 158 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 159 static int igbvf_get_regs(struct rte_eth_dev *dev,
 160                 struct rte_dev_reg_info *regs);
 161
 162 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 163                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 164                                    uint16_t reta_size);
 165 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 166                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 167                                   uint16_t reta_size);
 168
 169 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 170                         struct rte_eth_syn_filter *filter,
 171                         bool add);
 172 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 173                         struct rte_eth_syn_filter *filter);
 174 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 175                         enum rte_filter_op filter_op,
 176                         void *arg);
 177 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 178                         struct rte_eth_ntuple_filter *ntuple_filter);
 179 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 180                         struct rte_eth_ntuple_filter *ntuple_filter);
 181 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 182                         struct rte_eth_flex_filter *filter,
 183                         bool add);
 184 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 185                         struct rte_eth_flex_filter *filter);
 186 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 187                         enum rte_filter_op filter_op,
 188                         void *arg);
 189 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 190                         struct rte_eth_ntuple_filter *ntuple_filter);
 191 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *filter,
 195                         bool add);
 196 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *filter);
 198 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 199                                 enum rte_filter_op filter_op,
 200                                 void *arg);
 201 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_ethertype_filter *filter,
 203                         bool add);
 204 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 205                                 enum rte_filter_op filter_op,
 206                                 void *arg);
 207 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ethertype_filter *filter);
 209 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 210                      enum rte_filter_type filter_type,
 211                      enum rte_filter_op filter_op,
 212                      void *arg);
 213 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 214 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 215                 struct rte_dev_reg_info *regs);
 216 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 217 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 218                 struct rte_dev_eeprom_info *eeprom);
 219 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 220                 struct rte_dev_eeprom_info *eeprom);
 221
 222 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 223                                     struct ether_addr *mc_addr_set,
 224                                     uint32_t nb_mc_addr);
 225 static int igb_timesync_enable(struct rte_eth_dev *dev);
 226 static int igb_timesync_disable(struct rte_eth_dev *dev);
 227 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 228                                           struct timespec *timestamp,
 229                                           uint32_t flags);
 230 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 231                                           struct timespec *timestamp);
 232
 233 /*
 234  * Define VF Stats MACRO for Non "cleared on read" register
 235  */
 236 #define UPDATE_VF_STAT(reg, last, cur)            \
 237 {                                                 \
 238         u32 latest = E1000_READ_REG(hw, reg);     \
 239         cur += latest - last;                     \
 240         last = latest;                            \
 241 }
 242
 243
 244 #define IGB_FC_PAUSE_TIME 0x0680
 245 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 246 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 247
 248 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 249
 250 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 251
 252 /*
 253  * The set of PCI devices this driver supports
 254  */
 255 static const struct rte_pci_id pci_id_igb_map[] = {
 256
 257 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 258 #include "rte_pci_dev_ids.h"
 259
 260 {0},
 261 };
 262
 263 /*
 264  * The set of PCI devices this driver supports (for 82576&I350 VF)
 265  */
 266 static const struct rte_pci_id pci_id_igbvf_map[] = {
 267
 268 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 269 #include "rte_pci_dev_ids.h"
 270
 271 {0},
 272 };
 273
 274 static const struct eth_dev_ops eth_igb_ops = {
 275         .dev_configure        = eth_igb_configure,
 276         .dev_start            = eth_igb_start,
 277         .dev_stop             = eth_igb_stop,
 278         .dev_close            = eth_igb_close,
 279         .promiscuous_enable   = eth_igb_promiscuous_enable,
 280         .promiscuous_disable  = eth_igb_promiscuous_disable,
 281         .allmulticast_enable  = eth_igb_allmulticast_enable,
 282         .allmulticast_disable = eth_igb_allmulticast_disable,
 283         .link_update          = eth_igb_link_update,
 284         .stats_get            = eth_igb_stats_get,
 285         .stats_reset          = eth_igb_stats_reset,
 286         .dev_infos_get        = eth_igb_infos_get,
 287         .mtu_set              = eth_igb_mtu_set,
 288         .vlan_filter_set      = eth_igb_vlan_filter_set,
 289         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 290         .vlan_offload_set     = eth_igb_vlan_offload_set,
 291         .rx_queue_setup       = eth_igb_rx_queue_setup,
 292         .rx_queue_release     = eth_igb_rx_queue_release,
 293         .rx_queue_count       = eth_igb_rx_queue_count,
 294         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 295         .tx_queue_setup       = eth_igb_tx_queue_setup,
 296         .tx_queue_release     = eth_igb_tx_queue_release,
 297         .dev_led_on           = eth_igb_led_on,
 298         .dev_led_off          = eth_igb_led_off,
 299         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 300         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 301         .mac_addr_add         = eth_igb_rar_set,
 302         .mac_addr_remove      = eth_igb_rar_clear,
 303         .mac_addr_set         = eth_igb_default_mac_addr_set,
 304         .reta_update          = eth_igb_rss_reta_update,
 305         .reta_query           = eth_igb_rss_reta_query,
 306         .rss_hash_update      = eth_igb_rss_hash_update,
 307         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 308         .filter_ctrl          = eth_igb_filter_ctrl,
 309         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 310         .timesync_enable      = igb_timesync_enable,
 311         .timesync_disable     = igb_timesync_disable,
 312         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 313         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 314         .get_reg_length       = eth_igb_get_reg_length,
 315         .get_reg              = eth_igb_get_regs,
 316         .get_eeprom_length    = eth_igb_get_eeprom_length,
 317         .get_eeprom           = eth_igb_get_eeprom,
 318         .set_eeprom           = eth_igb_set_eeprom,
 319 };
 320
 321 /*
 322  * dev_ops for virtual function, bare necessities for basic vf
 323  * operation have been implemented
 324  */
 325 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 326         .dev_configure        = igbvf_dev_configure,
 327         .dev_start            = igbvf_dev_start,
 328         .dev_stop             = igbvf_dev_stop,
 329         .dev_close            = igbvf_dev_close,
 330         .link_update          = eth_igb_link_update,
 331         .stats_get            = eth_igbvf_stats_get,
 332         .stats_reset          = eth_igbvf_stats_reset,
 333         .vlan_filter_set      = igbvf_vlan_filter_set,
 334         .dev_infos_get        = eth_igbvf_infos_get,
 335         .rx_queue_setup       = eth_igb_rx_queue_setup,
 336         .rx_queue_release     = eth_igb_rx_queue_release,
 337         .tx_queue_setup       = eth_igb_tx_queue_setup,
 338         .tx_queue_release     = eth_igb_tx_queue_release,
 339         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 340         .mac_addr_set         = igbvf_default_mac_addr_set,
 341         .get_reg_length       = igbvf_get_reg_length,
 342         .get_reg              = igbvf_get_regs,
 343 };
 344
 345 /**
 346  * Atomically reads the link status information from global
 347  * structure rte_eth_dev.
 348  *
 349  * @param dev
 350  *   - Pointer to the structure rte_eth_dev to read from.
 351  *   - Pointer to the buffer to be saved with the link status.
 352  *
 353  * @return
 354  *   - On success, zero.
 355  *   - On failure, negative value.
 356  */
 357 static inline int
 358 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 359                                 struct rte_eth_link *link)
 360 {
 361         struct rte_eth_link *dst = link;
 362         struct rte_eth_link *src = &(dev->data->dev_link);
 363
 364         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 365                                         *(uint64_t *)src) == 0)
 366                 return -1;
 367
 368         return 0;
 369 }
 370
 371 /**
 372  * Atomically writes the link status information into global
 373  * structure rte_eth_dev.
 374  *
 375  * @param dev
 376  *   - Pointer to the structure rte_eth_dev to read from.
 377  *   - Pointer to the buffer to be saved with the link status.
 378  *
 379  * @return
 380  *   - On success, zero.
 381  *   - On failure, negative value.
 382  */
 383 static inline int
 384 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 385                                 struct rte_eth_link *link)
 386 {
 387         struct rte_eth_link *dst = &(dev->data->dev_link);
 388         struct rte_eth_link *src = link;
 389
 390         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 391                                         *(uint64_t *)src) == 0)
 392                 return -1;
 393
 394         return 0;
 395 }
 396
 397 static inline void
 398 igb_intr_enable(struct rte_eth_dev *dev)
 399 {
 400         struct e1000_interrupt *intr =
 401                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 402         struct e1000_hw *hw =
 403                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 404
 405         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 406         E1000_WRITE_FLUSH(hw);
 407 }
 408
 409 static void
 410 igb_intr_disable(struct e1000_hw *hw)
 411 {
 412         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 413         E1000_WRITE_FLUSH(hw);
 414 }
 415
 416 static inline int32_t
 417 igb_pf_reset_hw(struct e1000_hw *hw)
 418 {
 419         uint32_t ctrl_ext;
 420         int32_t status;
 421
 422         status = e1000_reset_hw(hw);
 423
 424         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 425         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 426         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 427         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 428         E1000_WRITE_FLUSH(hw);
 429
 430         return status;
 431 }
 432
 433 static void
 434 igb_identify_hardware(struct rte_eth_dev *dev)
 435 {
 436         struct e1000_hw *hw =
 437                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 438
 439         hw->vendor_id = dev->pci_dev->id.vendor_id;
 440         hw->device_id = dev->pci_dev->id.device_id;
 441         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 442         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 443
 444         e1000_set_mac_type(hw);
 445
 446         /* need to check if it is a vf device below */
 447 }
 448
 449 static int
 450 igb_reset_swfw_lock(struct e1000_hw *hw)
 451 {
 452         int ret_val;
 453
 454         /*
 455          * Do mac ops initialization manually here, since we will need
 456          * some function pointers set by this call.
 457          */
 458         ret_val = e1000_init_mac_params(hw);
 459         if (ret_val)
 460                 return ret_val;
 461
 462         /*
 463          * SMBI lock should not fail in this early stage. If this is the case,
 464          * it is due to an improper exit of the application.
 465          * So force the release of the faulty lock.
 466          */
 467         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 468                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 469         }
 470         e1000_put_hw_semaphore_generic(hw);
 471
 472         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 473                 uint16_t mask;
 474
 475                 /*
 476                  * Phy lock should not fail in this early stage. If this is the case,
 477                  * it is due to an improper exit of the application.
 478                  * So force the release of the faulty lock.
 479                  */
 480                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 481                 if (hw->bus.func > E1000_FUNC_1)
 482                         mask <<= 2;
 483                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 484                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 485                                     hw->bus.func);
 486                 }
 487                 hw->mac.ops.release_swfw_sync(hw, mask);
 488
 489                 /*
 490                  * This one is more tricky since it is common to all ports; but
 491                  * swfw_sync retries last long enough (1s) to be almost sure that if
 492                  * lock can not be taken it is due to an improper lock of the
 493                  * semaphore.
 494                  */
 495                 mask = E1000_SWFW_EEP_SM;
 496                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 497                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 498                 }
 499                 hw->mac.ops.release_swfw_sync(hw, mask);
 500         }
 501
 502         return E1000_SUCCESS;
 503 }
 504
 505 static int
 506 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 507 {
 508         int error = 0;
 509         struct rte_pci_device *pci_dev;
 510         struct e1000_hw *hw =
 511                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 512         struct e1000_vfta * shadow_vfta =
 513                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 514         struct e1000_filter_info *filter_info =
 515                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 516         struct e1000_adapter *adapter =
 517                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 518
 519         uint32_t ctrl_ext;
 520
 521         pci_dev = eth_dev->pci_dev;
 522         eth_dev->dev_ops = &eth_igb_ops;
 523         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 524         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 525
 526         /* for secondary processes, we don't initialise any further as primary
 527          * has already done this work. Only check we don't need a different
 528          * RX function */
 529         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 530                 if (eth_dev->data->scattered_rx)
 531                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 532                 return 0;
 533         }
 534
 535         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 536
 537         igb_identify_hardware(eth_dev);
 538         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 539                 error = -EIO;
 540                 goto err_late;
 541         }
 542
 543         e1000_get_bus_info(hw);
 544
 545         /* Reset any pending lock */
 546         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 547                 error = -EIO;
 548                 goto err_late;
 549         }
 550
 551         /* Finish initialization */
 552         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 553                 error = -EIO;
 554                 goto err_late;
 555         }
 556
 557         hw->mac.autoneg = 1;
 558         hw->phy.autoneg_wait_to_complete = 0;
 559         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 560
 561         /* Copper options */
 562         if (hw->phy.media_type == e1000_media_type_copper) {
 563                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 564                 hw->phy.disable_polarity_correction = 0;
 565                 hw->phy.ms_type = e1000_ms_hw_default;
 566         }
 567
 568         /*
 569          * Start from a known state, this is important in reading the nvm
 570          * and mac from that.
 571          */
 572         igb_pf_reset_hw(hw);
 573
 574         /* Make sure we have a good EEPROM before we read from it */
 575         if (e1000_validate_nvm_checksum(hw) < 0) {
 576                 /*
 577                  * Some PCI-E parts fail the first check due to
 578                  * the link being in sleep state, call it again,
 579                  * if it fails a second time its a real issue.
 580                  */
 581                 if (e1000_validate_nvm_checksum(hw) < 0) {
 582                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 583                         error = -EIO;
 584                         goto err_late;
 585                 }
 586         }
 587
 588         /* Read the permanent MAC address out of the EEPROM */
 589         if (e1000_read_mac_addr(hw) != 0) {
 590                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 591                 error = -EIO;
 592                 goto err_late;
 593         }
 594
 595         /* Allocate memory for storing MAC addresses */
 596         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 597                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 598         if (eth_dev->data->mac_addrs == NULL) {
 599                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 600                                                 "store MAC addresses",
 601                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 602                 error = -ENOMEM;
 603                 goto err_late;
 604         }
 605
 606         /* Copy the permanent MAC address */
 607         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 608
 609         /* initialize the vfta */
 610         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 611
 612         /* Now initialize the hardware */
 613         if (igb_hardware_init(hw) != 0) {
 614                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 615                 rte_free(eth_dev->data->mac_addrs);
 616                 eth_dev->data->mac_addrs = NULL;
 617                 error = -ENODEV;
 618                 goto err_late;
 619         }
 620         hw->mac.get_link_status = 1;
 621         adapter->stopped = 0;
 622
 623         /* Indicate SOL/IDER usage */
 624         if (e1000_check_reset_block(hw) < 0) {
 625                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 626                                         "SOL/IDER session");
 627         }
 628
 629         /* initialize PF if max_vfs not zero */
 630         igb_pf_host_init(eth_dev);
 631
 632         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 633         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 634         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 635         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 636         E1000_WRITE_FLUSH(hw);
 637
 638         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 639                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 640                      pci_dev->id.device_id);
 641
 642         rte_intr_callback_register(&(pci_dev->intr_handle),
 643                 eth_igb_interrupt_handler, (void *)eth_dev);
 644
 645         /* enable uio intr after callback register */
 646         rte_intr_enable(&(pci_dev->intr_handle));
 647
 648         /* enable support intr */
 649         igb_intr_enable(eth_dev);
 650
 651         TAILQ_INIT(&filter_info->flex_list);
 652         filter_info->flex_mask = 0;
 653         TAILQ_INIT(&filter_info->twotuple_list);
 654         filter_info->twotuple_mask = 0;
 655         TAILQ_INIT(&filter_info->fivetuple_list);
 656         filter_info->fivetuple_mask = 0;
 657
 658         return 0;
 659
 660 err_late:
 661         igb_hw_control_release(hw);
 662
 663         return (error);
 664 }
 665
 666 static int
 667 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 668 {
 669         struct rte_pci_device *pci_dev;
 670         struct e1000_hw *hw;
 671         struct e1000_adapter *adapter =
 672                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 673
 674         PMD_INIT_FUNC_TRACE();
 675
 676         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 677                 return -EPERM;
 678
 679         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 680         pci_dev = eth_dev->pci_dev;
 681
 682         if (adapter->stopped == 0)
 683                 eth_igb_close(eth_dev);
 684
 685         eth_dev->dev_ops = NULL;
 686         eth_dev->rx_pkt_burst = NULL;
 687         eth_dev->tx_pkt_burst = NULL;
 688
 689         /* Reset any pending lock */
 690         igb_reset_swfw_lock(hw);
 691
 692         rte_free(eth_dev->data->mac_addrs);
 693         eth_dev->data->mac_addrs = NULL;
 694
 695         /* uninitialize PF if max_vfs not zero */
 696         igb_pf_host_uninit(eth_dev);
 697
 698         /* disable uio intr before callback unregister */
 699         rte_intr_disable(&(pci_dev->intr_handle));
 700         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 701                 eth_igb_interrupt_handler, (void *)eth_dev);
 702
 703         return 0;
 704 }
 705
 706 /*
 707  * Virtual Function device init
 708  */
 709 static int
 710 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 711 {
 712         struct rte_pci_device *pci_dev;
 713         struct e1000_adapter *adapter =
 714                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 715         struct e1000_hw *hw =
 716                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 717         int diag;
 718
 719         PMD_INIT_FUNC_TRACE();
 720
 721         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 722         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 723         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 724
 725         /* for secondary processes, we don't initialise any further as primary
 726          * has already done this work. Only check we don't need a different
 727          * RX function */
 728         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 729                 if (eth_dev->data->scattered_rx)
 730                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 731                 return 0;
 732         }
 733
 734         pci_dev = eth_dev->pci_dev;
 735
 736         hw->device_id = pci_dev->id.device_id;
 737         hw->vendor_id = pci_dev->id.vendor_id;
 738         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 739         adapter->stopped = 0;
 740
 741         /* Initialize the shared code (base driver) */
 742         diag = e1000_setup_init_funcs(hw, TRUE);
 743         if (diag != 0) {
 744                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 745                         diag);
 746                 return -EIO;
 747         }
 748
 749         /* init_mailbox_params */
 750         hw->mbx.ops.init_params(hw);
 751
 752         /* Disable the interrupts for VF */
 753         igbvf_intr_disable(hw);
 754
 755         diag = hw->mac.ops.reset_hw(hw);
 756
 757         /* Allocate memory for storing MAC addresses */
 758         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 759                 hw->mac.rar_entry_count, 0);
 760         if (eth_dev->data->mac_addrs == NULL) {
 761                 PMD_INIT_LOG(ERR,
 762                         "Failed to allocate %d bytes needed to store MAC "
 763                         "addresses",
 764                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 765                 return -ENOMEM;
 766         }
 767
 768         /* Copy the permanent MAC address */
 769         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 770                         &eth_dev->data->mac_addrs[0]);
 771
 772         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 773                      "mac.type=%s",
 774                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 775                      pci_dev->id.device_id, "igb_mac_82576_vf");
 776
 777         return 0;
 778 }
 779
 780 static int
 781 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 782 {
 783         struct e1000_adapter *adapter =
 784                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 785
 786         PMD_INIT_FUNC_TRACE();
 787
 788         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 789                 return -EPERM;
 790
 791         if (adapter->stopped == 0)
 792                 igbvf_dev_close(eth_dev);
 793
 794         eth_dev->dev_ops = NULL;
 795         eth_dev->rx_pkt_burst = NULL;
 796         eth_dev->tx_pkt_burst = NULL;
 797
 798         rte_free(eth_dev->data->mac_addrs);
 799         eth_dev->data->mac_addrs = NULL;
 800
 801         return 0;
 802 }
 803
 804 static struct eth_driver rte_igb_pmd = {
 805         .pci_drv = {
 806                 .name = "rte_igb_pmd",
 807                 .id_table = pci_id_igb_map,
 808                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 809                         RTE_PCI_DRV_DETACHABLE,
 810         },
 811         .eth_dev_init = eth_igb_dev_init,
 812         .eth_dev_uninit = eth_igb_dev_uninit,
 813         .dev_private_size = sizeof(struct e1000_adapter),
 814 };
 815
 816 /*
 817  * virtual function driver struct
 818  */
 819 static struct eth_driver rte_igbvf_pmd = {
 820         .pci_drv = {
 821                 .name = "rte_igbvf_pmd",
 822                 .id_table = pci_id_igbvf_map,
 823                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 824         },
 825         .eth_dev_init = eth_igbvf_dev_init,
 826         .eth_dev_uninit = eth_igbvf_dev_uninit,
 827         .dev_private_size = sizeof(struct e1000_adapter),
 828 };
 829
 830 static int
 831 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 832 {
 833         rte_eth_driver_register(&rte_igb_pmd);
 834         return 0;
 835 }
 836
 837 static void
 838 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 839 {
 840         struct e1000_hw *hw =
 841                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 842         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 843         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 844         rctl |= E1000_RCTL_VFE;
 845         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 846 }
 847
 848 /*
 849  * VF Driver initialization routine.
 850  * Invoked one at EAL init time.
 851  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 852  */
 853 static int
 854 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 855 {
 856         PMD_INIT_FUNC_TRACE();
 857
 858         rte_eth_driver_register(&rte_igbvf_pmd);
 859         return (0);
 860 }
 861
 862 static int
 863 eth_igb_configure(struct rte_eth_dev *dev)
 864 {
 865         struct e1000_interrupt *intr =
 866                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 867
 868         PMD_INIT_FUNC_TRACE();
 869         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 870         PMD_INIT_FUNC_TRACE();
 871
 872         return (0);
 873 }
 874
 875 static int
 876 eth_igb_start(struct rte_eth_dev *dev)
 877 {
 878         struct e1000_hw *hw =
 879                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 880         struct e1000_adapter *adapter =
 881                 E1000_DEV_PRIVATE(dev->data->dev_private);
 882         int ret, i, mask;
 883         uint32_t ctrl_ext;
 884
 885         PMD_INIT_FUNC_TRACE();
 886
 887         /* Power up the phy. Needed to make the link go Up */
 888         e1000_power_up_phy(hw);
 889
 890         /*
 891          * Packet Buffer Allocation (PBA)
 892          * Writing PBA sets the receive portion of the buffer
 893          * the remainder is used for the transmit buffer.
 894          */
 895         if (hw->mac.type == e1000_82575) {
 896                 uint32_t pba;
 897
 898                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 899                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 900         }
 901
 902         /* Put the address into the Receive Address Array */
 903         e1000_rar_set(hw, hw->mac.addr, 0);
 904
 905         /* Initialize the hardware */
 906         if (igb_hardware_init(hw)) {
 907                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 908                 return (-EIO);
 909         }
 910         adapter->stopped = 0;
 911
 912         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 913
 914         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 915         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 916         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 917         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 918         E1000_WRITE_FLUSH(hw);
 919
 920         /* configure PF module if SRIOV enabled */
 921         igb_pf_host_configure(dev);
 922
 923         /* Configure for OS presence */
 924         igb_init_manageability(hw);
 925
 926         eth_igb_tx_init(dev);
 927
 928         /* This can fail when allocating mbufs for descriptor rings */
 929         ret = eth_igb_rx_init(dev);
 930         if (ret) {
 931                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 932                 igb_dev_clear_queues(dev);
 933                 return ret;
 934         }
 935
 936         e1000_clear_hw_cntrs_base_generic(hw);
 937
 938         /*
 939          * VLAN Offload Settings
 940          */
 941         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 942                         ETH_VLAN_EXTEND_MASK;
 943         eth_igb_vlan_offload_set(dev, mask);
 944
 945         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 946                 /* Enable VLAN filter since VMDq always use VLAN filter */
 947                 igb_vmdq_vlan_hw_filter_enable(dev);
 948         }
 949
 950         /*
 951          * Configure the Interrupt Moderation register (EITR) with the maximum
 952          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 953          * spurious [DMA] memory updates of RX and TX ring descriptors.
 954          *
 955          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 956          * spurious memory updates per second should be expected.
 957          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 958          *
 959          * Because interrupts are not used at all, the MSI-X is not activated
 960          * and interrupt moderation is controlled by EITR[0].
 961          *
 962          * Note that having [almost] disabled memory updates of RX and TX ring
 963          * descriptors through the Interrupt Moderation mechanism, memory
 964          * updates of ring descriptors are now moderated by the configurable
 965          * value of Write-Back Threshold registers.
 966          */
 967         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 968                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 969                 (hw->mac.type == e1000_i211)) {
 970                 uint32_t ivar;
 971
 972                 /* Enable all RX & TX queues in the IVAR registers */
 973                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 974                 for (i = 0; i < 8; i++)
 975                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 976
 977                 /* Configure EITR with the maximum possible value (0xFFFF) */
 978                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 979         }
 980
 981         /* Setup link speed and duplex */
 982         switch (dev->data->dev_conf.link_speed) {
 983         case ETH_LINK_SPEED_AUTONEG:
 984                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 985                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 986                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 987                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 988                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 989                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 990                 else
 991                         goto error_invalid_config;
 992                 break;
 993         case ETH_LINK_SPEED_10:
 994                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 995                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 996                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 997                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 998                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 999                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1000                 else
1001                         goto error_invalid_config;
1002                 break;
1003         case ETH_LINK_SPEED_100:
1004                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1005                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1006                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1007                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1008                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1009                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1010                 else
1011                         goto error_invalid_config;
1012                 break;
1013         case ETH_LINK_SPEED_1000:
1014                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1015                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1016                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1017                 else
1018                         goto error_invalid_config;
1019                 break;
1020         case ETH_LINK_SPEED_10000:
1021         default:
1022                 goto error_invalid_config;
1023         }
1024         e1000_setup_link(hw);
1025
1026         /* check if lsc interrupt feature is enabled */
1027         if (dev->data->dev_conf.intr_conf.lsc != 0)
1028                 ret = eth_igb_lsc_interrupt_setup(dev);
1029
1030         /* resume enabled intr since hw reset */
1031         igb_intr_enable(dev);
1032
1033         PMD_INIT_LOG(DEBUG, "<<");
1034
1035         return (0);
1036
1037 error_invalid_config:
1038         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1039                      dev->data->dev_conf.link_speed,
1040                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1041         igb_dev_clear_queues(dev);
1042         return (-EINVAL);
1043 }
1044
1045 /*********************************************************************
1046  *
1047  *  This routine disables all traffic on the adapter by issuing a
1048  *  global reset on the MAC.
1049  *
1050  **********************************************************************/
1051 static void
1052 eth_igb_stop(struct rte_eth_dev *dev)
1053 {
1054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055         struct e1000_filter_info *filter_info =
1056                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1057         struct rte_eth_link link;
1058         struct e1000_flex_filter *p_flex;
1059         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1060         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1061
1062         igb_intr_disable(hw);
1063         igb_pf_reset_hw(hw);
1064         E1000_WRITE_REG(hw, E1000_WUC, 0);
1065
1066         /* Set bit for Go Link disconnect */
1067         if (hw->mac.type >= e1000_82580) {
1068                 uint32_t phpm_reg;
1069
1070                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1071                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1072                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1073         }
1074
1075         /* Power down the phy. Needed to make the link go Down */
1076         if (hw->phy.media_type == e1000_media_type_copper)
1077                 e1000_power_down_phy(hw);
1078         else
1079                 e1000_shutdown_fiber_serdes_link(hw);
1080
1081         igb_dev_clear_queues(dev);
1082
1083         /* clear the recorded link status */
1084         memset(&link, 0, sizeof(link));
1085         rte_igb_dev_atomic_write_link_status(dev, &link);
1086
1087         /* Remove all flex filters of the device */
1088         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1089                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1090                 rte_free(p_flex);
1091         }
1092         filter_info->flex_mask = 0;
1093
1094         /* Remove all ntuple filters of the device */
1095         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1096              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1097                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1098                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1099                              p_5tuple, entries);
1100                 rte_free(p_5tuple);
1101         }
1102         filter_info->fivetuple_mask = 0;
1103         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1104              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1105                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1106                 TAILQ_REMOVE(&filter_info->twotuple_list,
1107                              p_2tuple, entries);
1108                 rte_free(p_2tuple);
1109         }
1110         filter_info->twotuple_mask = 0;
1111 }
1112
1113 static void
1114 eth_igb_close(struct rte_eth_dev *dev)
1115 {
1116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117         struct e1000_adapter *adapter =
1118                 E1000_DEV_PRIVATE(dev->data->dev_private);
1119         struct rte_eth_link link;
1120
1121         eth_igb_stop(dev);
1122         adapter->stopped = 1;
1123
1124         e1000_phy_hw_reset(hw);
1125         igb_release_manageability(hw);
1126         igb_hw_control_release(hw);
1127
1128         /* Clear bit for Go Link disconnect */
1129         if (hw->mac.type >= e1000_82580) {
1130                 uint32_t phpm_reg;
1131
1132                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1133                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1134                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1135         }
1136
1137         igb_dev_clear_queues(dev);
1138
1139         memset(&link, 0, sizeof(link));
1140         rte_igb_dev_atomic_write_link_status(dev, &link);
1141 }
1142
1143 static int
1144 igb_get_rx_buffer_size(struct e1000_hw *hw)
1145 {
1146         uint32_t rx_buf_size;
1147         if (hw->mac.type == e1000_82576) {
1148                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1149         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1150                 /* PBS needs to be translated according to a lookup table */
1151                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1152                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1153                 rx_buf_size = (rx_buf_size << 10);
1154         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1155                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1156         } else {
1157                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1158         }
1159
1160         return rx_buf_size;
1161 }
1162
1163 /*********************************************************************
1164  *
1165  *  Initialize the hardware
1166  *
1167  **********************************************************************/
1168 static int
1169 igb_hardware_init(struct e1000_hw *hw)
1170 {
1171         uint32_t rx_buf_size;
1172         int diag;
1173
1174         /* Let the firmware know the OS is in control */
1175         igb_hw_control_acquire(hw);
1176
1177         /*
1178          * These parameters control the automatic generation (Tx) and
1179          * response (Rx) to Ethernet PAUSE frames.
1180          * - High water mark should allow for at least two standard size (1518)
1181          *   frames to be received after sending an XOFF.
1182          * - Low water mark works best when it is very near the high water mark.
1183          *   This allows the receiver to restart by sending XON when it has
1184          *   drained a bit. Here we use an arbitrary value of 1500 which will
1185          *   restart after one full frame is pulled from the buffer. There
1186          *   could be several smaller frames in the buffer and if so they will
1187          *   not trigger the XON until their total number reduces the buffer
1188          *   by 1500.
1189          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1190          */
1191         rx_buf_size = igb_get_rx_buffer_size(hw);
1192
1193         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1194         hw->fc.low_water = hw->fc.high_water - 1500;
1195         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1196         hw->fc.send_xon = 1;
1197
1198         /* Set Flow control, use the tunable location if sane */
1199         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1200                 hw->fc.requested_mode = igb_fc_setting;
1201         else
1202                 hw->fc.requested_mode = e1000_fc_none;
1203
1204         /* Issue a global reset */
1205         igb_pf_reset_hw(hw);
1206         E1000_WRITE_REG(hw, E1000_WUC, 0);
1207
1208         diag = e1000_init_hw(hw);
1209         if (diag < 0)
1210                 return (diag);
1211
1212         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1213         e1000_get_phy_info(hw);
1214         e1000_check_for_link(hw);
1215
1216         return (0);
1217 }
1218
1219 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1220 static void
1221 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1222 {
1223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224         struct e1000_hw_stats *stats =
1225                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1226         int pause_frames;
1227
1228         if(hw->phy.media_type == e1000_media_type_copper ||
1229             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1230                 stats->symerrs +=
1231                     E1000_READ_REG(hw,E1000_SYMERRS);
1232                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1233         }
1234
1235         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1236         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1237         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1238         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1239
1240         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1241         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1242         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1243         stats->dc += E1000_READ_REG(hw, E1000_DC);
1244         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1245         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1246         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1247         /*
1248         ** For watchdog management we need to know if we have been
1249         ** paused during the last interval, so capture that here.
1250         */
1251         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1252         stats->xoffrxc += pause_frames;
1253         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1254         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1255         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1256         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1257         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1258         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1259         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1260         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1261         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1262         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1263         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1264         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1265
1266         /* For the 64-bit byte counters the low dword must be read first. */
1267         /* Both registers clear on the read of the high dword */
1268
1269         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1270         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1271         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1272         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1273
1274         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1275         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1276         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1277         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1278         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1279
1280         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1281         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1282
1283         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1284         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1285         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1286         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1287         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1288         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1289         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1290         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1291         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1292         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1293
1294         /* Interrupt Counts */
1295
1296         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1297         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1298         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1299         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1300         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1301         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1302         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1303         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1304         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1305
1306         /* Host to Card Statistics */
1307
1308         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1309         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1310         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1311         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1312         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1313         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1314         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1315         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1316         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1317         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1318         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1319         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1320         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1321         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1322
1323         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1324         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1325         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1326         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1327         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1328         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1329
1330         if (rte_stats == NULL)
1331                 return;
1332
1333         /* Rx Errors */
1334         rte_stats->ibadcrc = stats->crcerrs;
1335         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1336         rte_stats->imissed = stats->mpc;
1337         rte_stats->ierrors = rte_stats->ibadcrc +
1338                              rte_stats->ibadlen +
1339                              rte_stats->imissed +
1340                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1341
1342         /* Tx Errors */
1343         rte_stats->oerrors = stats->ecol + stats->latecol;
1344
1345         /* XON/XOFF pause frames */
1346         rte_stats->tx_pause_xon  = stats->xontxc;
1347         rte_stats->rx_pause_xon  = stats->xonrxc;
1348         rte_stats->tx_pause_xoff = stats->xofftxc;
1349         rte_stats->rx_pause_xoff = stats->xoffrxc;
1350
1351         rte_stats->ipackets = stats->gprc;
1352         rte_stats->opackets = stats->gptc;
1353         rte_stats->ibytes   = stats->gorc;
1354         rte_stats->obytes   = stats->gotc;
1355 }
1356
1357 static void
1358 eth_igb_stats_reset(struct rte_eth_dev *dev)
1359 {
1360         struct e1000_hw_stats *hw_stats =
1361                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1362
1363         /* HW registers are cleared on read */
1364         eth_igb_stats_get(dev, NULL);
1365
1366         /* Reset software totals */
1367         memset(hw_stats, 0, sizeof(*hw_stats));
1368 }
1369
1370 static void
1371 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1372 {
1373         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1375                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1376
1377         /* Good Rx packets, include VF loopback */
1378         UPDATE_VF_STAT(E1000_VFGPRC,
1379             hw_stats->last_gprc, hw_stats->gprc);
1380
1381         /* Good Rx octets, include VF loopback */
1382         UPDATE_VF_STAT(E1000_VFGORC,
1383             hw_stats->last_gorc, hw_stats->gorc);
1384
1385         /* Good Tx packets, include VF loopback */
1386         UPDATE_VF_STAT(E1000_VFGPTC,
1387             hw_stats->last_gptc, hw_stats->gptc);
1388
1389         /* Good Tx octets, include VF loopback */
1390         UPDATE_VF_STAT(E1000_VFGOTC,
1391             hw_stats->last_gotc, hw_stats->gotc);
1392
1393         /* Rx Multicst packets */
1394         UPDATE_VF_STAT(E1000_VFMPRC,
1395             hw_stats->last_mprc, hw_stats->mprc);
1396
1397         /* Good Rx loopback packets */
1398         UPDATE_VF_STAT(E1000_VFGPRLBC,
1399             hw_stats->last_gprlbc, hw_stats->gprlbc);
1400
1401         /* Good Rx loopback octets */
1402         UPDATE_VF_STAT(E1000_VFGORLBC,
1403             hw_stats->last_gorlbc, hw_stats->gorlbc);
1404
1405         /* Good Tx loopback packets */
1406         UPDATE_VF_STAT(E1000_VFGPTLBC,
1407             hw_stats->last_gptlbc, hw_stats->gptlbc);
1408
1409         /* Good Tx loopback octets */
1410         UPDATE_VF_STAT(E1000_VFGOTLBC,
1411             hw_stats->last_gotlbc, hw_stats->gotlbc);
1412
1413         if (rte_stats == NULL)
1414                 return;
1415
1416         rte_stats->ipackets = hw_stats->gprc;
1417         rte_stats->ibytes = hw_stats->gorc;
1418         rte_stats->opackets = hw_stats->gptc;
1419         rte_stats->obytes = hw_stats->gotc;
1420         rte_stats->imcasts = hw_stats->mprc;
1421         rte_stats->ilbpackets = hw_stats->gprlbc;
1422         rte_stats->ilbbytes = hw_stats->gorlbc;
1423         rte_stats->olbpackets = hw_stats->gptlbc;
1424         rte_stats->olbbytes = hw_stats->gotlbc;
1425
1426 }
1427
1428 static void
1429 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1430 {
1431         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1432                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1433
1434         /* Sync HW register to the last stats */
1435         eth_igbvf_stats_get(dev, NULL);
1436
1437         /* reset HW current stats*/
1438         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1439                offsetof(struct e1000_vf_stats, gprc));
1440
1441 }
1442
1443 static void
1444 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1445 {
1446         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1447
1448         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1449         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1450         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1451         dev_info->rx_offload_capa =
1452                 DEV_RX_OFFLOAD_VLAN_STRIP |
1453                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1454                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1455                 DEV_RX_OFFLOAD_TCP_CKSUM;
1456         dev_info->tx_offload_capa =
1457                 DEV_TX_OFFLOAD_VLAN_INSERT |
1458                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1459                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1460                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1461                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1462
1463         switch (hw->mac.type) {
1464         case e1000_82575:
1465                 dev_info->max_rx_queues = 4;
1466                 dev_info->max_tx_queues = 4;
1467                 dev_info->max_vmdq_pools = 0;
1468                 break;
1469
1470         case e1000_82576:
1471                 dev_info->max_rx_queues = 16;
1472                 dev_info->max_tx_queues = 16;
1473                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1474                 dev_info->vmdq_queue_num = 16;
1475                 break;
1476
1477         case e1000_82580:
1478                 dev_info->max_rx_queues = 8;
1479                 dev_info->max_tx_queues = 8;
1480                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1481                 dev_info->vmdq_queue_num = 8;
1482                 break;
1483
1484         case e1000_i350:
1485                 dev_info->max_rx_queues = 8;
1486                 dev_info->max_tx_queues = 8;
1487                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1488                 dev_info->vmdq_queue_num = 8;
1489                 break;
1490
1491         case e1000_i354:
1492                 dev_info->max_rx_queues = 8;
1493                 dev_info->max_tx_queues = 8;
1494                 break;
1495
1496         case e1000_i210:
1497                 dev_info->max_rx_queues = 4;
1498                 dev_info->max_tx_queues = 4;
1499                 dev_info->max_vmdq_pools = 0;
1500                 break;
1501
1502         case e1000_i211:
1503                 dev_info->max_rx_queues = 2;
1504                 dev_info->max_tx_queues = 2;
1505                 dev_info->max_vmdq_pools = 0;
1506                 break;
1507
1508         default:
1509                 /* Should not happen */
1510                 break;
1511         }
1512         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1513         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1514         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1515
1516         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1517                 .rx_thresh = {
1518                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1519                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1520                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1521                 },
1522                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1523                 .rx_drop_en = 0,
1524         };
1525
1526         dev_info->default_txconf = (struct rte_eth_txconf) {
1527                 .tx_thresh = {
1528                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1529                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1530                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1531                 },
1532                 .txq_flags = 0,
1533         };
1534 }
1535
1536 static void
1537 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1538 {
1539         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540
1541         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1542         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1543         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1544         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1545                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1546                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1547                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1548         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1549                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1550                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1551                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1552                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1553         switch (hw->mac.type) {
1554         case e1000_vfadapt:
1555                 dev_info->max_rx_queues = 2;
1556                 dev_info->max_tx_queues = 2;
1557                 break;
1558         case e1000_vfadapt_i350:
1559                 dev_info->max_rx_queues = 1;
1560                 dev_info->max_tx_queues = 1;
1561                 break;
1562         default:
1563                 /* Should not happen */
1564                 break;
1565         }
1566
1567         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1568                 .rx_thresh = {
1569                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1570                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1571                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1572                 },
1573                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1574                 .rx_drop_en = 0,
1575         };
1576
1577         dev_info->default_txconf = (struct rte_eth_txconf) {
1578                 .tx_thresh = {
1579                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1580                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1581                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1582                 },
1583                 .txq_flags = 0,
1584         };
1585 }
1586
1587 /* return 0 means link status changed, -1 means not changed */
1588 static int
1589 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1590 {
1591         struct e1000_hw *hw =
1592                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593         struct rte_eth_link link, old;
1594         int link_check, count;
1595
1596         link_check = 0;
1597         hw->mac.get_link_status = 1;
1598
1599         /* possible wait-to-complete in up to 9 seconds */
1600         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1601                 /* Read the real link status */
1602                 switch (hw->phy.media_type) {
1603                 case e1000_media_type_copper:
1604                         /* Do the work to read phy */
1605                         e1000_check_for_link(hw);
1606                         link_check = !hw->mac.get_link_status;
1607                         break;
1608
1609                 case e1000_media_type_fiber:
1610                         e1000_check_for_link(hw);
1611                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1612                                       E1000_STATUS_LU);
1613                         break;
1614
1615                 case e1000_media_type_internal_serdes:
1616                         e1000_check_for_link(hw);
1617                         link_check = hw->mac.serdes_has_link;
1618                         break;
1619
1620                 /* VF device is type_unknown */
1621                 case e1000_media_type_unknown:
1622                         eth_igbvf_link_update(hw);
1623                         link_check = !hw->mac.get_link_status;
1624                         break;
1625
1626                 default:
1627                         break;
1628                 }
1629                 if (link_check || wait_to_complete == 0)
1630                         break;
1631                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1632         }
1633         memset(&link, 0, sizeof(link));
1634         rte_igb_dev_atomic_read_link_status(dev, &link);
1635         old = link;
1636
1637         /* Now we check if a transition has happened */
1638         if (link_check) {
1639                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1640                                           &link.link_duplex);
1641                 link.link_status = 1;
1642         } else if (!link_check) {
1643                 link.link_speed = 0;
1644                 link.link_duplex = 0;
1645                 link.link_status = 0;
1646         }
1647         rte_igb_dev_atomic_write_link_status(dev, &link);
1648
1649         /* not changed */
1650         if (old.link_status == link.link_status)
1651                 return -1;
1652
1653         /* changed */
1654         return 0;
1655 }
1656
1657 /*
1658  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1659  * For ASF and Pass Through versions of f/w this means
1660  * that the driver is loaded.
1661  */
1662 static void
1663 igb_hw_control_acquire(struct e1000_hw *hw)
1664 {
1665         uint32_t ctrl_ext;
1666
1667         /* Let firmware know the driver has taken over */
1668         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1669         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1670 }
1671
1672 /*
1673  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1674  * For ASF and Pass Through versions of f/w this means that the
1675  * driver is no longer loaded.
1676  */
1677 static void
1678 igb_hw_control_release(struct e1000_hw *hw)
1679 {
1680         uint32_t ctrl_ext;
1681
1682         /* Let firmware taken over control of h/w */
1683         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1684         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1685                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1686 }
1687
1688 /*
1689  * Bit of a misnomer, what this really means is
1690  * to enable OS management of the system... aka
1691  * to disable special hardware management features.
1692  */
1693 static void
1694 igb_init_manageability(struct e1000_hw *hw)
1695 {
1696         if (e1000_enable_mng_pass_thru(hw)) {
1697                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1698                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1699
1700                 /* disable hardware interception of ARP */
1701                 manc &= ~(E1000_MANC_ARP_EN);
1702
1703                 /* enable receiving management packets to the host */
1704                 manc |= E1000_MANC_EN_MNG2HOST;
1705                 manc2h |= 1 << 5;  /* Mng Port 623 */
1706                 manc2h |= 1 << 6;  /* Mng Port 664 */
1707                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1708                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1709         }
1710 }
1711
1712 static void
1713 igb_release_manageability(struct e1000_hw *hw)
1714 {
1715         if (e1000_enable_mng_pass_thru(hw)) {
1716                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1717
1718                 manc |= E1000_MANC_ARP_EN;
1719                 manc &= ~E1000_MANC_EN_MNG2HOST;
1720
1721                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1722         }
1723 }
1724
1725 static void
1726 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1727 {
1728         struct e1000_hw *hw =
1729                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1730         uint32_t rctl;
1731
1732         rctl = E1000_READ_REG(hw, E1000_RCTL);
1733         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1734         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1735 }
1736
1737 static void
1738 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1739 {
1740         struct e1000_hw *hw =
1741                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742         uint32_t rctl;
1743
1744         rctl = E1000_READ_REG(hw, E1000_RCTL);
1745         rctl &= (~E1000_RCTL_UPE);
1746         if (dev->data->all_multicast == 1)
1747                 rctl |= E1000_RCTL_MPE;
1748         else
1749                 rctl &= (~E1000_RCTL_MPE);
1750         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1751 }
1752
1753 static void
1754 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1755 {
1756         struct e1000_hw *hw =
1757                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758         uint32_t rctl;
1759
1760         rctl = E1000_READ_REG(hw, E1000_RCTL);
1761         rctl |= E1000_RCTL_MPE;
1762         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1763 }
1764
1765 static void
1766 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1767 {
1768         struct e1000_hw *hw =
1769                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         uint32_t rctl;
1771
1772         if (dev->data->promiscuous == 1)
1773                 return; /* must remain in all_multicast mode */
1774         rctl = E1000_READ_REG(hw, E1000_RCTL);
1775         rctl &= (~E1000_RCTL_MPE);
1776         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1777 }
1778
1779 static int
1780 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1781 {
1782         struct e1000_hw *hw =
1783                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784         struct e1000_vfta * shadow_vfta =
1785                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1786         uint32_t vfta;
1787         uint32_t vid_idx;
1788         uint32_t vid_bit;
1789
1790         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1791                               E1000_VFTA_ENTRY_MASK);
1792         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1793         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1794         if (on)
1795                 vfta |= vid_bit;
1796         else
1797                 vfta &= ~vid_bit;
1798         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1799
1800         /* update local VFTA copy */
1801         shadow_vfta->vfta[vid_idx] = vfta;
1802
1803         return 0;
1804 }
1805
1806 static void
1807 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1808 {
1809         struct e1000_hw *hw =
1810                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811         uint32_t reg = ETHER_TYPE_VLAN ;
1812
1813         reg |= (tpid << 16);
1814         E1000_WRITE_REG(hw, E1000_VET, reg);
1815 }
1816
1817 static void
1818 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1819 {
1820         struct e1000_hw *hw =
1821                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         uint32_t reg;
1823
1824         /* Filter Table Disable */
1825         reg = E1000_READ_REG(hw, E1000_RCTL);
1826         reg &= ~E1000_RCTL_CFIEN;
1827         reg &= ~E1000_RCTL_VFE;
1828         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1829 }
1830
1831 static void
1832 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1833 {
1834         struct e1000_hw *hw =
1835                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         struct e1000_vfta * shadow_vfta =
1837                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1838         uint32_t reg;
1839         int i;
1840
1841         /* Filter Table Enable, CFI not used for packet acceptance */
1842         reg = E1000_READ_REG(hw, E1000_RCTL);
1843         reg &= ~E1000_RCTL_CFIEN;
1844         reg |= E1000_RCTL_VFE;
1845         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1846
1847         /* restore VFTA table */
1848         for (i = 0; i < IGB_VFTA_SIZE; i++)
1849                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1850 }
1851
1852 static void
1853 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1854 {
1855         struct e1000_hw *hw =
1856                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         uint32_t reg;
1858
1859         /* VLAN Mode Disable */
1860         reg = E1000_READ_REG(hw, E1000_CTRL);
1861         reg &= ~E1000_CTRL_VME;
1862         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1863 }
1864
1865 static void
1866 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1867 {
1868         struct e1000_hw *hw =
1869                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         uint32_t reg;
1871
1872         /* VLAN Mode Enable */
1873         reg = E1000_READ_REG(hw, E1000_CTRL);
1874         reg |= E1000_CTRL_VME;
1875         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1876 }
1877
1878 static void
1879 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1880 {
1881         struct e1000_hw *hw =
1882                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         uint32_t reg;
1884
1885         /* CTRL_EXT: Extended VLAN */
1886         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1887         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1888         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1889
1890         /* Update maximum packet length */
1891         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1892                 E1000_WRITE_REG(hw, E1000_RLPML,
1893                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1894                                                 VLAN_TAG_SIZE);
1895 }
1896
1897 static void
1898 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1899 {
1900         struct e1000_hw *hw =
1901                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902         uint32_t reg;
1903
1904         /* CTRL_EXT: Extended VLAN */
1905         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1906         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1907         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1908
1909         /* Update maximum packet length */
1910         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1911                 E1000_WRITE_REG(hw, E1000_RLPML,
1912                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1913                                                 2 * VLAN_TAG_SIZE);
1914 }
1915
1916 static void
1917 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1918 {
1919         if(mask & ETH_VLAN_STRIP_MASK){
1920                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1921                         igb_vlan_hw_strip_enable(dev);
1922                 else
1923                         igb_vlan_hw_strip_disable(dev);
1924         }
1925
1926         if(mask & ETH_VLAN_FILTER_MASK){
1927                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1928                         igb_vlan_hw_filter_enable(dev);
1929                 else
1930                         igb_vlan_hw_filter_disable(dev);
1931         }
1932
1933         if(mask & ETH_VLAN_EXTEND_MASK){
1934                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1935                         igb_vlan_hw_extend_enable(dev);
1936                 else
1937                         igb_vlan_hw_extend_disable(dev);
1938         }
1939 }
1940
1941
1942 /**
1943  * It enables the interrupt mask and then enable the interrupt.
1944  *
1945  * @param dev
1946  *  Pointer to struct rte_eth_dev.
1947  *
1948  * @return
1949  *  - On success, zero.
1950  *  - On failure, a negative value.
1951  */
1952 static int
1953 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1954 {
1955         struct e1000_interrupt *intr =
1956                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1957
1958         intr->mask |= E1000_ICR_LSC;
1959
1960         return 0;
1961 }
1962
1963 /*
1964  * It reads ICR and gets interrupt causes, check it and set a bit flag
1965  * to update link status.
1966  *
1967  * @param dev
1968  *  Pointer to struct rte_eth_dev.
1969  *
1970  * @return
1971  *  - On success, zero.
1972  *  - On failure, a negative value.
1973  */
1974 static int
1975 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1976 {
1977         uint32_t icr;
1978         struct e1000_hw *hw =
1979                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         struct e1000_interrupt *intr =
1981                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1982
1983         igb_intr_disable(hw);
1984
1985         /* read-on-clear nic registers here */
1986         icr = E1000_READ_REG(hw, E1000_ICR);
1987
1988         intr->flags = 0;
1989         if (icr & E1000_ICR_LSC) {
1990                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1991         }
1992
1993         if (icr & E1000_ICR_VMMB)
1994                 intr->flags |= E1000_FLAG_MAILBOX;
1995
1996         return 0;
1997 }
1998
1999 /*
2000  * It executes link_update after knowing an interrupt is prsent.
2001  *
2002  * @param dev
2003  *  Pointer to struct rte_eth_dev.
2004  *
2005  * @return
2006  *  - On success, zero.
2007  *  - On failure, a negative value.
2008  */
2009 static int
2010 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2011 {
2012         struct e1000_hw *hw =
2013                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014         struct e1000_interrupt *intr =
2015                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2016         uint32_t tctl, rctl;
2017         struct rte_eth_link link;
2018         int ret;
2019
2020         if (intr->flags & E1000_FLAG_MAILBOX) {
2021                 igb_pf_mbx_process(dev);
2022                 intr->flags &= ~E1000_FLAG_MAILBOX;
2023         }
2024
2025         igb_intr_enable(dev);
2026         rte_intr_enable(&(dev->pci_dev->intr_handle));
2027
2028         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2029                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2030
2031                 /* set get_link_status to check register later */
2032                 hw->mac.get_link_status = 1;
2033                 ret = eth_igb_link_update(dev, 0);
2034
2035                 /* check if link has changed */
2036                 if (ret < 0)
2037                         return 0;
2038
2039                 memset(&link, 0, sizeof(link));
2040                 rte_igb_dev_atomic_read_link_status(dev, &link);
2041                 if (link.link_status) {
2042                         PMD_INIT_LOG(INFO,
2043                                      " Port %d: Link Up - speed %u Mbps - %s",
2044                                      dev->data->port_id,
2045                                      (unsigned)link.link_speed,
2046                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2047                                      "full-duplex" : "half-duplex");
2048                 } else {
2049                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2050                                      dev->data->port_id);
2051                 }
2052                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2053                              dev->pci_dev->addr.domain,
2054                              dev->pci_dev->addr.bus,
2055                              dev->pci_dev->addr.devid,
2056                              dev->pci_dev->addr.function);
2057                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2058                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2059                 if (link.link_status) {
2060                         /* enable Tx/Rx */
2061                         tctl |= E1000_TCTL_EN;
2062                         rctl |= E1000_RCTL_EN;
2063                 } else {
2064                         /* disable Tx/Rx */
2065                         tctl &= ~E1000_TCTL_EN;
2066                         rctl &= ~E1000_RCTL_EN;
2067                 }
2068                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2069                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2070                 E1000_WRITE_FLUSH(hw);
2071                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2072         }
2073
2074         return 0;
2075 }
2076
2077 /**
2078  * Interrupt handler which shall be registered at first.
2079  *
2080  * @param handle
2081  *  Pointer to interrupt handle.
2082  * @param param
2083  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2084  *
2085  * @return
2086  *  void
2087  */
2088 static void
2089 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2090                                                         void *param)
2091 {
2092         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2093
2094         eth_igb_interrupt_get_status(dev);
2095         eth_igb_interrupt_action(dev);
2096 }
2097
2098 static int
2099 eth_igb_led_on(struct rte_eth_dev *dev)
2100 {
2101         struct e1000_hw *hw;
2102
2103         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2105 }
2106
2107 static int
2108 eth_igb_led_off(struct rte_eth_dev *dev)
2109 {
2110         struct e1000_hw *hw;
2111
2112         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2114 }
2115
2116 static int
2117 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2118 {
2119         struct e1000_hw *hw;
2120         uint32_t ctrl;
2121         int tx_pause;
2122         int rx_pause;
2123
2124         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         fc_conf->pause_time = hw->fc.pause_time;
2126         fc_conf->high_water = hw->fc.high_water;
2127         fc_conf->low_water = hw->fc.low_water;
2128         fc_conf->send_xon = hw->fc.send_xon;
2129         fc_conf->autoneg = hw->mac.autoneg;
2130
2131         /*
2132          * Return rx_pause and tx_pause status according to actual setting of
2133          * the TFCE and RFCE bits in the CTRL register.
2134          */
2135         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2136         if (ctrl & E1000_CTRL_TFCE)
2137                 tx_pause = 1;
2138         else
2139                 tx_pause = 0;
2140
2141         if (ctrl & E1000_CTRL_RFCE)
2142                 rx_pause = 1;
2143         else
2144                 rx_pause = 0;
2145
2146         if (rx_pause && tx_pause)
2147                 fc_conf->mode = RTE_FC_FULL;
2148         else if (rx_pause)
2149                 fc_conf->mode = RTE_FC_RX_PAUSE;
2150         else if (tx_pause)
2151                 fc_conf->mode = RTE_FC_TX_PAUSE;
2152         else
2153                 fc_conf->mode = RTE_FC_NONE;
2154
2155         return 0;
2156 }
2157
2158 static int
2159 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2160 {
2161         struct e1000_hw *hw;
2162         int err;
2163         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2164                 e1000_fc_none,
2165                 e1000_fc_rx_pause,
2166                 e1000_fc_tx_pause,
2167                 e1000_fc_full
2168         };
2169         uint32_t rx_buf_size;
2170         uint32_t max_high_water;
2171         uint32_t rctl;
2172
2173         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         if (fc_conf->autoneg != hw->mac.autoneg)
2175                 return -ENOTSUP;
2176         rx_buf_size = igb_get_rx_buffer_size(hw);
2177         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2178
2179         /* At least reserve one Ethernet frame for watermark */
2180         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2181         if ((fc_conf->high_water > max_high_water) ||
2182             (fc_conf->high_water < fc_conf->low_water)) {
2183                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2184                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2185                 return (-EINVAL);
2186         }
2187
2188         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2189         hw->fc.pause_time     = fc_conf->pause_time;
2190         hw->fc.high_water     = fc_conf->high_water;
2191         hw->fc.low_water      = fc_conf->low_water;
2192         hw->fc.send_xon       = fc_conf->send_xon;
2193
2194         err = e1000_setup_link_generic(hw);
2195         if (err == E1000_SUCCESS) {
2196
2197                 /* check if we want to forward MAC frames - driver doesn't have native
2198                  * capability to do that, so we'll write the registers ourselves */
2199
2200                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2201
2202                 /* set or clear MFLCN.PMCF bit depending on configuration */
2203                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2204                         rctl |= E1000_RCTL_PMCF;
2205                 else
2206                         rctl &= ~E1000_RCTL_PMCF;
2207
2208                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2209                 E1000_WRITE_FLUSH(hw);
2210
2211                 return 0;
2212         }
2213
2214         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2215         return (-EIO);
2216 }
2217
2218 #define E1000_RAH_POOLSEL_SHIFT      (18)
2219 static void
2220 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2221                 uint32_t index, __rte_unused uint32_t pool)
2222 {
2223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224         uint32_t rah;
2225
2226         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2227         rah = E1000_READ_REG(hw, E1000_RAH(index));
2228         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2229         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2230 }
2231
2232 static void
2233 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2234 {
2235         uint8_t addr[ETHER_ADDR_LEN];
2236         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237
2238         memset(addr, 0, sizeof(addr));
2239
2240         e1000_rar_set(hw, addr, index);
2241 }
2242
2243 static void
2244 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2245                                 struct ether_addr *addr)
2246 {
2247         eth_igb_rar_clear(dev, 0);
2248
2249         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2250 }
2251 /*
2252  * Virtual Function operations
2253  */
2254 static void
2255 igbvf_intr_disable(struct e1000_hw *hw)
2256 {
2257         PMD_INIT_FUNC_TRACE();
2258
2259         /* Clear interrupt mask to stop from interrupts being generated */
2260         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2261
2262         E1000_WRITE_FLUSH(hw);
2263 }
2264
2265 static void
2266 igbvf_stop_adapter(struct rte_eth_dev *dev)
2267 {
2268         u32 reg_val;
2269         u16 i;
2270         struct rte_eth_dev_info dev_info;
2271         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272
2273         memset(&dev_info, 0, sizeof(dev_info));
2274         eth_igbvf_infos_get(dev, &dev_info);
2275
2276         /* Clear interrupt mask to stop from interrupts being generated */
2277         igbvf_intr_disable(hw);
2278
2279         /* Clear any pending interrupts, flush previous writes */
2280         E1000_READ_REG(hw, E1000_EICR);
2281
2282         /* Disable the transmit unit.  Each queue must be disabled. */
2283         for (i = 0; i < dev_info.max_tx_queues; i++)
2284                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2285
2286         /* Disable the receive unit by stopping each queue */
2287         for (i = 0; i < dev_info.max_rx_queues; i++) {
2288                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2289                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2290                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2291                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2292                         ;
2293         }
2294
2295         /* flush all queues disables */
2296         E1000_WRITE_FLUSH(hw);
2297         msec_delay(2);
2298 }
2299
2300 static int eth_igbvf_link_update(struct e1000_hw *hw)
2301 {
2302         struct e1000_mbx_info *mbx = &hw->mbx;
2303         struct e1000_mac_info *mac = &hw->mac;
2304         int ret_val = E1000_SUCCESS;
2305
2306         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2307
2308         /*
2309          * We only want to run this if there has been a rst asserted.
2310          * in this case that could mean a link change, device reset,
2311          * or a virtual function reset
2312          */
2313
2314         /* If we were hit with a reset or timeout drop the link */
2315         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2316                 mac->get_link_status = TRUE;
2317
2318         if (!mac->get_link_status)
2319                 goto out;
2320
2321         /* if link status is down no point in checking to see if pf is up */
2322         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2323                 goto out;
2324
2325         /* if we passed all the tests above then the link is up and we no
2326          * longer need to check for link */
2327         mac->get_link_status = FALSE;
2328
2329 out:
2330         return ret_val;
2331 }
2332
2333
2334 static int
2335 igbvf_dev_configure(struct rte_eth_dev *dev)
2336 {
2337         struct rte_eth_conf* conf = &dev->data->dev_conf;
2338
2339         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2340                      dev->data->port_id);
2341
2342         /*
2343          * VF has no ability to enable/disable HW CRC
2344          * Keep the persistent behavior the same as Host PF
2345          */
2346 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2347         if (!conf->rxmode.hw_strip_crc) {
2348                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2349                 conf->rxmode.hw_strip_crc = 1;
2350         }
2351 #else
2352         if (conf->rxmode.hw_strip_crc) {
2353                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2354                 conf->rxmode.hw_strip_crc = 0;
2355         }
2356 #endif
2357
2358         return 0;
2359 }
2360
2361 static int
2362 igbvf_dev_start(struct rte_eth_dev *dev)
2363 {
2364         struct e1000_hw *hw =
2365                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366         struct e1000_adapter *adapter =
2367                 E1000_DEV_PRIVATE(dev->data->dev_private);
2368         int ret;
2369
2370         PMD_INIT_FUNC_TRACE();
2371
2372         hw->mac.ops.reset_hw(hw);
2373         adapter->stopped = 0;
2374
2375         /* Set all vfta */
2376         igbvf_set_vfta_all(dev,1);
2377
2378         eth_igbvf_tx_init(dev);
2379
2380         /* This can fail when allocating mbufs for descriptor rings */
2381         ret = eth_igbvf_rx_init(dev);
2382         if (ret) {
2383                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2384                 igb_dev_clear_queues(dev);
2385                 return ret;
2386         }
2387
2388         return 0;
2389 }
2390
2391 static void
2392 igbvf_dev_stop(struct rte_eth_dev *dev)
2393 {
2394         PMD_INIT_FUNC_TRACE();
2395
2396         igbvf_stop_adapter(dev);
2397
2398         /*
2399           * Clear what we set, but we still keep shadow_vfta to
2400           * restore after device starts
2401           */
2402         igbvf_set_vfta_all(dev,0);
2403
2404         igb_dev_clear_queues(dev);
2405 }
2406
2407 static void
2408 igbvf_dev_close(struct rte_eth_dev *dev)
2409 {
2410         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411         struct e1000_adapter *adapter =
2412                 E1000_DEV_PRIVATE(dev->data->dev_private);
2413
2414         PMD_INIT_FUNC_TRACE();
2415
2416         e1000_reset_hw(hw);
2417
2418         igbvf_dev_stop(dev);
2419         adapter->stopped = 1;
2420 }
2421
2422 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2423 {
2424         struct e1000_mbx_info *mbx = &hw->mbx;
2425         uint32_t msgbuf[2];
2426
2427         /* After set vlan, vlan strip will also be enabled in igb driver*/
2428         msgbuf[0] = E1000_VF_SET_VLAN;
2429         msgbuf[1] = vid;
2430         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2431         if (on)
2432                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2433
2434         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2435 }
2436
2437 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2438 {
2439         struct e1000_hw *hw =
2440                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         struct e1000_vfta * shadow_vfta =
2442                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2443         int i = 0, j = 0, vfta = 0, mask = 1;
2444
2445         for (i = 0; i < IGB_VFTA_SIZE; i++){
2446                 vfta = shadow_vfta->vfta[i];
2447                 if(vfta){
2448                         mask = 1;
2449                         for (j = 0; j < 32; j++){
2450                                 if(vfta & mask)
2451                                         igbvf_set_vfta(hw,
2452                                                 (uint16_t)((i<<5)+j), on);
2453                                 mask<<=1;
2454                         }
2455                 }
2456         }
2457
2458 }
2459
2460 static int
2461 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2462 {
2463         struct e1000_hw *hw =
2464                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         struct e1000_vfta * shadow_vfta =
2466                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2467         uint32_t vid_idx = 0;
2468         uint32_t vid_bit = 0;
2469         int ret = 0;
2470
2471         PMD_INIT_FUNC_TRACE();
2472
2473         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2474         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2475         if(ret){
2476                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2477                 return ret;
2478         }
2479         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2480         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2481
2482         /*Save what we set and retore it after device reset*/
2483         if (on)
2484                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2485         else
2486                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2487
2488         return 0;
2489 }
2490
2491 static void
2492 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2493 {
2494         struct e1000_hw *hw =
2495                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496
2497         /* index is not used by rar_set() */
2498         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2499 }
2500
2501
2502 static int
2503 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2504                         struct rte_eth_rss_reta_entry64 *reta_conf,
2505                         uint16_t reta_size)
2506 {
2507         uint8_t i, j, mask;
2508         uint32_t reta, r;
2509         uint16_t idx, shift;
2510         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511
2512         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2513                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2514                         "(%d) doesn't match the number hardware can supported "
2515                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2516                 return -EINVAL;
2517         }
2518
2519         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2520                 idx = i / RTE_RETA_GROUP_SIZE;
2521                 shift = i % RTE_RETA_GROUP_SIZE;
2522                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2523                                                 IGB_4_BIT_MASK);
2524                 if (!mask)
2525                         continue;
2526                 if (mask == IGB_4_BIT_MASK)
2527                         r = 0;
2528                 else
2529                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2530                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2531                         if (mask & (0x1 << j))
2532                                 reta |= reta_conf[idx].reta[shift + j] <<
2533                                                         (CHAR_BIT * j);
2534                         else
2535                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2536                 }
2537                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2538         }
2539
2540         return 0;
2541 }
2542
2543 static int
2544 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2545                        struct rte_eth_rss_reta_entry64 *reta_conf,
2546                        uint16_t reta_size)
2547 {
2548         uint8_t i, j, mask;
2549         uint32_t reta;
2550         uint16_t idx, shift;
2551         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552
2553         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2554                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2555                         "(%d) doesn't match the number hardware can supported "
2556                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2557                 return -EINVAL;
2558         }
2559
2560         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2561                 idx = i / RTE_RETA_GROUP_SIZE;
2562                 shift = i % RTE_RETA_GROUP_SIZE;
2563                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2564                                                 IGB_4_BIT_MASK);
2565                 if (!mask)
2566                         continue;
2567                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2568                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2569                         if (mask & (0x1 << j))
2570                                 reta_conf[idx].reta[shift + j] =
2571                                         ((reta >> (CHAR_BIT * j)) &
2572                                                 IGB_8_BIT_MASK);
2573                 }
2574         }
2575
2576         return 0;
2577 }
2578
2579 #define MAC_TYPE_FILTER_SUP(type)    do {\
2580         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2581                 (type) != e1000_82576)\
2582                 return -ENOTSUP;\
2583 } while (0)
2584
2585 static int
2586 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2587                         struct rte_eth_syn_filter *filter,
2588                         bool add)
2589 {
2590         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         uint32_t synqf, rfctl;
2592
2593         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2594                 return -EINVAL;
2595
2596         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2597
2598         if (add) {
2599                 if (synqf & E1000_SYN_FILTER_ENABLE)
2600                         return -EINVAL;
2601
2602                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2603                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2604
2605                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2606                 if (filter->hig_pri)
2607                         rfctl |= E1000_RFCTL_SYNQFP;
2608                 else
2609                         rfctl &= ~E1000_RFCTL_SYNQFP;
2610
2611                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2612         } else {
2613                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2614                         return -ENOENT;
2615                 synqf = 0;
2616         }
2617
2618         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2619         E1000_WRITE_FLUSH(hw);
2620         return 0;
2621 }
2622
2623 static int
2624 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2625                         struct rte_eth_syn_filter *filter)
2626 {
2627         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628         uint32_t synqf, rfctl;
2629
2630         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2631         if (synqf & E1000_SYN_FILTER_ENABLE) {
2632                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2633                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2634                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2635                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2636                 return 0;
2637         }
2638
2639         return -ENOENT;
2640 }
2641
2642 static int
2643 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2644                         enum rte_filter_op filter_op,
2645                         void *arg)
2646 {
2647         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648         int ret;
2649
2650         MAC_TYPE_FILTER_SUP(hw->mac.type);
2651
2652         if (filter_op == RTE_ETH_FILTER_NOP)
2653                 return 0;
2654
2655         if (arg == NULL) {
2656                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2657                             filter_op);
2658                 return -EINVAL;
2659         }
2660
2661         switch (filter_op) {
2662         case RTE_ETH_FILTER_ADD:
2663                 ret = eth_igb_syn_filter_set(dev,
2664                                 (struct rte_eth_syn_filter *)arg,
2665                                 TRUE);
2666                 break;
2667         case RTE_ETH_FILTER_DELETE:
2668                 ret = eth_igb_syn_filter_set(dev,
2669                                 (struct rte_eth_syn_filter *)arg,
2670                                 FALSE);
2671                 break;
2672         case RTE_ETH_FILTER_GET:
2673                 ret = eth_igb_syn_filter_get(dev,
2674                                 (struct rte_eth_syn_filter *)arg);
2675                 break;
2676         default:
2677                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2678                 ret = -EINVAL;
2679                 break;
2680         }
2681
2682         return ret;
2683 }
2684
2685 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2686         if ((type) != e1000_82580 && (type) != e1000_i350)\
2687                 return -ENOSYS; \
2688 } while (0)
2689
2690 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2691 static inline int
2692 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2693                         struct e1000_2tuple_filter_info *filter_info)
2694 {
2695         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2696                 return -EINVAL;
2697         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2698                 return -EINVAL;  /* filter index is out of range. */
2699         if (filter->tcp_flags > TCP_FLAG_ALL)
2700                 return -EINVAL;  /* flags is invalid. */
2701
2702         switch (filter->dst_port_mask) {
2703         case UINT16_MAX:
2704                 filter_info->dst_port_mask = 0;
2705                 filter_info->dst_port = filter->dst_port;
2706                 break;
2707         case 0:
2708                 filter_info->dst_port_mask = 1;
2709                 break;
2710         default:
2711                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2712                 return -EINVAL;
2713         }
2714
2715         switch (filter->proto_mask) {
2716         case UINT8_MAX:
2717                 filter_info->proto_mask = 0;
2718                 filter_info->proto = filter->proto;
2719                 break;
2720         case 0:
2721                 filter_info->proto_mask = 1;
2722                 break;
2723         default:
2724                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2725                 return -EINVAL;
2726         }
2727
2728         filter_info->priority = (uint8_t)filter->priority;
2729         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2730                 filter_info->tcp_flags = filter->tcp_flags;
2731         else
2732                 filter_info->tcp_flags = 0;
2733
2734         return 0;
2735 }
2736
2737 static inline struct e1000_2tuple_filter *
2738 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2739                         struct e1000_2tuple_filter_info *key)
2740 {
2741         struct e1000_2tuple_filter *it;
2742
2743         TAILQ_FOREACH(it, filter_list, entries) {
2744                 if (memcmp(key, &it->filter_info,
2745                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2746                         return it;
2747                 }
2748         }
2749         return NULL;
2750 }
2751
2752 /*
2753  * igb_add_2tuple_filter - add a 2tuple filter
2754  *
2755  * @param
2756  * dev: Pointer to struct rte_eth_dev.
2757  * ntuple_filter: ponter to the filter that will be added.
2758  *
2759  * @return
2760  *    - On success, zero.
2761  *    - On failure, a negative value.
2762  */
2763 static int
2764 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2765                         struct rte_eth_ntuple_filter *ntuple_filter)
2766 {
2767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768         struct e1000_filter_info *filter_info =
2769                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2770         struct e1000_2tuple_filter *filter;
2771         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2772         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2773         int i, ret;
2774
2775         filter = rte_zmalloc("e1000_2tuple_filter",
2776                         sizeof(struct e1000_2tuple_filter), 0);
2777         if (filter == NULL)
2778                 return -ENOMEM;
2779
2780         ret = ntuple_filter_to_2tuple(ntuple_filter,
2781                                       &filter->filter_info);
2782         if (ret < 0) {
2783                 rte_free(filter);
2784                 return ret;
2785         }
2786         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2787                                          &filter->filter_info) != NULL) {
2788                 PMD_DRV_LOG(ERR, "filter exists.");
2789                 rte_free(filter);
2790                 return -EEXIST;
2791         }
2792         filter->queue = ntuple_filter->queue;
2793
2794         /*
2795          * look for an unused 2tuple filter index,
2796          * and insert the filter to list.
2797          */
2798         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2799                 if (!(filter_info->twotuple_mask & (1 << i))) {
2800                         filter_info->twotuple_mask |= 1 << i;
2801                         filter->index = i;
2802                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2803                                           filter,
2804                                           entries);
2805                         break;
2806                 }
2807         }
2808         if (i >= E1000_MAX_TTQF_FILTERS) {
2809                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2810                 rte_free(filter);
2811                 return -ENOSYS;
2812         }
2813
2814         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2815         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2816                 imir |= E1000_IMIR_PORT_BP;
2817         else
2818                 imir &= ~E1000_IMIR_PORT_BP;
2819
2820         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2821
2822         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2823         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2824         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2825         if (filter->filter_info.proto_mask == 0)
2826                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2827
2828         /* tcp flags bits setting. */
2829         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2830                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2831                         imir_ext |= E1000_IMIREXT_CTRL_URG;
2832                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2833                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
2834                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2835                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
2836                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2837                         imir_ext |= E1000_IMIREXT_CTRL_RST;
2838                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2839                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
2840                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2841                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
2842         } else
2843                 imir_ext |= E1000_IMIREXT_CTRL_BP;
2844         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2845         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2846         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2847         return 0;
2848 }
2849
2850 /*
2851  * igb_remove_2tuple_filter - remove a 2tuple filter
2852  *
2853  * @param
2854  * dev: Pointer to struct rte_eth_dev.
2855  * ntuple_filter: ponter to the filter that will be removed.
2856  *
2857  * @return
2858  *    - On success, zero.
2859  *    - On failure, a negative value.
2860  */
2861 static int
2862 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2863                         struct rte_eth_ntuple_filter *ntuple_filter)
2864 {
2865         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2866         struct e1000_filter_info *filter_info =
2867                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2868         struct e1000_2tuple_filter_info filter_2tuple;
2869         struct e1000_2tuple_filter *filter;
2870         int ret;
2871
2872         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2873         ret = ntuple_filter_to_2tuple(ntuple_filter,
2874                                       &filter_2tuple);
2875         if (ret < 0)
2876                 return ret;
2877
2878         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2879                                          &filter_2tuple);
2880         if (filter == NULL) {
2881                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2882                 return -ENOENT;
2883         }
2884
2885         filter_info->twotuple_mask &= ~(1 << filter->index);
2886         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2887         rte_free(filter);
2888
2889         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2890         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2891         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2892         return 0;
2893 }
2894
2895 static inline struct e1000_flex_filter *
2896 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2897                         struct e1000_flex_filter_info *key)
2898 {
2899         struct e1000_flex_filter *it;
2900
2901         TAILQ_FOREACH(it, filter_list, entries) {
2902                 if (memcmp(key, &it->filter_info,
2903                         sizeof(struct e1000_flex_filter_info)) == 0)
2904                         return it;
2905         }
2906
2907         return NULL;
2908 }
2909
2910 static int
2911 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2912                         struct rte_eth_flex_filter *filter,
2913                         bool add)
2914 {
2915         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         struct e1000_filter_info *filter_info =
2917                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2918         struct e1000_flex_filter *flex_filter, *it;
2919         uint32_t wufc, queueing, mask;
2920         uint32_t reg_off;
2921         uint8_t shift, i, j = 0;
2922
2923         flex_filter = rte_zmalloc("e1000_flex_filter",
2924                         sizeof(struct e1000_flex_filter), 0);
2925         if (flex_filter == NULL)
2926                 return -ENOMEM;
2927
2928         flex_filter->filter_info.len = filter->len;
2929         flex_filter->filter_info.priority = filter->priority;
2930         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2931         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2932                 mask = 0;
2933                 /* reverse bits in flex filter's mask*/
2934                 for (shift = 0; shift < CHAR_BIT; shift++) {
2935                         if (filter->mask[i] & (0x01 << shift))
2936                                 mask |= (0x80 >> shift);
2937                 }
2938                 flex_filter->filter_info.mask[i] = mask;
2939         }
2940
2941         wufc = E1000_READ_REG(hw, E1000_WUFC);
2942         if (flex_filter->index < E1000_MAX_FHFT)
2943                 reg_off = E1000_FHFT(flex_filter->index);
2944         else
2945                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2946
2947         if (add) {
2948                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2949                                 &flex_filter->filter_info) != NULL) {
2950                         PMD_DRV_LOG(ERR, "filter exists.");
2951                         rte_free(flex_filter);
2952                         return -EEXIST;
2953                 }
2954                 flex_filter->queue = filter->queue;
2955                 /*
2956                  * look for an unused flex filter index
2957                  * and insert the filter into the list.
2958                  */
2959                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2960                         if (!(filter_info->flex_mask & (1 << i))) {
2961                                 filter_info->flex_mask |= 1 << i;
2962                                 flex_filter->index = i;
2963                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2964                                         flex_filter,
2965                                         entries);
2966                                 break;
2967                         }
2968                 }
2969                 if (i >= E1000_MAX_FLEX_FILTERS) {
2970                         PMD_DRV_LOG(ERR, "flex filters are full.");
2971                         rte_free(flex_filter);
2972                         return -ENOSYS;
2973                 }
2974
2975                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2976                                 (E1000_WUFC_FLX0 << flex_filter->index));
2977                 queueing = filter->len |
2978                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2979                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2980                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2981                                 queueing);
2982                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2983                         E1000_WRITE_REG(hw, reg_off,
2984                                         flex_filter->filter_info.dwords[j]);
2985                         reg_off += sizeof(uint32_t);
2986                         E1000_WRITE_REG(hw, reg_off,
2987                                         flex_filter->filter_info.dwords[++j]);
2988                         reg_off += sizeof(uint32_t);
2989                         E1000_WRITE_REG(hw, reg_off,
2990                                 (uint32_t)flex_filter->filter_info.mask[i]);
2991                         reg_off += sizeof(uint32_t) * 2;
2992                         ++j;
2993                 }
2994         } else {
2995                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2996                                 &flex_filter->filter_info);
2997                 if (it == NULL) {
2998                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
2999                         rte_free(flex_filter);
3000                         return -ENOENT;
3001                 }
3002
3003                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3004                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3005                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3006                         (~(E1000_WUFC_FLX0 << it->index)));
3007
3008                 filter_info->flex_mask &= ~(1 << it->index);
3009                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3010                 rte_free(it);
3011                 rte_free(flex_filter);
3012         }
3013
3014         return 0;
3015 }
3016
3017 static int
3018 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3019                         struct rte_eth_flex_filter *filter)
3020 {
3021         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022         struct e1000_filter_info *filter_info =
3023                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3024         struct e1000_flex_filter flex_filter, *it;
3025         uint32_t wufc, queueing, wufc_en = 0;
3026
3027         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3028         flex_filter.filter_info.len = filter->len;
3029         flex_filter.filter_info.priority = filter->priority;
3030         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3031         memcpy(flex_filter.filter_info.mask, filter->mask,
3032                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3033
3034         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3035                                 &flex_filter.filter_info);
3036         if (it == NULL) {
3037                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3038                 return -ENOENT;
3039         }
3040
3041         wufc = E1000_READ_REG(hw, E1000_WUFC);
3042         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3043
3044         if ((wufc & wufc_en) == wufc_en) {
3045                 uint32_t reg_off = 0;
3046                 if (it->index < E1000_MAX_FHFT)
3047                         reg_off = E1000_FHFT(it->index);
3048                 else
3049                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3050
3051                 queueing = E1000_READ_REG(hw,
3052                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3053                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3054                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3055                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3056                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3057                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3058                 return 0;
3059         }
3060         return -ENOENT;
3061 }
3062
3063 static int
3064 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3065                         enum rte_filter_op filter_op,
3066                         void *arg)
3067 {
3068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069         struct rte_eth_flex_filter *filter;
3070         int ret = 0;
3071
3072         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3073
3074         if (filter_op == RTE_ETH_FILTER_NOP)
3075                 return ret;
3076
3077         if (arg == NULL) {
3078                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3079                             filter_op);
3080                 return -EINVAL;
3081         }
3082
3083         filter = (struct rte_eth_flex_filter *)arg;
3084         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3085             || filter->len % sizeof(uint64_t) != 0) {
3086                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3087                 return -EINVAL;
3088         }
3089         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3090                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3091                 return -EINVAL;
3092         }
3093
3094         switch (filter_op) {
3095         case RTE_ETH_FILTER_ADD:
3096                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3097                 break;
3098         case RTE_ETH_FILTER_DELETE:
3099                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3100                 break;
3101         case RTE_ETH_FILTER_GET:
3102                 ret = eth_igb_get_flex_filter(dev, filter);
3103                 break;
3104         default:
3105                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3106                 ret = -EINVAL;
3107                 break;
3108         }
3109
3110         return ret;
3111 }
3112
3113 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3114 static inline int
3115 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3116                         struct e1000_5tuple_filter_info *filter_info)
3117 {
3118         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3119                 return -EINVAL;
3120         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3121                 return -EINVAL;  /* filter index is out of range. */
3122         if (filter->tcp_flags > TCP_FLAG_ALL)
3123                 return -EINVAL;  /* flags is invalid. */
3124
3125         switch (filter->dst_ip_mask) {
3126         case UINT32_MAX:
3127                 filter_info->dst_ip_mask = 0;
3128                 filter_info->dst_ip = filter->dst_ip;
3129                 break;
3130         case 0:
3131                 filter_info->dst_ip_mask = 1;
3132                 break;
3133         default:
3134                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3135                 return -EINVAL;
3136         }
3137
3138         switch (filter->src_ip_mask) {
3139         case UINT32_MAX:
3140                 filter_info->src_ip_mask = 0;
3141                 filter_info->src_ip = filter->src_ip;
3142                 break;
3143         case 0:
3144                 filter_info->src_ip_mask = 1;
3145                 break;
3146         default:
3147                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3148                 return -EINVAL;
3149         }
3150
3151         switch (filter->dst_port_mask) {
3152         case UINT16_MAX:
3153                 filter_info->dst_port_mask = 0;
3154                 filter_info->dst_port = filter->dst_port;
3155                 break;
3156         case 0:
3157                 filter_info->dst_port_mask = 1;
3158                 break;
3159         default:
3160                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3161                 return -EINVAL;
3162         }
3163
3164         switch (filter->src_port_mask) {
3165         case UINT16_MAX:
3166                 filter_info->src_port_mask = 0;
3167                 filter_info->src_port = filter->src_port;
3168                 break;
3169         case 0:
3170                 filter_info->src_port_mask = 1;
3171                 break;
3172         default:
3173                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3174                 return -EINVAL;
3175         }
3176
3177         switch (filter->proto_mask) {
3178         case UINT8_MAX:
3179                 filter_info->proto_mask = 0;
3180                 filter_info->proto = filter->proto;
3181                 break;
3182         case 0:
3183                 filter_info->proto_mask = 1;
3184                 break;
3185         default:
3186                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3187                 return -EINVAL;
3188         }
3189
3190         filter_info->priority = (uint8_t)filter->priority;
3191         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3192                 filter_info->tcp_flags = filter->tcp_flags;
3193         else
3194                 filter_info->tcp_flags = 0;
3195
3196         return 0;
3197 }
3198
3199 static inline struct e1000_5tuple_filter *
3200 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3201                         struct e1000_5tuple_filter_info *key)
3202 {
3203         struct e1000_5tuple_filter *it;
3204
3205         TAILQ_FOREACH(it, filter_list, entries) {
3206                 if (memcmp(key, &it->filter_info,
3207                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3208                         return it;
3209                 }
3210         }
3211         return NULL;
3212 }
3213
3214 /*
3215  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3216  *
3217  * @param
3218  * dev: Pointer to struct rte_eth_dev.
3219  * ntuple_filter: ponter to the filter that will be added.
3220  *
3221  * @return
3222  *    - On success, zero.
3223  *    - On failure, a negative value.
3224  */
3225 static int
3226 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3227                         struct rte_eth_ntuple_filter *ntuple_filter)
3228 {
3229         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3230         struct e1000_filter_info *filter_info =
3231                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3232         struct e1000_5tuple_filter *filter;
3233         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3234         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3235         uint8_t i;
3236         int ret;
3237
3238         filter = rte_zmalloc("e1000_5tuple_filter",
3239                         sizeof(struct e1000_5tuple_filter), 0);
3240         if (filter == NULL)
3241                 return -ENOMEM;
3242
3243         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3244                                             &filter->filter_info);
3245         if (ret < 0) {
3246                 rte_free(filter);
3247                 return ret;
3248         }
3249
3250         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3251                                          &filter->filter_info) != NULL) {
3252                 PMD_DRV_LOG(ERR, "filter exists.");
3253                 rte_free(filter);
3254                 return -EEXIST;
3255         }
3256         filter->queue = ntuple_filter->queue;
3257
3258         /*
3259          * look for an unused 5tuple filter index,
3260          * and insert the filter to list.
3261          */
3262         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3263                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3264                         filter_info->fivetuple_mask |= 1 << i;
3265                         filter->index = i;
3266                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3267                                           filter,
3268                                           entries);
3269                         break;
3270                 }
3271         }
3272         if (i >= E1000_MAX_FTQF_FILTERS) {
3273                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3274                 rte_free(filter);
3275                 return -ENOSYS;
3276         }
3277
3278         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3279         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3280                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3281         if (filter->filter_info.dst_ip_mask == 0)
3282                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3283         if (filter->filter_info.src_port_mask == 0)
3284                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3285         if (filter->filter_info.proto_mask == 0)
3286                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3287         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3288                 E1000_FTQF_QUEUE_MASK;
3289         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3290         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3291         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3292         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3293
3294         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3295         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3296
3297         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3298         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3299                 imir |= E1000_IMIR_PORT_BP;
3300         else
3301                 imir &= ~E1000_IMIR_PORT_BP;
3302         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3303
3304         /* tcp flags bits setting. */
3305         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3306                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3307                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3308                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3309                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3310                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3311                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3312                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3313                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3314                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3315                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3316                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3317                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3318         } else
3319                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3320         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3321         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3322         return 0;
3323 }
3324
3325 /*
3326  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3327  *
3328  * @param
3329  * dev: Pointer to struct rte_eth_dev.
3330  * ntuple_filter: ponter to the filter that will be removed.
3331  *
3332  * @return
3333  *    - On success, zero.
3334  *    - On failure, a negative value.
3335  */
3336 static int
3337 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3338                                 struct rte_eth_ntuple_filter *ntuple_filter)
3339 {
3340         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341         struct e1000_filter_info *filter_info =
3342                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3343         struct e1000_5tuple_filter_info filter_5tuple;
3344         struct e1000_5tuple_filter *filter;
3345         int ret;
3346
3347         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3348         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3349                                             &filter_5tuple);
3350         if (ret < 0)
3351                 return ret;
3352
3353         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3354                                          &filter_5tuple);
3355         if (filter == NULL) {
3356                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3357                 return -ENOENT;
3358         }
3359
3360         filter_info->fivetuple_mask &= ~(1 << filter->index);
3361         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3362         rte_free(filter);
3363
3364         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3365                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3366         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3367         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3368         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3369         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3370         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3371         return 0;
3372 }
3373
3374 static int
3375 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3376 {
3377         uint32_t rctl;
3378         struct e1000_hw *hw;
3379         struct rte_eth_dev_info dev_info;
3380         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3381                                      VLAN_TAG_SIZE);
3382
3383         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384
3385 #ifdef RTE_LIBRTE_82571_SUPPORT
3386         /* XXX: not bigger than max_rx_pktlen */
3387         if (hw->mac.type == e1000_82571)
3388                 return -ENOTSUP;
3389 #endif
3390         eth_igb_infos_get(dev, &dev_info);
3391
3392         /* check that mtu is within the allowed range */
3393         if ((mtu < ETHER_MIN_MTU) ||
3394             (frame_size > dev_info.max_rx_pktlen))
3395                 return -EINVAL;
3396
3397         /* refuse mtu that requires the support of scattered packets when this
3398          * feature has not been enabled before. */
3399         if (!dev->data->scattered_rx &&
3400             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3401                 return -EINVAL;
3402
3403         rctl = E1000_READ_REG(hw, E1000_RCTL);
3404
3405         /* switch to jumbo mode if needed */
3406         if (frame_size > ETHER_MAX_LEN) {
3407                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3408                 rctl |= E1000_RCTL_LPE;
3409         } else {
3410                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3411                 rctl &= ~E1000_RCTL_LPE;
3412         }
3413         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3414
3415         /* update max frame size */
3416         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3417
3418         E1000_WRITE_REG(hw, E1000_RLPML,
3419                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3420
3421         return 0;
3422 }
3423
3424 /*
3425  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3426  *
3427  * @param
3428  * dev: Pointer to struct rte_eth_dev.
3429  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3430  * add: if true, add filter, if false, remove filter
3431  *
3432  * @return
3433  *    - On success, zero.
3434  *    - On failure, a negative value.
3435  */
3436 static int
3437 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3438                         struct rte_eth_ntuple_filter *ntuple_filter,
3439                         bool add)
3440 {
3441         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         int ret;
3443
3444         switch (ntuple_filter->flags) {
3445         case RTE_5TUPLE_FLAGS:
3446         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3447                 if (hw->mac.type != e1000_82576)
3448                         return -ENOTSUP;
3449                 if (add)
3450                         ret = igb_add_5tuple_filter_82576(dev,
3451                                                           ntuple_filter);
3452                 else
3453                         ret = igb_remove_5tuple_filter_82576(dev,
3454                                                              ntuple_filter);
3455                 break;
3456         case RTE_2TUPLE_FLAGS:
3457         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3458                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3459                         return -ENOTSUP;
3460                 if (add)
3461                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3462                 else
3463                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3464                 break;
3465         default:
3466                 ret = -EINVAL;
3467                 break;
3468         }
3469
3470         return ret;
3471 }
3472
3473 /*
3474  * igb_get_ntuple_filter - get a ntuple filter
3475  *
3476  * @param
3477  * dev: Pointer to struct rte_eth_dev.
3478  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3479  *
3480  * @return
3481  *    - On success, zero.
3482  *    - On failure, a negative value.
3483  */
3484 static int
3485 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3486                         struct rte_eth_ntuple_filter *ntuple_filter)
3487 {
3488         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489         struct e1000_filter_info *filter_info =
3490                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3491         struct e1000_5tuple_filter_info filter_5tuple;
3492         struct e1000_2tuple_filter_info filter_2tuple;
3493         struct e1000_5tuple_filter *p_5tuple_filter;
3494         struct e1000_2tuple_filter *p_2tuple_filter;
3495         int ret;
3496
3497         switch (ntuple_filter->flags) {
3498         case RTE_5TUPLE_FLAGS:
3499         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3500                 if (hw->mac.type != e1000_82576)
3501                         return -ENOTSUP;
3502                 memset(&filter_5tuple,
3503                         0,
3504                         sizeof(struct e1000_5tuple_filter_info));
3505                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3506                                                     &filter_5tuple);
3507                 if (ret < 0)
3508                         return ret;
3509                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3510                                         &filter_info->fivetuple_list,
3511                                         &filter_5tuple);
3512                 if (p_5tuple_filter == NULL) {
3513                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3514                         return -ENOENT;
3515                 }
3516                 ntuple_filter->queue = p_5tuple_filter->queue;
3517                 break;
3518         case RTE_2TUPLE_FLAGS:
3519         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3520                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3521                         return -ENOTSUP;
3522                 memset(&filter_2tuple,
3523                         0,
3524                         sizeof(struct e1000_2tuple_filter_info));
3525                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3526                 if (ret < 0)
3527                         return ret;
3528                 p_2tuple_filter = igb_2tuple_filter_lookup(
3529                                         &filter_info->twotuple_list,
3530                                         &filter_2tuple);
3531                 if (p_2tuple_filter == NULL) {
3532                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3533                         return -ENOENT;
3534                 }
3535                 ntuple_filter->queue = p_2tuple_filter->queue;
3536                 break;
3537         default:
3538                 ret = -EINVAL;
3539                 break;
3540         }
3541
3542         return 0;
3543 }
3544
3545 /*
3546  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3547  * @dev: pointer to rte_eth_dev structure
3548  * @filter_op:operation will be taken.
3549  * @arg: a pointer to specific structure corresponding to the filter_op
3550  */
3551 static int
3552 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3553                                 enum rte_filter_op filter_op,
3554                                 void *arg)
3555 {
3556         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557         int ret;
3558
3559         MAC_TYPE_FILTER_SUP(hw->mac.type);
3560
3561         if (filter_op == RTE_ETH_FILTER_NOP)
3562                 return 0;
3563
3564         if (arg == NULL) {
3565                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3566                             filter_op);
3567                 return -EINVAL;
3568         }
3569
3570         switch (filter_op) {
3571         case RTE_ETH_FILTER_ADD:
3572                 ret = igb_add_del_ntuple_filter(dev,
3573                         (struct rte_eth_ntuple_filter *)arg,
3574                         TRUE);
3575                 break;
3576         case RTE_ETH_FILTER_DELETE:
3577                 ret = igb_add_del_ntuple_filter(dev,
3578                         (struct rte_eth_ntuple_filter *)arg,
3579                         FALSE);
3580                 break;
3581         case RTE_ETH_FILTER_GET:
3582                 ret = igb_get_ntuple_filter(dev,
3583                         (struct rte_eth_ntuple_filter *)arg);
3584                 break;
3585         default:
3586                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3587                 ret = -EINVAL;
3588                 break;
3589         }
3590         return ret;
3591 }
3592
3593 static inline int
3594 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3595                         uint16_t ethertype)
3596 {
3597         int i;
3598
3599         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3600                 if (filter_info->ethertype_filters[i] == ethertype &&
3601                     (filter_info->ethertype_mask & (1 << i)))
3602                         return i;
3603         }
3604         return -1;
3605 }
3606
3607 static inline int
3608 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3609                         uint16_t ethertype)
3610 {
3611         int i;
3612
3613         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3614                 if (!(filter_info->ethertype_mask & (1 << i))) {
3615                         filter_info->ethertype_mask |= 1 << i;
3616                         filter_info->ethertype_filters[i] = ethertype;
3617                         return i;
3618                 }
3619         }
3620         return -1;
3621 }
3622
3623 static inline int
3624 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3625                         uint8_t idx)
3626 {
3627         if (idx >= E1000_MAX_ETQF_FILTERS)
3628                 return -1;
3629         filter_info->ethertype_mask &= ~(1 << idx);
3630         filter_info->ethertype_filters[idx] = 0;
3631         return idx;
3632 }
3633
3634
3635 static int
3636 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3637                         struct rte_eth_ethertype_filter *filter,
3638                         bool add)
3639 {
3640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         struct e1000_filter_info *filter_info =
3642                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3643         uint32_t etqf = 0;
3644         int ret;
3645
3646         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3647                 filter->ether_type == ETHER_TYPE_IPv6) {
3648                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3649                         " ethertype filter.", filter->ether_type);
3650                 return -EINVAL;
3651         }
3652
3653         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3654                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3655                 return -EINVAL;
3656         }
3657         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3658                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3659                 return -EINVAL;
3660         }
3661
3662         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3663         if (ret >= 0 && add) {
3664                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3665                             filter->ether_type);
3666                 return -EEXIST;
3667         }
3668         if (ret < 0 && !add) {
3669                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3670                             filter->ether_type);
3671                 return -ENOENT;
3672         }
3673
3674         if (add) {
3675                 ret = igb_ethertype_filter_insert(filter_info,
3676                         filter->ether_type);
3677                 if (ret < 0) {
3678                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3679                         return -ENOSYS;
3680                 }
3681
3682                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3683                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3684                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3685         } else {
3686                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3687                 if (ret < 0)
3688                         return -ENOSYS;
3689         }
3690         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3691         E1000_WRITE_FLUSH(hw);
3692
3693         return 0;
3694 }
3695
3696 static int
3697 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3698                         struct rte_eth_ethertype_filter *filter)
3699 {
3700         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701         struct e1000_filter_info *filter_info =
3702                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3703         uint32_t etqf;
3704         int ret;
3705
3706         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3707         if (ret < 0) {
3708                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3709                             filter->ether_type);
3710                 return -ENOENT;
3711         }
3712
3713         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3714         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3715                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3716                 filter->flags = 0;
3717                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3718                                 E1000_ETQF_QUEUE_SHIFT;
3719                 return 0;
3720         }
3721
3722         return -ENOENT;
3723 }
3724
3725 /*
3726  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3727  * @dev: pointer to rte_eth_dev structure
3728  * @filter_op:operation will be taken.
3729  * @arg: a pointer to specific structure corresponding to the filter_op
3730  */
3731 static int
3732 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3733                                 enum rte_filter_op filter_op,
3734                                 void *arg)
3735 {
3736         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         int ret;
3738
3739         MAC_TYPE_FILTER_SUP(hw->mac.type);
3740
3741         if (filter_op == RTE_ETH_FILTER_NOP)
3742                 return 0;
3743
3744         if (arg == NULL) {
3745                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3746                             filter_op);
3747                 return -EINVAL;
3748         }
3749
3750         switch (filter_op) {
3751         case RTE_ETH_FILTER_ADD:
3752                 ret = igb_add_del_ethertype_filter(dev,
3753                         (struct rte_eth_ethertype_filter *)arg,
3754                         TRUE);
3755                 break;
3756         case RTE_ETH_FILTER_DELETE:
3757                 ret = igb_add_del_ethertype_filter(dev,
3758                         (struct rte_eth_ethertype_filter *)arg,
3759                         FALSE);
3760                 break;
3761         case RTE_ETH_FILTER_GET:
3762                 ret = igb_get_ethertype_filter(dev,
3763                         (struct rte_eth_ethertype_filter *)arg);
3764                 break;
3765         default:
3766                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3767                 ret = -EINVAL;
3768                 break;
3769         }
3770         return ret;
3771 }
3772
3773 static int
3774 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3775                      enum rte_filter_type filter_type,
3776                      enum rte_filter_op filter_op,
3777                      void *arg)
3778 {
3779         int ret = -EINVAL;
3780
3781         switch (filter_type) {
3782         case RTE_ETH_FILTER_NTUPLE:
3783                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3784                 break;
3785         case RTE_ETH_FILTER_ETHERTYPE:
3786                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3787                 break;
3788         case RTE_ETH_FILTER_SYN:
3789                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3790                 break;
3791         case RTE_ETH_FILTER_FLEXIBLE:
3792                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3793                 break;
3794         default:
3795                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3796                                                         filter_type);
3797                 break;
3798         }
3799
3800         return ret;
3801 }
3802
3803 static int
3804 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3805                          struct ether_addr *mc_addr_set,
3806                          uint32_t nb_mc_addr)
3807 {
3808         struct e1000_hw *hw;
3809
3810         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3812         return 0;
3813 }
3814
3815 static int
3816 igb_timesync_enable(struct rte_eth_dev *dev)
3817 {
3818         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3819         uint32_t tsync_ctl;
3820
3821         /* Start incrementing the register used to timestamp PTP packets. */
3822         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
3823
3824         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3825         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
3826                         (ETHER_TYPE_1588 |
3827                          E1000_ETQF_FILTER_ENABLE |
3828                          E1000_ETQF_1588));
3829
3830         /* Enable timestamping of received PTP packets. */
3831         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3832         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
3833         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3834
3835         /* Enable Timestamping of transmitted PTP packets. */
3836         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3837         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
3838         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3839
3840         return 0;
3841 }
3842
3843 static int
3844 igb_timesync_disable(struct rte_eth_dev *dev)
3845 {
3846         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847         uint32_t tsync_ctl;
3848
3849         /* Disable timestamping of transmitted PTP packets. */
3850         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3851         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
3852         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
3853
3854         /* Disable timestamping of received PTP packets. */
3855         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3856         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
3857         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
3858
3859         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3860         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
3861
3862         /* Stop incrementating the System Time registers. */
3863         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
3864
3865         return 0;
3866 }
3867
3868 static int
3869 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3870                                struct timespec *timestamp,
3871                                uint32_t flags __rte_unused)
3872 {
3873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874         uint32_t tsync_rxctl;
3875         uint32_t rx_stmpl;
3876         uint32_t rx_stmph;
3877
3878         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
3879         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
3880                 return -EINVAL;
3881
3882         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
3883         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
3884
3885         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
3886         timestamp->tv_nsec = 0;
3887
3888         return  0;
3889 }
3890
3891 static int
3892 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3893                                struct timespec *timestamp)
3894 {
3895         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896         uint32_t tsync_txctl;
3897         uint32_t tx_stmpl;
3898         uint32_t tx_stmph;
3899
3900         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
3901         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
3902                 return -EINVAL;
3903
3904         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
3905         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
3906
3907         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
3908         timestamp->tv_nsec = 0;
3909
3910         return  0;
3911 }
3912
3913 static int
3914 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3915 {
3916         int count = 0;
3917         int g_ind = 0;
3918         const struct reg_info *reg_group;
3919
3920         while ((reg_group = igb_regs[g_ind++]))
3921                 count += igb_reg_group_count(reg_group);
3922
3923         return count;
3924 }
3925
3926 static int
3927 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3928 {
3929         int count = 0;
3930         int g_ind = 0;
3931         const struct reg_info *reg_group;
3932
3933         while ((reg_group = igbvf_regs[g_ind++]))
3934                 count += igb_reg_group_count(reg_group);
3935
3936         return count;
3937 }
3938
3939 static int
3940 eth_igb_get_regs(struct rte_eth_dev *dev,
3941         struct rte_dev_reg_info *regs)
3942 {
3943         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         uint32_t *data = regs->data;
3945         int g_ind = 0;
3946         int count = 0;
3947         const struct reg_info *reg_group;
3948
3949         /* Support only full register dump */
3950         if ((regs->length == 0) ||
3951             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
3952                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
3953                         hw->device_id;
3954                 while ((reg_group = igb_regs[g_ind++]))
3955                         count += igb_read_regs_group(dev, &data[count],
3956                                                         reg_group);
3957                 return 0;
3958         }
3959
3960         return -ENOTSUP;
3961 }
3962
3963 static int
3964 igbvf_get_regs(struct rte_eth_dev *dev,
3965         struct rte_dev_reg_info *regs)
3966 {
3967         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968         uint32_t *data = regs->data;
3969         int g_ind = 0;
3970         int count = 0;
3971         const struct reg_info *reg_group;
3972
3973         /* Support only full register dump */
3974         if ((regs->length == 0) ||
3975             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
3976                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
3977                         hw->device_id;
3978                 while ((reg_group = igbvf_regs[g_ind++]))
3979                         count += igb_read_regs_group(dev, &data[count],
3980                                                         reg_group);
3981                 return 0;
3982         }
3983
3984         return -ENOTSUP;
3985 }
3986
3987 static int
3988 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
3989 {
3990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991
3992         /* Return unit is byte count */
3993         return hw->nvm.word_size * 2;
3994 }
3995
3996 static int
3997 eth_igb_get_eeprom(struct rte_eth_dev *dev,
3998         struct rte_dev_eeprom_info *in_eeprom)
3999 {
4000         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         struct e1000_nvm_info *nvm = &hw->nvm;
4002         uint16_t *data = in_eeprom->data;
4003         int first, length;
4004
4005         first = in_eeprom->offset >> 1;
4006         length = in_eeprom->length >> 1;
4007         if ((first >= hw->nvm.word_size) ||
4008             ((first + length) >= hw->nvm.word_size))
4009                 return -EINVAL;
4010
4011         in_eeprom->magic = hw->vendor_id |
4012                 ((uint32_t)hw->device_id << 16);
4013
4014         if ((nvm->ops.read) == NULL)
4015                 return -ENOTSUP;
4016
4017         return nvm->ops.read(hw, first, length, data);
4018 }
4019
4020 static int
4021 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4022         struct rte_dev_eeprom_info *in_eeprom)
4023 {
4024         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4025         struct e1000_nvm_info *nvm = &hw->nvm;
4026         uint16_t *data = in_eeprom->data;
4027         int first, length;
4028
4029         first = in_eeprom->offset >> 1;
4030         length = in_eeprom->length >> 1;
4031         if ((first >= hw->nvm.word_size) ||
4032             ((first + length) >= hw->nvm.word_size))
4033                 return -EINVAL;
4034
4035         in_eeprom->magic = (uint32_t)hw->vendor_id |
4036                 ((uint32_t)hw->device_id << 16);
4037
4038         if ((nvm->ops.write) == NULL)
4039                 return -ENOTSUP;
4040         return nvm->ops.write(hw,  first, length, data);
4041 }
4042
4043 static struct rte_driver pmd_igb_drv = {
4044         .type = PMD_PDEV,
4045         .init = rte_igb_pmd_init,
4046 };
4047
4048 static struct rte_driver pmd_igbvf_drv = {
4049         .type = PMD_PDEV,
4050         .init = rte_igbvf_pmd_init,
4051 };
4052
4053 PMD_REGISTER_DRIVER(pmd_igb_drv);
4054 PMD_REGISTER_DRIVER(pmd_igbvf_drv);