1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_malloc.h>
26 #include "e1000_logs.h"
27 #include "base/e1000_api.h"
28 #include "e1000_ethdev.h"
32 * Default values for port configuration
34 #define IGB_DEFAULT_RX_FREE_THRESH 32
36 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
37 #define IGB_DEFAULT_RX_HTHRESH 8
38 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
40 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
41 #define IGB_DEFAULT_TX_HTHRESH 1
42 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
44 /* Bit shift and mask */
45 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
46 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
47 #define IGB_8_BIT_WIDTH CHAR_BIT
48 #define IGB_8_BIT_MASK UINT8_MAX
50 /* Additional timesync values. */
51 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
52 #define E1000_ETQF_FILTER_1588 3
53 #define IGB_82576_TSYNC_SHIFT 16
54 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
55 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
56 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
58 #define E1000_VTIVAR_MISC 0x01740
59 #define E1000_VTIVAR_MISC_MASK 0xFF
60 #define E1000_VTIVAR_VALID 0x80
61 #define E1000_VTIVAR_MISC_MAILBOX 0
62 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
64 /* External VLAN Enable bit mask */
65 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
67 /* External VLAN Ether Type bit mask and shift */
68 #define E1000_VET_VET_EXT 0xFFFF0000
69 #define E1000_VET_VET_EXT_SHIFT 16
71 static int eth_igb_configure(struct rte_eth_dev *dev);
72 static int eth_igb_start(struct rte_eth_dev *dev);
73 static void eth_igb_stop(struct rte_eth_dev *dev);
74 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
75 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
76 static void eth_igb_close(struct rte_eth_dev *dev);
77 static int eth_igb_reset(struct rte_eth_dev *dev);
78 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
79 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
80 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
81 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
82 static int eth_igb_link_update(struct rte_eth_dev *dev,
83 int wait_to_complete);
84 static int eth_igb_stats_get(struct rte_eth_dev *dev,
85 struct rte_eth_stats *rte_stats);
86 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
87 struct rte_eth_xstat *xstats, unsigned n);
88 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
90 uint64_t *values, unsigned int n);
91 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
92 struct rte_eth_xstat_name *xstats_names,
94 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
95 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
97 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
98 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
99 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
100 char *fw_version, size_t fw_size);
101 static void eth_igb_infos_get(struct rte_eth_dev *dev,
102 struct rte_eth_dev_info *dev_info);
103 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
104 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
105 struct rte_eth_dev_info *dev_info);
106 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
107 struct rte_eth_fc_conf *fc_conf);
108 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
109 struct rte_eth_fc_conf *fc_conf);
110 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
111 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
112 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
113 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
114 struct rte_intr_handle *handle);
115 static void eth_igb_interrupt_handler(void *param);
116 static int igb_hardware_init(struct e1000_hw *hw);
117 static void igb_hw_control_acquire(struct e1000_hw *hw);
118 static void igb_hw_control_release(struct e1000_hw *hw);
119 static void igb_init_manageability(struct e1000_hw *hw);
120 static void igb_release_manageability(struct e1000_hw *hw);
122 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
124 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
125 uint16_t vlan_id, int on);
126 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
127 enum rte_vlan_type vlan_type,
129 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
131 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
132 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
133 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
138 static int eth_igb_led_on(struct rte_eth_dev *dev);
139 static int eth_igb_led_off(struct rte_eth_dev *dev);
141 static void igb_intr_disable(struct e1000_hw *hw);
142 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
143 static int eth_igb_rar_set(struct rte_eth_dev *dev,
144 struct ether_addr *mac_addr,
145 uint32_t index, uint32_t pool);
146 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
147 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
148 struct ether_addr *addr);
150 static void igbvf_intr_disable(struct e1000_hw *hw);
151 static int igbvf_dev_configure(struct rte_eth_dev *dev);
152 static int igbvf_dev_start(struct rte_eth_dev *dev);
153 static void igbvf_dev_stop(struct rte_eth_dev *dev);
154 static void igbvf_dev_close(struct rte_eth_dev *dev);
155 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
156 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
157 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
158 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
159 static int eth_igbvf_link_update(struct e1000_hw *hw);
160 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
161 struct rte_eth_stats *rte_stats);
162 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
164 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
165 struct rte_eth_xstat_name *xstats_names,
167 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
168 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
169 uint16_t vlan_id, int on);
170 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
171 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
172 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
173 struct ether_addr *addr);
174 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
175 static int igbvf_get_regs(struct rte_eth_dev *dev,
176 struct rte_dev_reg_info *regs);
178 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
179 struct rte_eth_rss_reta_entry64 *reta_conf,
181 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
182 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
186 struct rte_eth_syn_filter *filter);
187 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
188 enum rte_filter_op filter_op,
190 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
191 struct rte_eth_ntuple_filter *ntuple_filter);
192 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
193 struct rte_eth_ntuple_filter *ntuple_filter);
194 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
195 struct rte_eth_flex_filter *filter);
196 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
197 enum rte_filter_op filter_op,
199 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
200 struct rte_eth_ntuple_filter *ntuple_filter);
201 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
202 struct rte_eth_ntuple_filter *ntuple_filter);
203 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *filter);
205 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
206 enum rte_filter_op filter_op,
208 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
209 enum rte_filter_op filter_op,
211 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
212 struct rte_eth_ethertype_filter *filter);
213 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
214 enum rte_filter_type filter_type,
215 enum rte_filter_op filter_op,
217 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
218 static int eth_igb_get_regs(struct rte_eth_dev *dev,
219 struct rte_dev_reg_info *regs);
220 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
221 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
222 struct rte_dev_eeprom_info *eeprom);
223 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
224 struct rte_dev_eeprom_info *eeprom);
225 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
226 struct rte_eth_dev_module_info *modinfo);
227 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *info);
229 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
230 struct ether_addr *mc_addr_set,
231 uint32_t nb_mc_addr);
232 static int igb_timesync_enable(struct rte_eth_dev *dev);
233 static int igb_timesync_disable(struct rte_eth_dev *dev);
234 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
235 struct timespec *timestamp,
237 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
238 struct timespec *timestamp);
239 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
240 static int igb_timesync_read_time(struct rte_eth_dev *dev,
241 struct timespec *timestamp);
242 static int igb_timesync_write_time(struct rte_eth_dev *dev,
243 const struct timespec *timestamp);
244 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
246 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
248 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
249 uint8_t queue, uint8_t msix_vector);
250 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
251 uint8_t index, uint8_t offset);
252 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
253 static void eth_igbvf_interrupt_handler(void *param);
254 static void igbvf_mbx_process(struct rte_eth_dev *dev);
255 static int igb_filter_restore(struct rte_eth_dev *dev);
258 * Define VF Stats MACRO for Non "cleared on read" register
260 #define UPDATE_VF_STAT(reg, last, cur) \
262 u32 latest = E1000_READ_REG(hw, reg); \
263 cur += (latest - last) & UINT_MAX; \
267 #define IGB_FC_PAUSE_TIME 0x0680
268 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
269 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
271 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
273 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
276 * The set of PCI devices this driver supports
278 static const struct rte_pci_id pci_id_igb_map[] = {
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
320 { .vendor_id = 0, /* sentinel */ },
324 * The set of PCI devices this driver supports (for 82576&I350 VF)
326 static const struct rte_pci_id pci_id_igbvf_map[] = {
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
331 { .vendor_id = 0, /* sentinel */ },
334 static const struct rte_eth_desc_lim rx_desc_lim = {
335 .nb_max = E1000_MAX_RING_DESC,
336 .nb_min = E1000_MIN_RING_DESC,
337 .nb_align = IGB_RXD_ALIGN,
340 static const struct rte_eth_desc_lim tx_desc_lim = {
341 .nb_max = E1000_MAX_RING_DESC,
342 .nb_min = E1000_MIN_RING_DESC,
343 .nb_align = IGB_RXD_ALIGN,
344 .nb_seg_max = IGB_TX_MAX_SEG,
345 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
348 static const struct eth_dev_ops eth_igb_ops = {
349 .dev_configure = eth_igb_configure,
350 .dev_start = eth_igb_start,
351 .dev_stop = eth_igb_stop,
352 .dev_set_link_up = eth_igb_dev_set_link_up,
353 .dev_set_link_down = eth_igb_dev_set_link_down,
354 .dev_close = eth_igb_close,
355 .dev_reset = eth_igb_reset,
356 .promiscuous_enable = eth_igb_promiscuous_enable,
357 .promiscuous_disable = eth_igb_promiscuous_disable,
358 .allmulticast_enable = eth_igb_allmulticast_enable,
359 .allmulticast_disable = eth_igb_allmulticast_disable,
360 .link_update = eth_igb_link_update,
361 .stats_get = eth_igb_stats_get,
362 .xstats_get = eth_igb_xstats_get,
363 .xstats_get_by_id = eth_igb_xstats_get_by_id,
364 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
365 .xstats_get_names = eth_igb_xstats_get_names,
366 .stats_reset = eth_igb_stats_reset,
367 .xstats_reset = eth_igb_xstats_reset,
368 .fw_version_get = eth_igb_fw_version_get,
369 .dev_infos_get = eth_igb_infos_get,
370 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
371 .mtu_set = eth_igb_mtu_set,
372 .vlan_filter_set = eth_igb_vlan_filter_set,
373 .vlan_tpid_set = eth_igb_vlan_tpid_set,
374 .vlan_offload_set = eth_igb_vlan_offload_set,
375 .rx_queue_setup = eth_igb_rx_queue_setup,
376 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
377 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
378 .rx_queue_release = eth_igb_rx_queue_release,
379 .rx_queue_count = eth_igb_rx_queue_count,
380 .rx_descriptor_done = eth_igb_rx_descriptor_done,
381 .rx_descriptor_status = eth_igb_rx_descriptor_status,
382 .tx_descriptor_status = eth_igb_tx_descriptor_status,
383 .tx_queue_setup = eth_igb_tx_queue_setup,
384 .tx_queue_release = eth_igb_tx_queue_release,
385 .tx_done_cleanup = eth_igb_tx_done_cleanup,
386 .dev_led_on = eth_igb_led_on,
387 .dev_led_off = eth_igb_led_off,
388 .flow_ctrl_get = eth_igb_flow_ctrl_get,
389 .flow_ctrl_set = eth_igb_flow_ctrl_set,
390 .mac_addr_add = eth_igb_rar_set,
391 .mac_addr_remove = eth_igb_rar_clear,
392 .mac_addr_set = eth_igb_default_mac_addr_set,
393 .reta_update = eth_igb_rss_reta_update,
394 .reta_query = eth_igb_rss_reta_query,
395 .rss_hash_update = eth_igb_rss_hash_update,
396 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
397 .filter_ctrl = eth_igb_filter_ctrl,
398 .set_mc_addr_list = eth_igb_set_mc_addr_list,
399 .rxq_info_get = igb_rxq_info_get,
400 .txq_info_get = igb_txq_info_get,
401 .timesync_enable = igb_timesync_enable,
402 .timesync_disable = igb_timesync_disable,
403 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
404 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
405 .get_reg = eth_igb_get_regs,
406 .get_eeprom_length = eth_igb_get_eeprom_length,
407 .get_eeprom = eth_igb_get_eeprom,
408 .set_eeprom = eth_igb_set_eeprom,
409 .get_module_info = eth_igb_get_module_info,
410 .get_module_eeprom = eth_igb_get_module_eeprom,
411 .timesync_adjust_time = igb_timesync_adjust_time,
412 .timesync_read_time = igb_timesync_read_time,
413 .timesync_write_time = igb_timesync_write_time,
417 * dev_ops for virtual function, bare necessities for basic vf
418 * operation have been implemented
420 static const struct eth_dev_ops igbvf_eth_dev_ops = {
421 .dev_configure = igbvf_dev_configure,
422 .dev_start = igbvf_dev_start,
423 .dev_stop = igbvf_dev_stop,
424 .dev_close = igbvf_dev_close,
425 .promiscuous_enable = igbvf_promiscuous_enable,
426 .promiscuous_disable = igbvf_promiscuous_disable,
427 .allmulticast_enable = igbvf_allmulticast_enable,
428 .allmulticast_disable = igbvf_allmulticast_disable,
429 .link_update = eth_igb_link_update,
430 .stats_get = eth_igbvf_stats_get,
431 .xstats_get = eth_igbvf_xstats_get,
432 .xstats_get_names = eth_igbvf_xstats_get_names,
433 .stats_reset = eth_igbvf_stats_reset,
434 .xstats_reset = eth_igbvf_stats_reset,
435 .vlan_filter_set = igbvf_vlan_filter_set,
436 .dev_infos_get = eth_igbvf_infos_get,
437 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
438 .rx_queue_setup = eth_igb_rx_queue_setup,
439 .rx_queue_release = eth_igb_rx_queue_release,
440 .rx_descriptor_done = eth_igb_rx_descriptor_done,
441 .rx_descriptor_status = eth_igb_rx_descriptor_status,
442 .tx_descriptor_status = eth_igb_tx_descriptor_status,
443 .tx_queue_setup = eth_igb_tx_queue_setup,
444 .tx_queue_release = eth_igb_tx_queue_release,
445 .set_mc_addr_list = eth_igb_set_mc_addr_list,
446 .rxq_info_get = igb_rxq_info_get,
447 .txq_info_get = igb_txq_info_get,
448 .mac_addr_set = igbvf_default_mac_addr_set,
449 .get_reg = igbvf_get_regs,
452 /* store statistics names and its offset in stats structure */
453 struct rte_igb_xstats_name_off {
454 char name[RTE_ETH_XSTATS_NAME_SIZE];
458 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
459 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
460 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
461 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
462 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
463 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
464 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
465 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
467 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
468 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
469 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
470 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
471 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
472 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
473 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
474 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
475 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
476 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
477 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
479 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
480 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
481 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
482 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
483 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
485 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
487 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
488 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
489 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
490 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
491 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
492 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
493 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
494 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
495 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
496 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
497 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
498 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
499 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
500 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
501 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
502 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
503 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
504 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
506 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
508 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
509 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
510 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
511 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
512 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
513 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
514 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
516 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
519 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
520 sizeof(rte_igb_stats_strings[0]))
522 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
523 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
524 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
525 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
526 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
527 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
530 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
531 sizeof(rte_igbvf_stats_strings[0]))
535 igb_intr_enable(struct rte_eth_dev *dev)
537 struct e1000_interrupt *intr =
538 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
539 struct e1000_hw *hw =
540 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
542 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
543 E1000_WRITE_FLUSH(hw);
547 igb_intr_disable(struct e1000_hw *hw)
549 E1000_WRITE_REG(hw, E1000_IMC, ~0);
550 E1000_WRITE_FLUSH(hw);
554 igbvf_intr_enable(struct rte_eth_dev *dev)
556 struct e1000_hw *hw =
557 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
559 /* only for mailbox */
560 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
561 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
562 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
563 E1000_WRITE_FLUSH(hw);
566 /* only for mailbox now. If RX/TX needed, should extend this function. */
568 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
573 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
574 tmp |= E1000_VTIVAR_VALID;
575 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
579 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
581 struct e1000_hw *hw =
582 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
584 /* Configure VF other cause ivar */
585 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
588 static inline int32_t
589 igb_pf_reset_hw(struct e1000_hw *hw)
594 status = e1000_reset_hw(hw);
596 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
597 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
598 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
599 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
600 E1000_WRITE_FLUSH(hw);
606 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
608 struct e1000_hw *hw =
609 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
612 hw->vendor_id = pci_dev->id.vendor_id;
613 hw->device_id = pci_dev->id.device_id;
614 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
615 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
617 e1000_set_mac_type(hw);
619 /* need to check if it is a vf device below */
623 igb_reset_swfw_lock(struct e1000_hw *hw)
628 * Do mac ops initialization manually here, since we will need
629 * some function pointers set by this call.
631 ret_val = e1000_init_mac_params(hw);
636 * SMBI lock should not fail in this early stage. If this is the case,
637 * it is due to an improper exit of the application.
638 * So force the release of the faulty lock.
640 if (e1000_get_hw_semaphore_generic(hw) < 0) {
641 PMD_DRV_LOG(DEBUG, "SMBI lock released");
643 e1000_put_hw_semaphore_generic(hw);
645 if (hw->mac.ops.acquire_swfw_sync != NULL) {
649 * Phy lock should not fail in this early stage. If this is the case,
650 * it is due to an improper exit of the application.
651 * So force the release of the faulty lock.
653 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
654 if (hw->bus.func > E1000_FUNC_1)
656 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
657 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
660 hw->mac.ops.release_swfw_sync(hw, mask);
663 * This one is more tricky since it is common to all ports; but
664 * swfw_sync retries last long enough (1s) to be almost sure that if
665 * lock can not be taken it is due to an improper lock of the
668 mask = E1000_SWFW_EEP_SM;
669 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
670 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
672 hw->mac.ops.release_swfw_sync(hw, mask);
675 return E1000_SUCCESS;
678 /* Remove all ntuple filters of the device */
679 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
681 struct e1000_filter_info *filter_info =
682 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
683 struct e1000_5tuple_filter *p_5tuple;
684 struct e1000_2tuple_filter *p_2tuple;
686 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
687 TAILQ_REMOVE(&filter_info->fivetuple_list,
691 filter_info->fivetuple_mask = 0;
692 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
693 TAILQ_REMOVE(&filter_info->twotuple_list,
697 filter_info->twotuple_mask = 0;
702 /* Remove all flex filters of the device */
703 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
705 struct e1000_filter_info *filter_info =
706 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
707 struct e1000_flex_filter *p_flex;
709 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
710 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
713 filter_info->flex_mask = 0;
719 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
722 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
723 struct e1000_hw *hw =
724 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
725 struct e1000_vfta * shadow_vfta =
726 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
727 struct e1000_filter_info *filter_info =
728 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
729 struct e1000_adapter *adapter =
730 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
734 eth_dev->dev_ops = ð_igb_ops;
735 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
736 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
737 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
739 /* for secondary processes, we don't initialise any further as primary
740 * has already done this work. Only check we don't need a different
742 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
743 if (eth_dev->data->scattered_rx)
744 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
748 rte_eth_copy_pci_info(eth_dev, pci_dev);
750 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
752 igb_identify_hardware(eth_dev, pci_dev);
753 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
758 e1000_get_bus_info(hw);
760 /* Reset any pending lock */
761 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
766 /* Finish initialization */
767 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
773 hw->phy.autoneg_wait_to_complete = 0;
774 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
777 if (hw->phy.media_type == e1000_media_type_copper) {
778 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
779 hw->phy.disable_polarity_correction = 0;
780 hw->phy.ms_type = e1000_ms_hw_default;
784 * Start from a known state, this is important in reading the nvm
789 /* Make sure we have a good EEPROM before we read from it */
790 if (e1000_validate_nvm_checksum(hw) < 0) {
792 * Some PCI-E parts fail the first check due to
793 * the link being in sleep state, call it again,
794 * if it fails a second time its a real issue.
796 if (e1000_validate_nvm_checksum(hw) < 0) {
797 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
803 /* Read the permanent MAC address out of the EEPROM */
804 if (e1000_read_mac_addr(hw) != 0) {
805 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
810 /* Allocate memory for storing MAC addresses */
811 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
812 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
813 if (eth_dev->data->mac_addrs == NULL) {
814 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
815 "store MAC addresses",
816 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
821 /* Copy the permanent MAC address */
822 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
824 /* initialize the vfta */
825 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
827 /* Now initialize the hardware */
828 if (igb_hardware_init(hw) != 0) {
829 PMD_INIT_LOG(ERR, "Hardware initialization failed");
830 rte_free(eth_dev->data->mac_addrs);
831 eth_dev->data->mac_addrs = NULL;
835 hw->mac.get_link_status = 1;
836 adapter->stopped = 0;
838 /* Indicate SOL/IDER usage */
839 if (e1000_check_reset_block(hw) < 0) {
840 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
844 /* initialize PF if max_vfs not zero */
845 igb_pf_host_init(eth_dev);
847 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
848 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
849 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
850 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
851 E1000_WRITE_FLUSH(hw);
853 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
854 eth_dev->data->port_id, pci_dev->id.vendor_id,
855 pci_dev->id.device_id);
857 rte_intr_callback_register(&pci_dev->intr_handle,
858 eth_igb_interrupt_handler,
861 /* enable uio/vfio intr/eventfd mapping */
862 rte_intr_enable(&pci_dev->intr_handle);
864 /* enable support intr */
865 igb_intr_enable(eth_dev);
867 /* initialize filter info */
868 memset(filter_info, 0,
869 sizeof(struct e1000_filter_info));
871 TAILQ_INIT(&filter_info->flex_list);
872 TAILQ_INIT(&filter_info->twotuple_list);
873 TAILQ_INIT(&filter_info->fivetuple_list);
875 TAILQ_INIT(&igb_filter_ntuple_list);
876 TAILQ_INIT(&igb_filter_ethertype_list);
877 TAILQ_INIT(&igb_filter_syn_list);
878 TAILQ_INIT(&igb_filter_flex_list);
879 TAILQ_INIT(&igb_filter_rss_list);
880 TAILQ_INIT(&igb_flow_list);
885 igb_hw_control_release(hw);
891 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
893 struct rte_pci_device *pci_dev;
894 struct rte_intr_handle *intr_handle;
896 struct e1000_adapter *adapter =
897 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
898 struct e1000_filter_info *filter_info =
899 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
901 PMD_INIT_FUNC_TRACE();
903 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
906 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
907 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
908 intr_handle = &pci_dev->intr_handle;
910 if (adapter->stopped == 0)
911 eth_igb_close(eth_dev);
913 eth_dev->dev_ops = NULL;
914 eth_dev->rx_pkt_burst = NULL;
915 eth_dev->tx_pkt_burst = NULL;
917 /* Reset any pending lock */
918 igb_reset_swfw_lock(hw);
920 /* uninitialize PF if max_vfs not zero */
921 igb_pf_host_uninit(eth_dev);
923 /* disable uio intr before callback unregister */
924 rte_intr_disable(intr_handle);
925 rte_intr_callback_unregister(intr_handle,
926 eth_igb_interrupt_handler, eth_dev);
928 /* clear the SYN filter info */
929 filter_info->syn_info = 0;
931 /* clear the ethertype filters info */
932 filter_info->ethertype_mask = 0;
933 memset(filter_info->ethertype_filters, 0,
934 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
936 /* clear the rss filter info */
937 memset(&filter_info->rss_info, 0,
938 sizeof(struct igb_rte_flow_rss_conf));
940 /* remove all ntuple filters of the device */
941 igb_ntuple_filter_uninit(eth_dev);
943 /* remove all flex filters of the device */
944 igb_flex_filter_uninit(eth_dev);
946 /* clear all the filters list */
947 igb_filterlist_flush(eth_dev);
953 * Virtual Function device init
956 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
958 struct rte_pci_device *pci_dev;
959 struct rte_intr_handle *intr_handle;
960 struct e1000_adapter *adapter =
961 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
962 struct e1000_hw *hw =
963 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
965 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
967 PMD_INIT_FUNC_TRACE();
969 eth_dev->dev_ops = &igbvf_eth_dev_ops;
970 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
971 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
972 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
974 /* for secondary processes, we don't initialise any further as primary
975 * has already done this work. Only check we don't need a different
977 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
978 if (eth_dev->data->scattered_rx)
979 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
983 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
984 rte_eth_copy_pci_info(eth_dev, pci_dev);
986 hw->device_id = pci_dev->id.device_id;
987 hw->vendor_id = pci_dev->id.vendor_id;
988 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
989 adapter->stopped = 0;
991 /* Initialize the shared code (base driver) */
992 diag = e1000_setup_init_funcs(hw, TRUE);
994 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
999 /* init_mailbox_params */
1000 hw->mbx.ops.init_params(hw);
1002 /* Disable the interrupts for VF */
1003 igbvf_intr_disable(hw);
1005 diag = hw->mac.ops.reset_hw(hw);
1007 /* Allocate memory for storing MAC addresses */
1008 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1009 hw->mac.rar_entry_count, 0);
1010 if (eth_dev->data->mac_addrs == NULL) {
1012 "Failed to allocate %d bytes needed to store MAC "
1014 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1018 /* Generate a random MAC address, if none was assigned by PF. */
1019 if (is_zero_ether_addr(perm_addr)) {
1020 eth_random_addr(perm_addr->addr_bytes);
1021 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1022 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1023 "%02x:%02x:%02x:%02x:%02x:%02x",
1024 perm_addr->addr_bytes[0],
1025 perm_addr->addr_bytes[1],
1026 perm_addr->addr_bytes[2],
1027 perm_addr->addr_bytes[3],
1028 perm_addr->addr_bytes[4],
1029 perm_addr->addr_bytes[5]);
1032 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1034 rte_free(eth_dev->data->mac_addrs);
1035 eth_dev->data->mac_addrs = NULL;
1038 /* Copy the permanent MAC address */
1039 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1040 ð_dev->data->mac_addrs[0]);
1042 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1044 eth_dev->data->port_id, pci_dev->id.vendor_id,
1045 pci_dev->id.device_id, "igb_mac_82576_vf");
1047 intr_handle = &pci_dev->intr_handle;
1048 rte_intr_callback_register(intr_handle,
1049 eth_igbvf_interrupt_handler, eth_dev);
1055 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1057 struct e1000_adapter *adapter =
1058 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1059 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1061 PMD_INIT_FUNC_TRACE();
1063 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1066 if (adapter->stopped == 0)
1067 igbvf_dev_close(eth_dev);
1069 eth_dev->dev_ops = NULL;
1070 eth_dev->rx_pkt_burst = NULL;
1071 eth_dev->tx_pkt_burst = NULL;
1073 /* disable uio intr before callback unregister */
1074 rte_intr_disable(&pci_dev->intr_handle);
1075 rte_intr_callback_unregister(&pci_dev->intr_handle,
1076 eth_igbvf_interrupt_handler,
1082 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1083 struct rte_pci_device *pci_dev)
1085 return rte_eth_dev_pci_generic_probe(pci_dev,
1086 sizeof(struct e1000_adapter), eth_igb_dev_init);
1089 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1091 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1094 static struct rte_pci_driver rte_igb_pmd = {
1095 .id_table = pci_id_igb_map,
1096 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1097 RTE_PCI_DRV_IOVA_AS_VA,
1098 .probe = eth_igb_pci_probe,
1099 .remove = eth_igb_pci_remove,
1103 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1104 struct rte_pci_device *pci_dev)
1106 return rte_eth_dev_pci_generic_probe(pci_dev,
1107 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1110 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1112 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1116 * virtual function driver struct
1118 static struct rte_pci_driver rte_igbvf_pmd = {
1119 .id_table = pci_id_igbvf_map,
1120 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1121 .probe = eth_igbvf_pci_probe,
1122 .remove = eth_igbvf_pci_remove,
1126 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1128 struct e1000_hw *hw =
1129 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1131 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1132 rctl |= E1000_RCTL_VFE;
1133 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1137 igb_check_mq_mode(struct rte_eth_dev *dev)
1139 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1140 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1141 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1142 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1144 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1145 tx_mq_mode == ETH_MQ_TX_DCB ||
1146 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1147 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1150 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1151 /* Check multi-queue mode.
1152 * To no break software we accept ETH_MQ_RX_NONE as this might
1153 * be used to turn off VLAN filter.
1156 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1157 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1158 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1159 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1161 /* Only support one queue on VFs.
1162 * RSS together with SRIOV is not supported.
1164 PMD_INIT_LOG(ERR, "SRIOV is active,"
1165 " wrong mq_mode rx %d.",
1169 /* TX mode is not used here, so mode might be ignored.*/
1170 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1171 /* SRIOV only works in VMDq enable mode */
1172 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1173 " TX mode %d is not supported. "
1174 " Driver will behave as %d mode.",
1175 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1178 /* check valid queue number */
1179 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1180 PMD_INIT_LOG(ERR, "SRIOV is active,"
1181 " only support one queue on VFs.");
1185 /* To no break software that set invalid mode, only display
1186 * warning if invalid mode is used.
1188 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1189 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1190 rx_mq_mode != ETH_MQ_RX_RSS) {
1191 /* RSS together with VMDq not supported*/
1192 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1197 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1198 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1199 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1200 " Due to txmode is meaningless in this"
1201 " driver, just ignore.",
1209 eth_igb_configure(struct rte_eth_dev *dev)
1211 struct e1000_interrupt *intr =
1212 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1215 PMD_INIT_FUNC_TRACE();
1217 /* multipe queue mode checking */
1218 ret = igb_check_mq_mode(dev);
1220 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1225 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1226 PMD_INIT_FUNC_TRACE();
1232 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1235 struct e1000_hw *hw =
1236 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237 uint32_t tctl, rctl;
1239 tctl = E1000_READ_REG(hw, E1000_TCTL);
1240 rctl = E1000_READ_REG(hw, E1000_RCTL);
1244 tctl |= E1000_TCTL_EN;
1245 rctl |= E1000_RCTL_EN;
1248 tctl &= ~E1000_TCTL_EN;
1249 rctl &= ~E1000_RCTL_EN;
1251 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1252 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1253 E1000_WRITE_FLUSH(hw);
1257 eth_igb_start(struct rte_eth_dev *dev)
1259 struct e1000_hw *hw =
1260 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1261 struct e1000_adapter *adapter =
1262 E1000_DEV_PRIVATE(dev->data->dev_private);
1263 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1264 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1266 uint32_t intr_vector = 0;
1272 PMD_INIT_FUNC_TRACE();
1274 /* disable uio/vfio intr/eventfd mapping */
1275 rte_intr_disable(intr_handle);
1277 /* Power up the phy. Needed to make the link go Up */
1278 eth_igb_dev_set_link_up(dev);
1281 * Packet Buffer Allocation (PBA)
1282 * Writing PBA sets the receive portion of the buffer
1283 * the remainder is used for the transmit buffer.
1285 if (hw->mac.type == e1000_82575) {
1288 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1289 E1000_WRITE_REG(hw, E1000_PBA, pba);
1292 /* Put the address into the Receive Address Array */
1293 e1000_rar_set(hw, hw->mac.addr, 0);
1295 /* Initialize the hardware */
1296 if (igb_hardware_init(hw)) {
1297 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1300 adapter->stopped = 0;
1302 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1304 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1305 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1307 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1308 E1000_WRITE_FLUSH(hw);
1310 /* configure PF module if SRIOV enabled */
1311 igb_pf_host_configure(dev);
1313 /* check and configure queue intr-vector mapping */
1314 if ((rte_intr_cap_multiple(intr_handle) ||
1315 !RTE_ETH_DEV_SRIOV(dev).active) &&
1316 dev->data->dev_conf.intr_conf.rxq != 0) {
1317 intr_vector = dev->data->nb_rx_queues;
1318 if (rte_intr_efd_enable(intr_handle, intr_vector))
1322 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1323 intr_handle->intr_vec =
1324 rte_zmalloc("intr_vec",
1325 dev->data->nb_rx_queues * sizeof(int), 0);
1326 if (intr_handle->intr_vec == NULL) {
1327 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1328 " intr_vec", dev->data->nb_rx_queues);
1333 /* confiugre msix for rx interrupt */
1334 eth_igb_configure_msix_intr(dev);
1336 /* Configure for OS presence */
1337 igb_init_manageability(hw);
1339 eth_igb_tx_init(dev);
1341 /* This can fail when allocating mbufs for descriptor rings */
1342 ret = eth_igb_rx_init(dev);
1344 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1345 igb_dev_clear_queues(dev);
1349 e1000_clear_hw_cntrs_base_generic(hw);
1352 * VLAN Offload Settings
1354 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1355 ETH_VLAN_EXTEND_MASK;
1356 ret = eth_igb_vlan_offload_set(dev, mask);
1358 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1359 igb_dev_clear_queues(dev);
1363 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1364 /* Enable VLAN filter since VMDq always use VLAN filter */
1365 igb_vmdq_vlan_hw_filter_enable(dev);
1368 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1369 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1370 (hw->mac.type == e1000_i211)) {
1371 /* Configure EITR with the maximum possible value (0xFFFF) */
1372 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1375 /* Setup link speed and duplex */
1376 speeds = &dev->data->dev_conf.link_speeds;
1377 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1378 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1379 hw->mac.autoneg = 1;
1382 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1385 hw->phy.autoneg_advertised = 0;
1387 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1388 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1389 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1391 goto error_invalid_config;
1393 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1394 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1397 if (*speeds & ETH_LINK_SPEED_10M) {
1398 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1401 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1402 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1405 if (*speeds & ETH_LINK_SPEED_100M) {
1406 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1409 if (*speeds & ETH_LINK_SPEED_1G) {
1410 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1413 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1414 goto error_invalid_config;
1416 /* Set/reset the mac.autoneg based on the link speed,
1420 hw->mac.autoneg = 0;
1421 hw->mac.forced_speed_duplex =
1422 hw->phy.autoneg_advertised;
1424 hw->mac.autoneg = 1;
1428 e1000_setup_link(hw);
1430 if (rte_intr_allow_others(intr_handle)) {
1431 /* check if lsc interrupt is enabled */
1432 if (dev->data->dev_conf.intr_conf.lsc != 0)
1433 eth_igb_lsc_interrupt_setup(dev, TRUE);
1435 eth_igb_lsc_interrupt_setup(dev, FALSE);
1437 rte_intr_callback_unregister(intr_handle,
1438 eth_igb_interrupt_handler,
1440 if (dev->data->dev_conf.intr_conf.lsc != 0)
1441 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1442 " no intr multiplex");
1445 /* check if rxq interrupt is enabled */
1446 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1447 rte_intr_dp_is_en(intr_handle))
1448 eth_igb_rxq_interrupt_setup(dev);
1450 /* enable uio/vfio intr/eventfd mapping */
1451 rte_intr_enable(intr_handle);
1453 /* resume enabled intr since hw reset */
1454 igb_intr_enable(dev);
1456 /* restore all types filter */
1457 igb_filter_restore(dev);
1459 eth_igb_rxtx_control(dev, true);
1460 eth_igb_link_update(dev, 0);
1462 PMD_INIT_LOG(DEBUG, "<<");
1466 error_invalid_config:
1467 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1468 dev->data->dev_conf.link_speeds, dev->data->port_id);
1469 igb_dev_clear_queues(dev);
1473 /*********************************************************************
1475 * This routine disables all traffic on the adapter by issuing a
1476 * global reset on the MAC.
1478 **********************************************************************/
1480 eth_igb_stop(struct rte_eth_dev *dev)
1482 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1484 struct rte_eth_link link;
1485 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1487 eth_igb_rxtx_control(dev, false);
1489 igb_intr_disable(hw);
1491 /* disable intr eventfd mapping */
1492 rte_intr_disable(intr_handle);
1494 igb_pf_reset_hw(hw);
1495 E1000_WRITE_REG(hw, E1000_WUC, 0);
1497 /* Set bit for Go Link disconnect */
1498 if (hw->mac.type >= e1000_82580) {
1501 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1502 phpm_reg |= E1000_82580_PM_GO_LINKD;
1503 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1506 /* Power down the phy. Needed to make the link go Down */
1507 eth_igb_dev_set_link_down(dev);
1509 igb_dev_clear_queues(dev);
1511 /* clear the recorded link status */
1512 memset(&link, 0, sizeof(link));
1513 rte_eth_linkstatus_set(dev, &link);
1515 if (!rte_intr_allow_others(intr_handle))
1516 /* resume to the default handler */
1517 rte_intr_callback_register(intr_handle,
1518 eth_igb_interrupt_handler,
1521 /* Clean datapath event and queue/vec mapping */
1522 rte_intr_efd_disable(intr_handle);
1523 if (intr_handle->intr_vec != NULL) {
1524 rte_free(intr_handle->intr_vec);
1525 intr_handle->intr_vec = NULL;
1530 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1532 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534 if (hw->phy.media_type == e1000_media_type_copper)
1535 e1000_power_up_phy(hw);
1537 e1000_power_up_fiber_serdes_link(hw);
1543 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1545 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1547 if (hw->phy.media_type == e1000_media_type_copper)
1548 e1000_power_down_phy(hw);
1550 e1000_shutdown_fiber_serdes_link(hw);
1556 eth_igb_close(struct rte_eth_dev *dev)
1558 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559 struct e1000_adapter *adapter =
1560 E1000_DEV_PRIVATE(dev->data->dev_private);
1561 struct rte_eth_link link;
1562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1566 adapter->stopped = 1;
1568 e1000_phy_hw_reset(hw);
1569 igb_release_manageability(hw);
1570 igb_hw_control_release(hw);
1572 /* Clear bit for Go Link disconnect */
1573 if (hw->mac.type >= e1000_82580) {
1576 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1577 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1578 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1581 igb_dev_free_queues(dev);
1583 if (intr_handle->intr_vec) {
1584 rte_free(intr_handle->intr_vec);
1585 intr_handle->intr_vec = NULL;
1588 memset(&link, 0, sizeof(link));
1589 rte_eth_linkstatus_set(dev, &link);
1596 eth_igb_reset(struct rte_eth_dev *dev)
1600 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1601 * its VF to make them align with it. The detailed notification
1602 * mechanism is PMD specific and is currently not implemented.
1603 * To avoid unexpected behavior in VF, currently reset of PF with
1604 * SR-IOV activation is not supported. It might be supported later.
1606 if (dev->data->sriov.active)
1609 ret = eth_igb_dev_uninit(dev);
1613 ret = eth_igb_dev_init(dev);
1620 igb_get_rx_buffer_size(struct e1000_hw *hw)
1622 uint32_t rx_buf_size;
1623 if (hw->mac.type == e1000_82576) {
1624 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1625 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1626 /* PBS needs to be translated according to a lookup table */
1627 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1628 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1629 rx_buf_size = (rx_buf_size << 10);
1630 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1631 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1633 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1639 /*********************************************************************
1641 * Initialize the hardware
1643 **********************************************************************/
1645 igb_hardware_init(struct e1000_hw *hw)
1647 uint32_t rx_buf_size;
1650 /* Let the firmware know the OS is in control */
1651 igb_hw_control_acquire(hw);
1654 * These parameters control the automatic generation (Tx) and
1655 * response (Rx) to Ethernet PAUSE frames.
1656 * - High water mark should allow for at least two standard size (1518)
1657 * frames to be received after sending an XOFF.
1658 * - Low water mark works best when it is very near the high water mark.
1659 * This allows the receiver to restart by sending XON when it has
1660 * drained a bit. Here we use an arbitrary value of 1500 which will
1661 * restart after one full frame is pulled from the buffer. There
1662 * could be several smaller frames in the buffer and if so they will
1663 * not trigger the XON until their total number reduces the buffer
1665 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1667 rx_buf_size = igb_get_rx_buffer_size(hw);
1669 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1670 hw->fc.low_water = hw->fc.high_water - 1500;
1671 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1672 hw->fc.send_xon = 1;
1674 /* Set Flow control, use the tunable location if sane */
1675 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1676 hw->fc.requested_mode = igb_fc_setting;
1678 hw->fc.requested_mode = e1000_fc_none;
1680 /* Issue a global reset */
1681 igb_pf_reset_hw(hw);
1682 E1000_WRITE_REG(hw, E1000_WUC, 0);
1684 diag = e1000_init_hw(hw);
1688 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1689 e1000_get_phy_info(hw);
1690 e1000_check_for_link(hw);
1695 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1697 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1701 uint64_t old_gprc = stats->gprc;
1702 uint64_t old_gptc = stats->gptc;
1703 uint64_t old_tpr = stats->tpr;
1704 uint64_t old_tpt = stats->tpt;
1705 uint64_t old_rpthc = stats->rpthc;
1706 uint64_t old_hgptc = stats->hgptc;
1708 if(hw->phy.media_type == e1000_media_type_copper ||
1709 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1711 E1000_READ_REG(hw,E1000_SYMERRS);
1712 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1715 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1716 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1717 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1718 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1720 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1721 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1722 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1723 stats->dc += E1000_READ_REG(hw, E1000_DC);
1724 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1725 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1726 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1728 ** For watchdog management we need to know if we have been
1729 ** paused during the last interval, so capture that here.
1731 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1732 stats->xoffrxc += pause_frames;
1733 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1734 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1735 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1736 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1737 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1738 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1739 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1740 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1741 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1742 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1743 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1744 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1746 /* For the 64-bit byte counters the low dword must be read first. */
1747 /* Both registers clear on the read of the high dword */
1749 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1750 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1751 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1752 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1753 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1754 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1755 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1757 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1758 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1759 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1760 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1761 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1763 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1764 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1766 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1767 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1768 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1769 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1770 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1771 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1773 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1774 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1775 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1776 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1777 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1778 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1779 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1780 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1782 /* Interrupt Counts */
1784 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1785 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1786 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1787 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1788 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1789 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1790 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1791 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1792 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1794 /* Host to Card Statistics */
1796 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1797 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1798 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1799 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1800 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1801 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1802 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1803 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1804 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1805 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1806 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1807 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1808 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1809 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1810 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1811 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1813 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1814 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1815 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1816 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1817 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1818 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1822 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1824 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825 struct e1000_hw_stats *stats =
1826 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1828 igb_read_stats_registers(hw, stats);
1830 if (rte_stats == NULL)
1834 rte_stats->imissed = stats->mpc;
1835 rte_stats->ierrors = stats->crcerrs +
1836 stats->rlec + stats->ruc + stats->roc +
1837 stats->rxerrc + stats->algnerrc + stats->cexterr;
1840 rte_stats->oerrors = stats->ecol + stats->latecol;
1842 rte_stats->ipackets = stats->gprc;
1843 rte_stats->opackets = stats->gptc;
1844 rte_stats->ibytes = stats->gorc;
1845 rte_stats->obytes = stats->gotc;
1850 eth_igb_stats_reset(struct rte_eth_dev *dev)
1852 struct e1000_hw_stats *hw_stats =
1853 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1855 /* HW registers are cleared on read */
1856 eth_igb_stats_get(dev, NULL);
1858 /* Reset software totals */
1859 memset(hw_stats, 0, sizeof(*hw_stats));
1863 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1865 struct e1000_hw_stats *stats =
1866 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1868 /* HW registers are cleared on read */
1869 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1871 /* Reset software totals */
1872 memset(stats, 0, sizeof(*stats));
1875 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1876 struct rte_eth_xstat_name *xstats_names,
1877 __rte_unused unsigned int size)
1881 if (xstats_names == NULL)
1882 return IGB_NB_XSTATS;
1884 /* Note: limit checked in rte_eth_xstats_names() */
1886 for (i = 0; i < IGB_NB_XSTATS; i++) {
1887 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1888 "%s", rte_igb_stats_strings[i].name);
1891 return IGB_NB_XSTATS;
1894 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1895 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1901 if (xstats_names == NULL)
1902 return IGB_NB_XSTATS;
1904 for (i = 0; i < IGB_NB_XSTATS; i++)
1905 snprintf(xstats_names[i].name,
1906 sizeof(xstats_names[i].name),
1907 "%s", rte_igb_stats_strings[i].name);
1909 return IGB_NB_XSTATS;
1912 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1914 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1917 for (i = 0; i < limit; i++) {
1918 if (ids[i] >= IGB_NB_XSTATS) {
1919 PMD_INIT_LOG(ERR, "id value isn't valid");
1922 strcpy(xstats_names[i].name,
1923 xstats_names_copy[ids[i]].name);
1930 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1933 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934 struct e1000_hw_stats *hw_stats =
1935 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1938 if (n < IGB_NB_XSTATS)
1939 return IGB_NB_XSTATS;
1941 igb_read_stats_registers(hw, hw_stats);
1943 /* If this is a reset xstats is NULL, and we have cleared the
1944 * registers by reading them.
1949 /* Extended stats */
1950 for (i = 0; i < IGB_NB_XSTATS; i++) {
1952 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1953 rte_igb_stats_strings[i].offset);
1956 return IGB_NB_XSTATS;
1960 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1961 uint64_t *values, unsigned int n)
1966 struct e1000_hw *hw =
1967 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968 struct e1000_hw_stats *hw_stats =
1969 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1971 if (n < IGB_NB_XSTATS)
1972 return IGB_NB_XSTATS;
1974 igb_read_stats_registers(hw, hw_stats);
1976 /* If this is a reset xstats is NULL, and we have cleared the
1977 * registers by reading them.
1982 /* Extended stats */
1983 for (i = 0; i < IGB_NB_XSTATS; i++)
1984 values[i] = *(uint64_t *)(((char *)hw_stats) +
1985 rte_igb_stats_strings[i].offset);
1987 return IGB_NB_XSTATS;
1990 uint64_t values_copy[IGB_NB_XSTATS];
1992 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1995 for (i = 0; i < n; i++) {
1996 if (ids[i] >= IGB_NB_XSTATS) {
1997 PMD_INIT_LOG(ERR, "id value isn't valid");
2000 values[i] = values_copy[ids[i]];
2007 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2009 /* Good Rx packets, include VF loopback */
2010 UPDATE_VF_STAT(E1000_VFGPRC,
2011 hw_stats->last_gprc, hw_stats->gprc);
2013 /* Good Rx octets, include VF loopback */
2014 UPDATE_VF_STAT(E1000_VFGORC,
2015 hw_stats->last_gorc, hw_stats->gorc);
2017 /* Good Tx packets, include VF loopback */
2018 UPDATE_VF_STAT(E1000_VFGPTC,
2019 hw_stats->last_gptc, hw_stats->gptc);
2021 /* Good Tx octets, include VF loopback */
2022 UPDATE_VF_STAT(E1000_VFGOTC,
2023 hw_stats->last_gotc, hw_stats->gotc);
2025 /* Rx Multicst packets */
2026 UPDATE_VF_STAT(E1000_VFMPRC,
2027 hw_stats->last_mprc, hw_stats->mprc);
2029 /* Good Rx loopback packets */
2030 UPDATE_VF_STAT(E1000_VFGPRLBC,
2031 hw_stats->last_gprlbc, hw_stats->gprlbc);
2033 /* Good Rx loopback octets */
2034 UPDATE_VF_STAT(E1000_VFGORLBC,
2035 hw_stats->last_gorlbc, hw_stats->gorlbc);
2037 /* Good Tx loopback packets */
2038 UPDATE_VF_STAT(E1000_VFGPTLBC,
2039 hw_stats->last_gptlbc, hw_stats->gptlbc);
2041 /* Good Tx loopback octets */
2042 UPDATE_VF_STAT(E1000_VFGOTLBC,
2043 hw_stats->last_gotlbc, hw_stats->gotlbc);
2046 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2047 struct rte_eth_xstat_name *xstats_names,
2048 __rte_unused unsigned limit)
2052 if (xstats_names != NULL)
2053 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2054 snprintf(xstats_names[i].name,
2055 sizeof(xstats_names[i].name), "%s",
2056 rte_igbvf_stats_strings[i].name);
2058 return IGBVF_NB_XSTATS;
2062 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2065 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2067 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2070 if (n < IGBVF_NB_XSTATS)
2071 return IGBVF_NB_XSTATS;
2073 igbvf_read_stats_registers(hw, hw_stats);
2078 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2080 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2081 rte_igbvf_stats_strings[i].offset);
2084 return IGBVF_NB_XSTATS;
2088 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2090 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2092 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2094 igbvf_read_stats_registers(hw, hw_stats);
2096 if (rte_stats == NULL)
2099 rte_stats->ipackets = hw_stats->gprc;
2100 rte_stats->ibytes = hw_stats->gorc;
2101 rte_stats->opackets = hw_stats->gptc;
2102 rte_stats->obytes = hw_stats->gotc;
2107 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2109 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2110 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2112 /* Sync HW register to the last stats */
2113 eth_igbvf_stats_get(dev, NULL);
2115 /* reset HW current stats*/
2116 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2117 offsetof(struct e1000_vf_stats, gprc));
2121 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2124 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 struct e1000_fw_version fw;
2128 e1000_get_fw_version(hw, &fw);
2130 switch (hw->mac.type) {
2133 if (!(e1000_get_flash_presence_i210(hw))) {
2134 ret = snprintf(fw_version, fw_size,
2136 fw.invm_major, fw.invm_minor,
2142 /* if option rom is valid, display its version too */
2144 ret = snprintf(fw_version, fw_size,
2145 "%d.%d, 0x%08x, %d.%d.%d",
2146 fw.eep_major, fw.eep_minor, fw.etrack_id,
2147 fw.or_major, fw.or_build, fw.or_patch);
2150 if (fw.etrack_id != 0X0000) {
2151 ret = snprintf(fw_version, fw_size,
2153 fw.eep_major, fw.eep_minor,
2156 ret = snprintf(fw_version, fw_size,
2158 fw.eep_major, fw.eep_minor,
2165 ret += 1; /* add the size of '\0' */
2166 if (fw_size < (u32)ret)
2173 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2175 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2178 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2179 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2180 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2181 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2182 dev_info->rx_queue_offload_capa;
2183 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2184 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2185 dev_info->tx_queue_offload_capa;
2187 switch (hw->mac.type) {
2189 dev_info->max_rx_queues = 4;
2190 dev_info->max_tx_queues = 4;
2191 dev_info->max_vmdq_pools = 0;
2195 dev_info->max_rx_queues = 16;
2196 dev_info->max_tx_queues = 16;
2197 dev_info->max_vmdq_pools = ETH_8_POOLS;
2198 dev_info->vmdq_queue_num = 16;
2202 dev_info->max_rx_queues = 8;
2203 dev_info->max_tx_queues = 8;
2204 dev_info->max_vmdq_pools = ETH_8_POOLS;
2205 dev_info->vmdq_queue_num = 8;
2209 dev_info->max_rx_queues = 8;
2210 dev_info->max_tx_queues = 8;
2211 dev_info->max_vmdq_pools = ETH_8_POOLS;
2212 dev_info->vmdq_queue_num = 8;
2216 dev_info->max_rx_queues = 8;
2217 dev_info->max_tx_queues = 8;
2221 dev_info->max_rx_queues = 4;
2222 dev_info->max_tx_queues = 4;
2223 dev_info->max_vmdq_pools = 0;
2227 dev_info->max_rx_queues = 2;
2228 dev_info->max_tx_queues = 2;
2229 dev_info->max_vmdq_pools = 0;
2233 /* Should not happen */
2236 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2237 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2238 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2240 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2242 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2243 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2244 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2246 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2251 dev_info->default_txconf = (struct rte_eth_txconf) {
2253 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2254 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2255 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2260 dev_info->rx_desc_lim = rx_desc_lim;
2261 dev_info->tx_desc_lim = tx_desc_lim;
2263 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2264 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2268 static const uint32_t *
2269 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2271 static const uint32_t ptypes[] = {
2272 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2275 RTE_PTYPE_L3_IPV4_EXT,
2277 RTE_PTYPE_L3_IPV6_EXT,
2281 RTE_PTYPE_TUNNEL_IP,
2282 RTE_PTYPE_INNER_L3_IPV6,
2283 RTE_PTYPE_INNER_L3_IPV6_EXT,
2284 RTE_PTYPE_INNER_L4_TCP,
2285 RTE_PTYPE_INNER_L4_UDP,
2289 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2290 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2296 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2298 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2301 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2302 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2303 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2304 DEV_TX_OFFLOAD_IPV4_CKSUM |
2305 DEV_TX_OFFLOAD_UDP_CKSUM |
2306 DEV_TX_OFFLOAD_TCP_CKSUM |
2307 DEV_TX_OFFLOAD_SCTP_CKSUM |
2308 DEV_TX_OFFLOAD_TCP_TSO;
2309 switch (hw->mac.type) {
2311 dev_info->max_rx_queues = 2;
2312 dev_info->max_tx_queues = 2;
2314 case e1000_vfadapt_i350:
2315 dev_info->max_rx_queues = 1;
2316 dev_info->max_tx_queues = 1;
2319 /* Should not happen */
2323 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2324 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2325 dev_info->rx_queue_offload_capa;
2326 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2327 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2328 dev_info->tx_queue_offload_capa;
2330 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2332 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2333 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2334 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2336 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2341 dev_info->default_txconf = (struct rte_eth_txconf) {
2343 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2344 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2345 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2350 dev_info->rx_desc_lim = rx_desc_lim;
2351 dev_info->tx_desc_lim = tx_desc_lim;
2354 /* return 0 means link status changed, -1 means not changed */
2356 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2358 struct e1000_hw *hw =
2359 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360 struct rte_eth_link link;
2361 int link_check, count;
2364 hw->mac.get_link_status = 1;
2366 /* possible wait-to-complete in up to 9 seconds */
2367 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2368 /* Read the real link status */
2369 switch (hw->phy.media_type) {
2370 case e1000_media_type_copper:
2371 /* Do the work to read phy */
2372 e1000_check_for_link(hw);
2373 link_check = !hw->mac.get_link_status;
2376 case e1000_media_type_fiber:
2377 e1000_check_for_link(hw);
2378 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2382 case e1000_media_type_internal_serdes:
2383 e1000_check_for_link(hw);
2384 link_check = hw->mac.serdes_has_link;
2387 /* VF device is type_unknown */
2388 case e1000_media_type_unknown:
2389 eth_igbvf_link_update(hw);
2390 link_check = !hw->mac.get_link_status;
2396 if (link_check || wait_to_complete == 0)
2398 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2400 memset(&link, 0, sizeof(link));
2402 /* Now we check if a transition has happened */
2404 uint16_t duplex, speed;
2405 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2406 link.link_duplex = (duplex == FULL_DUPLEX) ?
2407 ETH_LINK_FULL_DUPLEX :
2408 ETH_LINK_HALF_DUPLEX;
2409 link.link_speed = speed;
2410 link.link_status = ETH_LINK_UP;
2411 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2412 ETH_LINK_SPEED_FIXED);
2413 } else if (!link_check) {
2414 link.link_speed = 0;
2415 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2416 link.link_status = ETH_LINK_DOWN;
2417 link.link_autoneg = ETH_LINK_FIXED;
2420 return rte_eth_linkstatus_set(dev, &link);
2424 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2425 * For ASF and Pass Through versions of f/w this means
2426 * that the driver is loaded.
2429 igb_hw_control_acquire(struct e1000_hw *hw)
2433 /* Let firmware know the driver has taken over */
2434 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2435 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2439 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2440 * For ASF and Pass Through versions of f/w this means that the
2441 * driver is no longer loaded.
2444 igb_hw_control_release(struct e1000_hw *hw)
2448 /* Let firmware taken over control of h/w */
2449 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2450 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2451 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2455 * Bit of a misnomer, what this really means is
2456 * to enable OS management of the system... aka
2457 * to disable special hardware management features.
2460 igb_init_manageability(struct e1000_hw *hw)
2462 if (e1000_enable_mng_pass_thru(hw)) {
2463 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2464 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2466 /* disable hardware interception of ARP */
2467 manc &= ~(E1000_MANC_ARP_EN);
2469 /* enable receiving management packets to the host */
2470 manc |= E1000_MANC_EN_MNG2HOST;
2471 manc2h |= 1 << 5; /* Mng Port 623 */
2472 manc2h |= 1 << 6; /* Mng Port 664 */
2473 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2474 E1000_WRITE_REG(hw, E1000_MANC, manc);
2479 igb_release_manageability(struct e1000_hw *hw)
2481 if (e1000_enable_mng_pass_thru(hw)) {
2482 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2484 manc |= E1000_MANC_ARP_EN;
2485 manc &= ~E1000_MANC_EN_MNG2HOST;
2487 E1000_WRITE_REG(hw, E1000_MANC, manc);
2492 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2494 struct e1000_hw *hw =
2495 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 rctl = E1000_READ_REG(hw, E1000_RCTL);
2499 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2500 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2504 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2506 struct e1000_hw *hw =
2507 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510 rctl = E1000_READ_REG(hw, E1000_RCTL);
2511 rctl &= (~E1000_RCTL_UPE);
2512 if (dev->data->all_multicast == 1)
2513 rctl |= E1000_RCTL_MPE;
2515 rctl &= (~E1000_RCTL_MPE);
2516 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2520 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2522 struct e1000_hw *hw =
2523 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 rctl = E1000_READ_REG(hw, E1000_RCTL);
2527 rctl |= E1000_RCTL_MPE;
2528 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2534 struct e1000_hw *hw =
2535 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538 if (dev->data->promiscuous == 1)
2539 return; /* must remain in all_multicast mode */
2540 rctl = E1000_READ_REG(hw, E1000_RCTL);
2541 rctl &= (~E1000_RCTL_MPE);
2542 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2548 struct e1000_hw *hw =
2549 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550 struct e1000_vfta * shadow_vfta =
2551 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2556 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2557 E1000_VFTA_ENTRY_MASK);
2558 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2559 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2564 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2566 /* update local VFTA copy */
2567 shadow_vfta->vfta[vid_idx] = vfta;
2573 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2574 enum rte_vlan_type vlan_type,
2577 struct e1000_hw *hw =
2578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2582 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2584 /* only outer TPID of double VLAN can be configured*/
2585 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2586 reg = E1000_READ_REG(hw, E1000_VET);
2587 reg = (reg & (~E1000_VET_VET_EXT)) |
2588 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2589 E1000_WRITE_REG(hw, E1000_VET, reg);
2594 /* all other TPID values are read-only*/
2595 PMD_DRV_LOG(ERR, "Not supported");
2601 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2603 struct e1000_hw *hw =
2604 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607 /* Filter Table Disable */
2608 reg = E1000_READ_REG(hw, E1000_RCTL);
2609 reg &= ~E1000_RCTL_CFIEN;
2610 reg &= ~E1000_RCTL_VFE;
2611 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2615 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2617 struct e1000_hw *hw =
2618 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619 struct e1000_vfta * shadow_vfta =
2620 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2624 /* Filter Table Enable, CFI not used for packet acceptance */
2625 reg = E1000_READ_REG(hw, E1000_RCTL);
2626 reg &= ~E1000_RCTL_CFIEN;
2627 reg |= E1000_RCTL_VFE;
2628 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2630 /* restore VFTA table */
2631 for (i = 0; i < IGB_VFTA_SIZE; i++)
2632 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2636 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 /* VLAN Mode Disable */
2643 reg = E1000_READ_REG(hw, E1000_CTRL);
2644 reg &= ~E1000_CTRL_VME;
2645 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2649 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2651 struct e1000_hw *hw =
2652 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655 /* VLAN Mode Enable */
2656 reg = E1000_READ_REG(hw, E1000_CTRL);
2657 reg |= E1000_CTRL_VME;
2658 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2662 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2664 struct e1000_hw *hw =
2665 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 /* CTRL_EXT: Extended VLAN */
2669 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2670 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2671 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2673 /* Update maximum packet length */
2674 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2675 E1000_WRITE_REG(hw, E1000_RLPML,
2676 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2681 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2683 struct e1000_hw *hw =
2684 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687 /* CTRL_EXT: Extended VLAN */
2688 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2689 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2690 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2692 /* Update maximum packet length */
2693 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2694 E1000_WRITE_REG(hw, E1000_RLPML,
2695 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2700 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2702 struct rte_eth_rxmode *rxmode;
2704 rxmode = &dev->data->dev_conf.rxmode;
2705 if(mask & ETH_VLAN_STRIP_MASK){
2706 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2707 igb_vlan_hw_strip_enable(dev);
2709 igb_vlan_hw_strip_disable(dev);
2712 if(mask & ETH_VLAN_FILTER_MASK){
2713 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2714 igb_vlan_hw_filter_enable(dev);
2716 igb_vlan_hw_filter_disable(dev);
2719 if(mask & ETH_VLAN_EXTEND_MASK){
2720 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2721 igb_vlan_hw_extend_enable(dev);
2723 igb_vlan_hw_extend_disable(dev);
2731 * It enables the interrupt mask and then enable the interrupt.
2734 * Pointer to struct rte_eth_dev.
2739 * - On success, zero.
2740 * - On failure, a negative value.
2743 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2745 struct e1000_interrupt *intr =
2746 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2749 intr->mask |= E1000_ICR_LSC;
2751 intr->mask &= ~E1000_ICR_LSC;
2756 /* It clears the interrupt causes and enables the interrupt.
2757 * It will be called once only during nic initialized.
2760 * Pointer to struct rte_eth_dev.
2763 * - On success, zero.
2764 * - On failure, a negative value.
2766 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2768 uint32_t mask, regval;
2769 struct e1000_hw *hw =
2770 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771 struct rte_eth_dev_info dev_info;
2773 memset(&dev_info, 0, sizeof(dev_info));
2774 eth_igb_infos_get(dev, &dev_info);
2776 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2777 regval = E1000_READ_REG(hw, E1000_EIMS);
2778 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2784 * It reads ICR and gets interrupt causes, check it and set a bit flag
2785 * to update link status.
2788 * Pointer to struct rte_eth_dev.
2791 * - On success, zero.
2792 * - On failure, a negative value.
2795 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2798 struct e1000_hw *hw =
2799 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 struct e1000_interrupt *intr =
2801 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2803 igb_intr_disable(hw);
2805 /* read-on-clear nic registers here */
2806 icr = E1000_READ_REG(hw, E1000_ICR);
2809 if (icr & E1000_ICR_LSC) {
2810 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2813 if (icr & E1000_ICR_VMMB)
2814 intr->flags |= E1000_FLAG_MAILBOX;
2820 * It executes link_update after knowing an interrupt is prsent.
2823 * Pointer to struct rte_eth_dev.
2826 * - On success, zero.
2827 * - On failure, a negative value.
2830 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2831 struct rte_intr_handle *intr_handle)
2833 struct e1000_hw *hw =
2834 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835 struct e1000_interrupt *intr =
2836 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2837 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2838 struct rte_eth_link link;
2841 if (intr->flags & E1000_FLAG_MAILBOX) {
2842 igb_pf_mbx_process(dev);
2843 intr->flags &= ~E1000_FLAG_MAILBOX;
2846 igb_intr_enable(dev);
2847 rte_intr_enable(intr_handle);
2849 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2850 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2852 /* set get_link_status to check register later */
2853 hw->mac.get_link_status = 1;
2854 ret = eth_igb_link_update(dev, 0);
2856 /* check if link has changed */
2860 rte_eth_linkstatus_get(dev, &link);
2861 if (link.link_status) {
2863 " Port %d: Link Up - speed %u Mbps - %s",
2865 (unsigned)link.link_speed,
2866 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2867 "full-duplex" : "half-duplex");
2869 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2870 dev->data->port_id);
2873 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2874 pci_dev->addr.domain,
2876 pci_dev->addr.devid,
2877 pci_dev->addr.function);
2878 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2886 * Interrupt handler which shall be registered at first.
2889 * Pointer to interrupt handle.
2891 * The address of parameter (struct rte_eth_dev *) regsitered before.
2897 eth_igb_interrupt_handler(void *param)
2899 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2901 eth_igb_interrupt_get_status(dev);
2902 eth_igb_interrupt_action(dev, dev->intr_handle);
2906 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2909 struct e1000_hw *hw =
2910 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911 struct e1000_interrupt *intr =
2912 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2914 igbvf_intr_disable(hw);
2916 /* read-on-clear nic registers here */
2917 eicr = E1000_READ_REG(hw, E1000_EICR);
2920 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2921 intr->flags |= E1000_FLAG_MAILBOX;
2926 void igbvf_mbx_process(struct rte_eth_dev *dev)
2928 struct e1000_hw *hw =
2929 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930 struct e1000_mbx_info *mbx = &hw->mbx;
2933 /* peek the message first */
2934 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2936 /* PF reset VF event */
2937 if (in_msg == E1000_PF_CONTROL_MSG) {
2938 /* dummy mbx read to ack pf */
2939 if (mbx->ops.read(hw, &in_msg, 1, 0))
2941 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2947 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2949 struct e1000_interrupt *intr =
2950 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2952 if (intr->flags & E1000_FLAG_MAILBOX) {
2953 igbvf_mbx_process(dev);
2954 intr->flags &= ~E1000_FLAG_MAILBOX;
2957 igbvf_intr_enable(dev);
2958 rte_intr_enable(intr_handle);
2964 eth_igbvf_interrupt_handler(void *param)
2966 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2968 eth_igbvf_interrupt_get_status(dev);
2969 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2973 eth_igb_led_on(struct rte_eth_dev *dev)
2975 struct e1000_hw *hw;
2977 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2982 eth_igb_led_off(struct rte_eth_dev *dev)
2984 struct e1000_hw *hw;
2986 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2987 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2991 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2993 struct e1000_hw *hw;
2998 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999 fc_conf->pause_time = hw->fc.pause_time;
3000 fc_conf->high_water = hw->fc.high_water;
3001 fc_conf->low_water = hw->fc.low_water;
3002 fc_conf->send_xon = hw->fc.send_xon;
3003 fc_conf->autoneg = hw->mac.autoneg;
3006 * Return rx_pause and tx_pause status according to actual setting of
3007 * the TFCE and RFCE bits in the CTRL register.
3009 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3010 if (ctrl & E1000_CTRL_TFCE)
3015 if (ctrl & E1000_CTRL_RFCE)
3020 if (rx_pause && tx_pause)
3021 fc_conf->mode = RTE_FC_FULL;
3023 fc_conf->mode = RTE_FC_RX_PAUSE;
3025 fc_conf->mode = RTE_FC_TX_PAUSE;
3027 fc_conf->mode = RTE_FC_NONE;
3033 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3035 struct e1000_hw *hw;
3037 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3043 uint32_t rx_buf_size;
3044 uint32_t max_high_water;
3047 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048 if (fc_conf->autoneg != hw->mac.autoneg)
3050 rx_buf_size = igb_get_rx_buffer_size(hw);
3051 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3053 /* At least reserve one Ethernet frame for watermark */
3054 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3055 if ((fc_conf->high_water > max_high_water) ||
3056 (fc_conf->high_water < fc_conf->low_water)) {
3057 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3058 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3062 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3063 hw->fc.pause_time = fc_conf->pause_time;
3064 hw->fc.high_water = fc_conf->high_water;
3065 hw->fc.low_water = fc_conf->low_water;
3066 hw->fc.send_xon = fc_conf->send_xon;
3068 err = e1000_setup_link_generic(hw);
3069 if (err == E1000_SUCCESS) {
3071 /* check if we want to forward MAC frames - driver doesn't have native
3072 * capability to do that, so we'll write the registers ourselves */
3074 rctl = E1000_READ_REG(hw, E1000_RCTL);
3076 /* set or clear MFLCN.PMCF bit depending on configuration */
3077 if (fc_conf->mac_ctrl_frame_fwd != 0)
3078 rctl |= E1000_RCTL_PMCF;
3080 rctl &= ~E1000_RCTL_PMCF;
3082 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3083 E1000_WRITE_FLUSH(hw);
3088 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3092 #define E1000_RAH_POOLSEL_SHIFT (18)
3094 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3095 uint32_t index, uint32_t pool)
3097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3100 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3101 rah = E1000_READ_REG(hw, E1000_RAH(index));
3102 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3103 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3108 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3110 uint8_t addr[ETHER_ADDR_LEN];
3111 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113 memset(addr, 0, sizeof(addr));
3115 e1000_rar_set(hw, addr, index);
3119 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3120 struct ether_addr *addr)
3122 eth_igb_rar_clear(dev, 0);
3123 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3128 * Virtual Function operations
3131 igbvf_intr_disable(struct e1000_hw *hw)
3133 PMD_INIT_FUNC_TRACE();
3135 /* Clear interrupt mask to stop from interrupts being generated */
3136 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3138 E1000_WRITE_FLUSH(hw);
3142 igbvf_stop_adapter(struct rte_eth_dev *dev)
3146 struct rte_eth_dev_info dev_info;
3147 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149 memset(&dev_info, 0, sizeof(dev_info));
3150 eth_igbvf_infos_get(dev, &dev_info);
3152 /* Clear interrupt mask to stop from interrupts being generated */
3153 igbvf_intr_disable(hw);
3155 /* Clear any pending interrupts, flush previous writes */
3156 E1000_READ_REG(hw, E1000_EICR);
3158 /* Disable the transmit unit. Each queue must be disabled. */
3159 for (i = 0; i < dev_info.max_tx_queues; i++)
3160 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3162 /* Disable the receive unit by stopping each queue */
3163 for (i = 0; i < dev_info.max_rx_queues; i++) {
3164 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3165 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3166 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3167 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3171 /* flush all queues disables */
3172 E1000_WRITE_FLUSH(hw);
3176 static int eth_igbvf_link_update(struct e1000_hw *hw)
3178 struct e1000_mbx_info *mbx = &hw->mbx;
3179 struct e1000_mac_info *mac = &hw->mac;
3180 int ret_val = E1000_SUCCESS;
3182 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3185 * We only want to run this if there has been a rst asserted.
3186 * in this case that could mean a link change, device reset,
3187 * or a virtual function reset
3190 /* If we were hit with a reset or timeout drop the link */
3191 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3192 mac->get_link_status = TRUE;
3194 if (!mac->get_link_status)
3197 /* if link status is down no point in checking to see if pf is up */
3198 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3201 /* if we passed all the tests above then the link is up and we no
3202 * longer need to check for link */
3203 mac->get_link_status = FALSE;
3211 igbvf_dev_configure(struct rte_eth_dev *dev)
3213 struct rte_eth_conf* conf = &dev->data->dev_conf;
3215 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3216 dev->data->port_id);
3219 * VF has no ability to enable/disable HW CRC
3220 * Keep the persistent behavior the same as Host PF
3222 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3223 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3224 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3225 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3228 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3229 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3230 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3238 igbvf_dev_start(struct rte_eth_dev *dev)
3240 struct e1000_hw *hw =
3241 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242 struct e1000_adapter *adapter =
3243 E1000_DEV_PRIVATE(dev->data->dev_private);
3244 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3245 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3247 uint32_t intr_vector = 0;
3249 PMD_INIT_FUNC_TRACE();
3251 hw->mac.ops.reset_hw(hw);
3252 adapter->stopped = 0;
3255 igbvf_set_vfta_all(dev,1);
3257 eth_igbvf_tx_init(dev);
3259 /* This can fail when allocating mbufs for descriptor rings */
3260 ret = eth_igbvf_rx_init(dev);
3262 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3263 igb_dev_clear_queues(dev);
3267 /* check and configure queue intr-vector mapping */
3268 if (rte_intr_cap_multiple(intr_handle) &&
3269 dev->data->dev_conf.intr_conf.rxq) {
3270 intr_vector = dev->data->nb_rx_queues;
3271 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3276 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3277 intr_handle->intr_vec =
3278 rte_zmalloc("intr_vec",
3279 dev->data->nb_rx_queues * sizeof(int), 0);
3280 if (!intr_handle->intr_vec) {
3281 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3282 " intr_vec", dev->data->nb_rx_queues);
3287 eth_igbvf_configure_msix_intr(dev);
3289 /* enable uio/vfio intr/eventfd mapping */
3290 rte_intr_enable(intr_handle);
3292 /* resume enabled intr since hw reset */
3293 igbvf_intr_enable(dev);
3299 igbvf_dev_stop(struct rte_eth_dev *dev)
3301 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3302 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3304 PMD_INIT_FUNC_TRACE();
3306 igbvf_stop_adapter(dev);
3309 * Clear what we set, but we still keep shadow_vfta to
3310 * restore after device starts
3312 igbvf_set_vfta_all(dev,0);
3314 igb_dev_clear_queues(dev);
3316 /* disable intr eventfd mapping */
3317 rte_intr_disable(intr_handle);
3319 /* Clean datapath event and queue/vec mapping */
3320 rte_intr_efd_disable(intr_handle);
3321 if (intr_handle->intr_vec) {
3322 rte_free(intr_handle->intr_vec);
3323 intr_handle->intr_vec = NULL;
3328 igbvf_dev_close(struct rte_eth_dev *dev)
3330 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331 struct e1000_adapter *adapter =
3332 E1000_DEV_PRIVATE(dev->data->dev_private);
3333 struct ether_addr addr;
3335 PMD_INIT_FUNC_TRACE();
3339 igbvf_dev_stop(dev);
3340 adapter->stopped = 1;
3341 igb_dev_free_queues(dev);
3344 * reprogram the RAR with a zero mac address,
3345 * to ensure that the VF traffic goes to the PF
3346 * after stop, close and detach of the VF.
3349 memset(&addr, 0, sizeof(addr));
3350 igbvf_default_mac_addr_set(dev, &addr);
3354 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3356 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358 /* Set both unicast and multicast promisc */
3359 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3363 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3365 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367 /* If in allmulticast mode leave multicast promisc */
3368 if (dev->data->all_multicast == 1)
3369 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3371 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3375 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3377 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379 /* In promiscuous mode multicast promisc already set */
3380 if (dev->data->promiscuous == 0)
3381 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3385 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3389 /* In promiscuous mode leave multicast promisc enabled */
3390 if (dev->data->promiscuous == 0)
3391 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3394 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3396 struct e1000_mbx_info *mbx = &hw->mbx;
3400 /* After set vlan, vlan strip will also be enabled in igb driver*/
3401 msgbuf[0] = E1000_VF_SET_VLAN;
3403 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3405 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3407 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3411 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3415 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3416 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3423 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3425 struct e1000_hw *hw =
3426 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427 struct e1000_vfta * shadow_vfta =
3428 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3429 int i = 0, j = 0, vfta = 0, mask = 1;
3431 for (i = 0; i < IGB_VFTA_SIZE; i++){
3432 vfta = shadow_vfta->vfta[i];
3435 for (j = 0; j < 32; j++){
3438 (uint16_t)((i<<5)+j), on);
3447 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3449 struct e1000_hw *hw =
3450 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451 struct e1000_vfta * shadow_vfta =
3452 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3453 uint32_t vid_idx = 0;
3454 uint32_t vid_bit = 0;
3457 PMD_INIT_FUNC_TRACE();
3459 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3460 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3462 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3465 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3466 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3468 /*Save what we set and retore it after device reset*/
3470 shadow_vfta->vfta[vid_idx] |= vid_bit;
3472 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3478 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3480 struct e1000_hw *hw =
3481 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483 /* index is not used by rar_set() */
3484 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3490 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3491 struct rte_eth_rss_reta_entry64 *reta_conf,
3496 uint16_t idx, shift;
3497 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3499 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3500 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3501 "(%d) doesn't match the number hardware can supported "
3502 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3506 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3507 idx = i / RTE_RETA_GROUP_SIZE;
3508 shift = i % RTE_RETA_GROUP_SIZE;
3509 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3513 if (mask == IGB_4_BIT_MASK)
3516 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3517 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3518 if (mask & (0x1 << j))
3519 reta |= reta_conf[idx].reta[shift + j] <<
3522 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3524 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3531 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3532 struct rte_eth_rss_reta_entry64 *reta_conf,
3537 uint16_t idx, shift;
3538 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3541 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3542 "(%d) doesn't match the number hardware can supported "
3543 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3547 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3548 idx = i / RTE_RETA_GROUP_SIZE;
3549 shift = i % RTE_RETA_GROUP_SIZE;
3550 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3554 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3555 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3556 if (mask & (0x1 << j))
3557 reta_conf[idx].reta[shift + j] =
3558 ((reta >> (CHAR_BIT * j)) &
3567 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3568 struct rte_eth_syn_filter *filter,
3571 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572 struct e1000_filter_info *filter_info =
3573 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3574 uint32_t synqf, rfctl;
3576 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3579 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3582 if (synqf & E1000_SYN_FILTER_ENABLE)
3585 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3586 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3588 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3589 if (filter->hig_pri)
3590 rfctl |= E1000_RFCTL_SYNQFP;
3592 rfctl &= ~E1000_RFCTL_SYNQFP;
3594 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3596 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3601 filter_info->syn_info = synqf;
3602 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3603 E1000_WRITE_FLUSH(hw);
3608 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3609 struct rte_eth_syn_filter *filter)
3611 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612 uint32_t synqf, rfctl;
3614 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3615 if (synqf & E1000_SYN_FILTER_ENABLE) {
3616 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3617 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3618 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3619 E1000_SYN_FILTER_QUEUE_SHIFT);
3627 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3628 enum rte_filter_op filter_op,
3631 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634 MAC_TYPE_FILTER_SUP(hw->mac.type);
3636 if (filter_op == RTE_ETH_FILTER_NOP)
3640 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3645 switch (filter_op) {
3646 case RTE_ETH_FILTER_ADD:
3647 ret = eth_igb_syn_filter_set(dev,
3648 (struct rte_eth_syn_filter *)arg,
3651 case RTE_ETH_FILTER_DELETE:
3652 ret = eth_igb_syn_filter_set(dev,
3653 (struct rte_eth_syn_filter *)arg,
3656 case RTE_ETH_FILTER_GET:
3657 ret = eth_igb_syn_filter_get(dev,
3658 (struct rte_eth_syn_filter *)arg);
3661 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3669 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3671 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3672 struct e1000_2tuple_filter_info *filter_info)
3674 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3676 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3677 return -EINVAL; /* filter index is out of range. */
3678 if (filter->tcp_flags > TCP_FLAG_ALL)
3679 return -EINVAL; /* flags is invalid. */
3681 switch (filter->dst_port_mask) {
3683 filter_info->dst_port_mask = 0;
3684 filter_info->dst_port = filter->dst_port;
3687 filter_info->dst_port_mask = 1;
3690 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3694 switch (filter->proto_mask) {
3696 filter_info->proto_mask = 0;
3697 filter_info->proto = filter->proto;
3700 filter_info->proto_mask = 1;
3703 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3707 filter_info->priority = (uint8_t)filter->priority;
3708 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3709 filter_info->tcp_flags = filter->tcp_flags;
3711 filter_info->tcp_flags = 0;
3716 static inline struct e1000_2tuple_filter *
3717 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3718 struct e1000_2tuple_filter_info *key)
3720 struct e1000_2tuple_filter *it;
3722 TAILQ_FOREACH(it, filter_list, entries) {
3723 if (memcmp(key, &it->filter_info,
3724 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3731 /* inject a igb 2tuple filter to HW */
3733 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3734 struct e1000_2tuple_filter *filter)
3736 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3738 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3742 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3743 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3744 imir |= E1000_IMIR_PORT_BP;
3746 imir &= ~E1000_IMIR_PORT_BP;
3748 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3750 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3751 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3752 ttqf |= (uint32_t)(filter->filter_info.proto &
3753 E1000_TTQF_PROTOCOL_MASK);
3754 if (filter->filter_info.proto_mask == 0)
3755 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3757 /* tcp flags bits setting. */
3758 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3759 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3760 imir_ext |= E1000_IMIREXT_CTRL_URG;
3761 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3762 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3763 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3764 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3765 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3766 imir_ext |= E1000_IMIREXT_CTRL_RST;
3767 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3768 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3769 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3770 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3772 imir_ext |= E1000_IMIREXT_CTRL_BP;
3774 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3775 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3776 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3780 * igb_add_2tuple_filter - add a 2tuple filter
3783 * dev: Pointer to struct rte_eth_dev.
3784 * ntuple_filter: ponter to the filter that will be added.
3787 * - On success, zero.
3788 * - On failure, a negative value.
3791 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3792 struct rte_eth_ntuple_filter *ntuple_filter)
3794 struct e1000_filter_info *filter_info =
3795 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3796 struct e1000_2tuple_filter *filter;
3799 filter = rte_zmalloc("e1000_2tuple_filter",
3800 sizeof(struct e1000_2tuple_filter), 0);
3804 ret = ntuple_filter_to_2tuple(ntuple_filter,
3805 &filter->filter_info);
3810 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3811 &filter->filter_info) != NULL) {
3812 PMD_DRV_LOG(ERR, "filter exists.");
3816 filter->queue = ntuple_filter->queue;
3819 * look for an unused 2tuple filter index,
3820 * and insert the filter to list.
3822 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3823 if (!(filter_info->twotuple_mask & (1 << i))) {
3824 filter_info->twotuple_mask |= 1 << i;
3826 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3832 if (i >= E1000_MAX_TTQF_FILTERS) {
3833 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3838 igb_inject_2uple_filter(dev, filter);
3843 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3844 struct e1000_2tuple_filter *filter)
3846 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847 struct e1000_filter_info *filter_info =
3848 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3850 filter_info->twotuple_mask &= ~(1 << filter->index);
3851 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3854 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3855 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3856 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3861 * igb_remove_2tuple_filter - remove a 2tuple filter
3864 * dev: Pointer to struct rte_eth_dev.
3865 * ntuple_filter: ponter to the filter that will be removed.
3868 * - On success, zero.
3869 * - On failure, a negative value.
3872 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3873 struct rte_eth_ntuple_filter *ntuple_filter)
3875 struct e1000_filter_info *filter_info =
3876 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3877 struct e1000_2tuple_filter_info filter_2tuple;
3878 struct e1000_2tuple_filter *filter;
3881 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3882 ret = ntuple_filter_to_2tuple(ntuple_filter,
3887 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3889 if (filter == NULL) {
3890 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3894 igb_delete_2tuple_filter(dev, filter);
3899 /* inject a igb flex filter to HW */
3901 igb_inject_flex_filter(struct rte_eth_dev *dev,
3902 struct e1000_flex_filter *filter)
3904 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905 uint32_t wufc, queueing;
3909 wufc = E1000_READ_REG(hw, E1000_WUFC);
3910 if (filter->index < E1000_MAX_FHFT)
3911 reg_off = E1000_FHFT(filter->index);
3913 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3915 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3916 (E1000_WUFC_FLX0 << filter->index));
3917 queueing = filter->filter_info.len |
3918 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3919 (filter->filter_info.priority <<
3920 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3921 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3924 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3925 E1000_WRITE_REG(hw, reg_off,
3926 filter->filter_info.dwords[j]);
3927 reg_off += sizeof(uint32_t);
3928 E1000_WRITE_REG(hw, reg_off,
3929 filter->filter_info.dwords[++j]);
3930 reg_off += sizeof(uint32_t);
3931 E1000_WRITE_REG(hw, reg_off,
3932 (uint32_t)filter->filter_info.mask[i]);
3933 reg_off += sizeof(uint32_t) * 2;
3938 static inline struct e1000_flex_filter *
3939 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3940 struct e1000_flex_filter_info *key)
3942 struct e1000_flex_filter *it;
3944 TAILQ_FOREACH(it, filter_list, entries) {
3945 if (memcmp(key, &it->filter_info,
3946 sizeof(struct e1000_flex_filter_info)) == 0)
3953 /* remove a flex byte filter
3955 * dev: Pointer to struct rte_eth_dev.
3956 * filter: the pointer of the filter will be removed.
3959 igb_remove_flex_filter(struct rte_eth_dev *dev,
3960 struct e1000_flex_filter *filter)
3962 struct e1000_filter_info *filter_info =
3963 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3964 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3968 wufc = E1000_READ_REG(hw, E1000_WUFC);
3969 if (filter->index < E1000_MAX_FHFT)
3970 reg_off = E1000_FHFT(filter->index);
3972 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3974 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3975 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3977 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3978 (~(E1000_WUFC_FLX0 << filter->index)));
3980 filter_info->flex_mask &= ~(1 << filter->index);
3981 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3986 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3987 struct rte_eth_flex_filter *filter,
3990 struct e1000_filter_info *filter_info =
3991 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3992 struct e1000_flex_filter *flex_filter, *it;
3996 flex_filter = rte_zmalloc("e1000_flex_filter",
3997 sizeof(struct e1000_flex_filter), 0);
3998 if (flex_filter == NULL)
4001 flex_filter->filter_info.len = filter->len;
4002 flex_filter->filter_info.priority = filter->priority;
4003 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4004 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4006 /* reverse bits in flex filter's mask*/
4007 for (shift = 0; shift < CHAR_BIT; shift++) {
4008 if (filter->mask[i] & (0x01 << shift))
4009 mask |= (0x80 >> shift);
4011 flex_filter->filter_info.mask[i] = mask;
4014 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4015 &flex_filter->filter_info);
4016 if (it == NULL && !add) {
4017 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4018 rte_free(flex_filter);
4021 if (it != NULL && add) {
4022 PMD_DRV_LOG(ERR, "filter exists.");
4023 rte_free(flex_filter);
4028 flex_filter->queue = filter->queue;
4030 * look for an unused flex filter index
4031 * and insert the filter into the list.
4033 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4034 if (!(filter_info->flex_mask & (1 << i))) {
4035 filter_info->flex_mask |= 1 << i;
4036 flex_filter->index = i;
4037 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4043 if (i >= E1000_MAX_FLEX_FILTERS) {
4044 PMD_DRV_LOG(ERR, "flex filters are full.");
4045 rte_free(flex_filter);
4049 igb_inject_flex_filter(dev, flex_filter);
4052 igb_remove_flex_filter(dev, it);
4053 rte_free(flex_filter);
4060 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4061 struct rte_eth_flex_filter *filter)
4063 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064 struct e1000_filter_info *filter_info =
4065 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4066 struct e1000_flex_filter flex_filter, *it;
4067 uint32_t wufc, queueing, wufc_en = 0;
4069 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4070 flex_filter.filter_info.len = filter->len;
4071 flex_filter.filter_info.priority = filter->priority;
4072 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4073 memcpy(flex_filter.filter_info.mask, filter->mask,
4074 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4076 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4077 &flex_filter.filter_info);
4079 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4083 wufc = E1000_READ_REG(hw, E1000_WUFC);
4084 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4086 if ((wufc & wufc_en) == wufc_en) {
4087 uint32_t reg_off = 0;
4088 if (it->index < E1000_MAX_FHFT)
4089 reg_off = E1000_FHFT(it->index);
4091 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4093 queueing = E1000_READ_REG(hw,
4094 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4095 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4096 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4097 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4098 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4099 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4106 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4107 enum rte_filter_op filter_op,
4110 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4111 struct rte_eth_flex_filter *filter;
4114 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4116 if (filter_op == RTE_ETH_FILTER_NOP)
4120 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4125 filter = (struct rte_eth_flex_filter *)arg;
4126 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4127 || filter->len % sizeof(uint64_t) != 0) {
4128 PMD_DRV_LOG(ERR, "filter's length is out of range");
4131 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4132 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4136 switch (filter_op) {
4137 case RTE_ETH_FILTER_ADD:
4138 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4140 case RTE_ETH_FILTER_DELETE:
4141 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4143 case RTE_ETH_FILTER_GET:
4144 ret = eth_igb_get_flex_filter(dev, filter);
4147 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4155 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4157 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4158 struct e1000_5tuple_filter_info *filter_info)
4160 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4162 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4163 return -EINVAL; /* filter index is out of range. */
4164 if (filter->tcp_flags > TCP_FLAG_ALL)
4165 return -EINVAL; /* flags is invalid. */
4167 switch (filter->dst_ip_mask) {
4169 filter_info->dst_ip_mask = 0;
4170 filter_info->dst_ip = filter->dst_ip;
4173 filter_info->dst_ip_mask = 1;
4176 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4180 switch (filter->src_ip_mask) {
4182 filter_info->src_ip_mask = 0;
4183 filter_info->src_ip = filter->src_ip;
4186 filter_info->src_ip_mask = 1;
4189 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4193 switch (filter->dst_port_mask) {
4195 filter_info->dst_port_mask = 0;
4196 filter_info->dst_port = filter->dst_port;
4199 filter_info->dst_port_mask = 1;
4202 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4206 switch (filter->src_port_mask) {
4208 filter_info->src_port_mask = 0;
4209 filter_info->src_port = filter->src_port;
4212 filter_info->src_port_mask = 1;
4215 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4219 switch (filter->proto_mask) {
4221 filter_info->proto_mask = 0;
4222 filter_info->proto = filter->proto;
4225 filter_info->proto_mask = 1;
4228 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4232 filter_info->priority = (uint8_t)filter->priority;
4233 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4234 filter_info->tcp_flags = filter->tcp_flags;
4236 filter_info->tcp_flags = 0;
4241 static inline struct e1000_5tuple_filter *
4242 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4243 struct e1000_5tuple_filter_info *key)
4245 struct e1000_5tuple_filter *it;
4247 TAILQ_FOREACH(it, filter_list, entries) {
4248 if (memcmp(key, &it->filter_info,
4249 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4256 /* inject a igb 5-tuple filter to HW */
4258 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4259 struct e1000_5tuple_filter *filter)
4261 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4263 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4267 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4268 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4269 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4270 if (filter->filter_info.dst_ip_mask == 0)
4271 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4272 if (filter->filter_info.src_port_mask == 0)
4273 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4274 if (filter->filter_info.proto_mask == 0)
4275 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4276 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4277 E1000_FTQF_QUEUE_MASK;
4278 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4279 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4280 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4281 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4283 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4284 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4286 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4287 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4288 imir |= E1000_IMIR_PORT_BP;
4290 imir &= ~E1000_IMIR_PORT_BP;
4291 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4293 /* tcp flags bits setting. */
4294 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4295 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4296 imir_ext |= E1000_IMIREXT_CTRL_URG;
4297 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4298 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4299 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4300 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4301 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4302 imir_ext |= E1000_IMIREXT_CTRL_RST;
4303 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4304 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4305 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4306 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4308 imir_ext |= E1000_IMIREXT_CTRL_BP;
4310 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4311 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4315 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4318 * dev: Pointer to struct rte_eth_dev.
4319 * ntuple_filter: ponter to the filter that will be added.
4322 * - On success, zero.
4323 * - On failure, a negative value.
4326 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4327 struct rte_eth_ntuple_filter *ntuple_filter)
4329 struct e1000_filter_info *filter_info =
4330 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4331 struct e1000_5tuple_filter *filter;
4335 filter = rte_zmalloc("e1000_5tuple_filter",
4336 sizeof(struct e1000_5tuple_filter), 0);
4340 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4341 &filter->filter_info);
4347 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4348 &filter->filter_info) != NULL) {
4349 PMD_DRV_LOG(ERR, "filter exists.");
4353 filter->queue = ntuple_filter->queue;
4356 * look for an unused 5tuple filter index,
4357 * and insert the filter to list.
4359 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4360 if (!(filter_info->fivetuple_mask & (1 << i))) {
4361 filter_info->fivetuple_mask |= 1 << i;
4363 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4369 if (i >= E1000_MAX_FTQF_FILTERS) {
4370 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4375 igb_inject_5tuple_filter_82576(dev, filter);
4380 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4381 struct e1000_5tuple_filter *filter)
4383 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384 struct e1000_filter_info *filter_info =
4385 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4387 filter_info->fivetuple_mask &= ~(1 << filter->index);
4388 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4391 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4392 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4393 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4394 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4395 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4396 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4397 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4402 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4405 * dev: Pointer to struct rte_eth_dev.
4406 * ntuple_filter: ponter to the filter that will be removed.
4409 * - On success, zero.
4410 * - On failure, a negative value.
4413 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4414 struct rte_eth_ntuple_filter *ntuple_filter)
4416 struct e1000_filter_info *filter_info =
4417 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4418 struct e1000_5tuple_filter_info filter_5tuple;
4419 struct e1000_5tuple_filter *filter;
4422 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4423 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4428 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4430 if (filter == NULL) {
4431 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4435 igb_delete_5tuple_filter_82576(dev, filter);
4441 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4444 struct e1000_hw *hw;
4445 struct rte_eth_dev_info dev_info;
4446 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4449 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451 #ifdef RTE_LIBRTE_82571_SUPPORT
4452 /* XXX: not bigger than max_rx_pktlen */
4453 if (hw->mac.type == e1000_82571)
4456 eth_igb_infos_get(dev, &dev_info);
4458 /* check that mtu is within the allowed range */
4459 if ((mtu < ETHER_MIN_MTU) ||
4460 (frame_size > dev_info.max_rx_pktlen))
4463 /* refuse mtu that requires the support of scattered packets when this
4464 * feature has not been enabled before. */
4465 if (!dev->data->scattered_rx &&
4466 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4469 rctl = E1000_READ_REG(hw, E1000_RCTL);
4471 /* switch to jumbo mode if needed */
4472 if (frame_size > ETHER_MAX_LEN) {
4473 dev->data->dev_conf.rxmode.offloads |=
4474 DEV_RX_OFFLOAD_JUMBO_FRAME;
4475 rctl |= E1000_RCTL_LPE;
4477 dev->data->dev_conf.rxmode.offloads &=
4478 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4479 rctl &= ~E1000_RCTL_LPE;
4481 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4483 /* update max frame size */
4484 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4486 E1000_WRITE_REG(hw, E1000_RLPML,
4487 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4493 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4496 * dev: Pointer to struct rte_eth_dev.
4497 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4498 * add: if true, add filter, if false, remove filter
4501 * - On success, zero.
4502 * - On failure, a negative value.
4505 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4506 struct rte_eth_ntuple_filter *ntuple_filter,
4509 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512 switch (ntuple_filter->flags) {
4513 case RTE_5TUPLE_FLAGS:
4514 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4515 if (hw->mac.type != e1000_82576)
4518 ret = igb_add_5tuple_filter_82576(dev,
4521 ret = igb_remove_5tuple_filter_82576(dev,
4524 case RTE_2TUPLE_FLAGS:
4525 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4526 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4527 hw->mac.type != e1000_i210 &&
4528 hw->mac.type != e1000_i211)
4531 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4533 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4544 * igb_get_ntuple_filter - get a ntuple filter
4547 * dev: Pointer to struct rte_eth_dev.
4548 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4551 * - On success, zero.
4552 * - On failure, a negative value.
4555 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4556 struct rte_eth_ntuple_filter *ntuple_filter)
4558 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559 struct e1000_filter_info *filter_info =
4560 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4561 struct e1000_5tuple_filter_info filter_5tuple;
4562 struct e1000_2tuple_filter_info filter_2tuple;
4563 struct e1000_5tuple_filter *p_5tuple_filter;
4564 struct e1000_2tuple_filter *p_2tuple_filter;
4567 switch (ntuple_filter->flags) {
4568 case RTE_5TUPLE_FLAGS:
4569 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4570 if (hw->mac.type != e1000_82576)
4572 memset(&filter_5tuple,
4574 sizeof(struct e1000_5tuple_filter_info));
4575 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4579 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4580 &filter_info->fivetuple_list,
4582 if (p_5tuple_filter == NULL) {
4583 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4586 ntuple_filter->queue = p_5tuple_filter->queue;
4588 case RTE_2TUPLE_FLAGS:
4589 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4590 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4592 memset(&filter_2tuple,
4594 sizeof(struct e1000_2tuple_filter_info));
4595 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4598 p_2tuple_filter = igb_2tuple_filter_lookup(
4599 &filter_info->twotuple_list,
4601 if (p_2tuple_filter == NULL) {
4602 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4605 ntuple_filter->queue = p_2tuple_filter->queue;
4616 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4617 * @dev: pointer to rte_eth_dev structure
4618 * @filter_op:operation will be taken.
4619 * @arg: a pointer to specific structure corresponding to the filter_op
4622 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4623 enum rte_filter_op filter_op,
4626 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629 MAC_TYPE_FILTER_SUP(hw->mac.type);
4631 if (filter_op == RTE_ETH_FILTER_NOP)
4635 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4640 switch (filter_op) {
4641 case RTE_ETH_FILTER_ADD:
4642 ret = igb_add_del_ntuple_filter(dev,
4643 (struct rte_eth_ntuple_filter *)arg,
4646 case RTE_ETH_FILTER_DELETE:
4647 ret = igb_add_del_ntuple_filter(dev,
4648 (struct rte_eth_ntuple_filter *)arg,
4651 case RTE_ETH_FILTER_GET:
4652 ret = igb_get_ntuple_filter(dev,
4653 (struct rte_eth_ntuple_filter *)arg);
4656 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4664 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4669 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4670 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4671 (filter_info->ethertype_mask & (1 << i)))
4678 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4679 uint16_t ethertype, uint32_t etqf)
4683 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4684 if (!(filter_info->ethertype_mask & (1 << i))) {
4685 filter_info->ethertype_mask |= 1 << i;
4686 filter_info->ethertype_filters[i].ethertype = ethertype;
4687 filter_info->ethertype_filters[i].etqf = etqf;
4695 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4698 if (idx >= E1000_MAX_ETQF_FILTERS)
4700 filter_info->ethertype_mask &= ~(1 << idx);
4701 filter_info->ethertype_filters[idx].ethertype = 0;
4702 filter_info->ethertype_filters[idx].etqf = 0;
4708 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4709 struct rte_eth_ethertype_filter *filter,
4712 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713 struct e1000_filter_info *filter_info =
4714 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4718 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4719 filter->ether_type == ETHER_TYPE_IPv6) {
4720 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4721 " ethertype filter.", filter->ether_type);
4725 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4726 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4729 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4730 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4734 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4735 if (ret >= 0 && add) {
4736 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4737 filter->ether_type);
4740 if (ret < 0 && !add) {
4741 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4742 filter->ether_type);
4747 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4748 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4749 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4750 ret = igb_ethertype_filter_insert(filter_info,
4751 filter->ether_type, etqf);
4753 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4757 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4761 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4762 E1000_WRITE_FLUSH(hw);
4768 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4769 struct rte_eth_ethertype_filter *filter)
4771 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4772 struct e1000_filter_info *filter_info =
4773 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4777 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4779 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4780 filter->ether_type);
4784 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4785 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4786 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4788 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4789 E1000_ETQF_QUEUE_SHIFT;
4797 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4798 * @dev: pointer to rte_eth_dev structure
4799 * @filter_op:operation will be taken.
4800 * @arg: a pointer to specific structure corresponding to the filter_op
4803 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4804 enum rte_filter_op filter_op,
4807 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4810 MAC_TYPE_FILTER_SUP(hw->mac.type);
4812 if (filter_op == RTE_ETH_FILTER_NOP)
4816 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4821 switch (filter_op) {
4822 case RTE_ETH_FILTER_ADD:
4823 ret = igb_add_del_ethertype_filter(dev,
4824 (struct rte_eth_ethertype_filter *)arg,
4827 case RTE_ETH_FILTER_DELETE:
4828 ret = igb_add_del_ethertype_filter(dev,
4829 (struct rte_eth_ethertype_filter *)arg,
4832 case RTE_ETH_FILTER_GET:
4833 ret = igb_get_ethertype_filter(dev,
4834 (struct rte_eth_ethertype_filter *)arg);
4837 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4845 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4846 enum rte_filter_type filter_type,
4847 enum rte_filter_op filter_op,
4852 switch (filter_type) {
4853 case RTE_ETH_FILTER_NTUPLE:
4854 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4856 case RTE_ETH_FILTER_ETHERTYPE:
4857 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4859 case RTE_ETH_FILTER_SYN:
4860 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4862 case RTE_ETH_FILTER_FLEXIBLE:
4863 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4865 case RTE_ETH_FILTER_GENERIC:
4866 if (filter_op != RTE_ETH_FILTER_GET)
4868 *(const void **)arg = &igb_flow_ops;
4871 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4880 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4881 struct ether_addr *mc_addr_set,
4882 uint32_t nb_mc_addr)
4884 struct e1000_hw *hw;
4886 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4887 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4892 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4894 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895 uint64_t systime_cycles;
4897 switch (hw->mac.type) {
4901 * Need to read System Time Residue Register to be able
4902 * to read the other two registers.
4904 E1000_READ_REG(hw, E1000_SYSTIMR);
4905 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4906 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4907 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4914 * Need to read System Time Residue Register to be able
4915 * to read the other two registers.
4917 E1000_READ_REG(hw, E1000_SYSTIMR);
4918 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4919 /* Only the 8 LSB are valid. */
4920 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4924 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4925 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4930 return systime_cycles;
4934 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4936 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937 uint64_t rx_tstamp_cycles;
4939 switch (hw->mac.type) {
4942 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4943 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4944 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4950 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4951 /* Only the 8 LSB are valid. */
4952 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4956 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4957 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4962 return rx_tstamp_cycles;
4966 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969 uint64_t tx_tstamp_cycles;
4971 switch (hw->mac.type) {
4974 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4975 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4976 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4982 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4983 /* Only the 8 LSB are valid. */
4984 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4988 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4989 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4994 return tx_tstamp_cycles;
4998 igb_start_timecounters(struct rte_eth_dev *dev)
5000 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001 struct e1000_adapter *adapter =
5002 (struct e1000_adapter *)dev->data->dev_private;
5003 uint32_t incval = 1;
5005 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5007 switch (hw->mac.type) {
5011 /* 32 LSB bits + 8 MSB bits = 40 bits */
5012 mask = (1ULL << 40) - 1;
5017 * Start incrementing the register
5018 * used to timestamp PTP packets.
5020 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5023 incval = E1000_INCVALUE_82576;
5024 shift = IGB_82576_TSYNC_SHIFT;
5025 E1000_WRITE_REG(hw, E1000_TIMINCA,
5026 E1000_INCPERIOD_82576 | incval);
5033 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5034 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5035 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5037 adapter->systime_tc.cc_mask = mask;
5038 adapter->systime_tc.cc_shift = shift;
5039 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5041 adapter->rx_tstamp_tc.cc_mask = mask;
5042 adapter->rx_tstamp_tc.cc_shift = shift;
5043 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5045 adapter->tx_tstamp_tc.cc_mask = mask;
5046 adapter->tx_tstamp_tc.cc_shift = shift;
5047 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5051 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5053 struct e1000_adapter *adapter =
5054 (struct e1000_adapter *)dev->data->dev_private;
5056 adapter->systime_tc.nsec += delta;
5057 adapter->rx_tstamp_tc.nsec += delta;
5058 adapter->tx_tstamp_tc.nsec += delta;
5064 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5067 struct e1000_adapter *adapter =
5068 (struct e1000_adapter *)dev->data->dev_private;
5070 ns = rte_timespec_to_ns(ts);
5072 /* Set the timecounters to a new value. */
5073 adapter->systime_tc.nsec = ns;
5074 adapter->rx_tstamp_tc.nsec = ns;
5075 adapter->tx_tstamp_tc.nsec = ns;
5081 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5083 uint64_t ns, systime_cycles;
5084 struct e1000_adapter *adapter =
5085 (struct e1000_adapter *)dev->data->dev_private;
5087 systime_cycles = igb_read_systime_cyclecounter(dev);
5088 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5089 *ts = rte_ns_to_timespec(ns);
5095 igb_timesync_enable(struct rte_eth_dev *dev)
5097 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5101 /* Stop the timesync system time. */
5102 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5103 /* Reset the timesync system time value. */
5104 switch (hw->mac.type) {
5110 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5113 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5114 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5117 /* Not supported. */
5121 /* Enable system time for it isn't on by default. */
5122 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5123 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5124 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5126 igb_start_timecounters(dev);
5128 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5129 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5131 E1000_ETQF_FILTER_ENABLE |
5134 /* Enable timestamping of received PTP packets. */
5135 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5136 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5137 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5139 /* Enable Timestamping of transmitted PTP packets. */
5140 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5141 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5142 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5148 igb_timesync_disable(struct rte_eth_dev *dev)
5150 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153 /* Disable timestamping of transmitted PTP packets. */
5154 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5155 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5156 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5158 /* Disable timestamping of received PTP packets. */
5159 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5160 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5161 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5163 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5164 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5166 /* Stop incrementating the System Time registers. */
5167 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5173 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5174 struct timespec *timestamp,
5175 uint32_t flags __rte_unused)
5177 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5178 struct e1000_adapter *adapter =
5179 (struct e1000_adapter *)dev->data->dev_private;
5180 uint32_t tsync_rxctl;
5181 uint64_t rx_tstamp_cycles;
5184 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5185 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5188 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5189 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5190 *timestamp = rte_ns_to_timespec(ns);
5196 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5197 struct timespec *timestamp)
5199 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200 struct e1000_adapter *adapter =
5201 (struct e1000_adapter *)dev->data->dev_private;
5202 uint32_t tsync_txctl;
5203 uint64_t tx_tstamp_cycles;
5206 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5207 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5210 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5211 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5212 *timestamp = rte_ns_to_timespec(ns);
5218 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5222 const struct reg_info *reg_group;
5224 while ((reg_group = igb_regs[g_ind++]))
5225 count += igb_reg_group_count(reg_group);
5231 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5235 const struct reg_info *reg_group;
5237 while ((reg_group = igbvf_regs[g_ind++]))
5238 count += igb_reg_group_count(reg_group);
5244 eth_igb_get_regs(struct rte_eth_dev *dev,
5245 struct rte_dev_reg_info *regs)
5247 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248 uint32_t *data = regs->data;
5251 const struct reg_info *reg_group;
5254 regs->length = eth_igb_get_reg_length(dev);
5255 regs->width = sizeof(uint32_t);
5259 /* Support only full register dump */
5260 if ((regs->length == 0) ||
5261 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5262 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5264 while ((reg_group = igb_regs[g_ind++]))
5265 count += igb_read_regs_group(dev, &data[count],
5274 igbvf_get_regs(struct rte_eth_dev *dev,
5275 struct rte_dev_reg_info *regs)
5277 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5278 uint32_t *data = regs->data;
5281 const struct reg_info *reg_group;
5284 regs->length = igbvf_get_reg_length(dev);
5285 regs->width = sizeof(uint32_t);
5289 /* Support only full register dump */
5290 if ((regs->length == 0) ||
5291 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5292 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5294 while ((reg_group = igbvf_regs[g_ind++]))
5295 count += igb_read_regs_group(dev, &data[count],
5304 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5306 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5308 /* Return unit is byte count */
5309 return hw->nvm.word_size * 2;
5313 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5314 struct rte_dev_eeprom_info *in_eeprom)
5316 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5317 struct e1000_nvm_info *nvm = &hw->nvm;
5318 uint16_t *data = in_eeprom->data;
5321 first = in_eeprom->offset >> 1;
5322 length = in_eeprom->length >> 1;
5323 if ((first >= hw->nvm.word_size) ||
5324 ((first + length) >= hw->nvm.word_size))
5327 in_eeprom->magic = hw->vendor_id |
5328 ((uint32_t)hw->device_id << 16);
5330 if ((nvm->ops.read) == NULL)
5333 return nvm->ops.read(hw, first, length, data);
5337 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5338 struct rte_dev_eeprom_info *in_eeprom)
5340 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341 struct e1000_nvm_info *nvm = &hw->nvm;
5342 uint16_t *data = in_eeprom->data;
5345 first = in_eeprom->offset >> 1;
5346 length = in_eeprom->length >> 1;
5347 if ((first >= hw->nvm.word_size) ||
5348 ((first + length) >= hw->nvm.word_size))
5351 in_eeprom->magic = (uint32_t)hw->vendor_id |
5352 ((uint32_t)hw->device_id << 16);
5354 if ((nvm->ops.write) == NULL)
5356 return nvm->ops.write(hw, first, length, data);
5360 eth_igb_get_module_info(struct rte_eth_dev *dev,
5361 struct rte_eth_dev_module_info *modinfo)
5363 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5365 uint32_t status = 0;
5366 uint16_t sff8472_rev, addr_mode;
5367 bool page_swap = false;
5369 if (hw->phy.media_type == e1000_media_type_copper ||
5370 hw->phy.media_type == e1000_media_type_unknown)
5373 /* Check whether we support SFF-8472 or not */
5374 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5378 /* addressing mode is not supported */
5379 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5383 /* addressing mode is not supported */
5384 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5386 "Address change required to access page 0xA2, "
5387 "but not supported. Please report the module "
5388 "type to the driver maintainers.\n");
5392 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5393 /* We have an SFP, but it does not support SFF-8472 */
5394 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5395 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5397 /* We have an SFP which supports a revision of SFF-8472 */
5398 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5399 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5406 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5407 struct rte_dev_eeprom_info *info)
5409 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411 uint32_t status = 0;
5412 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5413 u16 first_word, last_word;
5416 if (info->length == 0)
5419 first_word = info->offset >> 1;
5420 last_word = (info->offset + info->length - 1) >> 1;
5422 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5423 for (i = 0; i < last_word - first_word + 1; i++) {
5424 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5427 /* Error occurred while reading module */
5431 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5434 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5440 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5442 struct e1000_hw *hw =
5443 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5444 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5445 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5446 uint32_t vec = E1000_MISC_VEC_ID;
5448 if (rte_intr_allow_others(intr_handle))
5449 vec = E1000_RX_VEC_START;
5451 uint32_t mask = 1 << (queue_id + vec);
5453 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5454 E1000_WRITE_FLUSH(hw);
5460 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5462 struct e1000_hw *hw =
5463 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5464 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5465 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5466 uint32_t vec = E1000_MISC_VEC_ID;
5468 if (rte_intr_allow_others(intr_handle))
5469 vec = E1000_RX_VEC_START;
5471 uint32_t mask = 1 << (queue_id + vec);
5474 regval = E1000_READ_REG(hw, E1000_EIMS);
5475 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5476 E1000_WRITE_FLUSH(hw);
5478 rte_intr_enable(intr_handle);
5484 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5485 uint8_t index, uint8_t offset)
5487 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5490 val &= ~((uint32_t)0xFF << offset);
5492 /* write vector and valid bit */
5493 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5495 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5499 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5500 uint8_t queue, uint8_t msix_vector)
5504 if (hw->mac.type == e1000_82575) {
5506 tmp = E1000_EICR_RX_QUEUE0 << queue;
5507 else if (direction == 1)
5508 tmp = E1000_EICR_TX_QUEUE0 << queue;
5509 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5510 } else if (hw->mac.type == e1000_82576) {
5511 if ((direction == 0) || (direction == 1))
5512 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5513 ((queue & 0x8) << 1) +
5515 } else if ((hw->mac.type == e1000_82580) ||
5516 (hw->mac.type == e1000_i350) ||
5517 (hw->mac.type == e1000_i354) ||
5518 (hw->mac.type == e1000_i210) ||
5519 (hw->mac.type == e1000_i211)) {
5520 if ((direction == 0) || (direction == 1))
5521 eth_igb_write_ivar(hw, msix_vector,
5523 ((queue & 0x1) << 4) +
5528 /* Sets up the hardware to generate MSI-X interrupts properly
5530 * board private structure
5533 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5536 uint32_t tmpval, regval, intr_mask;
5537 struct e1000_hw *hw =
5538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5539 uint32_t vec = E1000_MISC_VEC_ID;
5540 uint32_t base = E1000_MISC_VEC_ID;
5541 uint32_t misc_shift = 0;
5542 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5543 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5545 /* won't configure msix register if no mapping is done
5546 * between intr vector and event fd
5548 if (!rte_intr_dp_is_en(intr_handle))
5551 if (rte_intr_allow_others(intr_handle)) {
5552 vec = base = E1000_RX_VEC_START;
5556 /* set interrupt vector for other causes */
5557 if (hw->mac.type == e1000_82575) {
5558 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5559 /* enable MSI-X PBA support */
5560 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5562 /* Auto-Mask interrupts upon ICR read */
5563 tmpval |= E1000_CTRL_EXT_EIAME;
5564 tmpval |= E1000_CTRL_EXT_IRCA;
5566 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5568 /* enable msix_other interrupt */
5569 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5570 regval = E1000_READ_REG(hw, E1000_EIAC);
5571 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5572 regval = E1000_READ_REG(hw, E1000_EIAM);
5573 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5574 } else if ((hw->mac.type == e1000_82576) ||
5575 (hw->mac.type == e1000_82580) ||
5576 (hw->mac.type == e1000_i350) ||
5577 (hw->mac.type == e1000_i354) ||
5578 (hw->mac.type == e1000_i210) ||
5579 (hw->mac.type == e1000_i211)) {
5580 /* turn on MSI-X capability first */
5581 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5582 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5584 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5586 regval = E1000_READ_REG(hw, E1000_EIAC);
5587 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5589 /* enable msix_other interrupt */
5590 regval = E1000_READ_REG(hw, E1000_EIMS);
5591 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5592 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5593 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5596 /* use EIAM to auto-mask when MSI-X interrupt
5597 * is asserted, this saves a register write for every interrupt
5599 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5601 regval = E1000_READ_REG(hw, E1000_EIAM);
5602 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5604 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5605 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5606 intr_handle->intr_vec[queue_id] = vec;
5607 if (vec < base + intr_handle->nb_efd - 1)
5611 E1000_WRITE_FLUSH(hw);
5614 /* restore n-tuple filter */
5616 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5618 struct e1000_filter_info *filter_info =
5619 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5620 struct e1000_5tuple_filter *p_5tuple;
5621 struct e1000_2tuple_filter *p_2tuple;
5623 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5624 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5627 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5628 igb_inject_2uple_filter(dev, p_2tuple);
5632 /* restore SYN filter */
5634 igb_syn_filter_restore(struct rte_eth_dev *dev)
5636 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5637 struct e1000_filter_info *filter_info =
5638 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5641 synqf = filter_info->syn_info;
5643 if (synqf & E1000_SYN_FILTER_ENABLE) {
5644 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5645 E1000_WRITE_FLUSH(hw);
5649 /* restore ethernet type filter */
5651 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5653 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5654 struct e1000_filter_info *filter_info =
5655 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5658 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5659 if (filter_info->ethertype_mask & (1 << i)) {
5660 E1000_WRITE_REG(hw, E1000_ETQF(i),
5661 filter_info->ethertype_filters[i].etqf);
5662 E1000_WRITE_FLUSH(hw);
5667 /* restore flex byte filter */
5669 igb_flex_filter_restore(struct rte_eth_dev *dev)
5671 struct e1000_filter_info *filter_info =
5672 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5673 struct e1000_flex_filter *flex_filter;
5675 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5676 igb_inject_flex_filter(dev, flex_filter);
5680 /* restore rss filter */
5682 igb_rss_filter_restore(struct rte_eth_dev *dev)
5684 struct e1000_filter_info *filter_info =
5685 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5687 if (filter_info->rss_info.conf.queue_num)
5688 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5691 /* restore all types filter */
5693 igb_filter_restore(struct rte_eth_dev *dev)
5695 igb_ntuple_filter_restore(dev);
5696 igb_ethertype_filter_restore(dev);
5697 igb_syn_filter_restore(dev);
5698 igb_flex_filter_restore(dev);
5699 igb_rss_filter_restore(dev);
5704 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5705 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5706 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5707 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5708 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5709 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5711 /* see e1000_logs.c */
5712 RTE_INIT(e1000_init_log)
5714 e1000_igb_init_log();