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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "base/e1000_defines.h"
53 #include "base/e1000_regs.h"
54 #include "base/e1000_hw.h"
55 #include "e1000_ethdev.h"
57 static inline uint16_t
58 dev_num_vf(struct rte_eth_dev *eth_dev)
60 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
62 return pci_dev->max_vfs;
66 int igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
68 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
69 struct e1000_vf_info *vfinfo =
70 *E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
73 for (vfn = 0; vfn < vf_num; vfn++) {
74 eth_random_addr(vf_mac_addr);
75 /* keep the random address as default */
76 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
84 igb_mb_intr_setup(struct rte_eth_dev *dev)
86 struct e1000_interrupt *intr =
87 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
89 intr->mask |= E1000_ICR_VMMB;
94 void igb_pf_host_init(struct rte_eth_dev *eth_dev)
96 struct e1000_vf_info **vfinfo =
97 E1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
99 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
103 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
104 if (0 == (vf_num = dev_num_vf(eth_dev)))
107 if (hw->mac.type == e1000_i350)
109 else if(hw->mac.type == e1000_82576)
110 /* per datasheet, it should be 2, but 1 seems correct */
115 *vfinfo = rte_zmalloc("vf_info", sizeof(struct e1000_vf_info) * vf_num, 0);
117 rte_panic("Cannot allocate memory for private VF data\n");
119 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS;
120 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
121 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
122 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
124 igb_vf_perm_addr_gen(eth_dev, vf_num);
126 /* set mb interrupt mask */
127 igb_mb_intr_setup(eth_dev);
132 void igb_pf_host_uninit(struct rte_eth_dev *dev)
134 struct e1000_vf_info **vfinfo;
137 PMD_INIT_FUNC_TRACE();
139 vfinfo = E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
141 RTE_ETH_DEV_SRIOV(dev).active = 0;
142 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 0;
143 RTE_ETH_DEV_SRIOV(dev).def_vmdq_idx = 0;
144 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 0;
146 vf_num = dev_num_vf(dev);
154 #define E1000_RAH_POOLSEL_SHIFT (18)
155 int igb_pf_host_configure(struct rte_eth_dev *eth_dev)
159 struct e1000_hw *hw =
160 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
165 if (0 == (vf_num = dev_num_vf(eth_dev)))
168 /* enable VMDq and set the default pool for PF */
169 vtctl = E1000_READ_REG(hw, E1000_VT_CTL);
170 vtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK;
171 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
172 << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
173 vtctl |= E1000_VT_CTL_VM_REPL_EN;
174 E1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);
176 /* Enable pools reserved to PF only */
177 E1000_WRITE_REG(hw, E1000_VFRE, (~0U) << vf_num);
178 E1000_WRITE_REG(hw, E1000_VFTE, (~0U) << vf_num);
180 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
181 if (hw->mac.type == e1000_i350)
182 E1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
184 E1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
186 /* clear VMDq map to perment rar 0 */
187 rah = E1000_READ_REG(hw, E1000_RAH(0));
188 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
189 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
191 /* clear VMDq map to scan rar 32 */
192 rah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count));
193 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
194 E1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah);
196 /* set VMDq map to default PF pool */
197 rah = E1000_READ_REG(hw, E1000_RAH(0));
198 rah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx +
199 E1000_RAH_POOLSEL_SHIFT));
200 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
203 * enable vlan filtering and allow all vlan tags through
205 vlanctrl = E1000_READ_REG(hw, E1000_RCTL);
206 vlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */
207 E1000_WRITE_REG(hw, E1000_RCTL, vlanctrl);
209 /* VFTA - enable all vlan filters */
210 for (i = 0; i < IGB_VFTA_SIZE; i++) {
211 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF);
214 /* Enable/Disable MAC Anti-Spoofing */
215 e1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num);
221 set_rx_mode(struct rte_eth_dev *dev)
223 struct rte_eth_dev_data *dev_data = dev->data;
224 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
225 uint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE;
226 uint16_t vfn = dev_num_vf(dev);
228 /* Check for Promiscuous and All Multicast modes */
229 fctrl = E1000_READ_REG(hw, E1000_RCTL);
231 /* set all bits that we expect to always be set */
232 fctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */
233 fctrl |= E1000_RCTL_BAM;
235 /* clear the bits we are changing the status of */
236 fctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
238 if (dev_data->promiscuous) {
239 fctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
240 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
242 if (dev_data->all_multicast) {
243 fctrl |= E1000_RCTL_MPE;
244 vmolr |= E1000_VMOLR_MPME;
246 vmolr |= E1000_VMOLR_ROMPE;
250 if ((hw->mac.type == e1000_82576) ||
251 (hw->mac.type == e1000_i350)) {
252 vmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &
253 ~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE |
255 E1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);
258 E1000_WRITE_REG(hw, E1000_RCTL, fctrl);
262 igb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
264 struct e1000_hw *hw =
265 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
266 struct e1000_vf_info *vfinfo =
267 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
268 uint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
270 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE |
271 E1000_VMOLR_BAM | E1000_VMOLR_AUPE);
272 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
274 E1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);
276 /* reset multicast table array for vf */
277 vfinfo[vf].num_vf_mc_hashes = 0;
284 igb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
286 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
289 /* enable transmit and receive for vf */
290 reg = E1000_READ_REG(hw, E1000_VFTE);
291 reg |= (reg | (1 << vf));
292 E1000_WRITE_REG(hw, E1000_VFTE, reg);
294 reg = E1000_READ_REG(hw, E1000_VFRE);
295 reg |= (reg | (1 << vf));
296 E1000_WRITE_REG(hw, E1000_VFRE, reg);
298 igb_vf_reset_event(dev, vf);
302 igb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
304 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
305 struct e1000_vf_info *vfinfo =
306 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
307 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
308 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
309 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
312 igb_vf_reset_msg(dev, vf);
314 hw->mac.ops.rar_set(hw, vf_mac, rar_entry);
315 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
316 rah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT));
317 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
319 /* reply to reset with ack and vf mac address */
320 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
321 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
322 e1000_write_mbx(hw, msgbuf, 3, vf);
328 igb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
330 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
331 struct e1000_vf_info *vfinfo =
332 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
333 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
334 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
337 if (is_unicast_ether_addr((struct ether_addr *)new_mac)) {
338 if (!is_zero_ether_addr((struct ether_addr *)new_mac))
339 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
340 sizeof(vfinfo[vf].vf_mac_addresses));
341 hw->mac.ops.rar_set(hw, new_mac, rar_entry);
342 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
343 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + vf));
344 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
351 igb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
357 int entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >>
358 E1000_VT_MSGINFO_SHIFT;
359 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
360 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
361 struct e1000_vf_info *vfinfo =
362 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
364 /* only so many hash values supported */
365 entries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES);
368 * salt away the number of multi cast addresses assigned
369 * to this VF for later use to restore when the PF multi cast
372 vfinfo->num_vf_mc_hashes = (uint16_t)entries;
375 * VFs are limited to using the MTA hash table for their multicast
378 for (i = 0; i < entries; i++) {
379 vfinfo->vf_mc_hashes[i] = hash_list[i];
382 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
383 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;
384 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;
385 mta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg);
386 mta_reg |= (1 << vector_bit);
387 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg);
394 igb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
397 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
398 struct e1000_vf_info *vfinfo =
399 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
400 uint32_t vid_idx, vid_bit, vfta;
402 add = (msgbuf[0] & E1000_VT_MSGINFO_MASK)
403 >> E1000_VT_MSGINFO_SHIFT;
404 vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
407 vfinfo[vf].vlan_count++;
408 else if (vfinfo[vf].vlan_count)
409 vfinfo[vf].vlan_count--;
411 vid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) &
412 E1000_VFTA_ENTRY_MASK);
413 vid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
414 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
420 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
421 E1000_WRITE_FLUSH(hw);
427 igb_vf_set_rlpml(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
429 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
430 uint16_t rlpml = msgbuf[1] & E1000_VMOLR_RLPML_MASK;
431 uint32_t max_frame = rlpml + ETHER_HDR_LEN + ETHER_CRC_LEN;
434 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
437 vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
439 vmolr &= ~E1000_VMOLR_RLPML_MASK;
442 /* Enable Long Packet support */
443 vmolr |= E1000_VMOLR_LPE;
445 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
446 E1000_WRITE_FLUSH(hw);
452 igb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
454 uint16_t mbx_size = E1000_VFMAILBOX_SIZE;
455 uint32_t msgbuf[E1000_VFMAILBOX_SIZE];
457 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 retval = e1000_read_mbx(hw, msgbuf, mbx_size, vf);
461 PMD_INIT_LOG(ERR, "Error mbx recv msg from VF %d", vf);
465 /* do nothing with the message already processed */
466 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
469 /* flush the ack before we write any messages back */
470 E1000_WRITE_FLUSH(hw);
472 /* perform VF reset */
473 if (msgbuf[0] == E1000_VF_RESET) {
474 return igb_vf_reset(dev, vf, msgbuf);
477 /* check & process VF to PF mailbox message */
478 switch ((msgbuf[0] & 0xFFFF)) {
479 case E1000_VF_SET_MAC_ADDR:
480 retval = igb_vf_set_mac_addr(dev, vf, msgbuf);
482 case E1000_VF_SET_MULTICAST:
483 retval = igb_vf_set_multicast(dev, vf, msgbuf);
485 case E1000_VF_SET_LPE:
486 retval = igb_vf_set_rlpml(dev, vf, msgbuf);
488 case E1000_VF_SET_VLAN:
489 retval = igb_vf_set_vlan(dev, vf, msgbuf);
492 PMD_INIT_LOG(DEBUG, "Unhandled Msg %8.8x",
493 (unsigned) msgbuf[0]);
494 retval = E1000_ERR_MBX;
498 /* response the VF according to the message process result */
500 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
502 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
504 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
506 e1000_write_mbx(hw, msgbuf, 1, vf);
512 igb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
514 uint32_t msg = E1000_VT_MSGTYPE_NACK;
515 struct e1000_hw *hw =
516 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
518 e1000_write_mbx(hw, &msg, 1, vf);
521 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev)
524 struct e1000_hw *hw =
525 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
527 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
528 /* check & process vf function level reset */
529 if (!e1000_check_for_rst(hw, vf))
530 igb_vf_reset_event(eth_dev, vf);
532 /* check & process vf mailbox messages */
533 if (!e1000_check_for_msg(hw, vf))
534 igb_rcv_msg_from_vf(eth_dev, vf);
536 /* check & process acks from vf */
537 if (!e1000_check_for_ack(hw, vf))
538 igb_rcv_ack_from_vf(eth_dev, vf);