drivers/net/e1000/igb_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35
  36 #include <stdio.h>
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <errno.h>
  40 #include <stdint.h>
  41 #include <stdarg.h>
  42 #include <inttypes.h>
  43
  44 #include <rte_interrupts.h>
  45 #include <rte_byteorder.h>
  46 #include <rte_common.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_memory.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_memzone.h>
  53 #include <rte_launch.h>
  54 #include <rte_eal.h>
  55 #include <rte_per_lcore.h>
  56 #include <rte_lcore.h>
  57 #include <rte_atomic.h>
  58 #include <rte_branch_prediction.h>
  59 #include <rte_ring.h>
  60 #include <rte_mempool.h>
  61 #include <rte_malloc.h>
  62 #include <rte_mbuf.h>
  63 #include <rte_ether.h>
  64 #include <rte_ethdev.h>
  65 #include <rte_prefetch.h>
  66 #include <rte_udp.h>
  67 #include <rte_tcp.h>
  68 #include <rte_sctp.h>
  69 #include <rte_string_fns.h>
  70
  71 #include "e1000_logs.h"
  72 #include "base/e1000_api.h"
  73 #include "e1000_ethdev.h"
  74
  75 /* Bit Mask to indicate what bits required for building TX context */
  76 #define IGB_TX_OFFLOAD_MASK (                    \
  77                 PKT_TX_VLAN_PKT |                \
  78                 PKT_TX_IP_CKSUM |                \
  79                 PKT_TX_L4_MASK)
  80
  81 static inline struct rte_mbuf *
  82 rte_rxmbuf_alloc(struct rte_mempool *mp)
  83 {
  84         struct rte_mbuf *m;
  85
  86         m = __rte_mbuf_raw_alloc(mp);
  87         __rte_mbuf_sanity_check_raw(m, 0);
  88         return (m);
  89 }
  90
  91 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  92         (uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
  93
  94 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  95         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  96
  97 /**
  98  * Structure associated with each descriptor of the RX ring of a RX queue.
  99  */
 100 struct igb_rx_entry {
 101         struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
 102 };
 103
 104 /**
 105  * Structure associated with each descriptor of the TX ring of a TX queue.
 106  */
 107 struct igb_tx_entry {
 108         struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 109         uint16_t next_id; /**< Index of next descriptor in ring. */
 110         uint16_t last_id; /**< Index of last scattered descriptor. */
 111 };
 112
 113 /**
 114  * Structure associated with each RX queue.
 115  */
 116 struct igb_rx_queue {
 117         struct rte_mempool  *mb_pool;   /**< mbuf pool to populate RX ring. */
 118         volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
 119         uint64_t            rx_ring_phys_addr; /**< RX ring DMA address. */
 120         volatile uint32_t   *rdt_reg_addr; /**< RDT register address. */
 121         volatile uint32_t   *rdh_reg_addr; /**< RDH register address. */
 122         struct igb_rx_entry *sw_ring;   /**< address of RX software ring. */
 123         struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
 124         struct rte_mbuf *pkt_last_seg;  /**< Last segment of current packet. */
 125         uint16_t            nb_rx_desc; /**< number of RX descriptors. */
 126         uint16_t            rx_tail;    /**< current value of RDT register. */
 127         uint16_t            nb_rx_hold; /**< number of held free RX desc. */
 128         uint16_t            rx_free_thresh; /**< max free RX desc to hold. */
 129         uint16_t            queue_id;   /**< RX queue index. */
 130         uint16_t            reg_idx;    /**< RX queue register index. */
 131         uint8_t             port_id;    /**< Device port identifier. */
 132         uint8_t             pthresh;    /**< Prefetch threshold register. */
 133         uint8_t             hthresh;    /**< Host threshold register. */
 134         uint8_t             wthresh;    /**< Write-back threshold register. */
 135         uint8_t             crc_len;    /**< 0 if CRC stripped, 4 otherwise. */
 136         uint8_t             drop_en;  /**< If not 0, set SRRCTL.Drop_En. */
 137 };
 138
 139 /**
 140  * Hardware context number
 141  */
 142 enum igb_advctx_num {
 143         IGB_CTX_0    = 0, /**< CTX0    */
 144         IGB_CTX_1    = 1, /**< CTX1    */
 145         IGB_CTX_NUM  = 2, /**< CTX_NUM */
 146 };
 147
 148 /** Offload features */
 149 union igb_vlan_macip {
 150         uint32_t data;
 151         struct {
 152                 uint16_t l2_l3_len; /**< 7bit L2 and 9b L3 lengths combined */
 153                 uint16_t vlan_tci;
 154                 /**< VLAN Tag Control Identifier (CPU order). */
 155         } f;
 156 };
 157
 158 /*
 159  * Compare mask for vlan_macip_len.data,
 160  * should be in sync with igb_vlan_macip.f layout.
 161  * */
 162 #define TX_VLAN_CMP_MASK        0xFFFF0000  /**< VLAN length - 16-bits. */
 163 #define TX_MAC_LEN_CMP_MASK     0x0000FE00  /**< MAC length - 7-bits. */
 164 #define TX_IP_LEN_CMP_MASK      0x000001FF  /**< IP  length - 9-bits. */
 165 /** MAC+IP  length. */
 166 #define TX_MACIP_LEN_CMP_MASK   (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
 167
 168 /**
 169  * Strucutre to check if new context need be built
 170  */
 171 struct igb_advctx_info {
 172         uint64_t flags;           /**< ol_flags related to context build. */
 173         uint32_t cmp_mask;        /**< compare mask for vlan_macip_lens */
 174         union igb_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
 175 };
 176
 177 /**
 178  * Structure associated with each TX queue.
 179  */
 180 struct igb_tx_queue {
 181         volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
 182         uint64_t               tx_ring_phys_addr; /**< TX ring DMA address. */
 183         struct igb_tx_entry    *sw_ring; /**< virtual address of SW ring. */
 184         volatile uint32_t      *tdt_reg_addr; /**< Address of TDT register. */
 185         uint32_t               txd_type;      /**< Device-specific TXD type */
 186         uint16_t               nb_tx_desc;    /**< number of TX descriptors. */
 187         uint16_t               tx_tail; /**< Current value of TDT register. */
 188         uint16_t               tx_head;
 189         /**< Index of first used TX descriptor. */
 190         uint16_t               queue_id; /**< TX queue index. */
 191         uint16_t               reg_idx;  /**< TX queue register index. */
 192         uint8_t                port_id;  /**< Device port identifier. */
 193         uint8_t                pthresh;  /**< Prefetch threshold register. */
 194         uint8_t                hthresh;  /**< Host threshold register. */
 195         uint8_t                wthresh;  /**< Write-back threshold register. */
 196         uint32_t               ctx_curr;
 197         /**< Current used hardware descriptor. */
 198         uint32_t               ctx_start;
 199         /**< Start context position for transmit queue. */
 200         struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
 201         /**< Hardware context history.*/
 202 };
 203
 204 #if 1
 205 #define RTE_PMD_USE_PREFETCH
 206 #endif
 207
 208 #ifdef RTE_PMD_USE_PREFETCH
 209 #define rte_igb_prefetch(p)     rte_prefetch0(p)
 210 #else
 211 #define rte_igb_prefetch(p)     do {} while(0)
 212 #endif
 213
 214 #ifdef RTE_PMD_PACKET_PREFETCH
 215 #define rte_packet_prefetch(p) rte_prefetch1(p)
 216 #else
 217 #define rte_packet_prefetch(p)  do {} while(0)
 218 #endif
 219
 220 /*
 221  * Macro for VMDq feature for 1 GbE NIC.
 222  */
 223 #define E1000_VMOLR_SIZE                        (8)
 224
 225 /*********************************************************************
 226  *
 227  *  TX function
 228  *
 229  **********************************************************************/
 230
 231 /*
 232  * Advanced context descriptor are almost same between igb/ixgbe
 233  * This is a separate function, looking for optimization opportunity here
 234  * Rework required to go with the pre-defined values.
 235  */
 236
 237 static inline void
 238 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
 239                 volatile struct e1000_adv_tx_context_desc *ctx_txd,
 240                 uint64_t ol_flags, uint32_t vlan_macip_lens)
 241 {
 242         uint32_t type_tucmd_mlhl;
 243         uint32_t mss_l4len_idx;
 244         uint32_t ctx_idx, ctx_curr;
 245         uint32_t cmp_mask;
 246
 247         ctx_curr = txq->ctx_curr;
 248         ctx_idx = ctx_curr + txq->ctx_start;
 249
 250         cmp_mask = 0;
 251         type_tucmd_mlhl = 0;
 252
 253         if (ol_flags & PKT_TX_VLAN_PKT) {
 254                 cmp_mask |= TX_VLAN_CMP_MASK;
 255         }
 256
 257         if (ol_flags & PKT_TX_IP_CKSUM) {
 258                 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
 259                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 260         }
 261
 262         /* Specify which HW CTX to upload. */
 263         mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
 264         switch (ol_flags & PKT_TX_L4_MASK) {
 265         case PKT_TX_UDP_CKSUM:
 266                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
 267                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 268                 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 269                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 270                 break;
 271         case PKT_TX_TCP_CKSUM:
 272                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
 273                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 274                 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 275                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 276                 break;
 277         case PKT_TX_SCTP_CKSUM:
 278                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
 279                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 280                 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 281                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 282                 break;
 283         default:
 284                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
 285                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 286                 break;
 287         }
 288
 289         txq->ctx_cache[ctx_curr].flags           = ol_flags;
 290         txq->ctx_cache[ctx_curr].cmp_mask        = cmp_mask;
 291         txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
 292                 vlan_macip_lens & cmp_mask;
 293
 294         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 295         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 296         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 297         ctx_txd->seqnum_seed     = 0;
 298 }
 299
 300 /*
 301  * Check which hardware context can be used. Use the existing match
 302  * or create a new context descriptor.
 303  */
 304 static inline uint32_t
 305 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
 306                 uint32_t vlan_macip_lens)
 307 {
 308         /* If match with the current context */
 309         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 310                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 311                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 312                         return txq->ctx_curr;
 313         }
 314
 315         /* If match with the second context */
 316         txq->ctx_curr ^= 1;
 317         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 318                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 319                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 320                         return txq->ctx_curr;
 321         }
 322
 323         /* Mismatch, use the previous context */
 324         return (IGB_CTX_NUM);
 325 }
 326
 327 static inline uint32_t
 328 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 329 {
 330         static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
 331         static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
 332         uint32_t tmp;
 333
 334         tmp  = l4_olinfo[(ol_flags & PKT_TX_L4_MASK)  != PKT_TX_L4_NO_CKSUM];
 335         tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
 336         return tmp;
 337 }
 338
 339 static inline uint32_t
 340 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
 341 {
 342         static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
 343         return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
 344 }
 345
 346 uint16_t
 347 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 348                uint16_t nb_pkts)
 349 {
 350         struct igb_tx_queue *txq;
 351         struct igb_tx_entry *sw_ring;
 352         struct igb_tx_entry *txe, *txn;
 353         volatile union e1000_adv_tx_desc *txr;
 354         volatile union e1000_adv_tx_desc *txd;
 355         struct rte_mbuf     *tx_pkt;
 356         struct rte_mbuf     *m_seg;
 357         union igb_vlan_macip vlan_macip_lens;
 358         union {
 359                 uint16_t u16;
 360                 struct {
 361                         uint16_t l3_len:9;
 362                         uint16_t l2_len:7;
 363                 };
 364         } l2_l3_len;
 365         uint64_t buf_dma_addr;
 366         uint32_t olinfo_status;
 367         uint32_t cmd_type_len;
 368         uint32_t pkt_len;
 369         uint16_t slen;
 370         uint64_t ol_flags;
 371         uint16_t tx_end;
 372         uint16_t tx_id;
 373         uint16_t tx_last;
 374         uint16_t nb_tx;
 375         uint64_t tx_ol_req;
 376         uint32_t new_ctx = 0;
 377         uint32_t ctx = 0;
 378
 379         txq = tx_queue;
 380         sw_ring = txq->sw_ring;
 381         txr     = txq->tx_ring;
 382         tx_id   = txq->tx_tail;
 383         txe = &sw_ring[tx_id];
 384
 385         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 386                 tx_pkt = *tx_pkts++;
 387                 pkt_len = tx_pkt->pkt_len;
 388
 389                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
 390
 391                 /*
 392                  * The number of descriptors that must be allocated for a
 393                  * packet is the number of segments of that packet, plus 1
 394                  * Context Descriptor for the VLAN Tag Identifier, if any.
 395                  * Determine the last TX descriptor to allocate in the TX ring
 396                  * for the packet, starting from the current position (tx_id)
 397                  * in the ring.
 398                  */
 399                 tx_last = (uint16_t) (tx_id + tx_pkt->nb_segs - 1);
 400
 401                 ol_flags = tx_pkt->ol_flags;
 402                 l2_l3_len.l2_len = tx_pkt->l2_len;
 403                 l2_l3_len.l3_len = tx_pkt->l3_len;
 404                 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
 405                 vlan_macip_lens.f.l2_l3_len = l2_l3_len.u16;
 406                 tx_ol_req = ol_flags & IGB_TX_OFFLOAD_MASK;
 407
 408                 /* If a Context Descriptor need be built . */
 409                 if (tx_ol_req) {
 410                         ctx = what_advctx_update(txq, tx_ol_req,
 411                                 vlan_macip_lens.data);
 412                         /* Only allocate context descriptor if required*/
 413                         new_ctx = (ctx == IGB_CTX_NUM);
 414                         ctx = txq->ctx_curr;
 415                         tx_last = (uint16_t) (tx_last + new_ctx);
 416                 }
 417                 if (tx_last >= txq->nb_tx_desc)
 418                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 419
 420                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 421                            " tx_first=%u tx_last=%u",
 422                            (unsigned) txq->port_id,
 423                            (unsigned) txq->queue_id,
 424                            (unsigned) pkt_len,
 425                            (unsigned) tx_id,
 426                            (unsigned) tx_last);
 427
 428                 /*
 429                  * Check if there are enough free descriptors in the TX ring
 430                  * to transmit the next packet.
 431                  * This operation is based on the two following rules:
 432                  *
 433                  *   1- Only check that the last needed TX descriptor can be
 434                  *      allocated (by construction, if that descriptor is free,
 435                  *      all intermediate ones are also free).
 436                  *
 437                  *      For this purpose, the index of the last TX descriptor
 438                  *      used for a packet (the "last descriptor" of a packet)
 439                  *      is recorded in the TX entries (the last one included)
 440                  *      that are associated with all TX descriptors allocated
 441                  *      for that packet.
 442                  *
 443                  *   2- Avoid to allocate the last free TX descriptor of the
 444                  *      ring, in order to never set the TDT register with the
 445                  *      same value stored in parallel by the NIC in the TDH
 446                  *      register, which makes the TX engine of the NIC enter
 447                  *      in a deadlock situation.
 448                  *
 449                  *      By extension, avoid to allocate a free descriptor that
 450                  *      belongs to the last set of free descriptors allocated
 451                  *      to the same packet previously transmitted.
 452                  */
 453
 454                 /*
 455                  * The "last descriptor" of the previously sent packet, if any,
 456                  * which used the last descriptor to allocate.
 457                  */
 458                 tx_end = sw_ring[tx_last].last_id;
 459
 460                 /*
 461                  * The next descriptor following that "last descriptor" in the
 462                  * ring.
 463                  */
 464                 tx_end = sw_ring[tx_end].next_id;
 465
 466                 /*
 467                  * The "last descriptor" associated with that next descriptor.
 468                  */
 469                 tx_end = sw_ring[tx_end].last_id;
 470
 471                 /*
 472                  * Check that this descriptor is free.
 473                  */
 474                 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
 475                         if (nb_tx == 0)
 476                                 return (0);
 477                         goto end_of_tx;
 478                 }
 479
 480                 /*
 481                  * Set common flags of all TX Data Descriptors.
 482                  *
 483                  * The following bits must be set in all Data Descriptors:
 484                  *   - E1000_ADVTXD_DTYP_DATA
 485                  *   - E1000_ADVTXD_DCMD_DEXT
 486                  *
 487                  * The following bits must be set in the first Data Descriptor
 488                  * and are ignored in the other ones:
 489                  *   - E1000_ADVTXD_DCMD_IFCS
 490                  *   - E1000_ADVTXD_MAC_1588
 491                  *   - E1000_ADVTXD_DCMD_VLE
 492                  *
 493                  * The following bits must only be set in the last Data
 494                  * Descriptor:
 495                  *   - E1000_TXD_CMD_EOP
 496                  *
 497                  * The following bits can be set in any Data Descriptor, but
 498                  * are only set in the last Data Descriptor:
 499                  *   - E1000_TXD_CMD_RS
 500                  */
 501                 cmd_type_len = txq->txd_type |
 502                         E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
 503                 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
 504 #if defined(RTE_LIBRTE_IEEE1588)
 505                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 506                         cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
 507 #endif
 508                 if (tx_ol_req) {
 509                         /* Setup TX Advanced context descriptor if required */
 510                         if (new_ctx) {
 511                                 volatile struct e1000_adv_tx_context_desc *
 512                                     ctx_txd;
 513
 514                                 ctx_txd = (volatile struct
 515                                     e1000_adv_tx_context_desc *)
 516                                     &txr[tx_id];
 517
 518                                 txn = &sw_ring[txe->next_id];
 519                                 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
 520
 521                                 if (txe->mbuf != NULL) {
 522                                         rte_pktmbuf_free_seg(txe->mbuf);
 523                                         txe->mbuf = NULL;
 524                                 }
 525
 526                                 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 527                                     vlan_macip_lens.data);
 528
 529                                 txe->last_id = tx_last;
 530                                 tx_id = txe->next_id;
 531                                 txe = txn;
 532                         }
 533
 534                         /* Setup the TX Advanced Data Descriptor */
 535                         cmd_type_len  |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
 536                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 537                         olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
 538                 }
 539
 540                 m_seg = tx_pkt;
 541                 do {
 542                         txn = &sw_ring[txe->next_id];
 543                         txd = &txr[tx_id];
 544
 545                         if (txe->mbuf != NULL)
 546                                 rte_pktmbuf_free_seg(txe->mbuf);
 547                         txe->mbuf = m_seg;
 548
 549                         /*
 550                          * Set up transmit descriptor.
 551                          */
 552                         slen = (uint16_t) m_seg->data_len;
 553                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
 554                         txd->read.buffer_addr =
 555                                 rte_cpu_to_le_64(buf_dma_addr);
 556                         txd->read.cmd_type_len =
 557                                 rte_cpu_to_le_32(cmd_type_len | slen);
 558                         txd->read.olinfo_status =
 559                                 rte_cpu_to_le_32(olinfo_status);
 560                         txe->last_id = tx_last;
 561                         tx_id = txe->next_id;
 562                         txe = txn;
 563                         m_seg = m_seg->next;
 564                 } while (m_seg != NULL);
 565
 566                 /*
 567                  * The last packet data descriptor needs End Of Packet (EOP)
 568                  * and Report Status (RS).
 569                  */
 570                 txd->read.cmd_type_len |=
 571                         rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
 572         }
 573  end_of_tx:
 574         rte_wmb();
 575
 576         /*
 577          * Set the Transmit Descriptor Tail (TDT).
 578          */
 579         E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
 580         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 581                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 582                    (unsigned) tx_id, (unsigned) nb_tx);
 583         txq->tx_tail = tx_id;
 584
 585         return (nb_tx);
 586 }
 587
 588 /*********************************************************************
 589  *
 590  *  RX functions
 591  *
 592  **********************************************************************/
 593 static inline uint64_t
 594 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
 595 {
 596         uint64_t pkt_flags;
 597
 598         static uint64_t ip_pkt_types_map[16] = {
 599                 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
 600                 PKT_RX_IPV6_HDR, 0, 0, 0,
 601                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 602                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 603         };
 604
 605 #if defined(RTE_LIBRTE_IEEE1588)
 606         static uint32_t ip_pkt_etqf_map[8] = {
 607                 0, 0, 0, PKT_RX_IEEE1588_PTP,
 608                 0, 0, 0, 0,
 609         };
 610
 611         pkt_flags = (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?
 612                                 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
 613                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
 614 #else
 615         pkt_flags = (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :
 616                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
 617 #endif
 618         return pkt_flags | (((hl_tp_rs & 0x0F) == 0) ?  0 : PKT_RX_RSS_HASH);
 619 }
 620
 621 static inline uint64_t
 622 rx_desc_status_to_pkt_flags(uint32_t rx_status)
 623 {
 624         uint64_t pkt_flags;
 625
 626         /* Check if VLAN present */
 627         pkt_flags = (rx_status & E1000_RXD_STAT_VP) ?  PKT_RX_VLAN_PKT : 0;
 628
 629 #if defined(RTE_LIBRTE_IEEE1588)
 630         if (rx_status & E1000_RXD_STAT_TMST)
 631                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
 632 #endif
 633         return pkt_flags;
 634 }
 635
 636 static inline uint64_t
 637 rx_desc_error_to_pkt_flags(uint32_t rx_status)
 638 {
 639         /*
 640          * Bit 30: IPE, IPv4 checksum error
 641          * Bit 29: L4I, L4I integrity error
 642          */
 643
 644         static uint64_t error_to_pkt_flags_map[4] = {
 645                 0,  PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
 646                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
 647         };
 648         return error_to_pkt_flags_map[(rx_status >>
 649                 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
 650 }
 651
 652 uint16_t
 653 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 654                uint16_t nb_pkts)
 655 {
 656         struct igb_rx_queue *rxq;
 657         volatile union e1000_adv_rx_desc *rx_ring;
 658         volatile union e1000_adv_rx_desc *rxdp;
 659         struct igb_rx_entry *sw_ring;
 660         struct igb_rx_entry *rxe;
 661         struct rte_mbuf *rxm;
 662         struct rte_mbuf *nmb;
 663         union e1000_adv_rx_desc rxd;
 664         uint64_t dma_addr;
 665         uint32_t staterr;
 666         uint32_t hlen_type_rss;
 667         uint16_t pkt_len;
 668         uint16_t rx_id;
 669         uint16_t nb_rx;
 670         uint16_t nb_hold;
 671         uint64_t pkt_flags;
 672
 673         nb_rx = 0;
 674         nb_hold = 0;
 675         rxq = rx_queue;
 676         rx_id = rxq->rx_tail;
 677         rx_ring = rxq->rx_ring;
 678         sw_ring = rxq->sw_ring;
 679         while (nb_rx < nb_pkts) {
 680                 /*
 681                  * The order of operations here is important as the DD status
 682                  * bit must not be read after any other descriptor fields.
 683                  * rx_ring and rxdp are pointing to volatile data so the order
 684                  * of accesses cannot be reordered by the compiler. If they were
 685                  * not volatile, they could be reordered which could lead to
 686                  * using invalid descriptor fields when read from rxd.
 687                  */
 688                 rxdp = &rx_ring[rx_id];
 689                 staterr = rxdp->wb.upper.status_error;
 690                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 691                         break;
 692                 rxd = *rxdp;
 693
 694                 /*
 695                  * End of packet.
 696                  *
 697                  * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
 698                  * likely to be invalid and to be dropped by the various
 699                  * validation checks performed by the network stack.
 700                  *
 701                  * Allocate a new mbuf to replenish the RX ring descriptor.
 702                  * If the allocation fails:
 703                  *    - arrange for that RX descriptor to be the first one
 704                  *      being parsed the next time the receive function is
 705                  *      invoked [on the same queue].
 706                  *
 707                  *    - Stop parsing the RX ring and return immediately.
 708                  *
 709                  * This policy do not drop the packet received in the RX
 710                  * descriptor for which the allocation of a new mbuf failed.
 711                  * Thus, it allows that packet to be later retrieved if
 712                  * mbuf have been freed in the mean time.
 713                  * As a side effect, holding RX descriptors instead of
 714                  * systematically giving them back to the NIC may lead to
 715                  * RX ring exhaustion situations.
 716                  * However, the NIC can gracefully prevent such situations
 717                  * to happen by sending specific "back-pressure" flow control
 718                  * frames to its peer(s).
 719                  */
 720                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
 721                            "staterr=0x%x pkt_len=%u",
 722                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 723                            (unsigned) rx_id, (unsigned) staterr,
 724                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 725
 726                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 727                 if (nmb == NULL) {
 728                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 729                                    "queue_id=%u", (unsigned) rxq->port_id,
 730                                    (unsigned) rxq->queue_id);
 731                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 732                         break;
 733                 }
 734
 735                 nb_hold++;
 736                 rxe = &sw_ring[rx_id];
 737                 rx_id++;
 738                 if (rx_id == rxq->nb_rx_desc)
 739                         rx_id = 0;
 740
 741                 /* Prefetch next mbuf while processing current one. */
 742                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 743
 744                 /*
 745                  * When next RX descriptor is on a cache-line boundary,
 746                  * prefetch the next 4 RX descriptors and the next 8 pointers
 747                  * to mbufs.
 748                  */
 749                 if ((rx_id & 0x3) == 0) {
 750                         rte_igb_prefetch(&rx_ring[rx_id]);
 751                         rte_igb_prefetch(&sw_ring[rx_id]);
 752                 }
 753
 754                 rxm = rxe->mbuf;
 755                 rxe->mbuf = nmb;
 756                 dma_addr =
 757                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 758                 rxdp->read.hdr_addr = dma_addr;
 759                 rxdp->read.pkt_addr = dma_addr;
 760
 761                 /*
 762                  * Initialize the returned mbuf.
 763                  * 1) setup generic mbuf fields:
 764                  *    - number of segments,
 765                  *    - next segment,
 766                  *    - packet length,
 767                  *    - RX port identifier.
 768                  * 2) integrate hardware offload data, if any:
 769                  *    - RSS flag & hash,
 770                  *    - IP checksum flag,
 771                  *    - VLAN TCI, if any,
 772                  *    - error flags.
 773                  */
 774                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
 775                                       rxq->crc_len);
 776                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 777                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
 778                 rxm->nb_segs = 1;
 779                 rxm->next = NULL;
 780                 rxm->pkt_len = pkt_len;
 781                 rxm->data_len = pkt_len;
 782                 rxm->port = rxq->port_id;
 783
 784                 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
 785                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 786                 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
 787                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
 788
 789                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
 790                 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
 791                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
 792                 rxm->ol_flags = pkt_flags;
 793
 794                 /*
 795                  * Store the mbuf address into the next entry of the array
 796                  * of returned packets.
 797                  */
 798                 rx_pkts[nb_rx++] = rxm;
 799         }
 800         rxq->rx_tail = rx_id;
 801
 802         /*
 803          * If the number of free RX descriptors is greater than the RX free
 804          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 805          * register.
 806          * Update the RDT with the value of the last processed RX descriptor
 807          * minus 1, to guarantee that the RDT register is never equal to the
 808          * RDH register, which creates a "full" ring situtation from the
 809          * hardware point of view...
 810          */
 811         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
 812         if (nb_hold > rxq->rx_free_thresh) {
 813                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 814                            "nb_hold=%u nb_rx=%u",
 815                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 816                            (unsigned) rx_id, (unsigned) nb_hold,
 817                            (unsigned) nb_rx);
 818                 rx_id = (uint16_t) ((rx_id == 0) ?
 819                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
 820                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
 821                 nb_hold = 0;
 822         }
 823         rxq->nb_rx_hold = nb_hold;
 824         return (nb_rx);
 825 }
 826
 827 uint16_t
 828 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 829                          uint16_t nb_pkts)
 830 {
 831         struct igb_rx_queue *rxq;
 832         volatile union e1000_adv_rx_desc *rx_ring;
 833         volatile union e1000_adv_rx_desc *rxdp;
 834         struct igb_rx_entry *sw_ring;
 835         struct igb_rx_entry *rxe;
 836         struct rte_mbuf *first_seg;
 837         struct rte_mbuf *last_seg;
 838         struct rte_mbuf *rxm;
 839         struct rte_mbuf *nmb;
 840         union e1000_adv_rx_desc rxd;
 841         uint64_t dma; /* Physical address of mbuf data buffer */
 842         uint32_t staterr;
 843         uint32_t hlen_type_rss;
 844         uint16_t rx_id;
 845         uint16_t nb_rx;
 846         uint16_t nb_hold;
 847         uint16_t data_len;
 848         uint64_t pkt_flags;
 849
 850         nb_rx = 0;
 851         nb_hold = 0;
 852         rxq = rx_queue;
 853         rx_id = rxq->rx_tail;
 854         rx_ring = rxq->rx_ring;
 855         sw_ring = rxq->sw_ring;
 856
 857         /*
 858          * Retrieve RX context of current packet, if any.
 859          */
 860         first_seg = rxq->pkt_first_seg;
 861         last_seg = rxq->pkt_last_seg;
 862
 863         while (nb_rx < nb_pkts) {
 864         next_desc:
 865                 /*
 866                  * The order of operations here is important as the DD status
 867                  * bit must not be read after any other descriptor fields.
 868                  * rx_ring and rxdp are pointing to volatile data so the order
 869                  * of accesses cannot be reordered by the compiler. If they were
 870                  * not volatile, they could be reordered which could lead to
 871                  * using invalid descriptor fields when read from rxd.
 872                  */
 873                 rxdp = &rx_ring[rx_id];
 874                 staterr = rxdp->wb.upper.status_error;
 875                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 876                         break;
 877                 rxd = *rxdp;
 878
 879                 /*
 880                  * Descriptor done.
 881                  *
 882                  * Allocate a new mbuf to replenish the RX ring descriptor.
 883                  * If the allocation fails:
 884                  *    - arrange for that RX descriptor to be the first one
 885                  *      being parsed the next time the receive function is
 886                  *      invoked [on the same queue].
 887                  *
 888                  *    - Stop parsing the RX ring and return immediately.
 889                  *
 890                  * This policy does not drop the packet received in the RX
 891                  * descriptor for which the allocation of a new mbuf failed.
 892                  * Thus, it allows that packet to be later retrieved if
 893                  * mbuf have been freed in the mean time.
 894                  * As a side effect, holding RX descriptors instead of
 895                  * systematically giving them back to the NIC may lead to
 896                  * RX ring exhaustion situations.
 897                  * However, the NIC can gracefully prevent such situations
 898                  * to happen by sending specific "back-pressure" flow control
 899                  * frames to its peer(s).
 900                  */
 901                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
 902                            "staterr=0x%x data_len=%u",
 903                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 904                            (unsigned) rx_id, (unsigned) staterr,
 905                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 906
 907                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 908                 if (nmb == NULL) {
 909                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 910                                    "queue_id=%u", (unsigned) rxq->port_id,
 911                                    (unsigned) rxq->queue_id);
 912                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 913                         break;
 914                 }
 915
 916                 nb_hold++;
 917                 rxe = &sw_ring[rx_id];
 918                 rx_id++;
 919                 if (rx_id == rxq->nb_rx_desc)
 920                         rx_id = 0;
 921
 922                 /* Prefetch next mbuf while processing current one. */
 923                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 924
 925                 /*
 926                  * When next RX descriptor is on a cache-line boundary,
 927                  * prefetch the next 4 RX descriptors and the next 8 pointers
 928                  * to mbufs.
 929                  */
 930                 if ((rx_id & 0x3) == 0) {
 931                         rte_igb_prefetch(&rx_ring[rx_id]);
 932                         rte_igb_prefetch(&sw_ring[rx_id]);
 933                 }
 934
 935                 /*
 936                  * Update RX descriptor with the physical address of the new
 937                  * data buffer of the new allocated mbuf.
 938                  */
 939                 rxm = rxe->mbuf;
 940                 rxe->mbuf = nmb;
 941                 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 942                 rxdp->read.pkt_addr = dma;
 943                 rxdp->read.hdr_addr = dma;
 944
 945                 /*
 946                  * Set data length & data buffer address of mbuf.
 947                  */
 948                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
 949                 rxm->data_len = data_len;
 950                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 951
 952                 /*
 953                  * If this is the first buffer of the received packet,
 954                  * set the pointer to the first mbuf of the packet and
 955                  * initialize its context.
 956                  * Otherwise, update the total length and the number of segments
 957                  * of the current scattered packet, and update the pointer to
 958                  * the last mbuf of the current packet.
 959                  */
 960                 if (first_seg == NULL) {
 961                         first_seg = rxm;
 962                         first_seg->pkt_len = data_len;
 963                         first_seg->nb_segs = 1;
 964                 } else {
 965                         first_seg->pkt_len += data_len;
 966                         first_seg->nb_segs++;
 967                         last_seg->next = rxm;
 968                 }
 969
 970                 /*
 971                  * If this is not the last buffer of the received packet,
 972                  * update the pointer to the last mbuf of the current scattered
 973                  * packet and continue to parse the RX ring.
 974                  */
 975                 if (! (staterr & E1000_RXD_STAT_EOP)) {
 976                         last_seg = rxm;
 977                         goto next_desc;
 978                 }
 979
 980                 /*
 981                  * This is the last buffer of the received packet.
 982                  * If the CRC is not stripped by the hardware:
 983                  *   - Subtract the CRC length from the total packet length.
 984                  *   - If the last buffer only contains the whole CRC or a part
 985                  *     of it, free the mbuf associated to the last buffer.
 986                  *     If part of the CRC is also contained in the previous
 987                  *     mbuf, subtract the length of that CRC part from the
 988                  *     data length of the previous mbuf.
 989                  */
 990                 rxm->next = NULL;
 991                 if (unlikely(rxq->crc_len > 0)) {
 992                         first_seg->pkt_len -= ETHER_CRC_LEN;
 993                         if (data_len <= ETHER_CRC_LEN) {
 994                                 rte_pktmbuf_free_seg(rxm);
 995                                 first_seg->nb_segs--;
 996                                 last_seg->data_len = (uint16_t)
 997                                         (last_seg->data_len -
 998                                          (ETHER_CRC_LEN - data_len));
 999                                 last_seg->next = NULL;
1000                         } else
1001                                 rxm->data_len =
1002                                         (uint16_t) (data_len - ETHER_CRC_LEN);
1003                 }
1004
1005                 /*
1006                  * Initialize the first mbuf of the returned packet:
1007                  *    - RX port identifier,
1008                  *    - hardware offload data, if any:
1009                  *      - RSS flag & hash,
1010                  *      - IP checksum flag,
1011                  *      - VLAN TCI, if any,
1012                  *      - error flags.
1013                  */
1014                 first_seg->port = rxq->port_id;
1015                 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1016
1017                 /*
1018                  * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1019                  * set in the pkt_flags field.
1020                  */
1021                 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1022                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1023                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1024                 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1025                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1026                 first_seg->ol_flags = pkt_flags;
1027
1028                 /* Prefetch data of first segment, if configured to do so. */
1029                 rte_packet_prefetch((char *)first_seg->buf_addr +
1030                         first_seg->data_off);
1031
1032                 /*
1033                  * Store the mbuf address into the next entry of the array
1034                  * of returned packets.
1035                  */
1036                 rx_pkts[nb_rx++] = first_seg;
1037
1038                 /*
1039                  * Setup receipt context for a new packet.
1040                  */
1041                 first_seg = NULL;
1042         }
1043
1044         /*
1045          * Record index of the next RX descriptor to probe.
1046          */
1047         rxq->rx_tail = rx_id;
1048
1049         /*
1050          * Save receive context.
1051          */
1052         rxq->pkt_first_seg = first_seg;
1053         rxq->pkt_last_seg = last_seg;
1054
1055         /*
1056          * If the number of free RX descriptors is greater than the RX free
1057          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1058          * register.
1059          * Update the RDT with the value of the last processed RX descriptor
1060          * minus 1, to guarantee that the RDT register is never equal to the
1061          * RDH register, which creates a "full" ring situtation from the
1062          * hardware point of view...
1063          */
1064         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1065         if (nb_hold > rxq->rx_free_thresh) {
1066                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1067                            "nb_hold=%u nb_rx=%u",
1068                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1069                            (unsigned) rx_id, (unsigned) nb_hold,
1070                            (unsigned) nb_rx);
1071                 rx_id = (uint16_t) ((rx_id == 0) ?
1072                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1073                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1074                 nb_hold = 0;
1075         }
1076         rxq->nb_rx_hold = nb_hold;
1077         return (nb_rx);
1078 }
1079
1080 /*
1081  * Rings setup and release.
1082  *
1083  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1084  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1085  * This will also optimize cache line size effect.
1086  * H/W supports up to cache line size 128.
1087  */
1088 #define IGB_ALIGN 128
1089
1090 /*
1091  * Maximum number of Ring Descriptors.
1092  *
1093  * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1094  * desscriptors should meet the following condition:
1095  *      (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1096  */
1097 #define IGB_MIN_RING_DESC 32
1098 #define IGB_MAX_RING_DESC 4096
1099
1100 static const struct rte_memzone *
1101 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1102                       uint16_t queue_id, uint32_t ring_size, int socket_id)
1103 {
1104         char z_name[RTE_MEMZONE_NAMESIZE];
1105         const struct rte_memzone *mz;
1106
1107         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1108                         dev->driver->pci_drv.name, ring_name,
1109                                 dev->data->port_id, queue_id);
1110         mz = rte_memzone_lookup(z_name);
1111         if (mz)
1112                 return mz;
1113
1114 #ifdef RTE_LIBRTE_XEN_DOM0
1115         return rte_memzone_reserve_bounded(z_name, ring_size,
1116                         socket_id, 0, IGB_ALIGN, RTE_PGSIZE_2M);
1117 #else
1118         return rte_memzone_reserve_aligned(z_name, ring_size,
1119                         socket_id, 0, IGB_ALIGN);
1120 #endif
1121 }
1122
1123 static void
1124 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1125 {
1126         unsigned i;
1127
1128         if (txq->sw_ring != NULL) {
1129                 for (i = 0; i < txq->nb_tx_desc; i++) {
1130                         if (txq->sw_ring[i].mbuf != NULL) {
1131                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1132                                 txq->sw_ring[i].mbuf = NULL;
1133                         }
1134                 }
1135         }
1136 }
1137
1138 static void
1139 igb_tx_queue_release(struct igb_tx_queue *txq)
1140 {
1141         if (txq != NULL) {
1142                 igb_tx_queue_release_mbufs(txq);
1143                 rte_free(txq->sw_ring);
1144                 rte_free(txq);
1145         }
1146 }
1147
1148 void
1149 eth_igb_tx_queue_release(void *txq)
1150 {
1151         igb_tx_queue_release(txq);
1152 }
1153
1154 static void
1155 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1156 {
1157         txq->tx_head = 0;
1158         txq->tx_tail = 0;
1159         txq->ctx_curr = 0;
1160         memset((void*)&txq->ctx_cache, 0,
1161                 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1162 }
1163
1164 static void
1165 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1166 {
1167         static const union e1000_adv_tx_desc zeroed_desc = {{0}};
1168         struct igb_tx_entry *txe = txq->sw_ring;
1169         uint16_t i, prev;
1170         struct e1000_hw *hw;
1171
1172         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1173         /* Zero out HW ring memory */
1174         for (i = 0; i < txq->nb_tx_desc; i++) {
1175                 txq->tx_ring[i] = zeroed_desc;
1176         }
1177
1178         /* Initialize ring entries */
1179         prev = (uint16_t)(txq->nb_tx_desc - 1);
1180         for (i = 0; i < txq->nb_tx_desc; i++) {
1181                 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1182
1183                 txd->wb.status = E1000_TXD_STAT_DD;
1184                 txe[i].mbuf = NULL;
1185                 txe[i].last_id = i;
1186                 txe[prev].next_id = i;
1187                 prev = i;
1188         }
1189
1190         txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1191         /* 82575 specific, each tx queue will use 2 hw contexts */
1192         if (hw->mac.type == e1000_82575)
1193                 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1194
1195         igb_reset_tx_queue_stat(txq);
1196 }
1197
1198 int
1199 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1200                          uint16_t queue_idx,
1201                          uint16_t nb_desc,
1202                          unsigned int socket_id,
1203                          const struct rte_eth_txconf *tx_conf)
1204 {
1205         const struct rte_memzone *tz;
1206         struct igb_tx_queue *txq;
1207         struct e1000_hw     *hw;
1208         uint32_t size;
1209
1210         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211
1212         /*
1213          * Validate number of transmit descriptors.
1214          * It must not exceed hardware maximum, and must be multiple
1215          * of IGB_ALIGN.
1216          */
1217         if (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||
1218             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1219                 return -EINVAL;
1220         }
1221
1222         /*
1223          * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1224          * driver.
1225          */
1226         if (tx_conf->tx_free_thresh != 0)
1227                 PMD_INIT_LOG(WARNING, "The tx_free_thresh parameter is not "
1228                              "used for the 1G driver.");
1229         if (tx_conf->tx_rs_thresh != 0)
1230                 PMD_INIT_LOG(WARNING, "The tx_rs_thresh parameter is not "
1231                              "used for the 1G driver.");
1232         if (tx_conf->tx_thresh.wthresh == 0)
1233                 PMD_INIT_LOG(WARNING, "To improve 1G driver performance, "
1234                              "consider setting the TX WTHRESH value to 4, 8, "
1235                              "or 16.");
1236
1237         /* Free memory prior to re-allocation if needed */
1238         if (dev->data->tx_queues[queue_idx] != NULL) {
1239                 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1240                 dev->data->tx_queues[queue_idx] = NULL;
1241         }
1242
1243         /* First allocate the tx queue data structure */
1244         txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1245                                                         RTE_CACHE_LINE_SIZE);
1246         if (txq == NULL)
1247                 return (-ENOMEM);
1248
1249         /*
1250          * Allocate TX ring hardware descriptors. A memzone large enough to
1251          * handle the maximum ring size is allocated in order to allow for
1252          * resizing in later calls to the queue setup function.
1253          */
1254         size = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;
1255         tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1256                                         size, socket_id);
1257         if (tz == NULL) {
1258                 igb_tx_queue_release(txq);
1259                 return (-ENOMEM);
1260         }
1261
1262         txq->nb_tx_desc = nb_desc;
1263         txq->pthresh = tx_conf->tx_thresh.pthresh;
1264         txq->hthresh = tx_conf->tx_thresh.hthresh;
1265         txq->wthresh = tx_conf->tx_thresh.wthresh;
1266         if (txq->wthresh > 0 && hw->mac.type == e1000_82576)
1267                 txq->wthresh = 1;
1268         txq->queue_id = queue_idx;
1269         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1270                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1271         txq->port_id = dev->data->port_id;
1272
1273         txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1274 #ifndef RTE_LIBRTE_XEN_DOM0
1275         txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1276 #else
1277         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1278 #endif
1279          txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1280         /* Allocate software ring */
1281         txq->sw_ring = rte_zmalloc("txq->sw_ring",
1282                                    sizeof(struct igb_tx_entry) * nb_desc,
1283                                    RTE_CACHE_LINE_SIZE);
1284         if (txq->sw_ring == NULL) {
1285                 igb_tx_queue_release(txq);
1286                 return (-ENOMEM);
1287         }
1288         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1289                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1290
1291         igb_reset_tx_queue(txq, dev);
1292         dev->tx_pkt_burst = eth_igb_xmit_pkts;
1293         dev->data->tx_queues[queue_idx] = txq;
1294
1295         return (0);
1296 }
1297
1298 static void
1299 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1300 {
1301         unsigned i;
1302
1303         if (rxq->sw_ring != NULL) {
1304                 for (i = 0; i < rxq->nb_rx_desc; i++) {
1305                         if (rxq->sw_ring[i].mbuf != NULL) {
1306                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1307                                 rxq->sw_ring[i].mbuf = NULL;
1308                         }
1309                 }
1310         }
1311 }
1312
1313 static void
1314 igb_rx_queue_release(struct igb_rx_queue *rxq)
1315 {
1316         if (rxq != NULL) {
1317                 igb_rx_queue_release_mbufs(rxq);
1318                 rte_free(rxq->sw_ring);
1319                 rte_free(rxq);
1320         }
1321 }
1322
1323 void
1324 eth_igb_rx_queue_release(void *rxq)
1325 {
1326         igb_rx_queue_release(rxq);
1327 }
1328
1329 static void
1330 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1331 {
1332         static const union e1000_adv_rx_desc zeroed_desc = {{0}};
1333         unsigned i;
1334
1335         /* Zero out HW ring memory */
1336         for (i = 0; i < rxq->nb_rx_desc; i++) {
1337                 rxq->rx_ring[i] = zeroed_desc;
1338         }
1339
1340         rxq->rx_tail = 0;
1341         rxq->pkt_first_seg = NULL;
1342         rxq->pkt_last_seg = NULL;
1343 }
1344
1345 int
1346 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1347                          uint16_t queue_idx,
1348                          uint16_t nb_desc,
1349                          unsigned int socket_id,
1350                          const struct rte_eth_rxconf *rx_conf,
1351                          struct rte_mempool *mp)
1352 {
1353         const struct rte_memzone *rz;
1354         struct igb_rx_queue *rxq;
1355         struct e1000_hw     *hw;
1356         unsigned int size;
1357
1358         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359
1360         /*
1361          * Validate number of receive descriptors.
1362          * It must not exceed hardware maximum, and must be multiple
1363          * of IGB_ALIGN.
1364          */
1365         if (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||
1366             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1367                 return (-EINVAL);
1368         }
1369
1370         /* Free memory prior to re-allocation if needed */
1371         if (dev->data->rx_queues[queue_idx] != NULL) {
1372                 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1373                 dev->data->rx_queues[queue_idx] = NULL;
1374         }
1375
1376         /* First allocate the RX queue data structure. */
1377         rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1378                           RTE_CACHE_LINE_SIZE);
1379         if (rxq == NULL)
1380                 return (-ENOMEM);
1381         rxq->mb_pool = mp;
1382         rxq->nb_rx_desc = nb_desc;
1383         rxq->pthresh = rx_conf->rx_thresh.pthresh;
1384         rxq->hthresh = rx_conf->rx_thresh.hthresh;
1385         rxq->wthresh = rx_conf->rx_thresh.wthresh;
1386         if (rxq->wthresh > 0 && hw->mac.type == e1000_82576)
1387                 rxq->wthresh = 1;
1388         rxq->drop_en = rx_conf->rx_drop_en;
1389         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1390         rxq->queue_id = queue_idx;
1391         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1392                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1393         rxq->port_id = dev->data->port_id;
1394         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1395                                   ETHER_CRC_LEN);
1396
1397         /*
1398          *  Allocate RX ring hardware descriptors. A memzone large enough to
1399          *  handle the maximum ring size is allocated in order to allow for
1400          *  resizing in later calls to the queue setup function.
1401          */
1402         size = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;
1403         rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, size, socket_id);
1404         if (rz == NULL) {
1405                 igb_rx_queue_release(rxq);
1406                 return (-ENOMEM);
1407         }
1408         rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1409         rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1410 #ifndef RTE_LIBRTE_XEN_DOM0
1411         rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1412 #else
1413         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1414 #endif
1415         rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1416
1417         /* Allocate software ring. */
1418         rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1419                                    sizeof(struct igb_rx_entry) * nb_desc,
1420                                    RTE_CACHE_LINE_SIZE);
1421         if (rxq->sw_ring == NULL) {
1422                 igb_rx_queue_release(rxq);
1423                 return (-ENOMEM);
1424         }
1425         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1426                      rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1427
1428         dev->data->rx_queues[queue_idx] = rxq;
1429         igb_reset_rx_queue(rxq);
1430
1431         return 0;
1432 }
1433
1434 uint32_t
1435 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1436 {
1437 #define IGB_RXQ_SCAN_INTERVAL 4
1438         volatile union e1000_adv_rx_desc *rxdp;
1439         struct igb_rx_queue *rxq;
1440         uint32_t desc = 0;
1441
1442         if (rx_queue_id >= dev->data->nb_rx_queues) {
1443                 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
1444                 return 0;
1445         }
1446
1447         rxq = dev->data->rx_queues[rx_queue_id];
1448         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1449
1450         while ((desc < rxq->nb_rx_desc) &&
1451                 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1452                 desc += IGB_RXQ_SCAN_INTERVAL;
1453                 rxdp += IGB_RXQ_SCAN_INTERVAL;
1454                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1455                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1456                                 desc - rxq->nb_rx_desc]);
1457         }
1458
1459         return 0;
1460 }
1461
1462 int
1463 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1464 {
1465         volatile union e1000_adv_rx_desc *rxdp;
1466         struct igb_rx_queue *rxq = rx_queue;
1467         uint32_t desc;
1468
1469         if (unlikely(offset >= rxq->nb_rx_desc))
1470                 return 0;
1471         desc = rxq->rx_tail + offset;
1472         if (desc >= rxq->nb_rx_desc)
1473                 desc -= rxq->nb_rx_desc;
1474
1475         rxdp = &rxq->rx_ring[desc];
1476         return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1477 }
1478
1479 void
1480 igb_dev_clear_queues(struct rte_eth_dev *dev)
1481 {
1482         uint16_t i;
1483         struct igb_tx_queue *txq;
1484         struct igb_rx_queue *rxq;
1485
1486         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1487                 txq = dev->data->tx_queues[i];
1488                 if (txq != NULL) {
1489                         igb_tx_queue_release_mbufs(txq);
1490                         igb_reset_tx_queue(txq, dev);
1491                 }
1492         }
1493
1494         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1495                 rxq = dev->data->rx_queues[i];
1496                 if (rxq != NULL) {
1497                         igb_rx_queue_release_mbufs(rxq);
1498                         igb_reset_rx_queue(rxq);
1499                 }
1500         }
1501 }
1502
1503 /**
1504  * Receive Side Scaling (RSS).
1505  * See section 7.1.1.7 in the following document:
1506  *     "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1507  *
1508  * Principles:
1509  * The source and destination IP addresses of the IP header and the source and
1510  * destination ports of TCP/UDP headers, if any, of received packets are hashed
1511  * against a configurable random key to compute a 32-bit RSS hash result.
1512  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1513  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
1514  * RSS output index which is used as the RX queue index where to store the
1515  * received packets.
1516  * The following output is supplied in the RX write-back descriptor:
1517  *     - 32-bit result of the Microsoft RSS hash function,
1518  *     - 4-bit RSS type field.
1519  */
1520
1521 /*
1522  * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1523  * Used as the default key.
1524  */
1525 static uint8_t rss_intel_key[40] = {
1526         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1527         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1528         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1529         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1530         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1531 };
1532
1533 static void
1534 igb_rss_disable(struct rte_eth_dev *dev)
1535 {
1536         struct e1000_hw *hw;
1537         uint32_t mrqc;
1538
1539         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1541         mrqc &= ~E1000_MRQC_ENABLE_MASK;
1542         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1543 }
1544
1545 static void
1546 igb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf)
1547 {
1548         uint8_t  *hash_key;
1549         uint32_t rss_key;
1550         uint32_t mrqc;
1551         uint64_t rss_hf;
1552         uint16_t i;
1553
1554         hash_key = rss_conf->rss_key;
1555         if (hash_key != NULL) {
1556                 /* Fill in RSS hash key */
1557                 for (i = 0; i < 10; i++) {
1558                         rss_key  = hash_key[(i * 4)];
1559                         rss_key |= hash_key[(i * 4) + 1] << 8;
1560                         rss_key |= hash_key[(i * 4) + 2] << 16;
1561                         rss_key |= hash_key[(i * 4) + 3] << 24;
1562                         E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1563                 }
1564         }
1565
1566         /* Set configured hashing protocols in MRQC register */
1567         rss_hf = rss_conf->rss_hf;
1568         mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1569         if (rss_hf & ETH_RSS_IPV4)
1570                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1571         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1572                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1573         if (rss_hf & ETH_RSS_IPV6)
1574                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1575         if (rss_hf & ETH_RSS_IPV6_EX)
1576                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1577         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1578                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1579         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1580                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1581         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1582                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1583         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1584                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1585         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1586                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1587         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1588 }
1589
1590 int
1591 eth_igb_rss_hash_update(struct rte_eth_dev *dev,
1592                         struct rte_eth_rss_conf *rss_conf)
1593 {
1594         struct e1000_hw *hw;
1595         uint32_t mrqc;
1596         uint64_t rss_hf;
1597
1598         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599
1600         /*
1601          * Before changing anything, first check that the update RSS operation
1602          * does not attempt to disable RSS, if RSS was enabled at
1603          * initialization time, or does not attempt to enable RSS, if RSS was
1604          * disabled at initialization time.
1605          */
1606         rss_hf = rss_conf->rss_hf & IGB_RSS_OFFLOAD_ALL;
1607         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1608         if (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */
1609                 if (rss_hf != 0) /* Enable RSS */
1610                         return -(EINVAL);
1611                 return 0; /* Nothing to do */
1612         }
1613         /* RSS enabled */
1614         if (rss_hf == 0) /* Disable RSS */
1615                 return -(EINVAL);
1616         igb_hw_rss_hash_set(hw, rss_conf);
1617         return 0;
1618 }
1619
1620 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
1621                               struct rte_eth_rss_conf *rss_conf)
1622 {
1623         struct e1000_hw *hw;
1624         uint8_t *hash_key;
1625         uint32_t rss_key;
1626         uint32_t mrqc;
1627         uint64_t rss_hf;
1628         uint16_t i;
1629
1630         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         hash_key = rss_conf->rss_key;
1632         if (hash_key != NULL) {
1633                 /* Return RSS hash key */
1634                 for (i = 0; i < 10; i++) {
1635                         rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i);
1636                         hash_key[(i * 4)] = rss_key & 0x000000FF;
1637                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
1638                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
1639                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
1640                 }
1641         }
1642
1643         /* Get RSS functions configured in MRQC register */
1644         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1645         if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */
1646                 rss_conf->rss_hf = 0;
1647                 return 0;
1648         }
1649         rss_hf = 0;
1650         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4)
1651                 rss_hf |= ETH_RSS_IPV4;
1652         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP)
1653                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1654         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6)
1655                 rss_hf |= ETH_RSS_IPV6;
1656         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX)
1657                 rss_hf |= ETH_RSS_IPV6_EX;
1658         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP)
1659                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1660         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX)
1661                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
1662         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP)
1663                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1664         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP)
1665                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1666         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX)
1667                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
1668         rss_conf->rss_hf = rss_hf;
1669         return 0;
1670 }
1671
1672 static void
1673 igb_rss_configure(struct rte_eth_dev *dev)
1674 {
1675         struct rte_eth_rss_conf rss_conf;
1676         struct e1000_hw *hw;
1677         uint32_t shift;
1678         uint16_t i;
1679
1680         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681
1682         /* Fill in redirection table. */
1683         shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1684         for (i = 0; i < 128; i++) {
1685                 union e1000_reta {
1686                         uint32_t dword;
1687                         uint8_t  bytes[4];
1688                 } reta;
1689                 uint8_t q_idx;
1690
1691                 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1692                                    i % dev->data->nb_rx_queues : 0);
1693                 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1694                 if ((i & 3) == 3)
1695                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1696         }
1697
1698         /*
1699          * Configure the RSS key and the RSS protocols used to compute
1700          * the RSS hash of input packets.
1701          */
1702         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
1703         if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {
1704                 igb_rss_disable(dev);
1705                 return;
1706         }
1707         if (rss_conf.rss_key == NULL)
1708                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
1709         igb_hw_rss_hash_set(hw, &rss_conf);
1710 }
1711
1712 /*
1713  * Check if the mac type support VMDq or not.
1714  * Return 1 if it supports, otherwise, return 0.
1715  */
1716 static int
1717 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1718 {
1719         const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720
1721         switch (hw->mac.type) {
1722         case e1000_82576:
1723         case e1000_82580:
1724         case e1000_i350:
1725                 return 1;
1726         case e1000_82540:
1727         case e1000_82541:
1728         case e1000_82542:
1729         case e1000_82543:
1730         case e1000_82544:
1731         case e1000_82545:
1732         case e1000_82546:
1733         case e1000_82547:
1734         case e1000_82571:
1735         case e1000_82572:
1736         case e1000_82573:
1737         case e1000_82574:
1738         case e1000_82583:
1739         case e1000_i210:
1740         case e1000_i211:
1741         default:
1742                 PMD_INIT_LOG(ERR, "Cannot support VMDq feature");
1743                 return 0;
1744         }
1745 }
1746
1747 static int
1748 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1749 {
1750         struct rte_eth_vmdq_rx_conf *cfg;
1751         struct e1000_hw *hw;
1752         uint32_t mrqc, vt_ctl, vmolr, rctl;
1753         int i;
1754
1755         PMD_INIT_FUNC_TRACE();
1756
1757         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1759
1760         /* Check if mac type can support VMDq, return value of 0 means NOT support */
1761         if (igb_is_vmdq_supported(dev) == 0)
1762                 return -1;
1763
1764         igb_rss_disable(dev);
1765
1766         /* RCTL: eanble VLAN filter */
1767         rctl = E1000_READ_REG(hw, E1000_RCTL);
1768         rctl |= E1000_RCTL_VFE;
1769         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1770
1771         /* MRQC: enable vmdq */
1772         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1773         mrqc |= E1000_MRQC_ENABLE_VMDQ;
1774         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1775
1776         /* VTCTL:  pool selection according to VLAN tag */
1777         vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1778         if (cfg->enable_default_pool)
1779                 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1780         vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1781         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1782
1783         for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1784                 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1785                 vmolr &= ~(E1000_VMOLR_AUPE | E1000_VMOLR_ROMPE |
1786                         E1000_VMOLR_ROPE | E1000_VMOLR_BAM |
1787                         E1000_VMOLR_MPME);
1788
1789                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
1790                         vmolr |= E1000_VMOLR_AUPE;
1791                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
1792                         vmolr |= E1000_VMOLR_ROMPE;
1793                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
1794                         vmolr |= E1000_VMOLR_ROPE;
1795                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
1796                         vmolr |= E1000_VMOLR_BAM;
1797                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
1798                         vmolr |= E1000_VMOLR_MPME;
1799
1800                 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1801         }
1802
1803         /*
1804          * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1805          * Both 82576 and 82580 support it
1806          */
1807         if (hw->mac.type != e1000_i350) {
1808                 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1809                         vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1810                         vmolr |= E1000_VMOLR_STRVLAN;
1811                         E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1812                 }
1813         }
1814
1815         /* VFTA - enable all vlan filters */
1816         for (i = 0; i < IGB_VFTA_SIZE; i++)
1817                 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1818
1819         /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1820         if (hw->mac.type != e1000_82580)
1821                 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1822
1823         /*
1824          * RAH/RAL - allow pools to read specific mac addresses
1825          * In this case, all pools should be able to read from mac addr 0
1826          */
1827         E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1828         E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1829
1830         /* VLVF: set up filters for vlan tags as configured */
1831         for (i = 0; i < cfg->nb_pool_maps; i++) {
1832                 /* set vlan id in VF register and set the valid bit */
1833                 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1834                         (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1835                         ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1836                         E1000_VLVF_POOLSEL_MASK)));
1837         }
1838
1839         E1000_WRITE_FLUSH(hw);
1840
1841         return 0;
1842 }
1843
1844
1845 /*********************************************************************
1846  *
1847  *  Enable receive unit.
1848  *
1849  **********************************************************************/
1850
1851 static int
1852 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1853 {
1854         struct igb_rx_entry *rxe = rxq->sw_ring;
1855         uint64_t dma_addr;
1856         unsigned i;
1857
1858         /* Initialize software ring entries. */
1859         for (i = 0; i < rxq->nb_rx_desc; i++) {
1860                 volatile union e1000_adv_rx_desc *rxd;
1861                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1862
1863                 if (mbuf == NULL) {
1864                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1865                                      "queue_id=%hu", rxq->queue_id);
1866                         return (-ENOMEM);
1867                 }
1868                 dma_addr =
1869                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1870                 rxd = &rxq->rx_ring[i];
1871                 rxd->read.hdr_addr = dma_addr;
1872                 rxd->read.pkt_addr = dma_addr;
1873                 rxe[i].mbuf = mbuf;
1874         }
1875
1876         return 0;
1877 }
1878
1879 #define E1000_MRQC_DEF_Q_SHIFT               (3)
1880 static int
1881 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
1882 {
1883         struct e1000_hw *hw =
1884                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885         uint32_t mrqc;
1886
1887         if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
1888                 /*
1889                  * SRIOV active scheme
1890                  * FIXME if support RSS together with VMDq & SRIOV
1891                  */
1892                 mrqc = E1000_MRQC_ENABLE_VMDQ;
1893                 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
1894                 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
1895                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1896         } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
1897                 /*
1898                  * SRIOV inactive scheme
1899                  */
1900                 switch (dev->data->dev_conf.rxmode.mq_mode) {
1901                         case ETH_MQ_RX_RSS:
1902                                 igb_rss_configure(dev);
1903                                 break;
1904                         case ETH_MQ_RX_VMDQ_ONLY:
1905                                 /*Configure general VMDQ only RX parameters*/
1906                                 igb_vmdq_rx_hw_configure(dev);
1907                                 break;
1908                         case ETH_MQ_RX_NONE:
1909                                 /* if mq_mode is none, disable rss mode.*/
1910                         default:
1911                                 igb_rss_disable(dev);
1912                                 break;
1913                 }
1914         }
1915
1916         return 0;
1917 }
1918
1919 int
1920 eth_igb_rx_init(struct rte_eth_dev *dev)
1921 {
1922         struct e1000_hw     *hw;
1923         struct igb_rx_queue *rxq;
1924         uint32_t rctl;
1925         uint32_t rxcsum;
1926         uint32_t srrctl;
1927         uint16_t buf_size;
1928         uint16_t rctl_bsize;
1929         uint16_t i;
1930         int ret;
1931
1932         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         srrctl = 0;
1934
1935         /*
1936          * Make sure receives are disabled while setting
1937          * up the descriptor ring.
1938          */
1939         rctl = E1000_READ_REG(hw, E1000_RCTL);
1940         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1941
1942         /*
1943          * Configure support of jumbo frames, if any.
1944          */
1945         if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1946                 rctl |= E1000_RCTL_LPE;
1947
1948                 /*
1949                  * Set maximum packet length by default, and might be updated
1950                  * together with enabling/disabling dual VLAN.
1951                  */
1952                 E1000_WRITE_REG(hw, E1000_RLPML,
1953                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1954                                                 VLAN_TAG_SIZE);
1955         } else
1956                 rctl &= ~E1000_RCTL_LPE;
1957
1958         /* Configure and enable each RX queue. */
1959         rctl_bsize = 0;
1960         dev->rx_pkt_burst = eth_igb_recv_pkts;
1961         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1962                 uint64_t bus_addr;
1963                 uint32_t rxdctl;
1964
1965                 rxq = dev->data->rx_queues[i];
1966
1967                 /* Allocate buffers for descriptor rings and set up queue */
1968                 ret = igb_alloc_rx_queue_mbufs(rxq);
1969                 if (ret)
1970                         return ret;
1971
1972                 /*
1973                  * Reset crc_len in case it was changed after queue setup by a
1974                  *  call to configure
1975                  */
1976                 rxq->crc_len =
1977                         (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1978                                                         0 : ETHER_CRC_LEN);
1979
1980                 bus_addr = rxq->rx_ring_phys_addr;
1981                 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
1982                                 rxq->nb_rx_desc *
1983                                 sizeof(union e1000_adv_rx_desc));
1984                 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
1985                                 (uint32_t)(bus_addr >> 32));
1986                 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
1987
1988                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1989
1990                 /*
1991                  * Configure RX buffer size.
1992                  */
1993                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1994                         RTE_PKTMBUF_HEADROOM);
1995                 if (buf_size >= 1024) {
1996                         /*
1997                          * Configure the BSIZEPACKET field of the SRRCTL
1998                          * register of the queue.
1999                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2000                          * If this field is equal to 0b, then RCTL.BSIZE
2001                          * determines the RX packet buffer size.
2002                          */
2003                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2004                                    E1000_SRRCTL_BSIZEPKT_MASK);
2005                         buf_size = (uint16_t) ((srrctl &
2006                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2007                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2008
2009                         /* It adds dual VLAN length for supporting dual VLAN */
2010                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2011                                                 2 * VLAN_TAG_SIZE) > buf_size){
2012                                 if (!dev->data->scattered_rx)
2013                                         PMD_INIT_LOG(DEBUG,
2014                                                      "forcing scatter mode");
2015                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2016                                 dev->data->scattered_rx = 1;
2017                         }
2018                 } else {
2019                         /*
2020                          * Use BSIZE field of the device RCTL register.
2021                          */
2022                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2023                                 rctl_bsize = buf_size;
2024                         if (!dev->data->scattered_rx)
2025                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2026                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2027                         dev->data->scattered_rx = 1;
2028                 }
2029
2030                 /* Set if packets are dropped when no descriptors available */
2031                 if (rxq->drop_en)
2032                         srrctl |= E1000_SRRCTL_DROP_EN;
2033
2034                 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
2035
2036                 /* Enable this RX queue. */
2037                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
2038                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2039                 rxdctl &= 0xFFF00000;
2040                 rxdctl |= (rxq->pthresh & 0x1F);
2041                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2042                 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2043                 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
2044         }
2045
2046         if (dev->data->dev_conf.rxmode.enable_scatter) {
2047                 if (!dev->data->scattered_rx)
2048                         PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2049                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2050                 dev->data->scattered_rx = 1;
2051         }
2052
2053         /*
2054          * Setup BSIZE field of RCTL register, if needed.
2055          * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
2056          * register, since the code above configures the SRRCTL register of
2057          * the RX queue in such a case.
2058          * All configurable sizes are:
2059          * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
2060          *  8192: rctl |= (E1000_RCTL_SZ_8192  | E1000_RCTL_BSEX);
2061          *  4096: rctl |= (E1000_RCTL_SZ_4096  | E1000_RCTL_BSEX);
2062          *  2048: rctl |= E1000_RCTL_SZ_2048;
2063          *  1024: rctl |= E1000_RCTL_SZ_1024;
2064          *   512: rctl |= E1000_RCTL_SZ_512;
2065          *   256: rctl |= E1000_RCTL_SZ_256;
2066          */
2067         if (rctl_bsize > 0) {
2068                 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
2069                         rctl |= E1000_RCTL_SZ_512;
2070                 else /* 256 <= buf_size < 512 - use 256 */
2071                         rctl |= E1000_RCTL_SZ_256;
2072         }
2073
2074         /*
2075          * Configure RSS if device configured with multiple RX queues.
2076          */
2077         igb_dev_mq_rx_configure(dev);
2078
2079         /* Update the rctl since igb_dev_mq_rx_configure may change its value */
2080         rctl |= E1000_READ_REG(hw, E1000_RCTL);
2081
2082         /*
2083          * Setup the Checksum Register.
2084          * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
2085          */
2086         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2087         rxcsum |= E1000_RXCSUM_PCSD;
2088
2089         /* Enable both L3/L4 rx checksum offload */
2090         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
2091                 rxcsum |= (E1000_RXCSUM_IPOFL  | E1000_RXCSUM_TUOFL);
2092         else
2093                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2094         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2095
2096         /* Setup the Receive Control Register. */
2097         if (dev->data->dev_conf.rxmode.hw_strip_crc) {
2098                 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
2099
2100                 /* set STRCRC bit in all queues */
2101                 if (hw->mac.type == e1000_i350 ||
2102                     hw->mac.type == e1000_i210 ||
2103                     hw->mac.type == e1000_i211 ||
2104                     hw->mac.type == e1000_i354) {
2105                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2106                                 rxq = dev->data->rx_queues[i];
2107                                 uint32_t dvmolr = E1000_READ_REG(hw,
2108                                         E1000_DVMOLR(rxq->reg_idx));
2109                                 dvmolr |= E1000_DVMOLR_STRCRC;
2110                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2111                         }
2112                 }
2113         } else {
2114                 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
2115
2116                 /* clear STRCRC bit in all queues */
2117                 if (hw->mac.type == e1000_i350 ||
2118                     hw->mac.type == e1000_i210 ||
2119                     hw->mac.type == e1000_i211 ||
2120                     hw->mac.type == e1000_i354) {
2121                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2122                                 rxq = dev->data->rx_queues[i];
2123                                 uint32_t dvmolr = E1000_READ_REG(hw,
2124                                         E1000_DVMOLR(rxq->reg_idx));
2125                                 dvmolr &= ~E1000_DVMOLR_STRCRC;
2126                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2127                         }
2128                 }
2129         }
2130
2131         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2132         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2133                 E1000_RCTL_RDMTS_HALF |
2134                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2135
2136         /* Make sure VLAN Filters are off. */
2137         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
2138                 rctl &= ~E1000_RCTL_VFE;
2139         /* Don't store bad packets. */
2140         rctl &= ~E1000_RCTL_SBP;
2141
2142         /* Enable Receives. */
2143         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2144
2145         /*
2146          * Setup the HW Rx Head and Tail Descriptor Pointers.
2147          * This needs to be done after enable.
2148          */
2149         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2150                 rxq = dev->data->rx_queues[i];
2151                 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
2152                 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
2153         }
2154
2155         return 0;
2156 }
2157
2158 /*********************************************************************
2159  *
2160  *  Enable transmit unit.
2161  *
2162  **********************************************************************/
2163 void
2164 eth_igb_tx_init(struct rte_eth_dev *dev)
2165 {
2166         struct e1000_hw     *hw;
2167         struct igb_tx_queue *txq;
2168         uint32_t tctl;
2169         uint32_t txdctl;
2170         uint16_t i;
2171
2172         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173
2174         /* Setup the Base and Length of the Tx Descriptor Rings. */
2175         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2176                 uint64_t bus_addr;
2177                 txq = dev->data->tx_queues[i];
2178                 bus_addr = txq->tx_ring_phys_addr;
2179
2180                 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2181                                 txq->nb_tx_desc *
2182                                 sizeof(union e1000_adv_tx_desc));
2183                 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2184                                 (uint32_t)(bus_addr >> 32));
2185                 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2186
2187                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2188                 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2189                 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2190
2191                 /* Setup Transmit threshold registers. */
2192                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2193                 txdctl |= txq->pthresh & 0x1F;
2194                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2195                 txdctl |= ((txq->wthresh & 0x1F) << 16);
2196                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2197                 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2198         }
2199
2200         /* Program the Transmit Control Register. */
2201         tctl = E1000_READ_REG(hw, E1000_TCTL);
2202         tctl &= ~E1000_TCTL_CT;
2203         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2204                  (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2205
2206         e1000_config_collision_dist(hw);
2207
2208         /* This write will effectively turn on the transmit unit. */
2209         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2210 }
2211
2212 /*********************************************************************
2213  *
2214  *  Enable VF receive unit.
2215  *
2216  **********************************************************************/
2217 int
2218 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2219 {
2220         struct e1000_hw     *hw;
2221         struct igb_rx_queue *rxq;
2222         uint32_t srrctl;
2223         uint16_t buf_size;
2224         uint16_t rctl_bsize;
2225         uint16_t i;
2226         int ret;
2227
2228         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2229
2230         /* setup MTU */
2231         e1000_rlpml_set_vf(hw,
2232                 (uint16_t)(dev->data->dev_conf.rxmode.max_rx_pkt_len +
2233                 VLAN_TAG_SIZE));
2234
2235         /* Configure and enable each RX queue. */
2236         rctl_bsize = 0;
2237         dev->rx_pkt_burst = eth_igb_recv_pkts;
2238         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2239                 uint64_t bus_addr;
2240                 uint32_t rxdctl;
2241
2242                 rxq = dev->data->rx_queues[i];
2243
2244                 /* Allocate buffers for descriptor rings and set up queue */
2245                 ret = igb_alloc_rx_queue_mbufs(rxq);
2246                 if (ret)
2247                         return ret;
2248
2249                 bus_addr = rxq->rx_ring_phys_addr;
2250                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2251                                 rxq->nb_rx_desc *
2252                                 sizeof(union e1000_adv_rx_desc));
2253                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2254                                 (uint32_t)(bus_addr >> 32));
2255                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2256
2257                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2258
2259                 /*
2260                  * Configure RX buffer size.
2261                  */
2262                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2263                         RTE_PKTMBUF_HEADROOM);
2264                 if (buf_size >= 1024) {
2265                         /*
2266                          * Configure the BSIZEPACKET field of the SRRCTL
2267                          * register of the queue.
2268                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2269                          * If this field is equal to 0b, then RCTL.BSIZE
2270                          * determines the RX packet buffer size.
2271                          */
2272                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2273                                    E1000_SRRCTL_BSIZEPKT_MASK);
2274                         buf_size = (uint16_t) ((srrctl &
2275                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2276                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2277
2278                         /* It adds dual VLAN length for supporting dual VLAN */
2279                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2280                                                 2 * VLAN_TAG_SIZE) > buf_size){
2281                                 if (!dev->data->scattered_rx)
2282                                         PMD_INIT_LOG(DEBUG,
2283                                                      "forcing scatter mode");
2284                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2285                                 dev->data->scattered_rx = 1;
2286                         }
2287                 } else {
2288                         /*
2289                          * Use BSIZE field of the device RCTL register.
2290                          */
2291                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2292                                 rctl_bsize = buf_size;
2293                         if (!dev->data->scattered_rx)
2294                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2295                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2296                         dev->data->scattered_rx = 1;
2297                 }
2298
2299                 /* Set if packets are dropped when no descriptors available */
2300                 if (rxq->drop_en)
2301                         srrctl |= E1000_SRRCTL_DROP_EN;
2302
2303                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2304
2305                 /* Enable this RX queue. */
2306                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2307                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2308                 rxdctl &= 0xFFF00000;
2309                 rxdctl |= (rxq->pthresh & 0x1F);
2310                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2311                 if (hw->mac.type == e1000_vfadapt) {
2312                         /*
2313                          * Workaround of 82576 VF Erratum
2314                          * force set WTHRESH to 1
2315                          * to avoid Write-Back not triggered sometimes
2316                          */
2317                         rxdctl |= 0x10000;
2318                         PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !");
2319                 }
2320                 else
2321                         rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2322                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2323         }
2324
2325         if (dev->data->dev_conf.rxmode.enable_scatter) {
2326                 if (!dev->data->scattered_rx)
2327                         PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2328                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2329                 dev->data->scattered_rx = 1;
2330         }
2331
2332         /*
2333          * Setup the HW Rx Head and Tail Descriptor Pointers.
2334          * This needs to be done after enable.
2335          */
2336         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2337                 rxq = dev->data->rx_queues[i];
2338                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2339                 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2340         }
2341
2342         return 0;
2343 }
2344
2345 /*********************************************************************
2346  *
2347  *  Enable VF transmit unit.
2348  *
2349  **********************************************************************/
2350 void
2351 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2352 {
2353         struct e1000_hw     *hw;
2354         struct igb_tx_queue *txq;
2355         uint32_t txdctl;
2356         uint16_t i;
2357
2358         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359
2360         /* Setup the Base and Length of the Tx Descriptor Rings. */
2361         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2362                 uint64_t bus_addr;
2363
2364                 txq = dev->data->tx_queues[i];
2365                 bus_addr = txq->tx_ring_phys_addr;
2366                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2367                                 txq->nb_tx_desc *
2368                                 sizeof(union e1000_adv_tx_desc));
2369                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2370                                 (uint32_t)(bus_addr >> 32));
2371                 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2372
2373                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2374                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2375                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2376
2377                 /* Setup Transmit threshold registers. */
2378                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2379                 txdctl |= txq->pthresh & 0x1F;
2380                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2381                 if (hw->mac.type == e1000_82576) {
2382                         /*
2383                          * Workaround of 82576 VF Erratum
2384                          * force set WTHRESH to 1
2385                          * to avoid Write-Back not triggered sometimes
2386                          */
2387                         txdctl |= 0x10000;
2388                         PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !");
2389                 }
2390                 else
2391                         txdctl |= ((txq->wthresh & 0x1F) << 16);
2392                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2393                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2394         }
2395
2396 }