1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
15 #include <rte_interrupts.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
19 #include <rte_debug.h>
21 #include <rte_memory.h>
22 #include <rte_memcpy.h>
23 #include <rte_memzone.h>
24 #include <rte_launch.h>
26 #include <rte_per_lcore.h>
27 #include <rte_lcore.h>
28 #include <rte_atomic.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_mempool.h>
31 #include <rte_malloc.h>
33 #include <rte_ether.h>
34 #include <ethdev_driver.h>
35 #include <rte_prefetch.h>
40 #include <rte_string_fns.h>
42 #include "e1000_logs.h"
43 #include "base/e1000_api.h"
44 #include "e1000_ethdev.h"
46 #ifdef RTE_LIBRTE_IEEE1588
47 #define IGB_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
49 #define IGB_TX_IEEE1588_TMST 0
51 /* Bit Mask to indicate what bits required for building TX context */
52 #define IGB_TX_OFFLOAD_MASK ( \
63 #define IGB_TX_OFFLOAD_NOTSUP_MASK \
64 (PKT_TX_OFFLOAD_MASK ^ IGB_TX_OFFLOAD_MASK)
67 * Structure associated with each descriptor of the RX ring of a RX queue.
70 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
74 * Structure associated with each descriptor of the TX ring of a TX queue.
77 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
78 uint16_t next_id; /**< Index of next descriptor in ring. */
79 uint16_t last_id; /**< Index of last scattered descriptor. */
86 IGB_RXQ_FLAG_LB_BSWAP_VLAN = 0x01,
90 * Structure associated with each RX queue.
93 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
94 volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
95 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
96 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
97 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
98 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
99 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
100 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
101 uint16_t nb_rx_desc; /**< number of RX descriptors. */
102 uint16_t rx_tail; /**< current value of RDT register. */
103 uint16_t nb_rx_hold; /**< number of held free RX desc. */
104 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
105 uint16_t queue_id; /**< RX queue index. */
106 uint16_t reg_idx; /**< RX queue register index. */
107 uint16_t port_id; /**< Device port identifier. */
108 uint8_t pthresh; /**< Prefetch threshold register. */
109 uint8_t hthresh; /**< Host threshold register. */
110 uint8_t wthresh; /**< Write-back threshold register. */
111 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
112 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
113 uint32_t flags; /**< RX flags. */
114 uint64_t offloads; /**< offloads of DEV_RX_OFFLOAD_* */
115 const struct rte_memzone *mz;
119 * Hardware context number
121 enum igb_advctx_num {
122 IGB_CTX_0 = 0, /**< CTX0 */
123 IGB_CTX_1 = 1, /**< CTX1 */
124 IGB_CTX_NUM = 2, /**< CTX_NUM */
127 /** Offload features */
128 union igb_tx_offload {
131 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
132 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
133 uint64_t vlan_tci:16; /**< VLAN Tag Control Identifier(CPU order). */
134 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
135 uint64_t tso_segsz:16; /**< TCP TSO segment size. */
137 /* uint64_t unused:8; */
142 * Compare mask for igb_tx_offload.data,
143 * should be in sync with igb_tx_offload layout.
145 #define TX_MACIP_LEN_CMP_MASK 0x000000000000FFFFULL /**< L2L3 header mask. */
146 #define TX_VLAN_CMP_MASK 0x00000000FFFF0000ULL /**< Vlan mask. */
147 #define TX_TCP_LEN_CMP_MASK 0x000000FF00000000ULL /**< TCP header mask. */
148 #define TX_TSO_MSS_CMP_MASK 0x00FFFF0000000000ULL /**< TSO segsz mask. */
149 /** Mac + IP + TCP + Mss mask. */
150 #define TX_TSO_CMP_MASK \
151 (TX_MACIP_LEN_CMP_MASK | TX_TCP_LEN_CMP_MASK | TX_TSO_MSS_CMP_MASK)
154 * Strucutre to check if new context need be built
156 struct igb_advctx_info {
157 uint64_t flags; /**< ol_flags related to context build. */
158 /** tx offload: vlan, tso, l2-l3-l4 lengths. */
159 union igb_tx_offload tx_offload;
160 /** compare mask for tx offload. */
161 union igb_tx_offload tx_offload_mask;
165 * Structure associated with each TX queue.
167 struct igb_tx_queue {
168 volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
169 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
170 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
171 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
172 uint32_t txd_type; /**< Device-specific TXD type */
173 uint16_t nb_tx_desc; /**< number of TX descriptors. */
174 uint16_t tx_tail; /**< Current value of TDT register. */
176 /**< Index of first used TX descriptor. */
177 uint16_t queue_id; /**< TX queue index. */
178 uint16_t reg_idx; /**< TX queue register index. */
179 uint16_t port_id; /**< Device port identifier. */
180 uint8_t pthresh; /**< Prefetch threshold register. */
181 uint8_t hthresh; /**< Host threshold register. */
182 uint8_t wthresh; /**< Write-back threshold register. */
184 /**< Current used hardware descriptor. */
186 /**< Start context position for transmit queue. */
187 struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
188 /**< Hardware context history.*/
189 uint64_t offloads; /**< offloads of DEV_TX_OFFLOAD_* */
190 const struct rte_memzone *mz;
194 #define RTE_PMD_USE_PREFETCH
197 #ifdef RTE_PMD_USE_PREFETCH
198 #define rte_igb_prefetch(p) rte_prefetch0(p)
200 #define rte_igb_prefetch(p) do {} while(0)
203 #ifdef RTE_PMD_PACKET_PREFETCH
204 #define rte_packet_prefetch(p) rte_prefetch1(p)
206 #define rte_packet_prefetch(p) do {} while(0)
210 * Macro for VMDq feature for 1 GbE NIC.
212 #define E1000_VMOLR_SIZE (8)
213 #define IGB_TSO_MAX_HDRLEN (512)
214 #define IGB_TSO_MAX_MSS (9216)
216 /*********************************************************************
220 **********************************************************************/
223 *There're some limitations in hardware for TCP segmentation offload. We
224 *should check whether the parameters are valid.
226 static inline uint64_t
227 check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para)
229 if (!(ol_req & PKT_TX_TCP_SEG))
231 if ((ol_para.tso_segsz > IGB_TSO_MAX_MSS) || (ol_para.l2_len +
232 ol_para.l3_len + ol_para.l4_len > IGB_TSO_MAX_HDRLEN)) {
233 ol_req &= ~PKT_TX_TCP_SEG;
234 ol_req |= PKT_TX_TCP_CKSUM;
240 * Advanced context descriptor are almost same between igb/ixgbe
241 * This is a separate function, looking for optimization opportunity here
242 * Rework required to go with the pre-defined values.
246 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
247 volatile struct e1000_adv_tx_context_desc *ctx_txd,
248 uint64_t ol_flags, union igb_tx_offload tx_offload)
250 uint32_t type_tucmd_mlhl;
251 uint32_t mss_l4len_idx;
252 uint32_t ctx_idx, ctx_curr;
253 uint32_t vlan_macip_lens;
254 union igb_tx_offload tx_offload_mask;
256 ctx_curr = txq->ctx_curr;
257 ctx_idx = ctx_curr + txq->ctx_start;
259 tx_offload_mask.data = 0;
262 /* Specify which HW CTX to upload. */
263 mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
265 if (ol_flags & PKT_TX_VLAN_PKT)
266 tx_offload_mask.data |= TX_VLAN_CMP_MASK;
268 /* check if TCP segmentation required for this packet */
269 if (ol_flags & PKT_TX_TCP_SEG) {
270 /* implies IP cksum in IPv4 */
271 if (ol_flags & PKT_TX_IP_CKSUM)
272 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 |
273 E1000_ADVTXD_TUCMD_L4T_TCP |
274 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
276 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV6 |
277 E1000_ADVTXD_TUCMD_L4T_TCP |
278 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
280 tx_offload_mask.data |= TX_TSO_CMP_MASK;
281 mss_l4len_idx |= tx_offload.tso_segsz << E1000_ADVTXD_MSS_SHIFT;
282 mss_l4len_idx |= tx_offload.l4_len << E1000_ADVTXD_L4LEN_SHIFT;
283 } else { /* no TSO, check if hardware checksum is needed */
284 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
285 tx_offload_mask.data |= TX_MACIP_LEN_CMP_MASK;
287 if (ol_flags & PKT_TX_IP_CKSUM)
288 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
290 switch (ol_flags & PKT_TX_L4_MASK) {
291 case PKT_TX_UDP_CKSUM:
292 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
293 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
294 mss_l4len_idx |= sizeof(struct rte_udp_hdr)
295 << E1000_ADVTXD_L4LEN_SHIFT;
297 case PKT_TX_TCP_CKSUM:
298 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
299 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
300 mss_l4len_idx |= sizeof(struct rte_tcp_hdr)
301 << E1000_ADVTXD_L4LEN_SHIFT;
303 case PKT_TX_SCTP_CKSUM:
304 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
305 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
306 mss_l4len_idx |= sizeof(struct rte_sctp_hdr)
307 << E1000_ADVTXD_L4LEN_SHIFT;
310 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
311 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
316 txq->ctx_cache[ctx_curr].flags = ol_flags;
317 txq->ctx_cache[ctx_curr].tx_offload.data =
318 tx_offload_mask.data & tx_offload.data;
319 txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;
321 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
322 vlan_macip_lens = (uint32_t)tx_offload.data;
323 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
324 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
325 ctx_txd->u.seqnum_seed = 0;
329 * Check which hardware context can be used. Use the existing match
330 * or create a new context descriptor.
332 static inline uint32_t
333 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
334 union igb_tx_offload tx_offload)
336 /* If match with the current context */
337 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
338 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
339 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
340 return txq->ctx_curr;
343 /* If match with the second context */
345 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
346 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
347 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
348 return txq->ctx_curr;
351 /* Mismatch, use the previous context */
355 static inline uint32_t
356 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
358 static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
359 static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
362 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
363 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
364 tmp |= l4_olinfo[(ol_flags & PKT_TX_TCP_SEG) != 0];
368 static inline uint32_t
369 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
372 static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
373 static uint32_t tso_cmd[2] = {0, E1000_ADVTXD_DCMD_TSE};
374 cmdtype = vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
375 cmdtype |= tso_cmd[(ol_flags & PKT_TX_TCP_SEG) != 0];
380 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
383 struct igb_tx_queue *txq;
384 struct igb_tx_entry *sw_ring;
385 struct igb_tx_entry *txe, *txn;
386 volatile union e1000_adv_tx_desc *txr;
387 volatile union e1000_adv_tx_desc *txd;
388 struct rte_mbuf *tx_pkt;
389 struct rte_mbuf *m_seg;
390 uint64_t buf_dma_addr;
391 uint32_t olinfo_status;
392 uint32_t cmd_type_len;
401 uint32_t new_ctx = 0;
403 union igb_tx_offload tx_offload = {0};
406 sw_ring = txq->sw_ring;
408 tx_id = txq->tx_tail;
409 txe = &sw_ring[tx_id];
411 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
413 pkt_len = tx_pkt->pkt_len;
415 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
418 * The number of descriptors that must be allocated for a
419 * packet is the number of segments of that packet, plus 1
420 * Context Descriptor for the VLAN Tag Identifier, if any.
421 * Determine the last TX descriptor to allocate in the TX ring
422 * for the packet, starting from the current position (tx_id)
425 tx_last = (uint16_t) (tx_id + tx_pkt->nb_segs - 1);
427 ol_flags = tx_pkt->ol_flags;
428 tx_ol_req = ol_flags & IGB_TX_OFFLOAD_MASK;
430 /* If a Context Descriptor need be built . */
432 tx_offload.l2_len = tx_pkt->l2_len;
433 tx_offload.l3_len = tx_pkt->l3_len;
434 tx_offload.l4_len = tx_pkt->l4_len;
435 tx_offload.vlan_tci = tx_pkt->vlan_tci;
436 tx_offload.tso_segsz = tx_pkt->tso_segsz;
437 tx_ol_req = check_tso_para(tx_ol_req, tx_offload);
439 ctx = what_advctx_update(txq, tx_ol_req, tx_offload);
440 /* Only allocate context descriptor if required*/
441 new_ctx = (ctx == IGB_CTX_NUM);
442 ctx = txq->ctx_curr + txq->ctx_start;
443 tx_last = (uint16_t) (tx_last + new_ctx);
445 if (tx_last >= txq->nb_tx_desc)
446 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
448 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
449 " tx_first=%u tx_last=%u",
450 (unsigned) txq->port_id,
451 (unsigned) txq->queue_id,
457 * Check if there are enough free descriptors in the TX ring
458 * to transmit the next packet.
459 * This operation is based on the two following rules:
461 * 1- Only check that the last needed TX descriptor can be
462 * allocated (by construction, if that descriptor is free,
463 * all intermediate ones are also free).
465 * For this purpose, the index of the last TX descriptor
466 * used for a packet (the "last descriptor" of a packet)
467 * is recorded in the TX entries (the last one included)
468 * that are associated with all TX descriptors allocated
471 * 2- Avoid to allocate the last free TX descriptor of the
472 * ring, in order to never set the TDT register with the
473 * same value stored in parallel by the NIC in the TDH
474 * register, which makes the TX engine of the NIC enter
475 * in a deadlock situation.
477 * By extension, avoid to allocate a free descriptor that
478 * belongs to the last set of free descriptors allocated
479 * to the same packet previously transmitted.
483 * The "last descriptor" of the previously sent packet, if any,
484 * which used the last descriptor to allocate.
486 tx_end = sw_ring[tx_last].last_id;
489 * The next descriptor following that "last descriptor" in the
492 tx_end = sw_ring[tx_end].next_id;
495 * The "last descriptor" associated with that next descriptor.
497 tx_end = sw_ring[tx_end].last_id;
500 * Check that this descriptor is free.
502 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
509 * Set common flags of all TX Data Descriptors.
511 * The following bits must be set in all Data Descriptors:
512 * - E1000_ADVTXD_DTYP_DATA
513 * - E1000_ADVTXD_DCMD_DEXT
515 * The following bits must be set in the first Data Descriptor
516 * and are ignored in the other ones:
517 * - E1000_ADVTXD_DCMD_IFCS
518 * - E1000_ADVTXD_MAC_1588
519 * - E1000_ADVTXD_DCMD_VLE
521 * The following bits must only be set in the last Data
523 * - E1000_TXD_CMD_EOP
525 * The following bits can be set in any Data Descriptor, but
526 * are only set in the last Data Descriptor:
529 cmd_type_len = txq->txd_type |
530 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
531 if (tx_ol_req & PKT_TX_TCP_SEG)
532 pkt_len -= (tx_pkt->l2_len + tx_pkt->l3_len + tx_pkt->l4_len);
533 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
534 #if defined(RTE_LIBRTE_IEEE1588)
535 if (ol_flags & PKT_TX_IEEE1588_TMST)
536 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
539 /* Setup TX Advanced context descriptor if required */
541 volatile struct e1000_adv_tx_context_desc *
544 ctx_txd = (volatile struct
545 e1000_adv_tx_context_desc *)
548 txn = &sw_ring[txe->next_id];
549 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
551 if (txe->mbuf != NULL) {
552 rte_pktmbuf_free_seg(txe->mbuf);
556 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload);
558 txe->last_id = tx_last;
559 tx_id = txe->next_id;
563 /* Setup the TX Advanced Data Descriptor */
564 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(tx_ol_req);
565 olinfo_status |= tx_desc_cksum_flags_to_olinfo(tx_ol_req);
566 olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
571 txn = &sw_ring[txe->next_id];
574 if (txe->mbuf != NULL)
575 rte_pktmbuf_free_seg(txe->mbuf);
579 * Set up transmit descriptor.
581 slen = (uint16_t) m_seg->data_len;
582 buf_dma_addr = rte_mbuf_data_iova(m_seg);
583 txd->read.buffer_addr =
584 rte_cpu_to_le_64(buf_dma_addr);
585 txd->read.cmd_type_len =
586 rte_cpu_to_le_32(cmd_type_len | slen);
587 txd->read.olinfo_status =
588 rte_cpu_to_le_32(olinfo_status);
589 txe->last_id = tx_last;
590 tx_id = txe->next_id;
593 } while (m_seg != NULL);
596 * The last packet data descriptor needs End Of Packet (EOP)
597 * and Report Status (RS).
599 txd->read.cmd_type_len |=
600 rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
606 * Set the Transmit Descriptor Tail (TDT).
608 E1000_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
609 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
610 (unsigned) txq->port_id, (unsigned) txq->queue_id,
611 (unsigned) tx_id, (unsigned) nb_tx);
612 txq->tx_tail = tx_id;
617 /*********************************************************************
621 **********************************************************************/
623 eth_igb_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
629 for (i = 0; i < nb_pkts; i++) {
632 /* Check some limitations for TSO in hardware */
633 if (m->ol_flags & PKT_TX_TCP_SEG)
634 if ((m->tso_segsz > IGB_TSO_MAX_MSS) ||
635 (m->l2_len + m->l3_len + m->l4_len >
636 IGB_TSO_MAX_HDRLEN)) {
641 if (m->ol_flags & IGB_TX_OFFLOAD_NOTSUP_MASK) {
646 #ifdef RTE_ETHDEV_DEBUG_TX
647 ret = rte_validate_tx_offload(m);
653 ret = rte_net_intel_cksum_prepare(m);
663 /*********************************************************************
667 **********************************************************************/
668 #define IGB_PACKET_TYPE_IPV4 0X01
669 #define IGB_PACKET_TYPE_IPV4_TCP 0X11
670 #define IGB_PACKET_TYPE_IPV4_UDP 0X21
671 #define IGB_PACKET_TYPE_IPV4_SCTP 0X41
672 #define IGB_PACKET_TYPE_IPV4_EXT 0X03
673 #define IGB_PACKET_TYPE_IPV4_EXT_SCTP 0X43
674 #define IGB_PACKET_TYPE_IPV6 0X04
675 #define IGB_PACKET_TYPE_IPV6_TCP 0X14
676 #define IGB_PACKET_TYPE_IPV6_UDP 0X24
677 #define IGB_PACKET_TYPE_IPV6_EXT 0X0C
678 #define IGB_PACKET_TYPE_IPV6_EXT_TCP 0X1C
679 #define IGB_PACKET_TYPE_IPV6_EXT_UDP 0X2C
680 #define IGB_PACKET_TYPE_IPV4_IPV6 0X05
681 #define IGB_PACKET_TYPE_IPV4_IPV6_TCP 0X15
682 #define IGB_PACKET_TYPE_IPV4_IPV6_UDP 0X25
683 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
684 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
685 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
686 #define IGB_PACKET_TYPE_MAX 0X80
687 #define IGB_PACKET_TYPE_MASK 0X7F
688 #define IGB_PACKET_TYPE_SHIFT 0X04
689 static inline uint32_t
690 igb_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
692 static const uint32_t
693 ptype_table[IGB_PACKET_TYPE_MAX] __rte_cache_aligned = {
694 [IGB_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
696 [IGB_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
697 RTE_PTYPE_L3_IPV4_EXT,
698 [IGB_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
700 [IGB_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
701 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
702 RTE_PTYPE_INNER_L3_IPV6,
703 [IGB_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
704 RTE_PTYPE_L3_IPV6_EXT,
705 [IGB_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
706 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
707 RTE_PTYPE_INNER_L3_IPV6_EXT,
708 [IGB_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
709 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
710 [IGB_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
711 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
712 [IGB_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
713 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
714 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
715 [IGB_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
716 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
717 [IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
718 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
719 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
720 [IGB_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
721 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
722 [IGB_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
723 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
724 [IGB_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
725 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
726 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
727 [IGB_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
728 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
729 [IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
730 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
731 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
732 [IGB_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
733 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
734 [IGB_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
735 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
737 if (unlikely(pkt_info & E1000_RXDADV_PKTTYPE_ETQF))
738 return RTE_PTYPE_UNKNOWN;
740 pkt_info = (pkt_info >> IGB_PACKET_TYPE_SHIFT) & IGB_PACKET_TYPE_MASK;
742 return ptype_table[pkt_info];
745 static inline uint64_t
746 rx_desc_hlen_type_rss_to_pkt_flags(struct igb_rx_queue *rxq, uint32_t hl_tp_rs)
748 uint64_t pkt_flags = ((hl_tp_rs & 0x0F) == 0) ? 0 : PKT_RX_RSS_HASH;
750 #if defined(RTE_LIBRTE_IEEE1588)
751 static uint32_t ip_pkt_etqf_map[8] = {
752 0, 0, 0, PKT_RX_IEEE1588_PTP,
756 struct rte_eth_dev dev = rte_eth_devices[rxq->port_id];
757 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev.data->dev_private);
759 /* EtherType is in bits 8:10 in Packet Type, and not in the default 0:2 */
760 if (hw->mac.type == e1000_i210)
761 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 12) & 0x07];
763 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07];
771 static inline uint64_t
772 rx_desc_status_to_pkt_flags(uint32_t rx_status)
776 /* Check if VLAN present */
777 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
778 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED : 0);
780 #if defined(RTE_LIBRTE_IEEE1588)
781 if (rx_status & E1000_RXD_STAT_TMST)
782 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
787 static inline uint64_t
788 rx_desc_error_to_pkt_flags(uint32_t rx_status)
791 * Bit 30: IPE, IPv4 checksum error
792 * Bit 29: L4I, L4I integrity error
795 static uint64_t error_to_pkt_flags_map[4] = {
796 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
797 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
798 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
799 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
801 return error_to_pkt_flags_map[(rx_status >>
802 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
806 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
809 struct igb_rx_queue *rxq;
810 volatile union e1000_adv_rx_desc *rx_ring;
811 volatile union e1000_adv_rx_desc *rxdp;
812 struct igb_rx_entry *sw_ring;
813 struct igb_rx_entry *rxe;
814 struct rte_mbuf *rxm;
815 struct rte_mbuf *nmb;
816 union e1000_adv_rx_desc rxd;
819 uint32_t hlen_type_rss;
829 rx_id = rxq->rx_tail;
830 rx_ring = rxq->rx_ring;
831 sw_ring = rxq->sw_ring;
832 while (nb_rx < nb_pkts) {
834 * The order of operations here is important as the DD status
835 * bit must not be read after any other descriptor fields.
836 * rx_ring and rxdp are pointing to volatile data so the order
837 * of accesses cannot be reordered by the compiler. If they were
838 * not volatile, they could be reordered which could lead to
839 * using invalid descriptor fields when read from rxd.
841 rxdp = &rx_ring[rx_id];
842 staterr = rxdp->wb.upper.status_error;
843 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
850 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
851 * likely to be invalid and to be dropped by the various
852 * validation checks performed by the network stack.
854 * Allocate a new mbuf to replenish the RX ring descriptor.
855 * If the allocation fails:
856 * - arrange for that RX descriptor to be the first one
857 * being parsed the next time the receive function is
858 * invoked [on the same queue].
860 * - Stop parsing the RX ring and return immediately.
862 * This policy do not drop the packet received in the RX
863 * descriptor for which the allocation of a new mbuf failed.
864 * Thus, it allows that packet to be later retrieved if
865 * mbuf have been freed in the mean time.
866 * As a side effect, holding RX descriptors instead of
867 * systematically giving them back to the NIC may lead to
868 * RX ring exhaustion situations.
869 * However, the NIC can gracefully prevent such situations
870 * to happen by sending specific "back-pressure" flow control
871 * frames to its peer(s).
873 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
874 "staterr=0x%x pkt_len=%u",
875 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
876 (unsigned) rx_id, (unsigned) staterr,
877 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
879 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
881 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
882 "queue_id=%u", (unsigned) rxq->port_id,
883 (unsigned) rxq->queue_id);
884 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
889 rxe = &sw_ring[rx_id];
891 if (rx_id == rxq->nb_rx_desc)
894 /* Prefetch next mbuf while processing current one. */
895 rte_igb_prefetch(sw_ring[rx_id].mbuf);
898 * When next RX descriptor is on a cache-line boundary,
899 * prefetch the next 4 RX descriptors and the next 8 pointers
902 if ((rx_id & 0x3) == 0) {
903 rte_igb_prefetch(&rx_ring[rx_id]);
904 rte_igb_prefetch(&sw_ring[rx_id]);
910 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
911 rxdp->read.hdr_addr = 0;
912 rxdp->read.pkt_addr = dma_addr;
915 * Initialize the returned mbuf.
916 * 1) setup generic mbuf fields:
917 * - number of segments,
920 * - RX port identifier.
921 * 2) integrate hardware offload data, if any:
923 * - IP checksum flag,
924 * - VLAN TCI, if any,
927 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
929 rxm->data_off = RTE_PKTMBUF_HEADROOM;
930 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
933 rxm->pkt_len = pkt_len;
934 rxm->data_len = pkt_len;
935 rxm->port = rxq->port_id;
937 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
938 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
941 * The vlan_tci field is only valid when PKT_RX_VLAN is
942 * set in the pkt_flags field and must be in CPU byte order.
944 if ((staterr & rte_cpu_to_le_32(E1000_RXDEXT_STATERR_LB)) &&
945 (rxq->flags & IGB_RXQ_FLAG_LB_BSWAP_VLAN)) {
946 rxm->vlan_tci = rte_be_to_cpu_16(rxd.wb.upper.vlan);
948 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
950 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(rxq, hlen_type_rss);
951 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
952 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
953 rxm->ol_flags = pkt_flags;
954 rxm->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.lower.
955 lo_dword.hs_rss.pkt_info);
958 * Store the mbuf address into the next entry of the array
959 * of returned packets.
961 rx_pkts[nb_rx++] = rxm;
963 rxq->rx_tail = rx_id;
966 * If the number of free RX descriptors is greater than the RX free
967 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
969 * Update the RDT with the value of the last processed RX descriptor
970 * minus 1, to guarantee that the RDT register is never equal to the
971 * RDH register, which creates a "full" ring situtation from the
972 * hardware point of view...
974 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
975 if (nb_hold > rxq->rx_free_thresh) {
976 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
977 "nb_hold=%u nb_rx=%u",
978 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
979 (unsigned) rx_id, (unsigned) nb_hold,
981 rx_id = (uint16_t) ((rx_id == 0) ?
982 (rxq->nb_rx_desc - 1) : (rx_id - 1));
983 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
986 rxq->nb_rx_hold = nb_hold;
991 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
994 struct igb_rx_queue *rxq;
995 volatile union e1000_adv_rx_desc *rx_ring;
996 volatile union e1000_adv_rx_desc *rxdp;
997 struct igb_rx_entry *sw_ring;
998 struct igb_rx_entry *rxe;
999 struct rte_mbuf *first_seg;
1000 struct rte_mbuf *last_seg;
1001 struct rte_mbuf *rxm;
1002 struct rte_mbuf *nmb;
1003 union e1000_adv_rx_desc rxd;
1004 uint64_t dma; /* Physical address of mbuf data buffer */
1006 uint32_t hlen_type_rss;
1016 rx_id = rxq->rx_tail;
1017 rx_ring = rxq->rx_ring;
1018 sw_ring = rxq->sw_ring;
1021 * Retrieve RX context of current packet, if any.
1023 first_seg = rxq->pkt_first_seg;
1024 last_seg = rxq->pkt_last_seg;
1026 while (nb_rx < nb_pkts) {
1029 * The order of operations here is important as the DD status
1030 * bit must not be read after any other descriptor fields.
1031 * rx_ring and rxdp are pointing to volatile data so the order
1032 * of accesses cannot be reordered by the compiler. If they were
1033 * not volatile, they could be reordered which could lead to
1034 * using invalid descriptor fields when read from rxd.
1036 rxdp = &rx_ring[rx_id];
1037 staterr = rxdp->wb.upper.status_error;
1038 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
1045 * Allocate a new mbuf to replenish the RX ring descriptor.
1046 * If the allocation fails:
1047 * - arrange for that RX descriptor to be the first one
1048 * being parsed the next time the receive function is
1049 * invoked [on the same queue].
1051 * - Stop parsing the RX ring and return immediately.
1053 * This policy does not drop the packet received in the RX
1054 * descriptor for which the allocation of a new mbuf failed.
1055 * Thus, it allows that packet to be later retrieved if
1056 * mbuf have been freed in the mean time.
1057 * As a side effect, holding RX descriptors instead of
1058 * systematically giving them back to the NIC may lead to
1059 * RX ring exhaustion situations.
1060 * However, the NIC can gracefully prevent such situations
1061 * to happen by sending specific "back-pressure" flow control
1062 * frames to its peer(s).
1064 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1065 "staterr=0x%x data_len=%u",
1066 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1067 (unsigned) rx_id, (unsigned) staterr,
1068 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1070 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1072 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1073 "queue_id=%u", (unsigned) rxq->port_id,
1074 (unsigned) rxq->queue_id);
1075 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1080 rxe = &sw_ring[rx_id];
1082 if (rx_id == rxq->nb_rx_desc)
1085 /* Prefetch next mbuf while processing current one. */
1086 rte_igb_prefetch(sw_ring[rx_id].mbuf);
1089 * When next RX descriptor is on a cache-line boundary,
1090 * prefetch the next 4 RX descriptors and the next 8 pointers
1093 if ((rx_id & 0x3) == 0) {
1094 rte_igb_prefetch(&rx_ring[rx_id]);
1095 rte_igb_prefetch(&sw_ring[rx_id]);
1099 * Update RX descriptor with the physical address of the new
1100 * data buffer of the new allocated mbuf.
1104 dma = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1105 rxdp->read.pkt_addr = dma;
1106 rxdp->read.hdr_addr = 0;
1109 * Set data length & data buffer address of mbuf.
1111 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1112 rxm->data_len = data_len;
1113 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1116 * If this is the first buffer of the received packet,
1117 * set the pointer to the first mbuf of the packet and
1118 * initialize its context.
1119 * Otherwise, update the total length and the number of segments
1120 * of the current scattered packet, and update the pointer to
1121 * the last mbuf of the current packet.
1123 if (first_seg == NULL) {
1125 first_seg->pkt_len = data_len;
1126 first_seg->nb_segs = 1;
1128 first_seg->pkt_len += data_len;
1129 first_seg->nb_segs++;
1130 last_seg->next = rxm;
1134 * If this is not the last buffer of the received packet,
1135 * update the pointer to the last mbuf of the current scattered
1136 * packet and continue to parse the RX ring.
1138 if (! (staterr & E1000_RXD_STAT_EOP)) {
1144 * This is the last buffer of the received packet.
1145 * If the CRC is not stripped by the hardware:
1146 * - Subtract the CRC length from the total packet length.
1147 * - If the last buffer only contains the whole CRC or a part
1148 * of it, free the mbuf associated to the last buffer.
1149 * If part of the CRC is also contained in the previous
1150 * mbuf, subtract the length of that CRC part from the
1151 * data length of the previous mbuf.
1154 if (unlikely(rxq->crc_len > 0)) {
1155 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1156 if (data_len <= RTE_ETHER_CRC_LEN) {
1157 rte_pktmbuf_free_seg(rxm);
1158 first_seg->nb_segs--;
1159 last_seg->data_len = (uint16_t)
1160 (last_seg->data_len -
1161 (RTE_ETHER_CRC_LEN - data_len));
1162 last_seg->next = NULL;
1164 rxm->data_len = (uint16_t)
1165 (data_len - RTE_ETHER_CRC_LEN);
1169 * Initialize the first mbuf of the returned packet:
1170 * - RX port identifier,
1171 * - hardware offload data, if any:
1172 * - RSS flag & hash,
1173 * - IP checksum flag,
1174 * - VLAN TCI, if any,
1177 first_seg->port = rxq->port_id;
1178 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1181 * The vlan_tci field is only valid when PKT_RX_VLAN is
1182 * set in the pkt_flags field and must be in CPU byte order.
1184 if ((staterr & rte_cpu_to_le_32(E1000_RXDEXT_STATERR_LB)) &&
1185 (rxq->flags & IGB_RXQ_FLAG_LB_BSWAP_VLAN)) {
1186 first_seg->vlan_tci =
1187 rte_be_to_cpu_16(rxd.wb.upper.vlan);
1189 first_seg->vlan_tci =
1190 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1192 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1193 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(rxq, hlen_type_rss);
1194 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1195 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1196 first_seg->ol_flags = pkt_flags;
1197 first_seg->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.
1198 lower.lo_dword.hs_rss.pkt_info);
1200 /* Prefetch data of first segment, if configured to do so. */
1201 rte_packet_prefetch((char *)first_seg->buf_addr +
1202 first_seg->data_off);
1205 * Store the mbuf address into the next entry of the array
1206 * of returned packets.
1208 rx_pkts[nb_rx++] = first_seg;
1211 * Setup receipt context for a new packet.
1217 * Record index of the next RX descriptor to probe.
1219 rxq->rx_tail = rx_id;
1222 * Save receive context.
1224 rxq->pkt_first_seg = first_seg;
1225 rxq->pkt_last_seg = last_seg;
1228 * If the number of free RX descriptors is greater than the RX free
1229 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1231 * Update the RDT with the value of the last processed RX descriptor
1232 * minus 1, to guarantee that the RDT register is never equal to the
1233 * RDH register, which creates a "full" ring situtation from the
1234 * hardware point of view...
1236 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1237 if (nb_hold > rxq->rx_free_thresh) {
1238 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1239 "nb_hold=%u nb_rx=%u",
1240 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1241 (unsigned) rx_id, (unsigned) nb_hold,
1243 rx_id = (uint16_t) ((rx_id == 0) ?
1244 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1245 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1248 rxq->nb_rx_hold = nb_hold;
1253 * Maximum number of Ring Descriptors.
1255 * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1256 * desscriptors should meet the following condition:
1257 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1261 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1265 if (txq->sw_ring != NULL) {
1266 for (i = 0; i < txq->nb_tx_desc; i++) {
1267 if (txq->sw_ring[i].mbuf != NULL) {
1268 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1269 txq->sw_ring[i].mbuf = NULL;
1276 igb_tx_queue_release(struct igb_tx_queue *txq)
1279 igb_tx_queue_release_mbufs(txq);
1280 rte_free(txq->sw_ring);
1281 rte_memzone_free(txq->mz);
1287 eth_igb_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1289 igb_tx_queue_release(dev->data->tx_queues[qid]);
1293 igb_tx_done_cleanup(struct igb_tx_queue *txq, uint32_t free_cnt)
1295 struct igb_tx_entry *sw_ring;
1296 volatile union e1000_adv_tx_desc *txr;
1297 uint16_t tx_first; /* First segment analyzed. */
1298 uint16_t tx_id; /* Current segment being processed. */
1299 uint16_t tx_last; /* Last segment in the current packet. */
1300 uint16_t tx_next; /* First segment of the next packet. */
1306 sw_ring = txq->sw_ring;
1309 /* tx_tail is the last sent packet on the sw_ring. Goto the end
1310 * of that packet (the last segment in the packet chain) and
1311 * then the next segment will be the start of the oldest segment
1312 * in the sw_ring. This is the first packet that will be
1313 * attempted to be freed.
1316 /* Get last segment in most recently added packet. */
1317 tx_first = sw_ring[txq->tx_tail].last_id;
1319 /* Get the next segment, which is the oldest segment in ring. */
1320 tx_first = sw_ring[tx_first].next_id;
1322 /* Set the current index to the first. */
1325 /* Loop through each packet. For each packet, verify that an
1326 * mbuf exists and that the last segment is free. If so, free
1330 tx_last = sw_ring[tx_id].last_id;
1332 if (sw_ring[tx_last].mbuf) {
1333 if (txr[tx_last].wb.status &
1334 E1000_TXD_STAT_DD) {
1335 /* Increment the number of packets
1340 /* Get the start of the next packet. */
1341 tx_next = sw_ring[tx_last].next_id;
1343 /* Loop through all segments in a
1347 if (sw_ring[tx_id].mbuf) {
1348 rte_pktmbuf_free_seg(
1349 sw_ring[tx_id].mbuf);
1350 sw_ring[tx_id].mbuf = NULL;
1351 sw_ring[tx_id].last_id = tx_id;
1354 /* Move to next segemnt. */
1355 tx_id = sw_ring[tx_id].next_id;
1357 } while (tx_id != tx_next);
1359 if (unlikely(count == (int)free_cnt))
1362 /* mbuf still in use, nothing left to
1368 /* There are multiple reasons to be here:
1369 * 1) All the packets on the ring have been
1370 * freed - tx_id is equal to tx_first
1371 * and some packets have been freed.
1373 * 2) Interfaces has not sent a rings worth of
1374 * packets yet, so the segment after tail is
1375 * still empty. Or a previous call to this
1376 * function freed some of the segments but
1377 * not all so there is a hole in the list.
1378 * Hopefully this is a rare case.
1379 * - Walk the list and find the next mbuf. If
1380 * there isn't one, then done.
1382 if (likely(tx_id == tx_first && count != 0))
1385 /* Walk the list and find the next mbuf, if any. */
1387 /* Move to next segemnt. */
1388 tx_id = sw_ring[tx_id].next_id;
1390 if (sw_ring[tx_id].mbuf)
1393 } while (tx_id != tx_first);
1395 /* Determine why previous loop bailed. If there
1396 * is not an mbuf, done.
1398 if (!sw_ring[tx_id].mbuf)
1407 eth_igb_tx_done_cleanup(void *txq, uint32_t free_cnt)
1409 return igb_tx_done_cleanup(txq, free_cnt);
1413 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1418 memset((void*)&txq->ctx_cache, 0,
1419 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1423 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1425 static const union e1000_adv_tx_desc zeroed_desc = {{0}};
1426 struct igb_tx_entry *txe = txq->sw_ring;
1428 struct e1000_hw *hw;
1430 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431 /* Zero out HW ring memory */
1432 for (i = 0; i < txq->nb_tx_desc; i++) {
1433 txq->tx_ring[i] = zeroed_desc;
1436 /* Initialize ring entries */
1437 prev = (uint16_t)(txq->nb_tx_desc - 1);
1438 for (i = 0; i < txq->nb_tx_desc; i++) {
1439 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1441 txd->wb.status = E1000_TXD_STAT_DD;
1444 txe[prev].next_id = i;
1448 txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1449 /* 82575 specific, each tx queue will use 2 hw contexts */
1450 if (hw->mac.type == e1000_82575)
1451 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1453 igb_reset_tx_queue_stat(txq);
1457 igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1459 uint64_t tx_offload_capa;
1462 tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1463 DEV_TX_OFFLOAD_IPV4_CKSUM |
1464 DEV_TX_OFFLOAD_UDP_CKSUM |
1465 DEV_TX_OFFLOAD_TCP_CKSUM |
1466 DEV_TX_OFFLOAD_SCTP_CKSUM |
1467 DEV_TX_OFFLOAD_TCP_TSO |
1468 DEV_TX_OFFLOAD_MULTI_SEGS;
1470 return tx_offload_capa;
1474 igb_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1476 uint64_t tx_queue_offload_capa;
1478 tx_queue_offload_capa = igb_get_tx_port_offloads_capa(dev);
1480 return tx_queue_offload_capa;
1484 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1487 unsigned int socket_id,
1488 const struct rte_eth_txconf *tx_conf)
1490 const struct rte_memzone *tz;
1491 struct igb_tx_queue *txq;
1492 struct e1000_hw *hw;
1496 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1498 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501 * Validate number of transmit descriptors.
1502 * It must not exceed hardware maximum, and must be multiple
1505 if (nb_desc % IGB_TXD_ALIGN != 0 ||
1506 (nb_desc > E1000_MAX_RING_DESC) ||
1507 (nb_desc < E1000_MIN_RING_DESC)) {
1512 * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1515 if (tx_conf->tx_free_thresh != 0)
1516 PMD_INIT_LOG(INFO, "The tx_free_thresh parameter is not "
1517 "used for the 1G driver.");
1518 if (tx_conf->tx_rs_thresh != 0)
1519 PMD_INIT_LOG(INFO, "The tx_rs_thresh parameter is not "
1520 "used for the 1G driver.");
1521 if (tx_conf->tx_thresh.wthresh == 0 && hw->mac.type != e1000_82576)
1522 PMD_INIT_LOG(INFO, "To improve 1G driver performance, "
1523 "consider setting the TX WTHRESH value to 4, 8, "
1526 /* Free memory prior to re-allocation if needed */
1527 if (dev->data->tx_queues[queue_idx] != NULL) {
1528 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1529 dev->data->tx_queues[queue_idx] = NULL;
1532 /* First allocate the tx queue data structure */
1533 txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1534 RTE_CACHE_LINE_SIZE);
1539 * Allocate TX ring hardware descriptors. A memzone large enough to
1540 * handle the maximum ring size is allocated in order to allow for
1541 * resizing in later calls to the queue setup function.
1543 size = sizeof(union e1000_adv_tx_desc) * E1000_MAX_RING_DESC;
1544 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, size,
1545 E1000_ALIGN, socket_id);
1547 igb_tx_queue_release(txq);
1552 txq->nb_tx_desc = nb_desc;
1553 txq->pthresh = tx_conf->tx_thresh.pthresh;
1554 txq->hthresh = tx_conf->tx_thresh.hthresh;
1555 txq->wthresh = tx_conf->tx_thresh.wthresh;
1556 if (txq->wthresh > 0 && hw->mac.type == e1000_82576)
1558 txq->queue_id = queue_idx;
1559 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1560 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1561 txq->port_id = dev->data->port_id;
1563 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1564 txq->tx_ring_phys_addr = tz->iova;
1566 txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1567 /* Allocate software ring */
1568 txq->sw_ring = rte_zmalloc("txq->sw_ring",
1569 sizeof(struct igb_tx_entry) * nb_desc,
1570 RTE_CACHE_LINE_SIZE);
1571 if (txq->sw_ring == NULL) {
1572 igb_tx_queue_release(txq);
1575 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1576 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1578 igb_reset_tx_queue(txq, dev);
1579 dev->tx_pkt_burst = eth_igb_xmit_pkts;
1580 dev->tx_pkt_prepare = ð_igb_prep_pkts;
1581 dev->data->tx_queues[queue_idx] = txq;
1582 txq->offloads = offloads;
1588 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1592 if (rxq->sw_ring != NULL) {
1593 for (i = 0; i < rxq->nb_rx_desc; i++) {
1594 if (rxq->sw_ring[i].mbuf != NULL) {
1595 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1596 rxq->sw_ring[i].mbuf = NULL;
1603 igb_rx_queue_release(struct igb_rx_queue *rxq)
1606 igb_rx_queue_release_mbufs(rxq);
1607 rte_free(rxq->sw_ring);
1608 rte_memzone_free(rxq->mz);
1614 eth_igb_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1616 igb_rx_queue_release(dev->data->rx_queues[qid]);
1620 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1622 static const union e1000_adv_rx_desc zeroed_desc = {{0}};
1625 /* Zero out HW ring memory */
1626 for (i = 0; i < rxq->nb_rx_desc; i++) {
1627 rxq->rx_ring[i] = zeroed_desc;
1631 rxq->pkt_first_seg = NULL;
1632 rxq->pkt_last_seg = NULL;
1636 igb_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1638 uint64_t rx_offload_capa;
1639 struct e1000_hw *hw;
1641 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643 rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1644 DEV_RX_OFFLOAD_VLAN_FILTER |
1645 DEV_RX_OFFLOAD_IPV4_CKSUM |
1646 DEV_RX_OFFLOAD_UDP_CKSUM |
1647 DEV_RX_OFFLOAD_TCP_CKSUM |
1648 DEV_RX_OFFLOAD_KEEP_CRC |
1649 DEV_RX_OFFLOAD_SCATTER |
1650 DEV_RX_OFFLOAD_RSS_HASH;
1652 if (hw->mac.type == e1000_i350 ||
1653 hw->mac.type == e1000_i210 ||
1654 hw->mac.type == e1000_i211)
1655 rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_EXTEND;
1657 return rx_offload_capa;
1661 igb_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1663 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664 uint64_t rx_queue_offload_capa;
1666 switch (hw->mac.type) {
1667 case e1000_vfadapt_i350:
1669 * As only one Rx queue can be used, let per queue offloading
1670 * capability be same to per port queue offloading capability
1671 * for better convenience.
1673 rx_queue_offload_capa = igb_get_rx_port_offloads_capa(dev);
1676 rx_queue_offload_capa = 0;
1678 return rx_queue_offload_capa;
1682 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1685 unsigned int socket_id,
1686 const struct rte_eth_rxconf *rx_conf,
1687 struct rte_mempool *mp)
1689 const struct rte_memzone *rz;
1690 struct igb_rx_queue *rxq;
1691 struct e1000_hw *hw;
1695 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1697 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 * Validate number of receive descriptors.
1701 * It must not exceed hardware maximum, and must be multiple
1704 if (nb_desc % IGB_RXD_ALIGN != 0 ||
1705 (nb_desc > E1000_MAX_RING_DESC) ||
1706 (nb_desc < E1000_MIN_RING_DESC)) {
1710 /* Free memory prior to re-allocation if needed */
1711 if (dev->data->rx_queues[queue_idx] != NULL) {
1712 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1713 dev->data->rx_queues[queue_idx] = NULL;
1716 /* First allocate the RX queue data structure. */
1717 rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1718 RTE_CACHE_LINE_SIZE);
1721 rxq->offloads = offloads;
1723 rxq->nb_rx_desc = nb_desc;
1724 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1725 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1726 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1727 if (rxq->wthresh > 0 &&
1728 (hw->mac.type == e1000_82576 || hw->mac.type == e1000_vfadapt_i350))
1730 rxq->drop_en = rx_conf->rx_drop_en;
1731 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1732 rxq->queue_id = queue_idx;
1733 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1734 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1735 rxq->port_id = dev->data->port_id;
1736 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1737 rxq->crc_len = RTE_ETHER_CRC_LEN;
1742 * Allocate RX ring hardware descriptors. A memzone large enough to
1743 * handle the maximum ring size is allocated in order to allow for
1744 * resizing in later calls to the queue setup function.
1746 size = sizeof(union e1000_adv_rx_desc) * E1000_MAX_RING_DESC;
1747 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size,
1748 E1000_ALIGN, socket_id);
1750 igb_rx_queue_release(rxq);
1755 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1756 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1757 rxq->rx_ring_phys_addr = rz->iova;
1758 rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1760 /* Allocate software ring. */
1761 rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1762 sizeof(struct igb_rx_entry) * nb_desc,
1763 RTE_CACHE_LINE_SIZE);
1764 if (rxq->sw_ring == NULL) {
1765 igb_rx_queue_release(rxq);
1768 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1769 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1771 dev->data->rx_queues[queue_idx] = rxq;
1772 igb_reset_rx_queue(rxq);
1778 eth_igb_rx_queue_count(void *rx_queue)
1780 #define IGB_RXQ_SCAN_INTERVAL 4
1781 volatile union e1000_adv_rx_desc *rxdp;
1782 struct igb_rx_queue *rxq;
1786 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1788 while ((desc < rxq->nb_rx_desc) &&
1789 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1790 desc += IGB_RXQ_SCAN_INTERVAL;
1791 rxdp += IGB_RXQ_SCAN_INTERVAL;
1792 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1793 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1794 desc - rxq->nb_rx_desc]);
1801 eth_igb_rx_descriptor_status(void *rx_queue, uint16_t offset)
1803 struct igb_rx_queue *rxq = rx_queue;
1804 volatile uint32_t *status;
1807 if (unlikely(offset >= rxq->nb_rx_desc))
1810 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1811 return RTE_ETH_RX_DESC_UNAVAIL;
1813 desc = rxq->rx_tail + offset;
1814 if (desc >= rxq->nb_rx_desc)
1815 desc -= rxq->nb_rx_desc;
1817 status = &rxq->rx_ring[desc].wb.upper.status_error;
1818 if (*status & rte_cpu_to_le_32(E1000_RXD_STAT_DD))
1819 return RTE_ETH_RX_DESC_DONE;
1821 return RTE_ETH_RX_DESC_AVAIL;
1825 eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset)
1827 struct igb_tx_queue *txq = tx_queue;
1828 volatile uint32_t *status;
1831 if (unlikely(offset >= txq->nb_tx_desc))
1834 desc = txq->tx_tail + offset;
1835 if (desc >= txq->nb_tx_desc)
1836 desc -= txq->nb_tx_desc;
1838 status = &txq->tx_ring[desc].wb.status;
1839 if (*status & rte_cpu_to_le_32(E1000_TXD_STAT_DD))
1840 return RTE_ETH_TX_DESC_DONE;
1842 return RTE_ETH_TX_DESC_FULL;
1846 igb_dev_clear_queues(struct rte_eth_dev *dev)
1849 struct igb_tx_queue *txq;
1850 struct igb_rx_queue *rxq;
1852 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1853 txq = dev->data->tx_queues[i];
1855 igb_tx_queue_release_mbufs(txq);
1856 igb_reset_tx_queue(txq, dev);
1860 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1861 rxq = dev->data->rx_queues[i];
1863 igb_rx_queue_release_mbufs(rxq);
1864 igb_reset_rx_queue(rxq);
1870 igb_dev_free_queues(struct rte_eth_dev *dev)
1874 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1875 eth_igb_rx_queue_release(dev, i);
1876 dev->data->rx_queues[i] = NULL;
1878 dev->data->nb_rx_queues = 0;
1880 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1881 eth_igb_tx_queue_release(dev, i);
1882 dev->data->tx_queues[i] = NULL;
1884 dev->data->nb_tx_queues = 0;
1888 * Receive Side Scaling (RSS).
1889 * See section 7.1.1.7 in the following document:
1890 * "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1893 * The source and destination IP addresses of the IP header and the source and
1894 * destination ports of TCP/UDP headers, if any, of received packets are hashed
1895 * against a configurable random key to compute a 32-bit RSS hash result.
1896 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1897 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
1898 * RSS output index which is used as the RX queue index where to store the
1900 * The following output is supplied in the RX write-back descriptor:
1901 * - 32-bit result of the Microsoft RSS hash function,
1902 * - 4-bit RSS type field.
1906 * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1907 * Used as the default key.
1909 static uint8_t rss_intel_key[40] = {
1910 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1911 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1912 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1913 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1914 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1918 igb_rss_disable(struct rte_eth_dev *dev)
1920 struct e1000_hw *hw;
1923 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1925 mrqc &= ~E1000_MRQC_ENABLE_MASK;
1926 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1930 igb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf)
1938 hash_key = rss_conf->rss_key;
1939 if (hash_key != NULL) {
1940 /* Fill in RSS hash key */
1941 for (i = 0; i < 10; i++) {
1942 rss_key = hash_key[(i * 4)];
1943 rss_key |= hash_key[(i * 4) + 1] << 8;
1944 rss_key |= hash_key[(i * 4) + 2] << 16;
1945 rss_key |= hash_key[(i * 4) + 3] << 24;
1946 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1950 /* Set configured hashing protocols in MRQC register */
1951 rss_hf = rss_conf->rss_hf;
1952 mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1953 if (rss_hf & ETH_RSS_IPV4)
1954 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1955 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1956 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1957 if (rss_hf & ETH_RSS_IPV6)
1958 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1959 if (rss_hf & ETH_RSS_IPV6_EX)
1960 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1961 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1962 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1963 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1964 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1965 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1966 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1967 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1968 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1969 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1970 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1971 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1975 eth_igb_rss_hash_update(struct rte_eth_dev *dev,
1976 struct rte_eth_rss_conf *rss_conf)
1978 struct e1000_hw *hw;
1982 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 * Before changing anything, first check that the update RSS operation
1986 * does not attempt to disable RSS, if RSS was enabled at
1987 * initialization time, or does not attempt to enable RSS, if RSS was
1988 * disabled at initialization time.
1990 rss_hf = rss_conf->rss_hf & IGB_RSS_OFFLOAD_ALL;
1991 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1992 if (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */
1993 if (rss_hf != 0) /* Enable RSS */
1995 return 0; /* Nothing to do */
1998 if (rss_hf == 0) /* Disable RSS */
2000 igb_hw_rss_hash_set(hw, rss_conf);
2004 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
2005 struct rte_eth_rss_conf *rss_conf)
2007 struct e1000_hw *hw;
2014 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2015 hash_key = rss_conf->rss_key;
2016 if (hash_key != NULL) {
2017 /* Return RSS hash key */
2018 for (i = 0; i < 10; i++) {
2019 rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i);
2020 hash_key[(i * 4)] = rss_key & 0x000000FF;
2021 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2022 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2023 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2027 /* Get RSS functions configured in MRQC register */
2028 mrqc = E1000_READ_REG(hw, E1000_MRQC);
2029 if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */
2030 rss_conf->rss_hf = 0;
2034 if (mrqc & E1000_MRQC_RSS_FIELD_IPV4)
2035 rss_hf |= ETH_RSS_IPV4;
2036 if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP)
2037 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2038 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6)
2039 rss_hf |= ETH_RSS_IPV6;
2040 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX)
2041 rss_hf |= ETH_RSS_IPV6_EX;
2042 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP)
2043 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2044 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX)
2045 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2046 if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP)
2047 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2048 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP)
2049 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2050 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX)
2051 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2052 rss_conf->rss_hf = rss_hf;
2057 igb_rss_configure(struct rte_eth_dev *dev)
2059 struct rte_eth_rss_conf rss_conf;
2060 struct e1000_hw *hw;
2064 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066 /* Fill in redirection table. */
2067 shift = (hw->mac.type == e1000_82575) ? 6 : 0;
2068 for (i = 0; i < 128; i++) {
2075 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
2076 i % dev->data->nb_rx_queues : 0);
2077 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
2079 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
2083 * Configure the RSS key and the RSS protocols used to compute
2084 * the RSS hash of input packets.
2086 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2087 if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {
2088 igb_rss_disable(dev);
2091 if (rss_conf.rss_key == NULL)
2092 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2093 igb_hw_rss_hash_set(hw, &rss_conf);
2097 * Check if the mac type support VMDq or not.
2098 * Return 1 if it supports, otherwise, return 0.
2101 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
2103 const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 switch (hw->mac.type) {
2126 PMD_INIT_LOG(ERR, "Cannot support VMDq feature");
2132 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
2134 struct rte_eth_vmdq_rx_conf *cfg;
2135 struct e1000_hw *hw;
2136 uint32_t mrqc, vt_ctl, vmolr, rctl;
2139 PMD_INIT_FUNC_TRACE();
2141 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
2144 /* Check if mac type can support VMDq, return value of 0 means NOT support */
2145 if (igb_is_vmdq_supported(dev) == 0)
2148 igb_rss_disable(dev);
2150 /* RCTL: eanble VLAN filter */
2151 rctl = E1000_READ_REG(hw, E1000_RCTL);
2152 rctl |= E1000_RCTL_VFE;
2153 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2155 /* MRQC: enable vmdq */
2156 mrqc = E1000_READ_REG(hw, E1000_MRQC);
2157 mrqc |= E1000_MRQC_ENABLE_VMDQ;
2158 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2160 /* VTCTL: pool selection according to VLAN tag */
2161 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2162 if (cfg->enable_default_pool)
2163 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
2164 vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
2165 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2167 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
2168 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
2169 vmolr &= ~(E1000_VMOLR_AUPE | E1000_VMOLR_ROMPE |
2170 E1000_VMOLR_ROPE | E1000_VMOLR_BAM |
2173 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
2174 vmolr |= E1000_VMOLR_AUPE;
2175 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
2176 vmolr |= E1000_VMOLR_ROMPE;
2177 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
2178 vmolr |= E1000_VMOLR_ROPE;
2179 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
2180 vmolr |= E1000_VMOLR_BAM;
2181 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
2182 vmolr |= E1000_VMOLR_MPME;
2184 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
2188 * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
2189 * Both 82576 and 82580 support it
2191 if (hw->mac.type != e1000_i350) {
2192 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
2193 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
2194 vmolr |= E1000_VMOLR_STRVLAN;
2195 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
2199 /* VFTA - enable all vlan filters */
2200 for (i = 0; i < IGB_VFTA_SIZE; i++)
2201 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
2203 /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
2204 if (hw->mac.type != e1000_82580)
2205 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
2208 * RAH/RAL - allow pools to read specific mac addresses
2209 * In this case, all pools should be able to read from mac addr 0
2211 E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
2212 E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
2214 /* VLVF: set up filters for vlan tags as configured */
2215 for (i = 0; i < cfg->nb_pool_maps; i++) {
2216 /* set vlan id in VF register and set the valid bit */
2217 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
2218 (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
2219 ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
2220 E1000_VLVF_POOLSEL_MASK)));
2223 E1000_WRITE_FLUSH(hw);
2229 /*********************************************************************
2231 * Enable receive unit.
2233 **********************************************************************/
2236 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
2238 struct igb_rx_entry *rxe = rxq->sw_ring;
2242 /* Initialize software ring entries. */
2243 for (i = 0; i < rxq->nb_rx_desc; i++) {
2244 volatile union e1000_adv_rx_desc *rxd;
2245 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
2248 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
2249 "queue_id=%hu", rxq->queue_id);
2253 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2254 rxd = &rxq->rx_ring[i];
2255 rxd->read.hdr_addr = 0;
2256 rxd->read.pkt_addr = dma_addr;
2263 #define E1000_MRQC_DEF_Q_SHIFT (3)
2265 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
2267 struct e1000_hw *hw =
2268 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271 if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
2273 * SRIOV active scheme
2274 * FIXME if support RSS together with VMDq & SRIOV
2276 mrqc = E1000_MRQC_ENABLE_VMDQ;
2277 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
2278 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
2279 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2280 } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
2282 * SRIOV inactive scheme
2284 switch (dev->data->dev_conf.rxmode.mq_mode) {
2286 igb_rss_configure(dev);
2288 case ETH_MQ_RX_VMDQ_ONLY:
2289 /*Configure general VMDQ only RX parameters*/
2290 igb_vmdq_rx_hw_configure(dev);
2292 case ETH_MQ_RX_NONE:
2293 /* if mq_mode is none, disable rss mode.*/
2295 igb_rss_disable(dev);
2304 eth_igb_rx_init(struct rte_eth_dev *dev)
2306 struct rte_eth_rxmode *rxmode;
2307 struct e1000_hw *hw;
2308 struct igb_rx_queue *rxq;
2313 uint16_t rctl_bsize;
2318 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322 * Make sure receives are disabled while setting
2323 * up the descriptor ring.
2325 rctl = E1000_READ_REG(hw, E1000_RCTL);
2326 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2328 rxmode = &dev->data->dev_conf.rxmode;
2331 * Configure support of jumbo frames, if any.
2333 max_len = dev->data->mtu + E1000_ETH_OVERHEAD;
2334 if (dev->data->mtu > RTE_ETHER_MTU) {
2335 rctl |= E1000_RCTL_LPE;
2338 * Set maximum packet length by default, and might be updated
2339 * together with enabling/disabling dual VLAN.
2341 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2342 max_len += VLAN_TAG_SIZE;
2344 E1000_WRITE_REG(hw, E1000_RLPML, max_len);
2346 rctl &= ~E1000_RCTL_LPE;
2348 /* Configure and enable each RX queue. */
2350 dev->rx_pkt_burst = eth_igb_recv_pkts;
2351 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2355 rxq = dev->data->rx_queues[i];
2359 * i350 and i354 vlan packets have vlan tags byte swapped.
2361 if (hw->mac.type == e1000_i350 || hw->mac.type == e1000_i354) {
2362 rxq->flags |= IGB_RXQ_FLAG_LB_BSWAP_VLAN;
2363 PMD_INIT_LOG(DEBUG, "IGB rx vlan bswap required");
2365 PMD_INIT_LOG(DEBUG, "IGB rx vlan bswap not required");
2368 /* Allocate buffers for descriptor rings and set up queue */
2369 ret = igb_alloc_rx_queue_mbufs(rxq);
2374 * Reset crc_len in case it was changed after queue setup by a
2377 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
2378 rxq->crc_len = RTE_ETHER_CRC_LEN;
2382 bus_addr = rxq->rx_ring_phys_addr;
2383 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
2385 sizeof(union e1000_adv_rx_desc));
2386 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
2387 (uint32_t)(bus_addr >> 32));
2388 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
2390 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2393 * Configure RX buffer size.
2395 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2396 RTE_PKTMBUF_HEADROOM);
2397 if (buf_size >= 1024) {
2399 * Configure the BSIZEPACKET field of the SRRCTL
2400 * register of the queue.
2401 * Value is in 1 KB resolution, from 1 KB to 127 KB.
2402 * If this field is equal to 0b, then RCTL.BSIZE
2403 * determines the RX packet buffer size.
2405 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2406 E1000_SRRCTL_BSIZEPKT_MASK);
2407 buf_size = (uint16_t) ((srrctl &
2408 E1000_SRRCTL_BSIZEPKT_MASK) <<
2409 E1000_SRRCTL_BSIZEPKT_SHIFT);
2411 /* It adds dual VLAN length for supporting dual VLAN */
2412 if ((max_len + 2 * VLAN_TAG_SIZE) > buf_size) {
2413 if (!dev->data->scattered_rx)
2415 "forcing scatter mode");
2416 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2417 dev->data->scattered_rx = 1;
2421 * Use BSIZE field of the device RCTL register.
2423 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2424 rctl_bsize = buf_size;
2425 if (!dev->data->scattered_rx)
2426 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2427 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2428 dev->data->scattered_rx = 1;
2431 /* Set if packets are dropped when no descriptors available */
2433 srrctl |= E1000_SRRCTL_DROP_EN;
2435 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
2437 /* Enable this RX queue. */
2438 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
2439 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2440 rxdctl &= 0xFFF00000;
2441 rxdctl |= (rxq->pthresh & 0x1F);
2442 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2443 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2444 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
2447 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
2448 if (!dev->data->scattered_rx)
2449 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2450 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2451 dev->data->scattered_rx = 1;
2455 * Setup BSIZE field of RCTL register, if needed.
2456 * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
2457 * register, since the code above configures the SRRCTL register of
2458 * the RX queue in such a case.
2459 * All configurable sizes are:
2460 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
2461 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
2462 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
2463 * 2048: rctl |= E1000_RCTL_SZ_2048;
2464 * 1024: rctl |= E1000_RCTL_SZ_1024;
2465 * 512: rctl |= E1000_RCTL_SZ_512;
2466 * 256: rctl |= E1000_RCTL_SZ_256;
2468 if (rctl_bsize > 0) {
2469 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
2470 rctl |= E1000_RCTL_SZ_512;
2471 else /* 256 <= buf_size < 512 - use 256 */
2472 rctl |= E1000_RCTL_SZ_256;
2476 * Configure RSS if device configured with multiple RX queues.
2478 igb_dev_mq_rx_configure(dev);
2480 /* Update the rctl since igb_dev_mq_rx_configure may change its value */
2481 rctl |= E1000_READ_REG(hw, E1000_RCTL);
2484 * Setup the Checksum Register.
2485 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
2487 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2488 rxcsum |= E1000_RXCSUM_PCSD;
2490 /* Enable both L3/L4 rx checksum offload */
2491 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
2492 rxcsum |= E1000_RXCSUM_IPOFL;
2494 rxcsum &= ~E1000_RXCSUM_IPOFL;
2495 if (rxmode->offloads &
2496 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM))
2497 rxcsum |= E1000_RXCSUM_TUOFL;
2499 rxcsum &= ~E1000_RXCSUM_TUOFL;
2500 if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM)
2501 rxcsum |= E1000_RXCSUM_CRCOFL;
2503 rxcsum &= ~E1000_RXCSUM_CRCOFL;
2505 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2507 /* Setup the Receive Control Register. */
2508 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
2509 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
2511 /* clear STRCRC bit in all queues */
2512 if (hw->mac.type == e1000_i350 ||
2513 hw->mac.type == e1000_i210 ||
2514 hw->mac.type == e1000_i211 ||
2515 hw->mac.type == e1000_i354) {
2516 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2517 rxq = dev->data->rx_queues[i];
2518 uint32_t dvmolr = E1000_READ_REG(hw,
2519 E1000_DVMOLR(rxq->reg_idx));
2520 dvmolr &= ~E1000_DVMOLR_STRCRC;
2521 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2525 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
2527 /* set STRCRC bit in all queues */
2528 if (hw->mac.type == e1000_i350 ||
2529 hw->mac.type == e1000_i210 ||
2530 hw->mac.type == e1000_i211 ||
2531 hw->mac.type == e1000_i354) {
2532 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2533 rxq = dev->data->rx_queues[i];
2534 uint32_t dvmolr = E1000_READ_REG(hw,
2535 E1000_DVMOLR(rxq->reg_idx));
2536 dvmolr |= E1000_DVMOLR_STRCRC;
2537 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2542 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2543 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2544 E1000_RCTL_RDMTS_HALF |
2545 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2547 /* Make sure VLAN Filters are off. */
2548 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
2549 rctl &= ~E1000_RCTL_VFE;
2550 /* Don't store bad packets. */
2551 rctl &= ~E1000_RCTL_SBP;
2553 /* Enable Receives. */
2554 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2557 * Setup the HW Rx Head and Tail Descriptor Pointers.
2558 * This needs to be done after enable.
2560 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2561 rxq = dev->data->rx_queues[i];
2562 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
2563 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
2569 /*********************************************************************
2571 * Enable transmit unit.
2573 **********************************************************************/
2575 eth_igb_tx_init(struct rte_eth_dev *dev)
2577 struct e1000_hw *hw;
2578 struct igb_tx_queue *txq;
2583 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 /* Setup the Base and Length of the Tx Descriptor Rings. */
2586 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2588 txq = dev->data->tx_queues[i];
2589 bus_addr = txq->tx_ring_phys_addr;
2591 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2593 sizeof(union e1000_adv_tx_desc));
2594 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2595 (uint32_t)(bus_addr >> 32));
2596 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2598 /* Setup the HW Tx Head and Tail descriptor pointers. */
2599 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2600 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2602 /* Setup Transmit threshold registers. */
2603 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2604 txdctl |= txq->pthresh & 0x1F;
2605 txdctl |= ((txq->hthresh & 0x1F) << 8);
2606 txdctl |= ((txq->wthresh & 0x1F) << 16);
2607 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2608 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2611 /* Program the Transmit Control Register. */
2612 tctl = E1000_READ_REG(hw, E1000_TCTL);
2613 tctl &= ~E1000_TCTL_CT;
2614 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2615 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2617 e1000_config_collision_dist(hw);
2619 /* This write will effectively turn on the transmit unit. */
2620 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2623 /*********************************************************************
2625 * Enable VF receive unit.
2627 **********************************************************************/
2629 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2631 struct e1000_hw *hw;
2632 struct igb_rx_queue *rxq;
2635 uint16_t rctl_bsize;
2640 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2643 max_len = dev->data->mtu + E1000_ETH_OVERHEAD;
2644 e1000_rlpml_set_vf(hw, (uint16_t)(max_len + VLAN_TAG_SIZE));
2646 /* Configure and enable each RX queue. */
2648 dev->rx_pkt_burst = eth_igb_recv_pkts;
2649 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2653 rxq = dev->data->rx_queues[i];
2657 * i350VF LB vlan packets have vlan tags byte swapped.
2659 if (hw->mac.type == e1000_vfadapt_i350) {
2660 rxq->flags |= IGB_RXQ_FLAG_LB_BSWAP_VLAN;
2661 PMD_INIT_LOG(DEBUG, "IGB rx vlan bswap required");
2663 PMD_INIT_LOG(DEBUG, "IGB rx vlan bswap not required");
2666 /* Allocate buffers for descriptor rings and set up queue */
2667 ret = igb_alloc_rx_queue_mbufs(rxq);
2671 bus_addr = rxq->rx_ring_phys_addr;
2672 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2674 sizeof(union e1000_adv_rx_desc));
2675 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2676 (uint32_t)(bus_addr >> 32));
2677 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2679 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2682 * Configure RX buffer size.
2684 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2685 RTE_PKTMBUF_HEADROOM);
2686 if (buf_size >= 1024) {
2688 * Configure the BSIZEPACKET field of the SRRCTL
2689 * register of the queue.
2690 * Value is in 1 KB resolution, from 1 KB to 127 KB.
2691 * If this field is equal to 0b, then RCTL.BSIZE
2692 * determines the RX packet buffer size.
2694 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2695 E1000_SRRCTL_BSIZEPKT_MASK);
2696 buf_size = (uint16_t) ((srrctl &
2697 E1000_SRRCTL_BSIZEPKT_MASK) <<
2698 E1000_SRRCTL_BSIZEPKT_SHIFT);
2700 /* It adds dual VLAN length for supporting dual VLAN */
2701 if ((max_len + 2 * VLAN_TAG_SIZE) > buf_size) {
2702 if (!dev->data->scattered_rx)
2704 "forcing scatter mode");
2705 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2706 dev->data->scattered_rx = 1;
2710 * Use BSIZE field of the device RCTL register.
2712 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2713 rctl_bsize = buf_size;
2714 if (!dev->data->scattered_rx)
2715 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2716 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2717 dev->data->scattered_rx = 1;
2720 /* Set if packets are dropped when no descriptors available */
2722 srrctl |= E1000_SRRCTL_DROP_EN;
2724 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2726 /* Enable this RX queue. */
2727 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2728 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2729 rxdctl &= 0xFFF00000;
2730 rxdctl |= (rxq->pthresh & 0x1F);
2731 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2732 if (hw->mac.type == e1000_vfadapt) {
2734 * Workaround of 82576 VF Erratum
2735 * force set WTHRESH to 1
2736 * to avoid Write-Back not triggered sometimes
2739 PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !");
2742 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2743 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2746 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
2747 if (!dev->data->scattered_rx)
2748 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2749 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2750 dev->data->scattered_rx = 1;
2754 * Setup the HW Rx Head and Tail Descriptor Pointers.
2755 * This needs to be done after enable.
2757 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2758 rxq = dev->data->rx_queues[i];
2759 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2760 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2766 /*********************************************************************
2768 * Enable VF transmit unit.
2770 **********************************************************************/
2772 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2774 struct e1000_hw *hw;
2775 struct igb_tx_queue *txq;
2779 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781 /* Setup the Base and Length of the Tx Descriptor Rings. */
2782 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2785 txq = dev->data->tx_queues[i];
2786 bus_addr = txq->tx_ring_phys_addr;
2787 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2789 sizeof(union e1000_adv_tx_desc));
2790 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2791 (uint32_t)(bus_addr >> 32));
2792 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2794 /* Setup the HW Tx Head and Tail descriptor pointers. */
2795 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2796 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2798 /* Setup Transmit threshold registers. */
2799 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2800 txdctl |= txq->pthresh & 0x1F;
2801 txdctl |= ((txq->hthresh & 0x1F) << 8);
2802 if (hw->mac.type == e1000_82576) {
2804 * Workaround of 82576 VF Erratum
2805 * force set WTHRESH to 1
2806 * to avoid Write-Back not triggered sometimes
2809 PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !");
2812 txdctl |= ((txq->wthresh & 0x1F) << 16);
2813 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2814 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2820 igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2821 struct rte_eth_rxq_info *qinfo)
2823 struct igb_rx_queue *rxq;
2825 rxq = dev->data->rx_queues[queue_id];
2827 qinfo->mp = rxq->mb_pool;
2828 qinfo->scattered_rx = dev->data->scattered_rx;
2829 qinfo->nb_desc = rxq->nb_rx_desc;
2831 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2832 qinfo->conf.rx_drop_en = rxq->drop_en;
2833 qinfo->conf.offloads = rxq->offloads;
2837 igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2838 struct rte_eth_txq_info *qinfo)
2840 struct igb_tx_queue *txq;
2842 txq = dev->data->tx_queues[queue_id];
2844 qinfo->nb_desc = txq->nb_tx_desc;
2846 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2847 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2848 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2849 qinfo->conf.offloads = txq->offloads;
2853 igb_rss_conf_init(struct rte_eth_dev *dev,
2854 struct igb_rte_flow_rss_conf *out,
2855 const struct rte_flow_action_rss *in)
2857 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859 if (in->key_len > RTE_DIM(out->key) ||
2860 ((hw->mac.type == e1000_82576) &&
2861 (in->queue_num > IGB_MAX_RX_QUEUE_NUM_82576)) ||
2862 ((hw->mac.type != e1000_82576) &&
2863 (in->queue_num > IGB_MAX_RX_QUEUE_NUM)))
2865 out->conf = (struct rte_flow_action_rss){
2869 .key_len = in->key_len,
2870 .queue_num = in->queue_num,
2871 .key = memcpy(out->key, in->key, in->key_len),
2872 .queue = memcpy(out->queue, in->queue,
2873 sizeof(*in->queue) * in->queue_num),
2879 igb_action_rss_same(const struct rte_flow_action_rss *comp,
2880 const struct rte_flow_action_rss *with)
2882 return (comp->func == with->func &&
2883 comp->level == with->level &&
2884 comp->types == with->types &&
2885 comp->key_len == with->key_len &&
2886 comp->queue_num == with->queue_num &&
2887 !memcmp(comp->key, with->key, with->key_len) &&
2888 !memcmp(comp->queue, with->queue,
2889 sizeof(*with->queue) * with->queue_num));
2893 igb_config_rss_filter(struct rte_eth_dev *dev,
2894 struct igb_rte_flow_rss_conf *conf, bool add)
2898 struct rte_eth_rss_conf rss_conf = {
2899 .rss_key = conf->conf.key_len ?
2900 (void *)(uintptr_t)conf->conf.key : NULL,
2901 .rss_key_len = conf->conf.key_len,
2902 .rss_hf = conf->conf.types,
2904 struct e1000_filter_info *filter_info =
2905 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2906 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2908 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911 if (igb_action_rss_same(&filter_info->rss_info.conf,
2913 igb_rss_disable(dev);
2914 memset(&filter_info->rss_info, 0,
2915 sizeof(struct igb_rte_flow_rss_conf));
2921 if (filter_info->rss_info.conf.queue_num)
2924 /* Fill in redirection table. */
2925 shift = (hw->mac.type == e1000_82575) ? 6 : 0;
2926 for (i = 0, j = 0; i < 128; i++, j++) {
2933 if (j == conf->conf.queue_num)
2935 q_idx = conf->conf.queue[j];
2936 reta.bytes[i & 3] = (uint8_t)(q_idx << shift);
2938 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
2941 /* Configure the RSS key and the RSS protocols used to compute
2942 * the RSS hash of input packets.
2944 if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {
2945 igb_rss_disable(dev);
2948 if (rss_conf.rss_key == NULL)
2949 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2950 igb_hw_rss_hash_set(hw, &rss_conf);
2952 if (igb_rss_conf_init(dev, &filter_info->rss_info, &conf->conf))