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34 #include <sys/queue.h>
44 #include <rte_interrupts.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
48 #include <rte_debug.h>
50 #include <rte_memory.h>
51 #include <rte_memcpy.h>
52 #include <rte_memzone.h>
53 #include <rte_launch.h>
55 #include <rte_per_lcore.h>
56 #include <rte_lcore.h>
57 #include <rte_atomic.h>
58 #include <rte_branch_prediction.h>
59 #include <rte_mempool.h>
60 #include <rte_malloc.h>
62 #include <rte_ether.h>
63 #include <rte_ethdev.h>
64 #include <rte_prefetch.h>
68 #include <rte_string_fns.h>
70 #include "e1000_logs.h"
71 #include "base/e1000_api.h"
72 #include "e1000_ethdev.h"
74 /* Bit Mask to indicate what bits required for building TX context */
75 #define IGB_TX_OFFLOAD_MASK ( \
82 * Structure associated with each descriptor of the RX ring of a RX queue.
85 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
89 * Structure associated with each descriptor of the TX ring of a TX queue.
92 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
93 uint16_t next_id; /**< Index of next descriptor in ring. */
94 uint16_t last_id; /**< Index of last scattered descriptor. */
98 * Structure associated with each RX queue.
100 struct igb_rx_queue {
101 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
102 volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
103 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
104 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
105 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
106 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
107 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
108 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
109 uint16_t nb_rx_desc; /**< number of RX descriptors. */
110 uint16_t rx_tail; /**< current value of RDT register. */
111 uint16_t nb_rx_hold; /**< number of held free RX desc. */
112 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
113 uint16_t queue_id; /**< RX queue index. */
114 uint16_t reg_idx; /**< RX queue register index. */
115 uint8_t port_id; /**< Device port identifier. */
116 uint8_t pthresh; /**< Prefetch threshold register. */
117 uint8_t hthresh; /**< Host threshold register. */
118 uint8_t wthresh; /**< Write-back threshold register. */
119 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
120 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
124 * Hardware context number
126 enum igb_advctx_num {
127 IGB_CTX_0 = 0, /**< CTX0 */
128 IGB_CTX_1 = 1, /**< CTX1 */
129 IGB_CTX_NUM = 2, /**< CTX_NUM */
132 /** Offload features */
133 union igb_tx_offload {
136 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
137 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
138 uint64_t vlan_tci:16; /**< VLAN Tag Control Identifier(CPU order). */
139 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
140 uint64_t tso_segsz:16; /**< TCP TSO segment size. */
142 /* uint64_t unused:8; */
147 * Compare mask for igb_tx_offload.data,
148 * should be in sync with igb_tx_offload layout.
150 #define TX_MACIP_LEN_CMP_MASK 0x000000000000FFFFULL /**< L2L3 header mask. */
151 #define TX_VLAN_CMP_MASK 0x00000000FFFF0000ULL /**< Vlan mask. */
152 #define TX_TCP_LEN_CMP_MASK 0x000000FF00000000ULL /**< TCP header mask. */
153 #define TX_TSO_MSS_CMP_MASK 0x00FFFF0000000000ULL /**< TSO segsz mask. */
154 /** Mac + IP + TCP + Mss mask. */
155 #define TX_TSO_CMP_MASK \
156 (TX_MACIP_LEN_CMP_MASK | TX_TCP_LEN_CMP_MASK | TX_TSO_MSS_CMP_MASK)
159 * Strucutre to check if new context need be built
161 struct igb_advctx_info {
162 uint64_t flags; /**< ol_flags related to context build. */
163 /** tx offload: vlan, tso, l2-l3-l4 lengths. */
164 union igb_tx_offload tx_offload;
165 /** compare mask for tx offload. */
166 union igb_tx_offload tx_offload_mask;
170 * Structure associated with each TX queue.
172 struct igb_tx_queue {
173 volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
174 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
175 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
176 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
177 uint32_t txd_type; /**< Device-specific TXD type */
178 uint16_t nb_tx_desc; /**< number of TX descriptors. */
179 uint16_t tx_tail; /**< Current value of TDT register. */
181 /**< Index of first used TX descriptor. */
182 uint16_t queue_id; /**< TX queue index. */
183 uint16_t reg_idx; /**< TX queue register index. */
184 uint8_t port_id; /**< Device port identifier. */
185 uint8_t pthresh; /**< Prefetch threshold register. */
186 uint8_t hthresh; /**< Host threshold register. */
187 uint8_t wthresh; /**< Write-back threshold register. */
189 /**< Current used hardware descriptor. */
191 /**< Start context position for transmit queue. */
192 struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
193 /**< Hardware context history.*/
197 #define RTE_PMD_USE_PREFETCH
200 #ifdef RTE_PMD_USE_PREFETCH
201 #define rte_igb_prefetch(p) rte_prefetch0(p)
203 #define rte_igb_prefetch(p) do {} while(0)
206 #ifdef RTE_PMD_PACKET_PREFETCH
207 #define rte_packet_prefetch(p) rte_prefetch1(p)
209 #define rte_packet_prefetch(p) do {} while(0)
213 * Macro for VMDq feature for 1 GbE NIC.
215 #define E1000_VMOLR_SIZE (8)
216 #define IGB_TSO_MAX_HDRLEN (512)
217 #define IGB_TSO_MAX_MSS (9216)
219 /*********************************************************************
223 **********************************************************************/
226 *There're some limitations in hardware for TCP segmentation offload. We
227 *should check whether the parameters are valid.
229 static inline uint64_t
230 check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para)
232 if (!(ol_req & PKT_TX_TCP_SEG))
234 if ((ol_para.tso_segsz > IGB_TSO_MAX_MSS) || (ol_para.l2_len +
235 ol_para.l3_len + ol_para.l4_len > IGB_TSO_MAX_HDRLEN)) {
236 ol_req &= ~PKT_TX_TCP_SEG;
237 ol_req |= PKT_TX_TCP_CKSUM;
243 * Advanced context descriptor are almost same between igb/ixgbe
244 * This is a separate function, looking for optimization opportunity here
245 * Rework required to go with the pre-defined values.
249 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
250 volatile struct e1000_adv_tx_context_desc *ctx_txd,
251 uint64_t ol_flags, union igb_tx_offload tx_offload)
253 uint32_t type_tucmd_mlhl;
254 uint32_t mss_l4len_idx;
255 uint32_t ctx_idx, ctx_curr;
256 uint32_t vlan_macip_lens;
257 union igb_tx_offload tx_offload_mask;
259 ctx_curr = txq->ctx_curr;
260 ctx_idx = ctx_curr + txq->ctx_start;
262 tx_offload_mask.data = 0;
265 /* Specify which HW CTX to upload. */
266 mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
268 if (ol_flags & PKT_TX_VLAN_PKT)
269 tx_offload_mask.data |= TX_VLAN_CMP_MASK;
271 /* check if TCP segmentation required for this packet */
272 if (ol_flags & PKT_TX_TCP_SEG) {
273 /* implies IP cksum in IPv4 */
274 if (ol_flags & PKT_TX_IP_CKSUM)
275 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 |
276 E1000_ADVTXD_TUCMD_L4T_TCP |
277 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
279 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV6 |
280 E1000_ADVTXD_TUCMD_L4T_TCP |
281 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
283 tx_offload_mask.data |= TX_TSO_CMP_MASK;
284 mss_l4len_idx |= tx_offload.tso_segsz << E1000_ADVTXD_MSS_SHIFT;
285 mss_l4len_idx |= tx_offload.l4_len << E1000_ADVTXD_L4LEN_SHIFT;
286 } else { /* no TSO, check if hardware checksum is needed */
287 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
288 tx_offload_mask.data |= TX_MACIP_LEN_CMP_MASK;
290 if (ol_flags & PKT_TX_IP_CKSUM)
291 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
293 switch (ol_flags & PKT_TX_L4_MASK) {
294 case PKT_TX_UDP_CKSUM:
295 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
296 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
297 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
299 case PKT_TX_TCP_CKSUM:
300 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
301 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
302 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
304 case PKT_TX_SCTP_CKSUM:
305 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
306 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
307 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
310 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
311 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
316 txq->ctx_cache[ctx_curr].flags = ol_flags;
317 txq->ctx_cache[ctx_curr].tx_offload.data =
318 tx_offload_mask.data & tx_offload.data;
319 txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;
321 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
322 vlan_macip_lens = (uint32_t)tx_offload.data;
323 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
324 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
325 ctx_txd->seqnum_seed = 0;
329 * Check which hardware context can be used. Use the existing match
330 * or create a new context descriptor.
332 static inline uint32_t
333 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
334 union igb_tx_offload tx_offload)
336 /* If match with the current context */
337 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
338 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
339 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
340 return txq->ctx_curr;
343 /* If match with the second context */
345 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
346 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
347 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
348 return txq->ctx_curr;
351 /* Mismatch, use the previous context */
355 static inline uint32_t
356 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
358 static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
359 static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
362 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
363 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
364 tmp |= l4_olinfo[(ol_flags & PKT_TX_TCP_SEG) != 0];
368 static inline uint32_t
369 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
372 static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
373 static uint32_t tso_cmd[2] = {0, E1000_ADVTXD_DCMD_TSE};
374 cmdtype = vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
375 cmdtype |= tso_cmd[(ol_flags & PKT_TX_TCP_SEG) != 0];
380 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
383 struct igb_tx_queue *txq;
384 struct igb_tx_entry *sw_ring;
385 struct igb_tx_entry *txe, *txn;
386 volatile union e1000_adv_tx_desc *txr;
387 volatile union e1000_adv_tx_desc *txd;
388 struct rte_mbuf *tx_pkt;
389 struct rte_mbuf *m_seg;
390 uint64_t buf_dma_addr;
391 uint32_t olinfo_status;
392 uint32_t cmd_type_len;
401 uint32_t new_ctx = 0;
403 union igb_tx_offload tx_offload = {0};
406 sw_ring = txq->sw_ring;
408 tx_id = txq->tx_tail;
409 txe = &sw_ring[tx_id];
411 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
413 pkt_len = tx_pkt->pkt_len;
415 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
418 * The number of descriptors that must be allocated for a
419 * packet is the number of segments of that packet, plus 1
420 * Context Descriptor for the VLAN Tag Identifier, if any.
421 * Determine the last TX descriptor to allocate in the TX ring
422 * for the packet, starting from the current position (tx_id)
425 tx_last = (uint16_t) (tx_id + tx_pkt->nb_segs - 1);
427 ol_flags = tx_pkt->ol_flags;
428 tx_ol_req = ol_flags & IGB_TX_OFFLOAD_MASK;
430 /* If a Context Descriptor need be built . */
432 tx_offload.l2_len = tx_pkt->l2_len;
433 tx_offload.l3_len = tx_pkt->l3_len;
434 tx_offload.l4_len = tx_pkt->l4_len;
435 tx_offload.vlan_tci = tx_pkt->vlan_tci;
436 tx_offload.tso_segsz = tx_pkt->tso_segsz;
437 tx_ol_req = check_tso_para(tx_ol_req, tx_offload);
439 ctx = what_advctx_update(txq, tx_ol_req, tx_offload);
440 /* Only allocate context descriptor if required*/
441 new_ctx = (ctx == IGB_CTX_NUM);
442 ctx = txq->ctx_curr + txq->ctx_start;
443 tx_last = (uint16_t) (tx_last + new_ctx);
445 if (tx_last >= txq->nb_tx_desc)
446 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
448 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
449 " tx_first=%u tx_last=%u",
450 (unsigned) txq->port_id,
451 (unsigned) txq->queue_id,
457 * Check if there are enough free descriptors in the TX ring
458 * to transmit the next packet.
459 * This operation is based on the two following rules:
461 * 1- Only check that the last needed TX descriptor can be
462 * allocated (by construction, if that descriptor is free,
463 * all intermediate ones are also free).
465 * For this purpose, the index of the last TX descriptor
466 * used for a packet (the "last descriptor" of a packet)
467 * is recorded in the TX entries (the last one included)
468 * that are associated with all TX descriptors allocated
471 * 2- Avoid to allocate the last free TX descriptor of the
472 * ring, in order to never set the TDT register with the
473 * same value stored in parallel by the NIC in the TDH
474 * register, which makes the TX engine of the NIC enter
475 * in a deadlock situation.
477 * By extension, avoid to allocate a free descriptor that
478 * belongs to the last set of free descriptors allocated
479 * to the same packet previously transmitted.
483 * The "last descriptor" of the previously sent packet, if any,
484 * which used the last descriptor to allocate.
486 tx_end = sw_ring[tx_last].last_id;
489 * The next descriptor following that "last descriptor" in the
492 tx_end = sw_ring[tx_end].next_id;
495 * The "last descriptor" associated with that next descriptor.
497 tx_end = sw_ring[tx_end].last_id;
500 * Check that this descriptor is free.
502 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
509 * Set common flags of all TX Data Descriptors.
511 * The following bits must be set in all Data Descriptors:
512 * - E1000_ADVTXD_DTYP_DATA
513 * - E1000_ADVTXD_DCMD_DEXT
515 * The following bits must be set in the first Data Descriptor
516 * and are ignored in the other ones:
517 * - E1000_ADVTXD_DCMD_IFCS
518 * - E1000_ADVTXD_MAC_1588
519 * - E1000_ADVTXD_DCMD_VLE
521 * The following bits must only be set in the last Data
523 * - E1000_TXD_CMD_EOP
525 * The following bits can be set in any Data Descriptor, but
526 * are only set in the last Data Descriptor:
529 cmd_type_len = txq->txd_type |
530 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
531 if (tx_ol_req & PKT_TX_TCP_SEG)
532 pkt_len -= (tx_pkt->l2_len + tx_pkt->l3_len + tx_pkt->l4_len);
533 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
534 #if defined(RTE_LIBRTE_IEEE1588)
535 if (ol_flags & PKT_TX_IEEE1588_TMST)
536 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
539 /* Setup TX Advanced context descriptor if required */
541 volatile struct e1000_adv_tx_context_desc *
544 ctx_txd = (volatile struct
545 e1000_adv_tx_context_desc *)
548 txn = &sw_ring[txe->next_id];
549 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
551 if (txe->mbuf != NULL) {
552 rte_pktmbuf_free_seg(txe->mbuf);
556 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload);
558 txe->last_id = tx_last;
559 tx_id = txe->next_id;
563 /* Setup the TX Advanced Data Descriptor */
564 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(tx_ol_req);
565 olinfo_status |= tx_desc_cksum_flags_to_olinfo(tx_ol_req);
566 olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
571 txn = &sw_ring[txe->next_id];
574 if (txe->mbuf != NULL)
575 rte_pktmbuf_free_seg(txe->mbuf);
579 * Set up transmit descriptor.
581 slen = (uint16_t) m_seg->data_len;
582 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
583 txd->read.buffer_addr =
584 rte_cpu_to_le_64(buf_dma_addr);
585 txd->read.cmd_type_len =
586 rte_cpu_to_le_32(cmd_type_len | slen);
587 txd->read.olinfo_status =
588 rte_cpu_to_le_32(olinfo_status);
589 txe->last_id = tx_last;
590 tx_id = txe->next_id;
593 } while (m_seg != NULL);
596 * The last packet data descriptor needs End Of Packet (EOP)
597 * and Report Status (RS).
599 txd->read.cmd_type_len |=
600 rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
606 * Set the Transmit Descriptor Tail (TDT).
608 E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
609 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
610 (unsigned) txq->port_id, (unsigned) txq->queue_id,
611 (unsigned) tx_id, (unsigned) nb_tx);
612 txq->tx_tail = tx_id;
617 /*********************************************************************
621 **********************************************************************/
622 #define IGB_PACKET_TYPE_IPV4 0X01
623 #define IGB_PACKET_TYPE_IPV4_TCP 0X11
624 #define IGB_PACKET_TYPE_IPV4_UDP 0X21
625 #define IGB_PACKET_TYPE_IPV4_SCTP 0X41
626 #define IGB_PACKET_TYPE_IPV4_EXT 0X03
627 #define IGB_PACKET_TYPE_IPV4_EXT_SCTP 0X43
628 #define IGB_PACKET_TYPE_IPV6 0X04
629 #define IGB_PACKET_TYPE_IPV6_TCP 0X14
630 #define IGB_PACKET_TYPE_IPV6_UDP 0X24
631 #define IGB_PACKET_TYPE_IPV6_EXT 0X0C
632 #define IGB_PACKET_TYPE_IPV6_EXT_TCP 0X1C
633 #define IGB_PACKET_TYPE_IPV6_EXT_UDP 0X2C
634 #define IGB_PACKET_TYPE_IPV4_IPV6 0X05
635 #define IGB_PACKET_TYPE_IPV4_IPV6_TCP 0X15
636 #define IGB_PACKET_TYPE_IPV4_IPV6_UDP 0X25
637 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
638 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
639 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
640 #define IGB_PACKET_TYPE_MAX 0X80
641 #define IGB_PACKET_TYPE_MASK 0X7F
642 #define IGB_PACKET_TYPE_SHIFT 0X04
643 static inline uint32_t
644 igb_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
646 static const uint32_t
647 ptype_table[IGB_PACKET_TYPE_MAX] __rte_cache_aligned = {
648 [IGB_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
650 [IGB_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
651 RTE_PTYPE_L3_IPV4_EXT,
652 [IGB_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
654 [IGB_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
655 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
656 RTE_PTYPE_INNER_L3_IPV6,
657 [IGB_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
658 RTE_PTYPE_L3_IPV6_EXT,
659 [IGB_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
660 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
661 RTE_PTYPE_INNER_L3_IPV6_EXT,
662 [IGB_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
663 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
664 [IGB_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
665 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
666 [IGB_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
667 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
668 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
669 [IGB_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
670 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
671 [IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
672 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
673 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
674 [IGB_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
675 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
676 [IGB_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
677 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
678 [IGB_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
679 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
680 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
681 [IGB_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
682 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
683 [IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
684 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
685 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
686 [IGB_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
687 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
688 [IGB_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
689 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
691 if (unlikely(pkt_info & E1000_RXDADV_PKTTYPE_ETQF))
692 return RTE_PTYPE_UNKNOWN;
694 pkt_info = (pkt_info >> IGB_PACKET_TYPE_SHIFT) & IGB_PACKET_TYPE_MASK;
696 return ptype_table[pkt_info];
699 static inline uint64_t
700 rx_desc_hlen_type_rss_to_pkt_flags(struct igb_rx_queue *rxq, uint32_t hl_tp_rs)
702 uint64_t pkt_flags = ((hl_tp_rs & 0x0F) == 0) ? 0 : PKT_RX_RSS_HASH;
704 #if defined(RTE_LIBRTE_IEEE1588)
705 static uint32_t ip_pkt_etqf_map[8] = {
706 0, 0, 0, PKT_RX_IEEE1588_PTP,
710 struct rte_eth_dev dev = rte_eth_devices[rxq->port_id];
711 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev.data->dev_private);
713 /* EtherType is in bits 8:10 in Packet Type, and not in the default 0:2 */
714 if (hw->mac.type == e1000_i210)
715 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 12) & 0x07];
717 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07];
725 static inline uint64_t
726 rx_desc_status_to_pkt_flags(uint32_t rx_status)
730 /* Check if VLAN present */
731 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
732 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED : 0);
734 #if defined(RTE_LIBRTE_IEEE1588)
735 if (rx_status & E1000_RXD_STAT_TMST)
736 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
741 static inline uint64_t
742 rx_desc_error_to_pkt_flags(uint32_t rx_status)
745 * Bit 30: IPE, IPv4 checksum error
746 * Bit 29: L4I, L4I integrity error
749 static uint64_t error_to_pkt_flags_map[4] = {
750 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
751 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
752 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
753 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
755 return error_to_pkt_flags_map[(rx_status >>
756 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
760 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
763 struct igb_rx_queue *rxq;
764 volatile union e1000_adv_rx_desc *rx_ring;
765 volatile union e1000_adv_rx_desc *rxdp;
766 struct igb_rx_entry *sw_ring;
767 struct igb_rx_entry *rxe;
768 struct rte_mbuf *rxm;
769 struct rte_mbuf *nmb;
770 union e1000_adv_rx_desc rxd;
773 uint32_t hlen_type_rss;
783 rx_id = rxq->rx_tail;
784 rx_ring = rxq->rx_ring;
785 sw_ring = rxq->sw_ring;
786 while (nb_rx < nb_pkts) {
788 * The order of operations here is important as the DD status
789 * bit must not be read after any other descriptor fields.
790 * rx_ring and rxdp are pointing to volatile data so the order
791 * of accesses cannot be reordered by the compiler. If they were
792 * not volatile, they could be reordered which could lead to
793 * using invalid descriptor fields when read from rxd.
795 rxdp = &rx_ring[rx_id];
796 staterr = rxdp->wb.upper.status_error;
797 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
804 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
805 * likely to be invalid and to be dropped by the various
806 * validation checks performed by the network stack.
808 * Allocate a new mbuf to replenish the RX ring descriptor.
809 * If the allocation fails:
810 * - arrange for that RX descriptor to be the first one
811 * being parsed the next time the receive function is
812 * invoked [on the same queue].
814 * - Stop parsing the RX ring and return immediately.
816 * This policy do not drop the packet received in the RX
817 * descriptor for which the allocation of a new mbuf failed.
818 * Thus, it allows that packet to be later retrieved if
819 * mbuf have been freed in the mean time.
820 * As a side effect, holding RX descriptors instead of
821 * systematically giving them back to the NIC may lead to
822 * RX ring exhaustion situations.
823 * However, the NIC can gracefully prevent such situations
824 * to happen by sending specific "back-pressure" flow control
825 * frames to its peer(s).
827 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
828 "staterr=0x%x pkt_len=%u",
829 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
830 (unsigned) rx_id, (unsigned) staterr,
831 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
833 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
835 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
836 "queue_id=%u", (unsigned) rxq->port_id,
837 (unsigned) rxq->queue_id);
838 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
843 rxe = &sw_ring[rx_id];
845 if (rx_id == rxq->nb_rx_desc)
848 /* Prefetch next mbuf while processing current one. */
849 rte_igb_prefetch(sw_ring[rx_id].mbuf);
852 * When next RX descriptor is on a cache-line boundary,
853 * prefetch the next 4 RX descriptors and the next 8 pointers
856 if ((rx_id & 0x3) == 0) {
857 rte_igb_prefetch(&rx_ring[rx_id]);
858 rte_igb_prefetch(&sw_ring[rx_id]);
864 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
865 rxdp->read.hdr_addr = 0;
866 rxdp->read.pkt_addr = dma_addr;
869 * Initialize the returned mbuf.
870 * 1) setup generic mbuf fields:
871 * - number of segments,
874 * - RX port identifier.
875 * 2) integrate hardware offload data, if any:
877 * - IP checksum flag,
878 * - VLAN TCI, if any,
881 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
883 rxm->data_off = RTE_PKTMBUF_HEADROOM;
884 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
887 rxm->pkt_len = pkt_len;
888 rxm->data_len = pkt_len;
889 rxm->port = rxq->port_id;
891 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
892 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
893 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
894 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
896 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(rxq, hlen_type_rss);
897 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
898 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
899 rxm->ol_flags = pkt_flags;
900 rxm->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.lower.
901 lo_dword.hs_rss.pkt_info);
904 * Store the mbuf address into the next entry of the array
905 * of returned packets.
907 rx_pkts[nb_rx++] = rxm;
909 rxq->rx_tail = rx_id;
912 * If the number of free RX descriptors is greater than the RX free
913 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
915 * Update the RDT with the value of the last processed RX descriptor
916 * minus 1, to guarantee that the RDT register is never equal to the
917 * RDH register, which creates a "full" ring situtation from the
918 * hardware point of view...
920 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
921 if (nb_hold > rxq->rx_free_thresh) {
922 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
923 "nb_hold=%u nb_rx=%u",
924 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
925 (unsigned) rx_id, (unsigned) nb_hold,
927 rx_id = (uint16_t) ((rx_id == 0) ?
928 (rxq->nb_rx_desc - 1) : (rx_id - 1));
929 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
932 rxq->nb_rx_hold = nb_hold;
937 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
940 struct igb_rx_queue *rxq;
941 volatile union e1000_adv_rx_desc *rx_ring;
942 volatile union e1000_adv_rx_desc *rxdp;
943 struct igb_rx_entry *sw_ring;
944 struct igb_rx_entry *rxe;
945 struct rte_mbuf *first_seg;
946 struct rte_mbuf *last_seg;
947 struct rte_mbuf *rxm;
948 struct rte_mbuf *nmb;
949 union e1000_adv_rx_desc rxd;
950 uint64_t dma; /* Physical address of mbuf data buffer */
952 uint32_t hlen_type_rss;
962 rx_id = rxq->rx_tail;
963 rx_ring = rxq->rx_ring;
964 sw_ring = rxq->sw_ring;
967 * Retrieve RX context of current packet, if any.
969 first_seg = rxq->pkt_first_seg;
970 last_seg = rxq->pkt_last_seg;
972 while (nb_rx < nb_pkts) {
975 * The order of operations here is important as the DD status
976 * bit must not be read after any other descriptor fields.
977 * rx_ring and rxdp are pointing to volatile data so the order
978 * of accesses cannot be reordered by the compiler. If they were
979 * not volatile, they could be reordered which could lead to
980 * using invalid descriptor fields when read from rxd.
982 rxdp = &rx_ring[rx_id];
983 staterr = rxdp->wb.upper.status_error;
984 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
991 * Allocate a new mbuf to replenish the RX ring descriptor.
992 * If the allocation fails:
993 * - arrange for that RX descriptor to be the first one
994 * being parsed the next time the receive function is
995 * invoked [on the same queue].
997 * - Stop parsing the RX ring and return immediately.
999 * This policy does not drop the packet received in the RX
1000 * descriptor for which the allocation of a new mbuf failed.
1001 * Thus, it allows that packet to be later retrieved if
1002 * mbuf have been freed in the mean time.
1003 * As a side effect, holding RX descriptors instead of
1004 * systematically giving them back to the NIC may lead to
1005 * RX ring exhaustion situations.
1006 * However, the NIC can gracefully prevent such situations
1007 * to happen by sending specific "back-pressure" flow control
1008 * frames to its peer(s).
1010 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1011 "staterr=0x%x data_len=%u",
1012 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1013 (unsigned) rx_id, (unsigned) staterr,
1014 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1016 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1018 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1019 "queue_id=%u", (unsigned) rxq->port_id,
1020 (unsigned) rxq->queue_id);
1021 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1026 rxe = &sw_ring[rx_id];
1028 if (rx_id == rxq->nb_rx_desc)
1031 /* Prefetch next mbuf while processing current one. */
1032 rte_igb_prefetch(sw_ring[rx_id].mbuf);
1035 * When next RX descriptor is on a cache-line boundary,
1036 * prefetch the next 4 RX descriptors and the next 8 pointers
1039 if ((rx_id & 0x3) == 0) {
1040 rte_igb_prefetch(&rx_ring[rx_id]);
1041 rte_igb_prefetch(&sw_ring[rx_id]);
1045 * Update RX descriptor with the physical address of the new
1046 * data buffer of the new allocated mbuf.
1050 dma = rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1051 rxdp->read.pkt_addr = dma;
1052 rxdp->read.hdr_addr = 0;
1055 * Set data length & data buffer address of mbuf.
1057 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1058 rxm->data_len = data_len;
1059 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1062 * If this is the first buffer of the received packet,
1063 * set the pointer to the first mbuf of the packet and
1064 * initialize its context.
1065 * Otherwise, update the total length and the number of segments
1066 * of the current scattered packet, and update the pointer to
1067 * the last mbuf of the current packet.
1069 if (first_seg == NULL) {
1071 first_seg->pkt_len = data_len;
1072 first_seg->nb_segs = 1;
1074 first_seg->pkt_len += data_len;
1075 first_seg->nb_segs++;
1076 last_seg->next = rxm;
1080 * If this is not the last buffer of the received packet,
1081 * update the pointer to the last mbuf of the current scattered
1082 * packet and continue to parse the RX ring.
1084 if (! (staterr & E1000_RXD_STAT_EOP)) {
1090 * This is the last buffer of the received packet.
1091 * If the CRC is not stripped by the hardware:
1092 * - Subtract the CRC length from the total packet length.
1093 * - If the last buffer only contains the whole CRC or a part
1094 * of it, free the mbuf associated to the last buffer.
1095 * If part of the CRC is also contained in the previous
1096 * mbuf, subtract the length of that CRC part from the
1097 * data length of the previous mbuf.
1100 if (unlikely(rxq->crc_len > 0)) {
1101 first_seg->pkt_len -= ETHER_CRC_LEN;
1102 if (data_len <= ETHER_CRC_LEN) {
1103 rte_pktmbuf_free_seg(rxm);
1104 first_seg->nb_segs--;
1105 last_seg->data_len = (uint16_t)
1106 (last_seg->data_len -
1107 (ETHER_CRC_LEN - data_len));
1108 last_seg->next = NULL;
1111 (uint16_t) (data_len - ETHER_CRC_LEN);
1115 * Initialize the first mbuf of the returned packet:
1116 * - RX port identifier,
1117 * - hardware offload data, if any:
1118 * - RSS flag & hash,
1119 * - IP checksum flag,
1120 * - VLAN TCI, if any,
1123 first_seg->port = rxq->port_id;
1124 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1127 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1128 * set in the pkt_flags field.
1130 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1131 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1132 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(rxq, hlen_type_rss);
1133 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1134 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1135 first_seg->ol_flags = pkt_flags;
1136 first_seg->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.
1137 lower.lo_dword.hs_rss.pkt_info);
1139 /* Prefetch data of first segment, if configured to do so. */
1140 rte_packet_prefetch((char *)first_seg->buf_addr +
1141 first_seg->data_off);
1144 * Store the mbuf address into the next entry of the array
1145 * of returned packets.
1147 rx_pkts[nb_rx++] = first_seg;
1150 * Setup receipt context for a new packet.
1156 * Record index of the next RX descriptor to probe.
1158 rxq->rx_tail = rx_id;
1161 * Save receive context.
1163 rxq->pkt_first_seg = first_seg;
1164 rxq->pkt_last_seg = last_seg;
1167 * If the number of free RX descriptors is greater than the RX free
1168 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1170 * Update the RDT with the value of the last processed RX descriptor
1171 * minus 1, to guarantee that the RDT register is never equal to the
1172 * RDH register, which creates a "full" ring situtation from the
1173 * hardware point of view...
1175 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1176 if (nb_hold > rxq->rx_free_thresh) {
1177 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1178 "nb_hold=%u nb_rx=%u",
1179 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1180 (unsigned) rx_id, (unsigned) nb_hold,
1182 rx_id = (uint16_t) ((rx_id == 0) ?
1183 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1184 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1187 rxq->nb_rx_hold = nb_hold;
1192 * Maximum number of Ring Descriptors.
1194 * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1195 * desscriptors should meet the following condition:
1196 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1200 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1204 if (txq->sw_ring != NULL) {
1205 for (i = 0; i < txq->nb_tx_desc; i++) {
1206 if (txq->sw_ring[i].mbuf != NULL) {
1207 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1208 txq->sw_ring[i].mbuf = NULL;
1215 igb_tx_queue_release(struct igb_tx_queue *txq)
1218 igb_tx_queue_release_mbufs(txq);
1219 rte_free(txq->sw_ring);
1225 eth_igb_tx_queue_release(void *txq)
1227 igb_tx_queue_release(txq);
1231 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1236 memset((void*)&txq->ctx_cache, 0,
1237 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1241 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1243 static const union e1000_adv_tx_desc zeroed_desc = {{0}};
1244 struct igb_tx_entry *txe = txq->sw_ring;
1246 struct e1000_hw *hw;
1248 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249 /* Zero out HW ring memory */
1250 for (i = 0; i < txq->nb_tx_desc; i++) {
1251 txq->tx_ring[i] = zeroed_desc;
1254 /* Initialize ring entries */
1255 prev = (uint16_t)(txq->nb_tx_desc - 1);
1256 for (i = 0; i < txq->nb_tx_desc; i++) {
1257 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1259 txd->wb.status = E1000_TXD_STAT_DD;
1262 txe[prev].next_id = i;
1266 txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1267 /* 82575 specific, each tx queue will use 2 hw contexts */
1268 if (hw->mac.type == e1000_82575)
1269 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1271 igb_reset_tx_queue_stat(txq);
1275 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1278 unsigned int socket_id,
1279 const struct rte_eth_txconf *tx_conf)
1281 const struct rte_memzone *tz;
1282 struct igb_tx_queue *txq;
1283 struct e1000_hw *hw;
1286 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289 * Validate number of transmit descriptors.
1290 * It must not exceed hardware maximum, and must be multiple
1293 if (nb_desc % IGB_TXD_ALIGN != 0 ||
1294 (nb_desc > E1000_MAX_RING_DESC) ||
1295 (nb_desc < E1000_MIN_RING_DESC)) {
1300 * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1303 if (tx_conf->tx_free_thresh != 0)
1304 PMD_INIT_LOG(INFO, "The tx_free_thresh parameter is not "
1305 "used for the 1G driver.");
1306 if (tx_conf->tx_rs_thresh != 0)
1307 PMD_INIT_LOG(INFO, "The tx_rs_thresh parameter is not "
1308 "used for the 1G driver.");
1309 if (tx_conf->tx_thresh.wthresh == 0 && hw->mac.type != e1000_82576)
1310 PMD_INIT_LOG(INFO, "To improve 1G driver performance, "
1311 "consider setting the TX WTHRESH value to 4, 8, "
1314 /* Free memory prior to re-allocation if needed */
1315 if (dev->data->tx_queues[queue_idx] != NULL) {
1316 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1317 dev->data->tx_queues[queue_idx] = NULL;
1320 /* First allocate the tx queue data structure */
1321 txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1322 RTE_CACHE_LINE_SIZE);
1327 * Allocate TX ring hardware descriptors. A memzone large enough to
1328 * handle the maximum ring size is allocated in order to allow for
1329 * resizing in later calls to the queue setup function.
1331 size = sizeof(union e1000_adv_tx_desc) * E1000_MAX_RING_DESC;
1332 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, size,
1333 E1000_ALIGN, socket_id);
1335 igb_tx_queue_release(txq);
1339 txq->nb_tx_desc = nb_desc;
1340 txq->pthresh = tx_conf->tx_thresh.pthresh;
1341 txq->hthresh = tx_conf->tx_thresh.hthresh;
1342 txq->wthresh = tx_conf->tx_thresh.wthresh;
1343 if (txq->wthresh > 0 && hw->mac.type == e1000_82576)
1345 txq->queue_id = queue_idx;
1346 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1347 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1348 txq->port_id = dev->data->port_id;
1350 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1351 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1353 txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1354 /* Allocate software ring */
1355 txq->sw_ring = rte_zmalloc("txq->sw_ring",
1356 sizeof(struct igb_tx_entry) * nb_desc,
1357 RTE_CACHE_LINE_SIZE);
1358 if (txq->sw_ring == NULL) {
1359 igb_tx_queue_release(txq);
1362 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1363 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1365 igb_reset_tx_queue(txq, dev);
1366 dev->tx_pkt_burst = eth_igb_xmit_pkts;
1367 dev->data->tx_queues[queue_idx] = txq;
1373 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1377 if (rxq->sw_ring != NULL) {
1378 for (i = 0; i < rxq->nb_rx_desc; i++) {
1379 if (rxq->sw_ring[i].mbuf != NULL) {
1380 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1381 rxq->sw_ring[i].mbuf = NULL;
1388 igb_rx_queue_release(struct igb_rx_queue *rxq)
1391 igb_rx_queue_release_mbufs(rxq);
1392 rte_free(rxq->sw_ring);
1398 eth_igb_rx_queue_release(void *rxq)
1400 igb_rx_queue_release(rxq);
1404 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1406 static const union e1000_adv_rx_desc zeroed_desc = {{0}};
1409 /* Zero out HW ring memory */
1410 for (i = 0; i < rxq->nb_rx_desc; i++) {
1411 rxq->rx_ring[i] = zeroed_desc;
1415 rxq->pkt_first_seg = NULL;
1416 rxq->pkt_last_seg = NULL;
1420 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1423 unsigned int socket_id,
1424 const struct rte_eth_rxconf *rx_conf,
1425 struct rte_mempool *mp)
1427 const struct rte_memzone *rz;
1428 struct igb_rx_queue *rxq;
1429 struct e1000_hw *hw;
1432 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435 * Validate number of receive descriptors.
1436 * It must not exceed hardware maximum, and must be multiple
1439 if (nb_desc % IGB_RXD_ALIGN != 0 ||
1440 (nb_desc > E1000_MAX_RING_DESC) ||
1441 (nb_desc < E1000_MIN_RING_DESC)) {
1445 /* Free memory prior to re-allocation if needed */
1446 if (dev->data->rx_queues[queue_idx] != NULL) {
1447 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1448 dev->data->rx_queues[queue_idx] = NULL;
1451 /* First allocate the RX queue data structure. */
1452 rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1453 RTE_CACHE_LINE_SIZE);
1457 rxq->nb_rx_desc = nb_desc;
1458 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1459 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1460 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1461 if (rxq->wthresh > 0 &&
1462 (hw->mac.type == e1000_82576 || hw->mac.type == e1000_vfadapt_i350))
1464 rxq->drop_en = rx_conf->rx_drop_en;
1465 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1466 rxq->queue_id = queue_idx;
1467 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1468 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1469 rxq->port_id = dev->data->port_id;
1470 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1474 * Allocate RX ring hardware descriptors. A memzone large enough to
1475 * handle the maximum ring size is allocated in order to allow for
1476 * resizing in later calls to the queue setup function.
1478 size = sizeof(union e1000_adv_rx_desc) * E1000_MAX_RING_DESC;
1479 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size,
1480 E1000_ALIGN, socket_id);
1482 igb_rx_queue_release(rxq);
1485 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1486 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1487 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1488 rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1490 /* Allocate software ring. */
1491 rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1492 sizeof(struct igb_rx_entry) * nb_desc,
1493 RTE_CACHE_LINE_SIZE);
1494 if (rxq->sw_ring == NULL) {
1495 igb_rx_queue_release(rxq);
1498 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1499 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1501 dev->data->rx_queues[queue_idx] = rxq;
1502 igb_reset_rx_queue(rxq);
1508 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1510 #define IGB_RXQ_SCAN_INTERVAL 4
1511 volatile union e1000_adv_rx_desc *rxdp;
1512 struct igb_rx_queue *rxq;
1515 if (rx_queue_id >= dev->data->nb_rx_queues) {
1516 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
1520 rxq = dev->data->rx_queues[rx_queue_id];
1521 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1523 while ((desc < rxq->nb_rx_desc) &&
1524 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1525 desc += IGB_RXQ_SCAN_INTERVAL;
1526 rxdp += IGB_RXQ_SCAN_INTERVAL;
1527 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1528 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1529 desc - rxq->nb_rx_desc]);
1536 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1538 volatile union e1000_adv_rx_desc *rxdp;
1539 struct igb_rx_queue *rxq = rx_queue;
1542 if (unlikely(offset >= rxq->nb_rx_desc))
1544 desc = rxq->rx_tail + offset;
1545 if (desc >= rxq->nb_rx_desc)
1546 desc -= rxq->nb_rx_desc;
1548 rxdp = &rxq->rx_ring[desc];
1549 return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1553 igb_dev_clear_queues(struct rte_eth_dev *dev)
1556 struct igb_tx_queue *txq;
1557 struct igb_rx_queue *rxq;
1559 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1560 txq = dev->data->tx_queues[i];
1562 igb_tx_queue_release_mbufs(txq);
1563 igb_reset_tx_queue(txq, dev);
1567 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1568 rxq = dev->data->rx_queues[i];
1570 igb_rx_queue_release_mbufs(rxq);
1571 igb_reset_rx_queue(rxq);
1577 igb_dev_free_queues(struct rte_eth_dev *dev)
1581 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1582 eth_igb_rx_queue_release(dev->data->rx_queues[i]);
1583 dev->data->rx_queues[i] = NULL;
1585 dev->data->nb_rx_queues = 0;
1587 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1588 eth_igb_tx_queue_release(dev->data->tx_queues[i]);
1589 dev->data->tx_queues[i] = NULL;
1591 dev->data->nb_tx_queues = 0;
1595 * Receive Side Scaling (RSS).
1596 * See section 7.1.1.7 in the following document:
1597 * "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1600 * The source and destination IP addresses of the IP header and the source and
1601 * destination ports of TCP/UDP headers, if any, of received packets are hashed
1602 * against a configurable random key to compute a 32-bit RSS hash result.
1603 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1604 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
1605 * RSS output index which is used as the RX queue index where to store the
1607 * The following output is supplied in the RX write-back descriptor:
1608 * - 32-bit result of the Microsoft RSS hash function,
1609 * - 4-bit RSS type field.
1613 * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1614 * Used as the default key.
1616 static uint8_t rss_intel_key[40] = {
1617 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1618 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1619 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1620 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1621 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1625 igb_rss_disable(struct rte_eth_dev *dev)
1627 struct e1000_hw *hw;
1630 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1632 mrqc &= ~E1000_MRQC_ENABLE_MASK;
1633 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1637 igb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf)
1645 hash_key = rss_conf->rss_key;
1646 if (hash_key != NULL) {
1647 /* Fill in RSS hash key */
1648 for (i = 0; i < 10; i++) {
1649 rss_key = hash_key[(i * 4)];
1650 rss_key |= hash_key[(i * 4) + 1] << 8;
1651 rss_key |= hash_key[(i * 4) + 2] << 16;
1652 rss_key |= hash_key[(i * 4) + 3] << 24;
1653 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1657 /* Set configured hashing protocols in MRQC register */
1658 rss_hf = rss_conf->rss_hf;
1659 mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1660 if (rss_hf & ETH_RSS_IPV4)
1661 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1662 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1663 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1664 if (rss_hf & ETH_RSS_IPV6)
1665 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1666 if (rss_hf & ETH_RSS_IPV6_EX)
1667 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1668 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1669 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1670 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1671 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1672 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1673 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1674 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1675 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1676 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1677 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1678 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1682 eth_igb_rss_hash_update(struct rte_eth_dev *dev,
1683 struct rte_eth_rss_conf *rss_conf)
1685 struct e1000_hw *hw;
1689 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692 * Before changing anything, first check that the update RSS operation
1693 * does not attempt to disable RSS, if RSS was enabled at
1694 * initialization time, or does not attempt to enable RSS, if RSS was
1695 * disabled at initialization time.
1697 rss_hf = rss_conf->rss_hf & IGB_RSS_OFFLOAD_ALL;
1698 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1699 if (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */
1700 if (rss_hf != 0) /* Enable RSS */
1702 return 0; /* Nothing to do */
1705 if (rss_hf == 0) /* Disable RSS */
1707 igb_hw_rss_hash_set(hw, rss_conf);
1711 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
1712 struct rte_eth_rss_conf *rss_conf)
1714 struct e1000_hw *hw;
1721 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722 hash_key = rss_conf->rss_key;
1723 if (hash_key != NULL) {
1724 /* Return RSS hash key */
1725 for (i = 0; i < 10; i++) {
1726 rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i);
1727 hash_key[(i * 4)] = rss_key & 0x000000FF;
1728 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
1729 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
1730 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
1734 /* Get RSS functions configured in MRQC register */
1735 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1736 if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */
1737 rss_conf->rss_hf = 0;
1741 if (mrqc & E1000_MRQC_RSS_FIELD_IPV4)
1742 rss_hf |= ETH_RSS_IPV4;
1743 if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP)
1744 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1745 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6)
1746 rss_hf |= ETH_RSS_IPV6;
1747 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX)
1748 rss_hf |= ETH_RSS_IPV6_EX;
1749 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP)
1750 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1751 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX)
1752 rss_hf |= ETH_RSS_IPV6_TCP_EX;
1753 if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP)
1754 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1755 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP)
1756 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1757 if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX)
1758 rss_hf |= ETH_RSS_IPV6_UDP_EX;
1759 rss_conf->rss_hf = rss_hf;
1764 igb_rss_configure(struct rte_eth_dev *dev)
1766 struct rte_eth_rss_conf rss_conf;
1767 struct e1000_hw *hw;
1771 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773 /* Fill in redirection table. */
1774 shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1775 for (i = 0; i < 128; i++) {
1782 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1783 i % dev->data->nb_rx_queues : 0);
1784 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1786 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1790 * Configure the RSS key and the RSS protocols used to compute
1791 * the RSS hash of input packets.
1793 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
1794 if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {
1795 igb_rss_disable(dev);
1798 if (rss_conf.rss_key == NULL)
1799 rss_conf.rss_key = rss_intel_key; /* Default hash key */
1800 igb_hw_rss_hash_set(hw, &rss_conf);
1804 * Check if the mac type support VMDq or not.
1805 * Return 1 if it supports, otherwise, return 0.
1808 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1810 const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812 switch (hw->mac.type) {
1833 PMD_INIT_LOG(ERR, "Cannot support VMDq feature");
1839 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1841 struct rte_eth_vmdq_rx_conf *cfg;
1842 struct e1000_hw *hw;
1843 uint32_t mrqc, vt_ctl, vmolr, rctl;
1846 PMD_INIT_FUNC_TRACE();
1848 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1851 /* Check if mac type can support VMDq, return value of 0 means NOT support */
1852 if (igb_is_vmdq_supported(dev) == 0)
1855 igb_rss_disable(dev);
1857 /* RCTL: eanble VLAN filter */
1858 rctl = E1000_READ_REG(hw, E1000_RCTL);
1859 rctl |= E1000_RCTL_VFE;
1860 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1862 /* MRQC: enable vmdq */
1863 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1864 mrqc |= E1000_MRQC_ENABLE_VMDQ;
1865 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1867 /* VTCTL: pool selection according to VLAN tag */
1868 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1869 if (cfg->enable_default_pool)
1870 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1871 vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1872 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1874 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1875 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1876 vmolr &= ~(E1000_VMOLR_AUPE | E1000_VMOLR_ROMPE |
1877 E1000_VMOLR_ROPE | E1000_VMOLR_BAM |
1880 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
1881 vmolr |= E1000_VMOLR_AUPE;
1882 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
1883 vmolr |= E1000_VMOLR_ROMPE;
1884 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
1885 vmolr |= E1000_VMOLR_ROPE;
1886 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
1887 vmolr |= E1000_VMOLR_BAM;
1888 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
1889 vmolr |= E1000_VMOLR_MPME;
1891 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1895 * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1896 * Both 82576 and 82580 support it
1898 if (hw->mac.type != e1000_i350) {
1899 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1900 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1901 vmolr |= E1000_VMOLR_STRVLAN;
1902 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1906 /* VFTA - enable all vlan filters */
1907 for (i = 0; i < IGB_VFTA_SIZE; i++)
1908 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1910 /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1911 if (hw->mac.type != e1000_82580)
1912 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1915 * RAH/RAL - allow pools to read specific mac addresses
1916 * In this case, all pools should be able to read from mac addr 0
1918 E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1919 E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1921 /* VLVF: set up filters for vlan tags as configured */
1922 for (i = 0; i < cfg->nb_pool_maps; i++) {
1923 /* set vlan id in VF register and set the valid bit */
1924 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1925 (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1926 ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1927 E1000_VLVF_POOLSEL_MASK)));
1930 E1000_WRITE_FLUSH(hw);
1936 /*********************************************************************
1938 * Enable receive unit.
1940 **********************************************************************/
1943 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1945 struct igb_rx_entry *rxe = rxq->sw_ring;
1949 /* Initialize software ring entries. */
1950 for (i = 0; i < rxq->nb_rx_desc; i++) {
1951 volatile union e1000_adv_rx_desc *rxd;
1952 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
1955 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1956 "queue_id=%hu", rxq->queue_id);
1960 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
1961 rxd = &rxq->rx_ring[i];
1962 rxd->read.hdr_addr = 0;
1963 rxd->read.pkt_addr = dma_addr;
1970 #define E1000_MRQC_DEF_Q_SHIFT (3)
1972 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
1974 struct e1000_hw *hw =
1975 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978 if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
1980 * SRIOV active scheme
1981 * FIXME if support RSS together with VMDq & SRIOV
1983 mrqc = E1000_MRQC_ENABLE_VMDQ;
1984 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
1985 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
1986 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1987 } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
1989 * SRIOV inactive scheme
1991 switch (dev->data->dev_conf.rxmode.mq_mode) {
1993 igb_rss_configure(dev);
1995 case ETH_MQ_RX_VMDQ_ONLY:
1996 /*Configure general VMDQ only RX parameters*/
1997 igb_vmdq_rx_hw_configure(dev);
1999 case ETH_MQ_RX_NONE:
2000 /* if mq_mode is none, disable rss mode.*/
2002 igb_rss_disable(dev);
2011 eth_igb_rx_init(struct rte_eth_dev *dev)
2013 struct e1000_hw *hw;
2014 struct igb_rx_queue *rxq;
2019 uint16_t rctl_bsize;
2023 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027 * Make sure receives are disabled while setting
2028 * up the descriptor ring.
2030 rctl = E1000_READ_REG(hw, E1000_RCTL);
2031 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2034 * Configure support of jumbo frames, if any.
2036 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
2037 rctl |= E1000_RCTL_LPE;
2040 * Set maximum packet length by default, and might be updated
2041 * together with enabling/disabling dual VLAN.
2043 E1000_WRITE_REG(hw, E1000_RLPML,
2044 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2047 rctl &= ~E1000_RCTL_LPE;
2049 /* Configure and enable each RX queue. */
2051 dev->rx_pkt_burst = eth_igb_recv_pkts;
2052 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2056 rxq = dev->data->rx_queues[i];
2058 /* Allocate buffers for descriptor rings and set up queue */
2059 ret = igb_alloc_rx_queue_mbufs(rxq);
2064 * Reset crc_len in case it was changed after queue setup by a
2068 (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
2071 bus_addr = rxq->rx_ring_phys_addr;
2072 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
2074 sizeof(union e1000_adv_rx_desc));
2075 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
2076 (uint32_t)(bus_addr >> 32));
2077 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
2079 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2082 * Configure RX buffer size.
2084 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2085 RTE_PKTMBUF_HEADROOM);
2086 if (buf_size >= 1024) {
2088 * Configure the BSIZEPACKET field of the SRRCTL
2089 * register of the queue.
2090 * Value is in 1 KB resolution, from 1 KB to 127 KB.
2091 * If this field is equal to 0b, then RCTL.BSIZE
2092 * determines the RX packet buffer size.
2094 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2095 E1000_SRRCTL_BSIZEPKT_MASK);
2096 buf_size = (uint16_t) ((srrctl &
2097 E1000_SRRCTL_BSIZEPKT_MASK) <<
2098 E1000_SRRCTL_BSIZEPKT_SHIFT);
2100 /* It adds dual VLAN length for supporting dual VLAN */
2101 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2102 2 * VLAN_TAG_SIZE) > buf_size){
2103 if (!dev->data->scattered_rx)
2105 "forcing scatter mode");
2106 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2107 dev->data->scattered_rx = 1;
2111 * Use BSIZE field of the device RCTL register.
2113 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2114 rctl_bsize = buf_size;
2115 if (!dev->data->scattered_rx)
2116 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2117 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2118 dev->data->scattered_rx = 1;
2121 /* Set if packets are dropped when no descriptors available */
2123 srrctl |= E1000_SRRCTL_DROP_EN;
2125 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
2127 /* Enable this RX queue. */
2128 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
2129 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2130 rxdctl &= 0xFFF00000;
2131 rxdctl |= (rxq->pthresh & 0x1F);
2132 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2133 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2134 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
2137 if (dev->data->dev_conf.rxmode.enable_scatter) {
2138 if (!dev->data->scattered_rx)
2139 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2140 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2141 dev->data->scattered_rx = 1;
2145 * Setup BSIZE field of RCTL register, if needed.
2146 * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
2147 * register, since the code above configures the SRRCTL register of
2148 * the RX queue in such a case.
2149 * All configurable sizes are:
2150 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
2151 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
2152 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
2153 * 2048: rctl |= E1000_RCTL_SZ_2048;
2154 * 1024: rctl |= E1000_RCTL_SZ_1024;
2155 * 512: rctl |= E1000_RCTL_SZ_512;
2156 * 256: rctl |= E1000_RCTL_SZ_256;
2158 if (rctl_bsize > 0) {
2159 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
2160 rctl |= E1000_RCTL_SZ_512;
2161 else /* 256 <= buf_size < 512 - use 256 */
2162 rctl |= E1000_RCTL_SZ_256;
2166 * Configure RSS if device configured with multiple RX queues.
2168 igb_dev_mq_rx_configure(dev);
2170 /* Update the rctl since igb_dev_mq_rx_configure may change its value */
2171 rctl |= E1000_READ_REG(hw, E1000_RCTL);
2174 * Setup the Checksum Register.
2175 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
2177 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2178 rxcsum |= E1000_RXCSUM_PCSD;
2180 /* Enable both L3/L4 rx checksum offload */
2181 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
2182 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2184 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2185 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2187 /* Setup the Receive Control Register. */
2188 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
2189 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
2191 /* set STRCRC bit in all queues */
2192 if (hw->mac.type == e1000_i350 ||
2193 hw->mac.type == e1000_i210 ||
2194 hw->mac.type == e1000_i211 ||
2195 hw->mac.type == e1000_i354) {
2196 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2197 rxq = dev->data->rx_queues[i];
2198 uint32_t dvmolr = E1000_READ_REG(hw,
2199 E1000_DVMOLR(rxq->reg_idx));
2200 dvmolr |= E1000_DVMOLR_STRCRC;
2201 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2205 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
2207 /* clear STRCRC bit in all queues */
2208 if (hw->mac.type == e1000_i350 ||
2209 hw->mac.type == e1000_i210 ||
2210 hw->mac.type == e1000_i211 ||
2211 hw->mac.type == e1000_i354) {
2212 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2213 rxq = dev->data->rx_queues[i];
2214 uint32_t dvmolr = E1000_READ_REG(hw,
2215 E1000_DVMOLR(rxq->reg_idx));
2216 dvmolr &= ~E1000_DVMOLR_STRCRC;
2217 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2222 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2223 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2224 E1000_RCTL_RDMTS_HALF |
2225 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2227 /* Make sure VLAN Filters are off. */
2228 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
2229 rctl &= ~E1000_RCTL_VFE;
2230 /* Don't store bad packets. */
2231 rctl &= ~E1000_RCTL_SBP;
2233 /* Enable Receives. */
2234 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2237 * Setup the HW Rx Head and Tail Descriptor Pointers.
2238 * This needs to be done after enable.
2240 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2241 rxq = dev->data->rx_queues[i];
2242 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
2243 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
2249 /*********************************************************************
2251 * Enable transmit unit.
2253 **********************************************************************/
2255 eth_igb_tx_init(struct rte_eth_dev *dev)
2257 struct e1000_hw *hw;
2258 struct igb_tx_queue *txq;
2263 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265 /* Setup the Base and Length of the Tx Descriptor Rings. */
2266 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2268 txq = dev->data->tx_queues[i];
2269 bus_addr = txq->tx_ring_phys_addr;
2271 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2273 sizeof(union e1000_adv_tx_desc));
2274 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2275 (uint32_t)(bus_addr >> 32));
2276 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2278 /* Setup the HW Tx Head and Tail descriptor pointers. */
2279 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2280 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2282 /* Setup Transmit threshold registers. */
2283 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2284 txdctl |= txq->pthresh & 0x1F;
2285 txdctl |= ((txq->hthresh & 0x1F) << 8);
2286 txdctl |= ((txq->wthresh & 0x1F) << 16);
2287 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2288 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2291 /* Program the Transmit Control Register. */
2292 tctl = E1000_READ_REG(hw, E1000_TCTL);
2293 tctl &= ~E1000_TCTL_CT;
2294 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2295 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2297 e1000_config_collision_dist(hw);
2299 /* This write will effectively turn on the transmit unit. */
2300 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2303 /*********************************************************************
2305 * Enable VF receive unit.
2307 **********************************************************************/
2309 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2311 struct e1000_hw *hw;
2312 struct igb_rx_queue *rxq;
2315 uint16_t rctl_bsize;
2319 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322 e1000_rlpml_set_vf(hw,
2323 (uint16_t)(dev->data->dev_conf.rxmode.max_rx_pkt_len +
2326 /* Configure and enable each RX queue. */
2328 dev->rx_pkt_burst = eth_igb_recv_pkts;
2329 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2333 rxq = dev->data->rx_queues[i];
2335 /* Allocate buffers for descriptor rings and set up queue */
2336 ret = igb_alloc_rx_queue_mbufs(rxq);
2340 bus_addr = rxq->rx_ring_phys_addr;
2341 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2343 sizeof(union e1000_adv_rx_desc));
2344 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2345 (uint32_t)(bus_addr >> 32));
2346 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2348 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2351 * Configure RX buffer size.
2353 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2354 RTE_PKTMBUF_HEADROOM);
2355 if (buf_size >= 1024) {
2357 * Configure the BSIZEPACKET field of the SRRCTL
2358 * register of the queue.
2359 * Value is in 1 KB resolution, from 1 KB to 127 KB.
2360 * If this field is equal to 0b, then RCTL.BSIZE
2361 * determines the RX packet buffer size.
2363 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2364 E1000_SRRCTL_BSIZEPKT_MASK);
2365 buf_size = (uint16_t) ((srrctl &
2366 E1000_SRRCTL_BSIZEPKT_MASK) <<
2367 E1000_SRRCTL_BSIZEPKT_SHIFT);
2369 /* It adds dual VLAN length for supporting dual VLAN */
2370 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2371 2 * VLAN_TAG_SIZE) > buf_size){
2372 if (!dev->data->scattered_rx)
2374 "forcing scatter mode");
2375 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2376 dev->data->scattered_rx = 1;
2380 * Use BSIZE field of the device RCTL register.
2382 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2383 rctl_bsize = buf_size;
2384 if (!dev->data->scattered_rx)
2385 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2386 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2387 dev->data->scattered_rx = 1;
2390 /* Set if packets are dropped when no descriptors available */
2392 srrctl |= E1000_SRRCTL_DROP_EN;
2394 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2396 /* Enable this RX queue. */
2397 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2398 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2399 rxdctl &= 0xFFF00000;
2400 rxdctl |= (rxq->pthresh & 0x1F);
2401 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2402 if (hw->mac.type == e1000_vfadapt) {
2404 * Workaround of 82576 VF Erratum
2405 * force set WTHRESH to 1
2406 * to avoid Write-Back not triggered sometimes
2409 PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !");
2412 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2413 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2416 if (dev->data->dev_conf.rxmode.enable_scatter) {
2417 if (!dev->data->scattered_rx)
2418 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2419 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2420 dev->data->scattered_rx = 1;
2424 * Setup the HW Rx Head and Tail Descriptor Pointers.
2425 * This needs to be done after enable.
2427 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2428 rxq = dev->data->rx_queues[i];
2429 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2430 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2436 /*********************************************************************
2438 * Enable VF transmit unit.
2440 **********************************************************************/
2442 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2444 struct e1000_hw *hw;
2445 struct igb_tx_queue *txq;
2449 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451 /* Setup the Base and Length of the Tx Descriptor Rings. */
2452 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2455 txq = dev->data->tx_queues[i];
2456 bus_addr = txq->tx_ring_phys_addr;
2457 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2459 sizeof(union e1000_adv_tx_desc));
2460 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2461 (uint32_t)(bus_addr >> 32));
2462 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2464 /* Setup the HW Tx Head and Tail descriptor pointers. */
2465 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2466 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2468 /* Setup Transmit threshold registers. */
2469 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2470 txdctl |= txq->pthresh & 0x1F;
2471 txdctl |= ((txq->hthresh & 0x1F) << 8);
2472 if (hw->mac.type == e1000_82576) {
2474 * Workaround of 82576 VF Erratum
2475 * force set WTHRESH to 1
2476 * to avoid Write-Back not triggered sometimes
2479 PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !");
2482 txdctl |= ((txq->wthresh & 0x1F) << 16);
2483 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2484 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2490 igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2491 struct rte_eth_rxq_info *qinfo)
2493 struct igb_rx_queue *rxq;
2495 rxq = dev->data->rx_queues[queue_id];
2497 qinfo->mp = rxq->mb_pool;
2498 qinfo->scattered_rx = dev->data->scattered_rx;
2499 qinfo->nb_desc = rxq->nb_rx_desc;
2501 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2502 qinfo->conf.rx_drop_en = rxq->drop_en;
2506 igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2507 struct rte_eth_txq_info *qinfo)
2509 struct igb_tx_queue *txq;
2511 txq = dev->data->tx_queues[queue_id];
2513 qinfo->nb_desc = txq->nb_tx_desc;
2515 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2516 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2517 qinfo->conf.tx_thresh.wthresh = txq->wthresh;