drivers/net/ena/base/ena_com.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include "ena_com.h"
   7
   8 /*****************************************************************************/
   9 /*****************************************************************************/
  10
  11 /* Timeout in micro-sec */
  12 #define ADMIN_CMD_TIMEOUT_US (3000000)
  13
  14 #define ENA_ASYNC_QUEUE_DEPTH 16
  15 #define ENA_ADMIN_QUEUE_DEPTH 32
  16
  17 #define ENA_CTRL_MAJOR          0
  18 #define ENA_CTRL_MINOR          0
  19 #define ENA_CTRL_SUB_MINOR      1
  20
  21 #define MIN_ENA_CTRL_VER \
  22         (((ENA_CTRL_MAJOR) << \
  23         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  24         ((ENA_CTRL_MINOR) << \
  25         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  26         (ENA_CTRL_SUB_MINOR))
  27
  28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  30
  31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  32
  33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  34
  35 #define ENA_REGS_ADMIN_INTR_MASK 1
  36
  37 #define ENA_POLL_MS     5
  38
  39 /*****************************************************************************/
  40 /*****************************************************************************/
  41 /*****************************************************************************/
  42
  43 enum ena_cmd_status {
  44         ENA_CMD_SUBMITTED,
  45         ENA_CMD_COMPLETED,
  46         /* Abort - canceled by the driver */
  47         ENA_CMD_ABORTED,
  48 };
  49
  50 struct ena_comp_ctx {
  51         ena_wait_event_t wait_event;
  52         struct ena_admin_acq_entry *user_cqe;
  53         u32 comp_size;
  54         enum ena_cmd_status status;
  55         /* status from the device */
  56         u8 comp_status;
  57         u8 cmd_opcode;
  58         bool occupied;
  59 };
  60
  61 struct ena_com_stats_ctx {
  62         struct ena_admin_aq_get_stats_cmd get_cmd;
  63         struct ena_admin_acq_get_stats_resp get_resp;
  64 };
  65
  66 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  67                                        struct ena_common_mem_addr *ena_addr,
  68                                        dma_addr_t addr)
  69 {
  70         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  71                 ena_trc_err("dma address has more bits that the device supports\n");
  72                 return ENA_COM_INVAL;
  73         }
  74
  75         ena_addr->mem_addr_low = lower_32_bits(addr);
  76         ena_addr->mem_addr_high = upper_32_bits(addr);
  77
  78         return 0;
  79 }
  80
  81 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
  82 {
  83         struct ena_com_admin_sq *sq = &queue->sq;
  84         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
  85
  86         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
  87                                sq->mem_handle);
  88
  89         if (!sq->entries) {
  90                 ena_trc_err("memory allocation failed\n");
  91                 return ENA_COM_NO_MEM;
  92         }
  93
  94         sq->head = 0;
  95         sq->tail = 0;
  96         sq->phase = 1;
  97
  98         sq->db_addr = NULL;
  99
 100         return 0;
 101 }
 102
 103 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 104 {
 105         struct ena_com_admin_cq *cq = &queue->cq;
 106         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 107
 108         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
 109                                cq->mem_handle);
 110
 111         if (!cq->entries)  {
 112                 ena_trc_err("memory allocation failed\n");
 113                 return ENA_COM_NO_MEM;
 114         }
 115
 116         cq->head = 0;
 117         cq->phase = 1;
 118
 119         return 0;
 120 }
 121
 122 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 123                                    struct ena_aenq_handlers *aenq_handlers)
 124 {
 125         struct ena_com_aenq *aenq = &dev->aenq;
 126         u32 addr_low, addr_high, aenq_caps;
 127         u16 size;
 128
 129         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 130         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 131         ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
 132                         aenq->entries,
 133                         aenq->dma_addr,
 134                         aenq->mem_handle);
 135
 136         if (!aenq->entries) {
 137                 ena_trc_err("memory allocation failed\n");
 138                 return ENA_COM_NO_MEM;
 139         }
 140
 141         aenq->head = aenq->q_depth;
 142         aenq->phase = 1;
 143
 144         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 145         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 146
 147         ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 148         ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 149
 150         aenq_caps = 0;
 151         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 152         aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
 153                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 154                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 155         ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 156
 157         if (unlikely(!aenq_handlers)) {
 158                 ena_trc_err("aenq handlers pointer is NULL\n");
 159                 return ENA_COM_INVAL;
 160         }
 161
 162         aenq->aenq_handlers = aenq_handlers;
 163
 164         return 0;
 165 }
 166
 167 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 168                                      struct ena_comp_ctx *comp_ctx)
 169 {
 170         comp_ctx->occupied = false;
 171         ATOMIC32_DEC(&queue->outstanding_cmds);
 172 }
 173
 174 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 175                                           u16 command_id, bool capture)
 176 {
 177         if (unlikely(command_id >= queue->q_depth)) {
 178                 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 179                             command_id, queue->q_depth);
 180                 return NULL;
 181         }
 182
 183         if (unlikely(!queue->comp_ctx)) {
 184                 ena_trc_err("Completion context is NULL\n");
 185                 return NULL;
 186         }
 187
 188         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 189                 ena_trc_err("Completion context is occupied\n");
 190                 return NULL;
 191         }
 192
 193         if (capture) {
 194                 ATOMIC32_INC(&queue->outstanding_cmds);
 195                 queue->comp_ctx[command_id].occupied = true;
 196         }
 197
 198         return &queue->comp_ctx[command_id];
 199 }
 200
 201 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 202                                                        struct ena_admin_aq_entry *cmd,
 203                                                        size_t cmd_size_in_bytes,
 204                                                        struct ena_admin_acq_entry *comp,
 205                                                        size_t comp_size_in_bytes)
 206 {
 207         struct ena_comp_ctx *comp_ctx;
 208         u16 tail_masked, cmd_id;
 209         u16 queue_size_mask;
 210         u16 cnt;
 211
 212         queue_size_mask = admin_queue->q_depth - 1;
 213
 214         tail_masked = admin_queue->sq.tail & queue_size_mask;
 215
 216         /* In case of queue FULL */
 217         cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
 218         if (cnt >= admin_queue->q_depth) {
 219                 ena_trc_dbg("admin queue is full.\n");
 220                 admin_queue->stats.out_of_space++;
 221                 return ERR_PTR(ENA_COM_NO_SPACE);
 222         }
 223
 224         cmd_id = admin_queue->curr_cmd_id;
 225
 226         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 227                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 228
 229         cmd->aq_common_descriptor.command_id |= cmd_id &
 230                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 231
 232         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 233         if (unlikely(!comp_ctx))
 234                 return ERR_PTR(ENA_COM_INVAL);
 235
 236         comp_ctx->status = ENA_CMD_SUBMITTED;
 237         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 238         comp_ctx->user_cqe = comp;
 239         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 240
 241         ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
 242
 243         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 244
 245         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 246                 queue_size_mask;
 247
 248         admin_queue->sq.tail++;
 249         admin_queue->stats.submitted_cmd++;
 250
 251         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 252                 admin_queue->sq.phase = !admin_queue->sq.phase;
 253
 254         ENA_DB_SYNC(&admin_queue->sq.mem_handle);
 255         ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
 256                         admin_queue->sq.db_addr);
 257
 258         return comp_ctx;
 259 }
 260
 261 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 262 {
 263         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 264         struct ena_comp_ctx *comp_ctx;
 265         u16 i;
 266
 267         queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
 268         if (unlikely(!queue->comp_ctx)) {
 269                 ena_trc_err("memory allocation failed\n");
 270                 return ENA_COM_NO_MEM;
 271         }
 272
 273         for (i = 0; i < queue->q_depth; i++) {
 274                 comp_ctx = get_comp_ctxt(queue, i, false);
 275                 if (comp_ctx)
 276                         ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 283                                                      struct ena_admin_aq_entry *cmd,
 284                                                      size_t cmd_size_in_bytes,
 285                                                      struct ena_admin_acq_entry *comp,
 286                                                      size_t comp_size_in_bytes)
 287 {
 288         unsigned long flags = 0;
 289         struct ena_comp_ctx *comp_ctx;
 290
 291         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 292         if (unlikely(!admin_queue->running_state)) {
 293                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 294                 return ERR_PTR(ENA_COM_NO_DEVICE);
 295         }
 296         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 297                                               cmd_size_in_bytes,
 298                                               comp,
 299                                               comp_size_in_bytes);
 300         if (IS_ERR(comp_ctx))
 301                 admin_queue->running_state = false;
 302         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 303
 304         return comp_ctx;
 305 }
 306
 307 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 308                               struct ena_com_create_io_ctx *ctx,
 309                               struct ena_com_io_sq *io_sq)
 310 {
 311         size_t size;
 312         int dev_node = 0;
 313
 314         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 315
 316         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 317         io_sq->desc_entry_size =
 318                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 319                 sizeof(struct ena_eth_io_tx_desc) :
 320                 sizeof(struct ena_eth_io_rx_desc);
 321
 322         size = io_sq->desc_entry_size * io_sq->q_depth;
 323         io_sq->bus = ena_dev->bus;
 324
 325         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 326                 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 327                                             size,
 328                                             io_sq->desc_addr.virt_addr,
 329                                             io_sq->desc_addr.phys_addr,
 330                                             io_sq->desc_addr.mem_handle,
 331                                             ctx->numa_node,
 332                                             dev_node);
 333                 if (!io_sq->desc_addr.virt_addr) {
 334                         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 335                                                size,
 336                                                io_sq->desc_addr.virt_addr,
 337                                                io_sq->desc_addr.phys_addr,
 338                                                io_sq->desc_addr.mem_handle);
 339                 }
 340
 341                 if (!io_sq->desc_addr.virt_addr) {
 342                         ena_trc_err("memory allocation failed\n");
 343                         return ENA_COM_NO_MEM;
 344                 }
 345         }
 346
 347         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 348                 /* Allocate bounce buffers */
 349                 io_sq->bounce_buf_ctrl.buffer_size =
 350                         ena_dev->llq_info.desc_list_entry_size;
 351                 io_sq->bounce_buf_ctrl.buffers_num =
 352                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 353                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 354
 355                 size = io_sq->bounce_buf_ctrl.buffer_size *
 356                         io_sq->bounce_buf_ctrl.buffers_num;
 357
 358                 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
 359                                    size,
 360                                    io_sq->bounce_buf_ctrl.base_buffer,
 361                                    ctx->numa_node,
 362                                    dev_node);
 363                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 364                         io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
 365
 366                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 367                         ena_trc_err("bounce buffer memory allocation failed\n");
 368                         return ENA_COM_NO_MEM;
 369                 }
 370
 371                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 372                        sizeof(io_sq->llq_info));
 373
 374                 /* Initiate the first bounce buffer */
 375                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 376                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 377                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 378                        0x0, io_sq->llq_info.desc_list_entry_size);
 379                 io_sq->llq_buf_ctrl.descs_left_in_line =
 380                         io_sq->llq_info.descs_num_before_header;
 381
 382                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 383                         io_sq->entries_in_tx_burst_left =
 384                                 io_sq->llq_info.max_entries_in_tx_burst;
 385         }
 386
 387         io_sq->tail = 0;
 388         io_sq->next_to_comp = 0;
 389         io_sq->phase = 1;
 390
 391         return 0;
 392 }
 393
 394 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 395                               struct ena_com_create_io_ctx *ctx,
 396                               struct ena_com_io_cq *io_cq)
 397 {
 398         size_t size;
 399         int prev_node = 0;
 400
 401         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 402
 403         /* Use the basic completion descriptor for Rx */
 404         io_cq->cdesc_entry_size_in_bytes =
 405                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 406                 sizeof(struct ena_eth_io_tx_cdesc) :
 407                 sizeof(struct ena_eth_io_rx_cdesc_base);
 408
 409         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 410         io_cq->bus = ena_dev->bus;
 411
 412         ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 413                         size,
 414                         io_cq->cdesc_addr.virt_addr,
 415                         io_cq->cdesc_addr.phys_addr,
 416                         io_cq->cdesc_addr.mem_handle,
 417                         ctx->numa_node,
 418                         prev_node);
 419         if (!io_cq->cdesc_addr.virt_addr) {
 420                 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 421                                        size,
 422                                        io_cq->cdesc_addr.virt_addr,
 423                                        io_cq->cdesc_addr.phys_addr,
 424                                        io_cq->cdesc_addr.mem_handle);
 425         }
 426
 427         if (!io_cq->cdesc_addr.virt_addr) {
 428                 ena_trc_err("memory allocation failed\n");
 429                 return ENA_COM_NO_MEM;
 430         }
 431
 432         io_cq->phase = 1;
 433         io_cq->head = 0;
 434
 435         return 0;
 436 }
 437
 438 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 439                                                    struct ena_admin_acq_entry *cqe)
 440 {
 441         struct ena_comp_ctx *comp_ctx;
 442         u16 cmd_id;
 443
 444         cmd_id = cqe->acq_common_descriptor.command &
 445                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 446
 447         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 448         if (unlikely(!comp_ctx)) {
 449                 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
 450                 admin_queue->running_state = false;
 451                 return;
 452         }
 453
 454         comp_ctx->status = ENA_CMD_COMPLETED;
 455         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 456
 457         if (comp_ctx->user_cqe)
 458                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 459
 460         if (!admin_queue->polling)
 461                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
 462 }
 463
 464 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 465 {
 466         struct ena_admin_acq_entry *cqe = NULL;
 467         u16 comp_num = 0;
 468         u16 head_masked;
 469         u8 phase;
 470
 471         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 472         phase = admin_queue->cq.phase;
 473
 474         cqe = &admin_queue->cq.entries[head_masked];
 475
 476         /* Go over all the completions */
 477         while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
 478                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 479                 /* Do not read the rest of the completion entry before the
 480                  * phase bit was validated
 481                  */
 482                 dma_rmb();
 483                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 484
 485                 head_masked++;
 486                 comp_num++;
 487                 if (unlikely(head_masked == admin_queue->q_depth)) {
 488                         head_masked = 0;
 489                         phase = !phase;
 490                 }
 491
 492                 cqe = &admin_queue->cq.entries[head_masked];
 493         }
 494
 495         admin_queue->cq.head += comp_num;
 496         admin_queue->cq.phase = phase;
 497         admin_queue->sq.head += comp_num;
 498         admin_queue->stats.completed_cmd += comp_num;
 499 }
 500
 501 static int ena_com_comp_status_to_errno(u8 comp_status)
 502 {
 503         if (unlikely(comp_status != 0))
 504                 ena_trc_err("admin command failed[%u]\n", comp_status);
 505
 506         switch (comp_status) {
 507         case ENA_ADMIN_SUCCESS:
 508                 return ENA_COM_OK;
 509         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 510                 return ENA_COM_NO_MEM;
 511         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 512                 return ENA_COM_UNSUPPORTED;
 513         case ENA_ADMIN_BAD_OPCODE:
 514         case ENA_ADMIN_MALFORMED_REQUEST:
 515         case ENA_ADMIN_ILLEGAL_PARAMETER:
 516         case ENA_ADMIN_UNKNOWN_ERROR:
 517                 return ENA_COM_INVAL;
 518         }
 519
 520         return ENA_COM_INVAL;
 521 }
 522
 523 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 524                                                      struct ena_com_admin_queue *admin_queue)
 525 {
 526         unsigned long flags = 0;
 527         ena_time_t timeout;
 528         int ret;
 529
 530         timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
 531
 532         while (1) {
 533                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 534                 ena_com_handle_admin_completion(admin_queue);
 535                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 536
 537                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 538                         break;
 539
 540                 if (ENA_TIME_EXPIRE(timeout)) {
 541                         ena_trc_err("Wait for completion (polling) timeout\n");
 542                         /* ENA didn't have any completion */
 543                         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 544                         admin_queue->stats.no_completion++;
 545                         admin_queue->running_state = false;
 546                         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 547
 548                         ret = ENA_COM_TIMER_EXPIRED;
 549                         goto err;
 550                 }
 551
 552                 ENA_MSLEEP(ENA_POLL_MS);
 553         }
 554
 555         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 556                 ena_trc_err("Command was aborted\n");
 557                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 558                 admin_queue->stats.aborted_cmd++;
 559                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 560                 ret = ENA_COM_NO_DEVICE;
 561                 goto err;
 562         }
 563
 564         ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
 565                  "Invalid comp status %d\n", comp_ctx->status);
 566
 567         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 568 err:
 569         comp_ctxt_release(admin_queue, comp_ctx);
 570         return ret;
 571 }
 572
 573 /**
 574  * Set the LLQ configurations of the firmware
 575  *
 576  * The driver provides only the enabled feature values to the device,
 577  * which in turn, checks if they are supported.
 578  */
 579 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 580 {
 581         struct ena_com_admin_queue *admin_queue;
 582         struct ena_admin_set_feat_cmd cmd;
 583         struct ena_admin_set_feat_resp resp;
 584         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 585         int ret;
 586
 587         memset(&cmd, 0x0, sizeof(cmd));
 588         admin_queue = &ena_dev->admin_queue;
 589
 590         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 591         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 592
 593         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 594         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 595         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 596         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 597
 598         ret = ena_com_execute_admin_command(admin_queue,
 599                                             (struct ena_admin_aq_entry *)&cmd,
 600                                             sizeof(cmd),
 601                                             (struct ena_admin_acq_entry *)&resp,
 602                                             sizeof(resp));
 603
 604         if (unlikely(ret))
 605                 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
 606
 607         return ret;
 608 }
 609
 610 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 611                                    struct ena_admin_feature_llq_desc *llq_features,
 612                                    struct ena_llq_configurations *llq_default_cfg)
 613 {
 614         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 615         u16 supported_feat;
 616         int rc;
 617
 618         memset(llq_info, 0, sizeof(*llq_info));
 619
 620         supported_feat = llq_features->header_location_ctrl_supported;
 621
 622         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 623                 llq_info->header_location_ctrl =
 624                         llq_default_cfg->llq_header_location;
 625         } else {
 626                 ena_trc_err("Invalid header location control, supported: 0x%x\n",
 627                             supported_feat);
 628                 return -EINVAL;
 629         }
 630
 631         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 632                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 633                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 634                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 635                 } else  {
 636                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 637                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 638                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 639                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 640                         } else {
 641                                 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 642                                             supported_feat);
 643                                 return -EINVAL;
 644                         }
 645
 646                         ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 647                                     llq_default_cfg->llq_stride_ctrl,
 648                                     supported_feat,
 649                                     llq_info->desc_stride_ctrl);
 650                 }
 651         } else {
 652                 llq_info->desc_stride_ctrl = 0;
 653         }
 654
 655         supported_feat = llq_features->entry_size_ctrl_supported;
 656         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 657                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 658                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 659         } else {
 660                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 661                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 662                         llq_info->desc_list_entry_size = 128;
 663                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 664                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 665                         llq_info->desc_list_entry_size = 192;
 666                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 667                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 668                         llq_info->desc_list_entry_size = 256;
 669                 } else {
 670                         ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
 671                         return -EINVAL;
 672                 }
 673
 674                 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 675                             llq_default_cfg->llq_ring_entry_size,
 676                             supported_feat,
 677                             llq_info->desc_list_entry_size);
 678         }
 679         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 680                 /* The desc list entry size should be whole multiply of 8
 681                  * This requirement comes from __iowrite64_copy()
 682                  */
 683                 ena_trc_err("illegal entry size %d\n",
 684                             llq_info->desc_list_entry_size);
 685                 return -EINVAL;
 686         }
 687
 688         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 689                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 690                         sizeof(struct ena_eth_io_tx_desc);
 691         else
 692                 llq_info->descs_per_entry = 1;
 693
 694         supported_feat = llq_features->desc_num_before_header_supported;
 695         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 696                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 697         } else {
 698                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 699                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 700                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 701                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 702                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 703                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 704                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 705                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 706                 } else {
 707                         ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
 708                                     supported_feat);
 709                         return -EINVAL;
 710                 }
 711
 712                 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 713                             llq_default_cfg->llq_num_decs_before_header,
 714                             supported_feat,
 715                             llq_info->descs_num_before_header);
 716         }
 717
 718         llq_info->max_entries_in_tx_burst =
 719                 (u16)(llq_features->max_tx_burst_size / llq_default_cfg->llq_ring_entry_size_value);
 720
 721         rc = ena_com_set_llq(ena_dev);
 722         if (rc)
 723                 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
 724
 725         return rc;
 726 }
 727
 728 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 729                                                         struct ena_com_admin_queue *admin_queue)
 730 {
 731         unsigned long flags = 0;
 732         int ret;
 733
 734         ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
 735                             admin_queue->completion_timeout);
 736
 737         /* In case the command wasn't completed find out the root cause.
 738          * There might be 2 kinds of errors
 739          * 1) No completion (timeout reached)
 740          * 2) There is completion but the device didn't get any msi-x interrupt.
 741          */
 742         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 743                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 744                 ena_com_handle_admin_completion(admin_queue);
 745                 admin_queue->stats.no_completion++;
 746                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 747
 748                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 749                         ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 750                                     comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
 751                         /* Check if fallback to polling is enabled */
 752                         if (admin_queue->auto_polling)
 753                                 admin_queue->polling = true;
 754                 } else {
 755                         ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 756                                     comp_ctx->cmd_opcode, comp_ctx->status);
 757                 }
 758                 /* Check if shifted to polling mode.
 759                  * This will happen if there is a completion without an interrupt
 760                  * and autopolling mode is enabled. Continuing normal execution in such case
 761                  */
 762                 if (!admin_queue->polling) {
 763                         admin_queue->running_state = false;
 764                         ret = ENA_COM_TIMER_EXPIRED;
 765                         goto err;
 766                 }
 767         }
 768
 769         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 770 err:
 771         comp_ctxt_release(admin_queue, comp_ctx);
 772         return ret;
 773 }
 774
 775 /* This method read the hardware device register through posting writes
 776  * and waiting for response
 777  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 778  */
 779 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 780 {
 781         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 782         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 783                 mmio_read->read_resp;
 784         u32 mmio_read_reg, ret, i;
 785         unsigned long flags = 0;
 786         u32 timeout = mmio_read->reg_read_to;
 787
 788         ENA_MIGHT_SLEEP();
 789
 790         if (timeout == 0)
 791                 timeout = ENA_REG_READ_TIMEOUT;
 792
 793         /* If readless is disabled, perform regular read */
 794         if (!mmio_read->readless_supported)
 795                 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
 796
 797         ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
 798         mmio_read->seq_num++;
 799
 800         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 801         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 802                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 803         mmio_read_reg |= mmio_read->seq_num &
 804                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 805
 806         ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
 807                         ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 808
 809         for (i = 0; i < timeout; i++) {
 810                 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
 811                         break;
 812
 813                 ENA_UDELAY(1);
 814         }
 815
 816         if (unlikely(i == timeout)) {
 817                 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 818                             mmio_read->seq_num,
 819                             offset,
 820                             read_resp->req_id,
 821                             read_resp->reg_off);
 822                 ret = ENA_MMIO_READ_TIMEOUT;
 823                 goto err;
 824         }
 825
 826         if (read_resp->reg_off != offset) {
 827                 ena_trc_err("Read failure: wrong offset provided\n");
 828                 ret = ENA_MMIO_READ_TIMEOUT;
 829         } else {
 830                 ret = read_resp->reg_val;
 831         }
 832 err:
 833         ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
 834
 835         return ret;
 836 }
 837
 838 /* There are two types to wait for completion.
 839  * Polling mode - wait until the completion is available.
 840  * Async mode - wait on wait queue until the completion is ready
 841  * (or the timeout expired).
 842  * It is expected that the IRQ called ena_com_handle_admin_completion
 843  * to mark the completions.
 844  */
 845 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 846                                              struct ena_com_admin_queue *admin_queue)
 847 {
 848         if (admin_queue->polling)
 849                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 850                                                                  admin_queue);
 851
 852         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 853                                                             admin_queue);
 854 }
 855
 856 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 857                                  struct ena_com_io_sq *io_sq)
 858 {
 859         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 860         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 861         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 862         u8 direction;
 863         int ret;
 864
 865         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 866
 867         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 868                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 869         else
 870                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 871
 872         destroy_cmd.sq.sq_identity |= (direction <<
 873                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 874                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 875
 876         destroy_cmd.sq.sq_idx = io_sq->idx;
 877         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 878
 879         ret = ena_com_execute_admin_command(admin_queue,
 880                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 881                                             sizeof(destroy_cmd),
 882                                             (struct ena_admin_acq_entry *)&destroy_resp,
 883                                             sizeof(destroy_resp));
 884
 885         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
 886                 ena_trc_err("failed to destroy io sq error: %d\n", ret);
 887
 888         return ret;
 889 }
 890
 891 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 892                                   struct ena_com_io_sq *io_sq,
 893                                   struct ena_com_io_cq *io_cq)
 894 {
 895         size_t size;
 896
 897         if (io_cq->cdesc_addr.virt_addr) {
 898                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 899
 900                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 901                                       size,
 902                                       io_cq->cdesc_addr.virt_addr,
 903                                       io_cq->cdesc_addr.phys_addr,
 904                                       io_cq->cdesc_addr.mem_handle);
 905
 906                 io_cq->cdesc_addr.virt_addr = NULL;
 907         }
 908
 909         if (io_sq->desc_addr.virt_addr) {
 910                 size = io_sq->desc_entry_size * io_sq->q_depth;
 911
 912                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 913                                       size,
 914                                       io_sq->desc_addr.virt_addr,
 915                                       io_sq->desc_addr.phys_addr,
 916                                       io_sq->desc_addr.mem_handle);
 917
 918                 io_sq->desc_addr.virt_addr = NULL;
 919         }
 920
 921         if (io_sq->bounce_buf_ctrl.base_buffer) {
 922                 ENA_MEM_FREE(ena_dev->dmadev,
 923                              io_sq->bounce_buf_ctrl.base_buffer,
 924                              (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
 925                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 926         }
 927 }
 928
 929 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 930                                 u16 exp_state)
 931 {
 932         u32 val, i;
 933
 934         /* Convert timeout from resolution of 100ms to ENA_POLL_MS */
 935         timeout = (timeout * 100) / ENA_POLL_MS;
 936
 937         for (i = 0; i < timeout; i++) {
 938                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 939
 940                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 941                         ena_trc_err("Reg read timeout occurred\n");
 942                         return ENA_COM_TIMER_EXPIRED;
 943                 }
 944
 945                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 946                         exp_state)
 947                         return 0;
 948
 949                 ENA_MSLEEP(ENA_POLL_MS);
 950         }
 951
 952         return ENA_COM_TIMER_EXPIRED;
 953 }
 954
 955 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 956                                                enum ena_admin_aq_feature_id feature_id)
 957 {
 958         u32 feature_mask = 1 << feature_id;
 959
 960         /* Device attributes is always supported */
 961         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 962             !(ena_dev->supported_features & feature_mask))
 963                 return false;
 964
 965         return true;
 966 }
 967
 968 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 969                                   struct ena_admin_get_feat_resp *get_resp,
 970                                   enum ena_admin_aq_feature_id feature_id,
 971                                   dma_addr_t control_buf_dma_addr,
 972                                   u32 control_buff_size,
 973                                   u8 feature_ver)
 974 {
 975         struct ena_com_admin_queue *admin_queue;
 976         struct ena_admin_get_feat_cmd get_cmd;
 977         int ret;
 978
 979         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
 980                 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
 981                 return ENA_COM_UNSUPPORTED;
 982         }
 983
 984         memset(&get_cmd, 0x0, sizeof(get_cmd));
 985         admin_queue = &ena_dev->admin_queue;
 986
 987         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
 988
 989         if (control_buff_size)
 990                 get_cmd.aq_common_descriptor.flags =
 991                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
 992         else
 993                 get_cmd.aq_common_descriptor.flags = 0;
 994
 995         ret = ena_com_mem_addr_set(ena_dev,
 996                                    &get_cmd.control_buffer.address,
 997                                    control_buf_dma_addr);
 998         if (unlikely(ret)) {
 999                 ena_trc_err("memory address set failed\n");
1000                 return ret;
1001         }
1002
1003         get_cmd.control_buffer.length = control_buff_size;
1004         get_cmd.feat_common.feature_version = feature_ver;
1005         get_cmd.feat_common.feature_id = feature_id;
1006
1007         ret = ena_com_execute_admin_command(admin_queue,
1008                                             (struct ena_admin_aq_entry *)
1009                                             &get_cmd,
1010                                             sizeof(get_cmd),
1011                                             (struct ena_admin_acq_entry *)
1012                                             get_resp,
1013                                             sizeof(*get_resp));
1014
1015         if (unlikely(ret))
1016                 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1017                             feature_id, ret);
1018
1019         return ret;
1020 }
1021
1022 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1023                                struct ena_admin_get_feat_resp *get_resp,
1024                                enum ena_admin_aq_feature_id feature_id,
1025                                u8 feature_ver)
1026 {
1027         return ena_com_get_feature_ex(ena_dev,
1028                                       get_resp,
1029                                       feature_id,
1030                                       0,
1031                                       0,
1032                                       feature_ver);
1033 }
1034
1035 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1036 {
1037         struct ena_rss *rss = &ena_dev->rss;
1038
1039         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1040                                sizeof(*rss->hash_key),
1041                                rss->hash_key,
1042                                rss->hash_key_dma_addr,
1043                                rss->hash_key_mem_handle);
1044
1045         if (unlikely(!rss->hash_key))
1046                 return ENA_COM_NO_MEM;
1047
1048         return 0;
1049 }
1050
1051 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1052 {
1053         struct ena_rss *rss = &ena_dev->rss;
1054
1055         if (rss->hash_key)
1056                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1057                                       sizeof(*rss->hash_key),
1058                                       rss->hash_key,
1059                                       rss->hash_key_dma_addr,
1060                                       rss->hash_key_mem_handle);
1061         rss->hash_key = NULL;
1062 }
1063
1064 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1065 {
1066         struct ena_rss *rss = &ena_dev->rss;
1067
1068         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1069                                sizeof(*rss->hash_ctrl),
1070                                rss->hash_ctrl,
1071                                rss->hash_ctrl_dma_addr,
1072                                rss->hash_ctrl_mem_handle);
1073
1074         if (unlikely(!rss->hash_ctrl))
1075                 return ENA_COM_NO_MEM;
1076
1077         return 0;
1078 }
1079
1080 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1081 {
1082         struct ena_rss *rss = &ena_dev->rss;
1083
1084         if (rss->hash_ctrl)
1085                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1086                                       sizeof(*rss->hash_ctrl),
1087                                       rss->hash_ctrl,
1088                                       rss->hash_ctrl_dma_addr,
1089                                       rss->hash_ctrl_mem_handle);
1090         rss->hash_ctrl = NULL;
1091 }
1092
1093 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1094                                            u16 log_size)
1095 {
1096         struct ena_rss *rss = &ena_dev->rss;
1097         struct ena_admin_get_feat_resp get_resp;
1098         size_t tbl_size;
1099         int ret;
1100
1101         ret = ena_com_get_feature(ena_dev, &get_resp,
1102                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1103         if (unlikely(ret))
1104                 return ret;
1105
1106         if ((get_resp.u.ind_table.min_size > log_size) ||
1107             (get_resp.u.ind_table.max_size < log_size)) {
1108                 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1109                             1 << log_size,
1110                             1 << get_resp.u.ind_table.min_size,
1111                             1 << get_resp.u.ind_table.max_size);
1112                 return ENA_COM_INVAL;
1113         }
1114
1115         tbl_size = (1ULL << log_size) *
1116                 sizeof(struct ena_admin_rss_ind_table_entry);
1117
1118         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1119                              tbl_size,
1120                              rss->rss_ind_tbl,
1121                              rss->rss_ind_tbl_dma_addr,
1122                              rss->rss_ind_tbl_mem_handle);
1123         if (unlikely(!rss->rss_ind_tbl))
1124                 goto mem_err1;
1125
1126         tbl_size = (1ULL << log_size) * sizeof(u16);
1127         rss->host_rss_ind_tbl =
1128                 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1129         if (unlikely(!rss->host_rss_ind_tbl))
1130                 goto mem_err2;
1131
1132         rss->tbl_log_size = log_size;
1133
1134         return 0;
1135
1136 mem_err2:
1137         tbl_size = (1ULL << log_size) *
1138                 sizeof(struct ena_admin_rss_ind_table_entry);
1139
1140         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1141                               tbl_size,
1142                               rss->rss_ind_tbl,
1143                               rss->rss_ind_tbl_dma_addr,
1144                               rss->rss_ind_tbl_mem_handle);
1145         rss->rss_ind_tbl = NULL;
1146 mem_err1:
1147         rss->tbl_log_size = 0;
1148         return ENA_COM_NO_MEM;
1149 }
1150
1151 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1152 {
1153         struct ena_rss *rss = &ena_dev->rss;
1154         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1155                 sizeof(struct ena_admin_rss_ind_table_entry);
1156
1157         if (rss->rss_ind_tbl)
1158                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1159                                       tbl_size,
1160                                       rss->rss_ind_tbl,
1161                                       rss->rss_ind_tbl_dma_addr,
1162                                       rss->rss_ind_tbl_mem_handle);
1163         rss->rss_ind_tbl = NULL;
1164
1165         if (rss->host_rss_ind_tbl)
1166                 ENA_MEM_FREE(ena_dev->dmadev,
1167                              rss->host_rss_ind_tbl,
1168                              ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1169         rss->host_rss_ind_tbl = NULL;
1170 }
1171
1172 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1173                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1174 {
1175         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1176         struct ena_admin_aq_create_sq_cmd create_cmd;
1177         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1178         u8 direction;
1179         int ret;
1180
1181         memset(&create_cmd, 0x0, sizeof(create_cmd));
1182
1183         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1184
1185         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1186                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1187         else
1188                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1189
1190         create_cmd.sq_identity |= (direction <<
1191                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1192                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1193
1194         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1195                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1196
1197         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1198                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1199                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1200
1201         create_cmd.sq_caps_3 |=
1202                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1203
1204         create_cmd.cq_idx = cq_idx;
1205         create_cmd.sq_depth = io_sq->q_depth;
1206
1207         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1208                 ret = ena_com_mem_addr_set(ena_dev,
1209                                            &create_cmd.sq_ba,
1210                                            io_sq->desc_addr.phys_addr);
1211                 if (unlikely(ret)) {
1212                         ena_trc_err("memory address set failed\n");
1213                         return ret;
1214                 }
1215         }
1216
1217         ret = ena_com_execute_admin_command(admin_queue,
1218                                             (struct ena_admin_aq_entry *)&create_cmd,
1219                                             sizeof(create_cmd),
1220                                             (struct ena_admin_acq_entry *)&cmd_completion,
1221                                             sizeof(cmd_completion));
1222         if (unlikely(ret)) {
1223                 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1224                 return ret;
1225         }
1226
1227         io_sq->idx = cmd_completion.sq_idx;
1228
1229         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1230                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1231
1232         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1233                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1234                                 + cmd_completion.llq_headers_offset);
1235
1236                 io_sq->desc_addr.pbuf_dev_addr =
1237                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1238                         cmd_completion.llq_descriptors_offset);
1239         }
1240
1241         ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1242
1243         return ret;
1244 }
1245
1246 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1247 {
1248         struct ena_rss *rss = &ena_dev->rss;
1249         struct ena_com_io_sq *io_sq;
1250         u16 qid;
1251         int i;
1252
1253         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1254                 qid = rss->host_rss_ind_tbl[i];
1255                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1256                         return ENA_COM_INVAL;
1257
1258                 io_sq = &ena_dev->io_sq_queues[qid];
1259
1260                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1261                         return ENA_COM_INVAL;
1262
1263                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1270 {
1271         u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1272         struct ena_rss *rss = &ena_dev->rss;
1273         u8 idx;
1274         u16 i;
1275
1276         for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1277                 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1278
1279         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1280                 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1281                         return ENA_COM_INVAL;
1282                 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1283
1284                 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1285                         return ENA_COM_INVAL;
1286
1287                 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1294 {
1295         size_t size;
1296
1297         size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1298
1299         ena_dev->intr_moder_tbl = ENA_MEM_ALLOC(ena_dev->dmadev, size);
1300         if (!ena_dev->intr_moder_tbl)
1301                 return ENA_COM_NO_MEM;
1302
1303         ena_com_config_default_interrupt_moderation_table(ena_dev);
1304
1305         return 0;
1306 }
1307
1308 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1309                                                  u16 intr_delay_resolution)
1310 {
1311         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1312         unsigned int i;
1313
1314         if (!intr_delay_resolution) {
1315                 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1316                 intr_delay_resolution = 1;
1317         }
1318         ena_dev->intr_delay_resolution = intr_delay_resolution;
1319
1320         /* update Rx */
1321         for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1322                 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1323
1324         /* update Tx */
1325         ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1326 }
1327
1328 /*****************************************************************************/
1329 /*******************************      API       ******************************/
1330 /*****************************************************************************/
1331
1332 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1333                                   struct ena_admin_aq_entry *cmd,
1334                                   size_t cmd_size,
1335                                   struct ena_admin_acq_entry *comp,
1336                                   size_t comp_size)
1337 {
1338         struct ena_comp_ctx *comp_ctx;
1339         int ret;
1340
1341         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1342                                             comp, comp_size);
1343         if (IS_ERR(comp_ctx)) {
1344                 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1345                         ena_trc_dbg("Failed to submit command [%ld]\n",
1346                                     PTR_ERR(comp_ctx));
1347                 else
1348                         ena_trc_err("Failed to submit command [%ld]\n",
1349                                     PTR_ERR(comp_ctx));
1350
1351                 return PTR_ERR(comp_ctx);
1352         }
1353
1354         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1355         if (unlikely(ret)) {
1356                 if (admin_queue->running_state)
1357                         ena_trc_err("Failed to process command. ret = %d\n",
1358                                     ret);
1359                 else
1360                         ena_trc_dbg("Failed to process command. ret = %d\n",
1361                                     ret);
1362         }
1363         return ret;
1364 }
1365
1366 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1367                          struct ena_com_io_cq *io_cq)
1368 {
1369         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1370         struct ena_admin_aq_create_cq_cmd create_cmd;
1371         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1372         int ret;
1373
1374         memset(&create_cmd, 0x0, sizeof(create_cmd));
1375
1376         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1377
1378         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1379                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1380         create_cmd.cq_caps_1 |=
1381                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1382
1383         create_cmd.msix_vector = io_cq->msix_vector;
1384         create_cmd.cq_depth = io_cq->q_depth;
1385
1386         ret = ena_com_mem_addr_set(ena_dev,
1387                                    &create_cmd.cq_ba,
1388                                    io_cq->cdesc_addr.phys_addr);
1389         if (unlikely(ret)) {
1390                 ena_trc_err("memory address set failed\n");
1391                 return ret;
1392         }
1393
1394         ret = ena_com_execute_admin_command(admin_queue,
1395                                             (struct ena_admin_aq_entry *)&create_cmd,
1396                                             sizeof(create_cmd),
1397                                             (struct ena_admin_acq_entry *)&cmd_completion,
1398                                             sizeof(cmd_completion));
1399         if (unlikely(ret)) {
1400                 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1401                 return ret;
1402         }
1403
1404         io_cq->idx = cmd_completion.cq_idx;
1405
1406         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1407                 cmd_completion.cq_interrupt_unmask_register_offset);
1408
1409         if (cmd_completion.cq_head_db_register_offset)
1410                 io_cq->cq_head_db_reg =
1411                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1412                         cmd_completion.cq_head_db_register_offset);
1413
1414         if (cmd_completion.numa_node_register_offset)
1415                 io_cq->numa_node_cfg_reg =
1416                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1417                         cmd_completion.numa_node_register_offset);
1418
1419         ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1420
1421         return ret;
1422 }
1423
1424 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1425                             struct ena_com_io_sq **io_sq,
1426                             struct ena_com_io_cq **io_cq)
1427 {
1428         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1429                 ena_trc_err("Invalid queue number %d but the max is %d\n",
1430                             qid, ENA_TOTAL_NUM_QUEUES);
1431                 return ENA_COM_INVAL;
1432         }
1433
1434         *io_sq = &ena_dev->io_sq_queues[qid];
1435         *io_cq = &ena_dev->io_cq_queues[qid];
1436
1437         return 0;
1438 }
1439
1440 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1441 {
1442         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1443         struct ena_comp_ctx *comp_ctx;
1444         u16 i;
1445
1446         if (!admin_queue->comp_ctx)
1447                 return;
1448
1449         for (i = 0; i < admin_queue->q_depth; i++) {
1450                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1451                 if (unlikely(!comp_ctx))
1452                         break;
1453
1454                 comp_ctx->status = ENA_CMD_ABORTED;
1455
1456                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1457         }
1458 }
1459
1460 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1461 {
1462         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1463         unsigned long flags = 0;
1464
1465         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1466         while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1467                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1468                 ENA_MSLEEP(ENA_POLL_MS);
1469                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1470         }
1471         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1472 }
1473
1474 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1475                           struct ena_com_io_cq *io_cq)
1476 {
1477         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1478         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1479         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1480         int ret;
1481
1482         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1483
1484         destroy_cmd.cq_idx = io_cq->idx;
1485         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1486
1487         ret = ena_com_execute_admin_command(admin_queue,
1488                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1489                                             sizeof(destroy_cmd),
1490                                             (struct ena_admin_acq_entry *)&destroy_resp,
1491                                             sizeof(destroy_resp));
1492
1493         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1494                 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1495
1496         return ret;
1497 }
1498
1499 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1500 {
1501         return ena_dev->admin_queue.running_state;
1502 }
1503
1504 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1505 {
1506         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1507         unsigned long flags = 0;
1508
1509         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1510         ena_dev->admin_queue.running_state = state;
1511         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1512 }
1513
1514 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1515 {
1516         u16 depth = ena_dev->aenq.q_depth;
1517
1518         ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1519
1520         /* Init head_db to mark that all entries in the queue
1521          * are initially available
1522          */
1523         ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1524 }
1525
1526 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1527 {
1528         struct ena_com_admin_queue *admin_queue;
1529         struct ena_admin_set_feat_cmd cmd;
1530         struct ena_admin_set_feat_resp resp;
1531         struct ena_admin_get_feat_resp get_resp;
1532         int ret;
1533
1534         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1535         if (ret) {
1536                 ena_trc_info("Can't get aenq configuration\n");
1537                 return ret;
1538         }
1539
1540         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1541                 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1542                              get_resp.u.aenq.supported_groups,
1543                              groups_flag);
1544                 return ENA_COM_UNSUPPORTED;
1545         }
1546
1547         memset(&cmd, 0x0, sizeof(cmd));
1548         admin_queue = &ena_dev->admin_queue;
1549
1550         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1551         cmd.aq_common_descriptor.flags = 0;
1552         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1553         cmd.u.aenq.enabled_groups = groups_flag;
1554
1555         ret = ena_com_execute_admin_command(admin_queue,
1556                                             (struct ena_admin_aq_entry *)&cmd,
1557                                             sizeof(cmd),
1558                                             (struct ena_admin_acq_entry *)&resp,
1559                                             sizeof(resp));
1560
1561         if (unlikely(ret))
1562                 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1563
1564         return ret;
1565 }
1566
1567 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1568 {
1569         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1570         int width;
1571
1572         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1573                 ena_trc_err("Reg read timeout occurred\n");
1574                 return ENA_COM_TIMER_EXPIRED;
1575         }
1576
1577         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1578                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1579
1580         ena_trc_dbg("ENA dma width: %d\n", width);
1581
1582         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1583                 ena_trc_err("DMA width illegal value: %d\n", width);
1584                 return ENA_COM_INVAL;
1585         }
1586
1587         ena_dev->dma_addr_bits = width;
1588
1589         return width;
1590 }
1591
1592 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1593 {
1594         u32 ver;
1595         u32 ctrl_ver;
1596         u32 ctrl_ver_masked;
1597
1598         /* Make sure the ENA version and the controller version are at least
1599          * as the driver expects
1600          */
1601         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1602         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1603                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1604
1605         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1606                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1607                 ena_trc_err("Reg read timeout occurred\n");
1608                 return ENA_COM_TIMER_EXPIRED;
1609         }
1610
1611         ena_trc_info("ena device version: %d.%d\n",
1612                      (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1613                      ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1614                      ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1615
1616         ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1617                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1618                      >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1619                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1620                      >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1621                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1622                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1623                      ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1624
1625         ctrl_ver_masked =
1626                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1627                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1628                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1629
1630         /* Validate the ctrl version without the implementation ID */
1631         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1632                 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1633                 return -1;
1634         }
1635
1636         return 0;
1637 }
1638
1639 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1640 {
1641         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1642         struct ena_com_admin_cq *cq = &admin_queue->cq;
1643         struct ena_com_admin_sq *sq = &admin_queue->sq;
1644         struct ena_com_aenq *aenq = &ena_dev->aenq;
1645         u16 size;
1646
1647         ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1648         if (admin_queue->comp_ctx)
1649                 ENA_MEM_FREE(ena_dev->dmadev,
1650                              admin_queue->comp_ctx,
1651                              (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1652         admin_queue->comp_ctx = NULL;
1653         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1654         if (sq->entries)
1655                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1656                                       sq->dma_addr, sq->mem_handle);
1657         sq->entries = NULL;
1658
1659         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1660         if (cq->entries)
1661                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1662                                       cq->dma_addr, cq->mem_handle);
1663         cq->entries = NULL;
1664
1665         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1666         if (ena_dev->aenq.entries)
1667                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1668                                       aenq->dma_addr, aenq->mem_handle);
1669         aenq->entries = NULL;
1670         ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1671 }
1672
1673 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1674 {
1675         u32 mask_value = 0;
1676
1677         if (polling)
1678                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1679
1680         ENA_REG_WRITE32(ena_dev->bus, mask_value,
1681                         ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1682         ena_dev->admin_queue.polling = polling;
1683 }
1684
1685 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1686 {
1687         return ena_dev->admin_queue.polling;
1688 }
1689
1690 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1691                                          bool polling)
1692 {
1693         ena_dev->admin_queue.auto_polling = polling;
1694 }
1695
1696 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1697 {
1698         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1699
1700         ENA_SPINLOCK_INIT(mmio_read->lock);
1701         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1702                                sizeof(*mmio_read->read_resp),
1703                                mmio_read->read_resp,
1704                                mmio_read->read_resp_dma_addr,
1705                                mmio_read->read_resp_mem_handle);
1706         if (unlikely(!mmio_read->read_resp))
1707                 goto err;
1708
1709         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1710
1711         mmio_read->read_resp->req_id = 0x0;
1712         mmio_read->seq_num = 0x0;
1713         mmio_read->readless_supported = true;
1714
1715         return 0;
1716
1717 err:
1718                 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1719                 return ENA_COM_NO_MEM;
1720 }
1721
1722 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1723 {
1724         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1725
1726         mmio_read->readless_supported = readless_supported;
1727 }
1728
1729 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1730 {
1731         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1732
1733         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1734         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1735
1736         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1737                               sizeof(*mmio_read->read_resp),
1738                               mmio_read->read_resp,
1739                               mmio_read->read_resp_dma_addr,
1740                               mmio_read->read_resp_mem_handle);
1741
1742         mmio_read->read_resp = NULL;
1743         ENA_SPINLOCK_DESTROY(mmio_read->lock);
1744 }
1745
1746 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1747 {
1748         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1749         u32 addr_low, addr_high;
1750
1751         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1752         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1753
1754         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1755         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1756 }
1757
1758 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1759                        struct ena_aenq_handlers *aenq_handlers)
1760 {
1761         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1762         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1763         int ret;
1764
1765         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1766
1767         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1768                 ena_trc_err("Reg read timeout occurred\n");
1769                 return ENA_COM_TIMER_EXPIRED;
1770         }
1771
1772         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1773                 ena_trc_err("Device isn't ready, abort com init\n");
1774                 return ENA_COM_NO_DEVICE;
1775         }
1776
1777         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1778
1779         admin_queue->bus = ena_dev->bus;
1780         admin_queue->q_dmadev = ena_dev->dmadev;
1781         admin_queue->polling = false;
1782         admin_queue->curr_cmd_id = 0;
1783
1784         ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1785
1786         ENA_SPINLOCK_INIT(admin_queue->q_lock);
1787
1788         ret = ena_com_init_comp_ctxt(admin_queue);
1789         if (ret)
1790                 goto error;
1791
1792         ret = ena_com_admin_init_sq(admin_queue);
1793         if (ret)
1794                 goto error;
1795
1796         ret = ena_com_admin_init_cq(admin_queue);
1797         if (ret)
1798                 goto error;
1799
1800         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1801                 ENA_REGS_AQ_DB_OFF);
1802
1803         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1804         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1805
1806         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1807         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1808
1809         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1810         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1811
1812         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1813         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1814
1815         aq_caps = 0;
1816         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1817         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1818                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1819                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1820
1821         acq_caps = 0;
1822         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1823         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1824                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1825                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1826
1827         ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1828         ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1829         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1830         if (ret)
1831                 goto error;
1832
1833         admin_queue->running_state = true;
1834
1835         return 0;
1836 error:
1837         ena_com_admin_destroy(ena_dev);
1838
1839         return ret;
1840 }
1841
1842 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1843                             struct ena_com_create_io_ctx *ctx)
1844 {
1845         struct ena_com_io_sq *io_sq;
1846         struct ena_com_io_cq *io_cq;
1847         int ret;
1848
1849         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1850                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1851                             ctx->qid, ENA_TOTAL_NUM_QUEUES);
1852                 return ENA_COM_INVAL;
1853         }
1854
1855         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1856         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1857
1858         memset(io_sq, 0x0, sizeof(*io_sq));
1859         memset(io_cq, 0x0, sizeof(*io_cq));
1860
1861         /* Init CQ */
1862         io_cq->q_depth = ctx->queue_size;
1863         io_cq->direction = ctx->direction;
1864         io_cq->qid = ctx->qid;
1865
1866         io_cq->msix_vector = ctx->msix_vector;
1867
1868         io_sq->q_depth = ctx->queue_size;
1869         io_sq->direction = ctx->direction;
1870         io_sq->qid = ctx->qid;
1871
1872         io_sq->mem_queue_type = ctx->mem_queue_type;
1873
1874         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1875                 /* header length is limited to 8 bits */
1876                 io_sq->tx_max_header_size =
1877                         ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1878
1879         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1880         if (ret)
1881                 goto error;
1882         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1883         if (ret)
1884                 goto error;
1885
1886         ret = ena_com_create_io_cq(ena_dev, io_cq);
1887         if (ret)
1888                 goto error;
1889
1890         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1891         if (ret)
1892                 goto destroy_io_cq;
1893
1894         return 0;
1895
1896 destroy_io_cq:
1897         ena_com_destroy_io_cq(ena_dev, io_cq);
1898 error:
1899         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1900         return ret;
1901 }
1902
1903 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1904 {
1905         struct ena_com_io_sq *io_sq;
1906         struct ena_com_io_cq *io_cq;
1907
1908         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1909                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1910                             qid, ENA_TOTAL_NUM_QUEUES);
1911                 return;
1912         }
1913
1914         io_sq = &ena_dev->io_sq_queues[qid];
1915         io_cq = &ena_dev->io_cq_queues[qid];
1916
1917         ena_com_destroy_io_sq(ena_dev, io_sq);
1918         ena_com_destroy_io_cq(ena_dev, io_cq);
1919
1920         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1921 }
1922
1923 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1924                             struct ena_admin_get_feat_resp *resp)
1925 {
1926         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1927 }
1928
1929 int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev)
1930 {
1931         struct ena_admin_get_feat_resp resp;
1932         struct ena_extra_properties_strings *extra_properties_strings =
1933                         &ena_dev->extra_properties_strings;
1934         u32 rc;
1935         extra_properties_strings->size = ENA_ADMIN_EXTRA_PROPERTIES_COUNT *
1936                 ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN;
1937
1938         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1939                                extra_properties_strings->size,
1940                                extra_properties_strings->virt_addr,
1941                                extra_properties_strings->dma_addr,
1942                                extra_properties_strings->dma_handle);
1943         if (unlikely(!extra_properties_strings->virt_addr)) {
1944                 ena_trc_err("Failed to allocate extra properties strings\n");
1945                 return 0;
1946         }
1947
1948         rc = ena_com_get_feature_ex(ena_dev, &resp,
1949                                     ENA_ADMIN_EXTRA_PROPERTIES_STRINGS,
1950                                     extra_properties_strings->dma_addr,
1951                                     extra_properties_strings->size, 0);
1952         if (rc) {
1953                 ena_trc_dbg("Failed to get extra properties strings\n");
1954                 goto err;
1955         }
1956
1957         return resp.u.extra_properties_strings.count;
1958 err:
1959         ena_com_delete_extra_properties_strings(ena_dev);
1960         return 0;
1961 }
1962
1963 void ena_com_delete_extra_properties_strings(struct ena_com_dev *ena_dev)
1964 {
1965         struct ena_extra_properties_strings *extra_properties_strings =
1966                                 &ena_dev->extra_properties_strings;
1967
1968         if (extra_properties_strings->virt_addr) {
1969                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1970                                       extra_properties_strings->size,
1971                                       extra_properties_strings->virt_addr,
1972                                       extra_properties_strings->dma_addr,
1973                                       extra_properties_strings->dma_handle);
1974                 extra_properties_strings->virt_addr = NULL;
1975         }
1976 }
1977
1978 int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev,
1979                                        struct ena_admin_get_feat_resp *resp)
1980 {
1981         return ena_com_get_feature(ena_dev, resp,
1982                                    ENA_ADMIN_EXTRA_PROPERTIES_FLAGS, 0);
1983 }
1984
1985 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1986                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1987 {
1988         struct ena_admin_get_feat_resp get_resp;
1989         int rc;
1990
1991         rc = ena_com_get_feature(ena_dev, &get_resp,
1992                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1993         if (rc)
1994                 return rc;
1995
1996         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1997                sizeof(get_resp.u.dev_attr));
1998         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1999
2000         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
2001                 rc = ena_com_get_feature(ena_dev, &get_resp,
2002                                          ENA_ADMIN_MAX_QUEUES_EXT,
2003                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
2004                 if (rc)
2005                         return rc;
2006
2007                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
2008                         return -EINVAL;
2009
2010                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
2011                        sizeof(get_resp.u.max_queue_ext));
2012                 ena_dev->tx_max_header_size =
2013                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
2014         } else {
2015                 rc = ena_com_get_feature(ena_dev, &get_resp,
2016                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
2017                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
2018                        sizeof(get_resp.u.max_queue));
2019                 ena_dev->tx_max_header_size =
2020                         get_resp.u.max_queue.max_header_size;
2021
2022                 if (rc)
2023                         return rc;
2024         }
2025
2026         rc = ena_com_get_feature(ena_dev, &get_resp,
2027                                  ENA_ADMIN_AENQ_CONFIG, 0);
2028         if (rc)
2029                 return rc;
2030
2031         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
2032                sizeof(get_resp.u.aenq));
2033
2034         rc = ena_com_get_feature(ena_dev, &get_resp,
2035                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2036         if (rc)
2037                 return rc;
2038
2039         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
2040                sizeof(get_resp.u.offload));
2041
2042         /* Driver hints isn't mandatory admin command. So in case the
2043          * command isn't supported set driver hints to 0
2044          */
2045         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2046
2047         if (!rc)
2048                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2049                        sizeof(get_resp.u.hw_hints));
2050         else if (rc == ENA_COM_UNSUPPORTED)
2051                 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2052         else
2053                 return rc;
2054
2055         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2056         if (!rc)
2057                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2058                        sizeof(get_resp.u.llq));
2059         else if (rc == ENA_COM_UNSUPPORTED)
2060                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2061         else
2062                 return rc;
2063
2064         rc = ena_com_get_feature(ena_dev, &get_resp,
2065                                  ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2066         if (!rc)
2067                 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2068                        sizeof(get_resp.u.ind_table));
2069         else if (rc == ENA_COM_UNSUPPORTED)
2070                 memset(&get_feat_ctx->ind_table, 0x0,
2071                        sizeof(get_feat_ctx->ind_table));
2072         else
2073                 return rc;
2074
2075         return 0;
2076 }
2077
2078 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2079 {
2080         ena_com_handle_admin_completion(&ena_dev->admin_queue);
2081 }
2082
2083 /* ena_handle_specific_aenq_event:
2084  * return the handler that is relevant to the specific event group
2085  */
2086 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2087                                                      u16 group)
2088 {
2089         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2090
2091         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2092                 return aenq_handlers->handlers[group];
2093
2094         return aenq_handlers->unimplemented_handler;
2095 }
2096
2097 /* ena_aenq_intr_handler:
2098  * handles the aenq incoming events.
2099  * pop events from the queue and apply the specific handler
2100  */
2101 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2102 {
2103         struct ena_admin_aenq_entry *aenq_e;
2104         struct ena_admin_aenq_common_desc *aenq_common;
2105         struct ena_com_aenq *aenq  = &dev->aenq;
2106         u64 timestamp;
2107         ena_aenq_handler handler_cb;
2108         u16 masked_head, processed = 0;
2109         u8 phase;
2110
2111         masked_head = aenq->head & (aenq->q_depth - 1);
2112         phase = aenq->phase;
2113         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2114         aenq_common = &aenq_e->aenq_common_desc;
2115
2116         /* Go over all the events */
2117         while ((READ_ONCE8(aenq_common->flags) &
2118                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2119                 /* Make sure the phase bit (ownership) is as expected before
2120                  * reading the rest of the descriptor.
2121                  */
2122                 dma_rmb();
2123
2124                 timestamp = (u64)aenq_common->timestamp_low |
2125                         ((u64)aenq_common->timestamp_high << 32);
2126                 ENA_TOUCH(timestamp); /* In case debug is disabled */
2127                 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%"PRIu64"]\n",
2128                             aenq_common->group,
2129                             aenq_common->syndrom,
2130                             timestamp);
2131
2132                 /* Handle specific event*/
2133                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2134                                                           aenq_common->group);
2135                 handler_cb(data, aenq_e); /* call the actual event handler*/
2136
2137                 /* Get next event entry */
2138                 masked_head++;
2139                 processed++;
2140
2141                 if (unlikely(masked_head == aenq->q_depth)) {
2142                         masked_head = 0;
2143                         phase = !phase;
2144                 }
2145                 aenq_e = &aenq->entries[masked_head];
2146                 aenq_common = &aenq_e->aenq_common_desc;
2147         }
2148
2149         aenq->head += processed;
2150         aenq->phase = phase;
2151
2152         /* Don't update aenq doorbell if there weren't any processed events */
2153         if (!processed)
2154                 return;
2155
2156         /* write the aenq doorbell after all AENQ descriptors were read */
2157         mb();
2158         ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2159                                 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2160 #ifndef MMIOWB_NOT_DEFINED
2161         mmiowb();
2162 #endif
2163 }
2164
2165 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2166                       enum ena_regs_reset_reason_types reset_reason)
2167 {
2168         u32 stat, timeout, cap, reset_val;
2169         int rc;
2170
2171         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2172         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2173
2174         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2175                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2176                 ena_trc_err("Reg read32 timeout occurred\n");
2177                 return ENA_COM_TIMER_EXPIRED;
2178         }
2179
2180         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2181                 ena_trc_err("Device isn't ready, can't reset device\n");
2182                 return ENA_COM_INVAL;
2183         }
2184
2185         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2186                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2187         if (timeout == 0) {
2188                 ena_trc_err("Invalid timeout value\n");
2189                 return ENA_COM_INVAL;
2190         }
2191
2192         /* start reset */
2193         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2194         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2195                         ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2196         ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2197
2198         /* Write again the MMIO read request address */
2199         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2200
2201         rc = wait_for_reset_state(ena_dev, timeout,
2202                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2203         if (rc != 0) {
2204                 ena_trc_err("Reset indication didn't turn on\n");
2205                 return rc;
2206         }
2207
2208         /* reset done */
2209         ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2210         rc = wait_for_reset_state(ena_dev, timeout, 0);
2211         if (rc != 0) {
2212                 ena_trc_err("Reset indication didn't turn off\n");
2213                 return rc;
2214         }
2215
2216         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2217                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2218         if (timeout)
2219                 /* the resolution of timeout reg is 100ms */
2220                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2221         else
2222                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2223
2224         return 0;
2225 }
2226
2227 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2228                              struct ena_com_stats_ctx *ctx,
2229                              enum ena_admin_get_stats_type type)
2230 {
2231         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2232         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2233         struct ena_com_admin_queue *admin_queue;
2234         int ret;
2235
2236         admin_queue = &ena_dev->admin_queue;
2237
2238         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2239         get_cmd->aq_common_descriptor.flags = 0;
2240         get_cmd->type = type;
2241
2242         ret =  ena_com_execute_admin_command(admin_queue,
2243                                              (struct ena_admin_aq_entry *)get_cmd,
2244                                              sizeof(*get_cmd),
2245                                              (struct ena_admin_acq_entry *)get_resp,
2246                                              sizeof(*get_resp));
2247
2248         if (unlikely(ret))
2249                 ena_trc_err("Failed to get stats. error: %d\n", ret);
2250
2251         return ret;
2252 }
2253
2254 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2255                                 struct ena_admin_basic_stats *stats)
2256 {
2257         struct ena_com_stats_ctx ctx;
2258         int ret;
2259
2260         memset(&ctx, 0x0, sizeof(ctx));
2261         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2262         if (likely(ret == 0))
2263                 memcpy(stats, &ctx.get_resp.basic_stats,
2264                        sizeof(ctx.get_resp.basic_stats));
2265
2266         return ret;
2267 }
2268
2269 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2270 {
2271         struct ena_com_admin_queue *admin_queue;
2272         struct ena_admin_set_feat_cmd cmd;
2273         struct ena_admin_set_feat_resp resp;
2274         int ret;
2275
2276         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2277                 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2278                 return ENA_COM_UNSUPPORTED;
2279         }
2280
2281         memset(&cmd, 0x0, sizeof(cmd));
2282         admin_queue = &ena_dev->admin_queue;
2283
2284         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2285         cmd.aq_common_descriptor.flags = 0;
2286         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2287         cmd.u.mtu.mtu = mtu;
2288
2289         ret = ena_com_execute_admin_command(admin_queue,
2290                                             (struct ena_admin_aq_entry *)&cmd,
2291                                             sizeof(cmd),
2292                                             (struct ena_admin_acq_entry *)&resp,
2293                                             sizeof(resp));
2294
2295         if (unlikely(ret))
2296                 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2297
2298         return ret;
2299 }
2300
2301 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2302                                  struct ena_admin_feature_offload_desc *offload)
2303 {
2304         int ret;
2305         struct ena_admin_get_feat_resp resp;
2306
2307         ret = ena_com_get_feature(ena_dev, &resp,
2308                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2309         if (unlikely(ret)) {
2310                 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2311                 return ret;
2312         }
2313
2314         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2315
2316         return 0;
2317 }
2318
2319 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2320 {
2321         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2322         struct ena_rss *rss = &ena_dev->rss;
2323         struct ena_admin_set_feat_cmd cmd;
2324         struct ena_admin_set_feat_resp resp;
2325         struct ena_admin_get_feat_resp get_resp;
2326         int ret;
2327
2328         if (!ena_com_check_supported_feature_id(ena_dev,
2329                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2330                 ena_trc_dbg("Feature %d isn't supported\n",
2331                             ENA_ADMIN_RSS_HASH_FUNCTION);
2332                 return ENA_COM_UNSUPPORTED;
2333         }
2334
2335         /* Validate hash function is supported */
2336         ret = ena_com_get_feature(ena_dev, &get_resp,
2337                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2338         if (unlikely(ret))
2339                 return ret;
2340
2341         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2342                 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2343                             rss->hash_func);
2344                 return ENA_COM_UNSUPPORTED;
2345         }
2346
2347         memset(&cmd, 0x0, sizeof(cmd));
2348
2349         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2350         cmd.aq_common_descriptor.flags =
2351                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2352         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2353         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2354         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2355
2356         ret = ena_com_mem_addr_set(ena_dev,
2357                                    &cmd.control_buffer.address,
2358                                    rss->hash_key_dma_addr);
2359         if (unlikely(ret)) {
2360                 ena_trc_err("memory address set failed\n");
2361                 return ret;
2362         }
2363
2364         cmd.control_buffer.length = sizeof(*rss->hash_key);
2365
2366         ret = ena_com_execute_admin_command(admin_queue,
2367                                             (struct ena_admin_aq_entry *)&cmd,
2368                                             sizeof(cmd),
2369                                             (struct ena_admin_acq_entry *)&resp,
2370                                             sizeof(resp));
2371         if (unlikely(ret)) {
2372                 ena_trc_err("Failed to set hash function %d. error: %d\n",
2373                             rss->hash_func, ret);
2374                 return ENA_COM_INVAL;
2375         }
2376
2377         return 0;
2378 }
2379
2380 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2381                                enum ena_admin_hash_functions func,
2382                                const u8 *key, u16 key_len, u32 init_val)
2383 {
2384         struct ena_rss *rss = &ena_dev->rss;
2385         struct ena_admin_get_feat_resp get_resp;
2386         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2387                 rss->hash_key;
2388         int rc;
2389
2390         /* Make sure size is a mult of DWs */
2391         if (unlikely(key_len & 0x3))
2392                 return ENA_COM_INVAL;
2393
2394         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2395                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2396                                     rss->hash_key_dma_addr,
2397                                     sizeof(*rss->hash_key), 0);
2398         if (unlikely(rc))
2399                 return rc;
2400
2401         if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2402                 ena_trc_err("Flow hash function %d isn't supported\n", func);
2403                 return ENA_COM_UNSUPPORTED;
2404         }
2405
2406         switch (func) {
2407         case ENA_ADMIN_TOEPLITZ:
2408                 if (key_len > sizeof(hash_key->key)) {
2409                         ena_trc_err("key len (%hu) is bigger than the max supported (%zu)\n",
2410                                     key_len, sizeof(hash_key->key));
2411                         return ENA_COM_INVAL;
2412                 }
2413
2414                 memcpy(hash_key->key, key, key_len);
2415                 rss->hash_init_val = init_val;
2416                 hash_key->keys_num = key_len >> 2;
2417                 break;
2418         case ENA_ADMIN_CRC32:
2419                 rss->hash_init_val = init_val;
2420                 break;
2421         default:
2422                 ena_trc_err("Invalid hash function (%d)\n", func);
2423                 return ENA_COM_INVAL;
2424         }
2425
2426         rss->hash_func = func;
2427         rc = ena_com_set_hash_function(ena_dev);
2428
2429         /* Restore the old function */
2430         if (unlikely(rc))
2431                 ena_com_get_hash_function(ena_dev, NULL, NULL);
2432
2433         return rc;
2434 }
2435
2436 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2437                               enum ena_admin_hash_functions *func,
2438                               u8 *key)
2439 {
2440         struct ena_rss *rss = &ena_dev->rss;
2441         struct ena_admin_get_feat_resp get_resp;
2442         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2443                 rss->hash_key;
2444         int rc;
2445
2446         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2447                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2448                                     rss->hash_key_dma_addr,
2449                                     sizeof(*rss->hash_key), 0);
2450         if (unlikely(rc))
2451                 return rc;
2452
2453         rss->hash_func = get_resp.u.flow_hash_func.selected_func;
2454         if (func)
2455                 *func = rss->hash_func;
2456
2457         if (key)
2458                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2459
2460         return 0;
2461 }
2462
2463 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2464                           enum ena_admin_flow_hash_proto proto,
2465                           u16 *fields)
2466 {
2467         struct ena_rss *rss = &ena_dev->rss;
2468         struct ena_admin_get_feat_resp get_resp;
2469         int rc;
2470
2471         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2472                                     ENA_ADMIN_RSS_HASH_INPUT,
2473                                     rss->hash_ctrl_dma_addr,
2474                                     sizeof(*rss->hash_ctrl), 0);
2475         if (unlikely(rc))
2476                 return rc;
2477
2478         if (fields)
2479                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2480
2481         return 0;
2482 }
2483
2484 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2485 {
2486         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2487         struct ena_rss *rss = &ena_dev->rss;
2488         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2489         struct ena_admin_set_feat_cmd cmd;
2490         struct ena_admin_set_feat_resp resp;
2491         int ret;
2492
2493         if (!ena_com_check_supported_feature_id(ena_dev,
2494                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2495                 ena_trc_dbg("Feature %d isn't supported\n",
2496                             ENA_ADMIN_RSS_HASH_INPUT);
2497                 return ENA_COM_UNSUPPORTED;
2498         }
2499
2500         memset(&cmd, 0x0, sizeof(cmd));
2501
2502         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2503         cmd.aq_common_descriptor.flags =
2504                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2505         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2506         cmd.u.flow_hash_input.enabled_input_sort =
2507                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2508                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2509
2510         ret = ena_com_mem_addr_set(ena_dev,
2511                                    &cmd.control_buffer.address,
2512                                    rss->hash_ctrl_dma_addr);
2513         if (unlikely(ret)) {
2514                 ena_trc_err("memory address set failed\n");
2515                 return ret;
2516         }
2517         cmd.control_buffer.length = sizeof(*hash_ctrl);
2518
2519         ret = ena_com_execute_admin_command(admin_queue,
2520                                             (struct ena_admin_aq_entry *)&cmd,
2521                                             sizeof(cmd),
2522                                             (struct ena_admin_acq_entry *)&resp,
2523                                             sizeof(resp));
2524         if (unlikely(ret))
2525                 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2526
2527         return ret;
2528 }
2529
2530 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2531 {
2532         struct ena_rss *rss = &ena_dev->rss;
2533         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2534                 rss->hash_ctrl;
2535         u16 available_fields = 0;
2536         int rc, i;
2537
2538         /* Get the supported hash input */
2539         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2540         if (unlikely(rc))
2541                 return rc;
2542
2543         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2544                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2545                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2546
2547         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2548                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2549                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2550
2551         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2552                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2553                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2554
2555         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2556                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2557                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2558
2559         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2560                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2561
2562         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2563                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2564
2565         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2566                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2567
2568         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2569                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2570
2571         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2572                 available_fields = hash_ctrl->selected_fields[i].fields &
2573                                 hash_ctrl->supported_fields[i].fields;
2574                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2575                         ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2576                                     i, hash_ctrl->supported_fields[i].fields,
2577                                     hash_ctrl->selected_fields[i].fields);
2578                         return ENA_COM_UNSUPPORTED;
2579                 }
2580         }
2581
2582         rc = ena_com_set_hash_ctrl(ena_dev);
2583
2584         /* In case of failure, restore the old hash ctrl */
2585         if (unlikely(rc))
2586                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2587
2588         return rc;
2589 }
2590
2591 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2592                            enum ena_admin_flow_hash_proto proto,
2593                            u16 hash_fields)
2594 {
2595         struct ena_rss *rss = &ena_dev->rss;
2596         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2597         u16 supported_fields;
2598         int rc;
2599
2600         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2601                 ena_trc_err("Invalid proto num (%u)\n", proto);
2602                 return ENA_COM_INVAL;
2603         }
2604
2605         /* Get the ctrl table */
2606         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2607         if (unlikely(rc))
2608                 return rc;
2609
2610         /* Make sure all the fields are supported */
2611         supported_fields = hash_ctrl->supported_fields[proto].fields;
2612         if ((hash_fields & supported_fields) != hash_fields) {
2613                 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2614                             proto, hash_fields, supported_fields);
2615         }
2616
2617         hash_ctrl->selected_fields[proto].fields = hash_fields;
2618
2619         rc = ena_com_set_hash_ctrl(ena_dev);
2620
2621         /* In case of failure, restore the old hash ctrl */
2622         if (unlikely(rc))
2623                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2624
2625         return 0;
2626 }
2627
2628 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2629                                       u16 entry_idx, u16 entry_value)
2630 {
2631         struct ena_rss *rss = &ena_dev->rss;
2632
2633         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2634                 return ENA_COM_INVAL;
2635
2636         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2637                 return ENA_COM_INVAL;
2638
2639         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2640
2641         return 0;
2642 }
2643
2644 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2645 {
2646         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2647         struct ena_rss *rss = &ena_dev->rss;
2648         struct ena_admin_set_feat_cmd cmd;
2649         struct ena_admin_set_feat_resp resp;
2650         int ret;
2651
2652         if (!ena_com_check_supported_feature_id(ena_dev,
2653                                                 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2654                 ena_trc_dbg("Feature %d isn't supported\n",
2655                             ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2656                 return ENA_COM_UNSUPPORTED;
2657         }
2658
2659         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2660         if (ret) {
2661                 ena_trc_err("Failed to convert host indirection table to device table\n");
2662                 return ret;
2663         }
2664
2665         memset(&cmd, 0x0, sizeof(cmd));
2666
2667         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2668         cmd.aq_common_descriptor.flags =
2669                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2670         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2671         cmd.u.ind_table.size = rss->tbl_log_size;
2672         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2673
2674         ret = ena_com_mem_addr_set(ena_dev,
2675                                    &cmd.control_buffer.address,
2676                                    rss->rss_ind_tbl_dma_addr);
2677         if (unlikely(ret)) {
2678                 ena_trc_err("memory address set failed\n");
2679                 return ret;
2680         }
2681
2682         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2683                 sizeof(struct ena_admin_rss_ind_table_entry);
2684
2685         ret = ena_com_execute_admin_command(admin_queue,
2686                                             (struct ena_admin_aq_entry *)&cmd,
2687                                             sizeof(cmd),
2688                                             (struct ena_admin_acq_entry *)&resp,
2689                                             sizeof(resp));
2690
2691         if (unlikely(ret))
2692                 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2693
2694         return ret;
2695 }
2696
2697 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2698 {
2699         struct ena_rss *rss = &ena_dev->rss;
2700         struct ena_admin_get_feat_resp get_resp;
2701         u32 tbl_size;
2702         int i, rc;
2703
2704         tbl_size = (1ULL << rss->tbl_log_size) *
2705                 sizeof(struct ena_admin_rss_ind_table_entry);
2706
2707         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2708                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2709                                     rss->rss_ind_tbl_dma_addr,
2710                                     tbl_size, 0);
2711         if (unlikely(rc))
2712                 return rc;
2713
2714         if (!ind_tbl)
2715                 return 0;
2716
2717         rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2718         if (unlikely(rc))
2719                 return rc;
2720
2721         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2722                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2723
2724         return 0;
2725 }
2726
2727 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2728 {
2729         int rc;
2730
2731         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2732
2733         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2734         if (unlikely(rc))
2735                 goto err_indr_tbl;
2736
2737         rc = ena_com_hash_key_allocate(ena_dev);
2738         if (unlikely(rc))
2739                 goto err_hash_key;
2740
2741         rc = ena_com_hash_ctrl_init(ena_dev);
2742         if (unlikely(rc))
2743                 goto err_hash_ctrl;
2744
2745         return 0;
2746
2747 err_hash_ctrl:
2748         ena_com_hash_key_destroy(ena_dev);
2749 err_hash_key:
2750         ena_com_indirect_table_destroy(ena_dev);
2751 err_indr_tbl:
2752
2753         return rc;
2754 }
2755
2756 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2757 {
2758         ena_com_indirect_table_destroy(ena_dev);
2759         ena_com_hash_key_destroy(ena_dev);
2760         ena_com_hash_ctrl_destroy(ena_dev);
2761
2762         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2763 }
2764
2765 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2766 {
2767         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2768
2769         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2770                                SZ_4K,
2771                                host_attr->host_info,
2772                                host_attr->host_info_dma_addr,
2773                                host_attr->host_info_dma_handle);
2774         if (unlikely(!host_attr->host_info))
2775                 return ENA_COM_NO_MEM;
2776
2777         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2778                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2779                 (ENA_COMMON_SPEC_VERSION_MINOR));
2780
2781         return 0;
2782 }
2783
2784 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2785                                 u32 debug_area_size)
2786 {
2787         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2788
2789         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2790                                debug_area_size,
2791                                host_attr->debug_area_virt_addr,
2792                                host_attr->debug_area_dma_addr,
2793                                host_attr->debug_area_dma_handle);
2794         if (unlikely(!host_attr->debug_area_virt_addr)) {
2795                 host_attr->debug_area_size = 0;
2796                 return ENA_COM_NO_MEM;
2797         }
2798
2799         host_attr->debug_area_size = debug_area_size;
2800
2801         return 0;
2802 }
2803
2804 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2805 {
2806         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2807
2808         if (host_attr->host_info) {
2809                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2810                                       SZ_4K,
2811                                       host_attr->host_info,
2812                                       host_attr->host_info_dma_addr,
2813                                       host_attr->host_info_dma_handle);
2814                 host_attr->host_info = NULL;
2815         }
2816 }
2817
2818 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2819 {
2820         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2821
2822         if (host_attr->debug_area_virt_addr) {
2823                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2824                                       host_attr->debug_area_size,
2825                                       host_attr->debug_area_virt_addr,
2826                                       host_attr->debug_area_dma_addr,
2827                                       host_attr->debug_area_dma_handle);
2828                 host_attr->debug_area_virt_addr = NULL;
2829         }
2830 }
2831
2832 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2833 {
2834         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2835         struct ena_com_admin_queue *admin_queue;
2836         struct ena_admin_set_feat_cmd cmd;
2837         struct ena_admin_set_feat_resp resp;
2838
2839         int ret;
2840
2841         /* Host attribute config is called before ena_com_get_dev_attr_feat
2842          * so ena_com can't check if the feature is supported.
2843          */
2844
2845         memset(&cmd, 0x0, sizeof(cmd));
2846         admin_queue = &ena_dev->admin_queue;
2847
2848         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2849         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2850
2851         ret = ena_com_mem_addr_set(ena_dev,
2852                                    &cmd.u.host_attr.debug_ba,
2853                                    host_attr->debug_area_dma_addr);
2854         if (unlikely(ret)) {
2855                 ena_trc_err("memory address set failed\n");
2856                 return ret;
2857         }
2858
2859         ret = ena_com_mem_addr_set(ena_dev,
2860                                    &cmd.u.host_attr.os_info_ba,
2861                                    host_attr->host_info_dma_addr);
2862         if (unlikely(ret)) {
2863                 ena_trc_err("memory address set failed\n");
2864                 return ret;
2865         }
2866
2867         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2868
2869         ret = ena_com_execute_admin_command(admin_queue,
2870                                             (struct ena_admin_aq_entry *)&cmd,
2871                                             sizeof(cmd),
2872                                             (struct ena_admin_acq_entry *)&resp,
2873                                             sizeof(resp));
2874
2875         if (unlikely(ret))
2876                 ena_trc_err("Failed to set host attributes: %d\n", ret);
2877
2878         return ret;
2879 }
2880
2881 /* Interrupt moderation */
2882 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2883 {
2884         return ena_com_check_supported_feature_id(ena_dev,
2885                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2886 }
2887
2888 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2889                                                       u32 tx_coalesce_usecs)
2890 {
2891         if (!ena_dev->intr_delay_resolution) {
2892                 ena_trc_err("Illegal interrupt delay granularity value\n");
2893                 return ENA_COM_FAULT;
2894         }
2895
2896         ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2897                 ena_dev->intr_delay_resolution;
2898
2899         return 0;
2900 }
2901
2902 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2903                                                       u32 rx_coalesce_usecs)
2904 {
2905         if (!ena_dev->intr_delay_resolution) {
2906                 ena_trc_err("Illegal interrupt delay granularity value\n");
2907                 return ENA_COM_FAULT;
2908         }
2909
2910         /* We use LOWEST entry of moderation table for storing
2911          * nonadaptive interrupt coalescing values
2912          */
2913         ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2914                 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2915
2916         return 0;
2917 }
2918
2919 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2920 {
2921         if (ena_dev->intr_moder_tbl)
2922                 ENA_MEM_FREE(ena_dev->dmadev,
2923                              ena_dev->intr_moder_tbl,
2924                              (sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS));
2925         ena_dev->intr_moder_tbl = NULL;
2926 }
2927
2928 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2929 {
2930         struct ena_admin_get_feat_resp get_resp;
2931         u16 delay_resolution;
2932         int rc;
2933
2934         rc = ena_com_get_feature(ena_dev, &get_resp,
2935                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2936
2937         if (rc) {
2938                 if (rc == ENA_COM_UNSUPPORTED) {
2939                         ena_trc_dbg("Feature %d isn't supported\n",
2940                                     ENA_ADMIN_INTERRUPT_MODERATION);
2941                         rc = 0;
2942                 } else {
2943                         ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2944                                     rc);
2945                 }
2946
2947                 /* no moderation supported, disable adaptive support */
2948                 ena_com_disable_adaptive_moderation(ena_dev);
2949                 return rc;
2950         }
2951
2952         rc = ena_com_init_interrupt_moderation_table(ena_dev);
2953         if (rc)
2954                 goto err;
2955
2956         /* if moderation is supported by device we set adaptive moderation */
2957         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2958         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2959
2960         /* Disable adaptive moderation by default - can be enabled later */
2961         ena_com_disable_adaptive_moderation(ena_dev);
2962
2963         return 0;
2964 err:
2965         ena_com_destroy_interrupt_moderation(ena_dev);
2966         return rc;
2967 }
2968
2969 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2970 {
2971         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2972
2973         if (!intr_moder_tbl)
2974                 return;
2975
2976         intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2977                 ENA_INTR_LOWEST_USECS;
2978         intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2979                 ENA_INTR_LOWEST_PKTS;
2980         intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2981                 ENA_INTR_LOWEST_BYTES;
2982
2983         intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2984                 ENA_INTR_LOW_USECS;
2985         intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2986                 ENA_INTR_LOW_PKTS;
2987         intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2988                 ENA_INTR_LOW_BYTES;
2989
2990         intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2991                 ENA_INTR_MID_USECS;
2992         intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2993                 ENA_INTR_MID_PKTS;
2994         intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2995                 ENA_INTR_MID_BYTES;
2996
2997         intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2998                 ENA_INTR_HIGH_USECS;
2999         intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
3000                 ENA_INTR_HIGH_PKTS;
3001         intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
3002                 ENA_INTR_HIGH_BYTES;
3003
3004         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
3005                 ENA_INTR_HIGHEST_USECS;
3006         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
3007                 ENA_INTR_HIGHEST_PKTS;
3008         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
3009                 ENA_INTR_HIGHEST_BYTES;
3010 }
3011
3012 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
3013 {
3014         return ena_dev->intr_moder_tx_interval;
3015 }
3016
3017 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
3018 {
3019         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
3020
3021         if (intr_moder_tbl)
3022                 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
3023
3024         return 0;
3025 }
3026
3027 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
3028                                         enum ena_intr_moder_level level,
3029                                         struct ena_intr_moder_entry *entry)
3030 {
3031         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
3032
3033         if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
3034                 return;
3035
3036         intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
3037         if (ena_dev->intr_delay_resolution)
3038                 intr_moder_tbl[level].intr_moder_interval /=
3039                         ena_dev->intr_delay_resolution;
3040         intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
3041
3042         /* use hardcoded value until ethtool supports bytecount parameter */
3043         if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
3044                 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
3045 }
3046
3047 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
3048                                        enum ena_intr_moder_level level,
3049                                        struct ena_intr_moder_entry *entry)
3050 {
3051         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
3052
3053         if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
3054                 return;
3055
3056         entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
3057         if (ena_dev->intr_delay_resolution)
3058                 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
3059         entry->pkts_per_interval =
3060         intr_moder_tbl[level].pkts_per_interval;
3061         entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
3062 }
3063
3064 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
3065                             struct ena_admin_feature_llq_desc *llq_features,
3066                             struct ena_llq_configurations *llq_default_cfg)
3067 {
3068         int rc;
3069         struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
3070
3071         if (!llq_features->max_llq_num) {
3072                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3073                 return 0;
3074         }
3075
3076         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
3077         if (rc)
3078                 return rc;
3079
3080         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
3081                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
3082
3083         if (ena_dev->tx_max_header_size == 0) {
3084                 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
3085                 return -EINVAL;
3086         }
3087
3088         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
3089
3090         return 0;
3091 }