1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
8 /*****************************************************************************/
9 /*****************************************************************************/
11 /* Timeout in micro-sec */
12 #define ADMIN_CMD_TIMEOUT_US (3000000)
14 #define ENA_ASYNC_QUEUE_DEPTH 16
15 #define ENA_ADMIN_QUEUE_DEPTH 32
17 #define ENA_CTRL_MAJOR 0
18 #define ENA_CTRL_MINOR 0
19 #define ENA_CTRL_SUB_MINOR 1
21 #define MIN_ENA_CTRL_VER \
22 (((ENA_CTRL_MAJOR) << \
23 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
24 ((ENA_CTRL_MINOR) << \
25 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
35 #define ENA_REGS_ADMIN_INTR_MASK 1
37 #define ENA_MIN_ADMIN_POLL_US 100
39 #define ENA_MAX_ADMIN_POLL_US 5000
41 /*****************************************************************************/
42 /*****************************************************************************/
43 /*****************************************************************************/
48 /* Abort - canceled by the driver */
53 ena_wait_event_t wait_event;
54 struct ena_admin_acq_entry *user_cqe;
56 enum ena_cmd_status status;
57 /* status from the device */
63 struct ena_com_stats_ctx {
64 struct ena_admin_aq_get_stats_cmd get_cmd;
65 struct ena_admin_acq_get_stats_resp get_resp;
68 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
69 struct ena_common_mem_addr *ena_addr,
72 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
73 ena_trc_err("dma address has more bits that the device supports\n");
77 ena_addr->mem_addr_low = lower_32_bits(addr);
78 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
83 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
85 struct ena_com_admin_sq *sq = &queue->sq;
86 u16 size = ADMIN_SQ_SIZE(queue->q_depth);
88 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
92 ena_trc_err("memory allocation failed\n");
93 return ENA_COM_NO_MEM;
105 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
107 struct ena_com_admin_cq *cq = &queue->cq;
108 u16 size = ADMIN_CQ_SIZE(queue->q_depth);
110 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
114 ena_trc_err("memory allocation failed\n");
115 return ENA_COM_NO_MEM;
124 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
125 struct ena_aenq_handlers *aenq_handlers)
127 struct ena_com_aenq *aenq = &dev->aenq;
128 u32 addr_low, addr_high, aenq_caps;
131 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
132 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
133 ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
138 if (!aenq->entries) {
139 ena_trc_err("memory allocation failed\n");
140 return ENA_COM_NO_MEM;
143 aenq->head = aenq->q_depth;
146 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
147 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
149 ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
150 ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
153 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
154 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
155 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
156 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
157 ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
159 if (unlikely(!aenq_handlers)) {
160 ena_trc_err("aenq handlers pointer is NULL\n");
161 return ENA_COM_INVAL;
164 aenq->aenq_handlers = aenq_handlers;
169 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
170 struct ena_comp_ctx *comp_ctx)
172 comp_ctx->occupied = false;
173 ATOMIC32_DEC(&queue->outstanding_cmds);
176 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
177 u16 command_id, bool capture)
179 if (unlikely(command_id >= queue->q_depth)) {
180 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
181 command_id, queue->q_depth);
185 if (unlikely(!queue->comp_ctx)) {
186 ena_trc_err("Completion context is NULL\n");
190 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
191 ena_trc_err("Completion context is occupied\n");
196 ATOMIC32_INC(&queue->outstanding_cmds);
197 queue->comp_ctx[command_id].occupied = true;
200 return &queue->comp_ctx[command_id];
203 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
204 struct ena_admin_aq_entry *cmd,
205 size_t cmd_size_in_bytes,
206 struct ena_admin_acq_entry *comp,
207 size_t comp_size_in_bytes)
209 struct ena_comp_ctx *comp_ctx;
210 u16 tail_masked, cmd_id;
214 queue_size_mask = admin_queue->q_depth - 1;
216 tail_masked = admin_queue->sq.tail & queue_size_mask;
218 /* In case of queue FULL */
219 cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
220 if (cnt >= admin_queue->q_depth) {
221 ena_trc_dbg("admin queue is full.\n");
222 admin_queue->stats.out_of_space++;
223 return ERR_PTR(ENA_COM_NO_SPACE);
226 cmd_id = admin_queue->curr_cmd_id;
228 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
229 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
231 cmd->aq_common_descriptor.command_id |= cmd_id &
232 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
234 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
235 if (unlikely(!comp_ctx))
236 return ERR_PTR(ENA_COM_INVAL);
238 comp_ctx->status = ENA_CMD_SUBMITTED;
239 comp_ctx->comp_size = (u32)comp_size_in_bytes;
240 comp_ctx->user_cqe = comp;
241 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
243 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
245 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
247 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
250 admin_queue->sq.tail++;
251 admin_queue->stats.submitted_cmd++;
253 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
254 admin_queue->sq.phase = !admin_queue->sq.phase;
256 ENA_DB_SYNC(&admin_queue->sq.mem_handle);
257 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
258 admin_queue->sq.db_addr);
263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
265 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
266 struct ena_comp_ctx *comp_ctx;
269 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
270 if (unlikely(!queue->comp_ctx)) {
271 ena_trc_err("memory allocation failed\n");
272 return ENA_COM_NO_MEM;
275 for (i = 0; i < queue->q_depth; i++) {
276 comp_ctx = get_comp_ctxt(queue, i, false);
278 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
284 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
285 struct ena_admin_aq_entry *cmd,
286 size_t cmd_size_in_bytes,
287 struct ena_admin_acq_entry *comp,
288 size_t comp_size_in_bytes)
290 unsigned long flags = 0;
291 struct ena_comp_ctx *comp_ctx;
293 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
294 if (unlikely(!admin_queue->running_state)) {
295 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
296 return ERR_PTR(ENA_COM_NO_DEVICE);
298 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
302 if (IS_ERR(comp_ctx))
303 admin_queue->running_state = false;
304 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
309 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
310 struct ena_com_create_io_ctx *ctx,
311 struct ena_com_io_sq *io_sq)
316 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
318 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
319 io_sq->desc_entry_size =
320 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
321 sizeof(struct ena_eth_io_tx_desc) :
322 sizeof(struct ena_eth_io_rx_desc);
324 size = io_sq->desc_entry_size * io_sq->q_depth;
325 io_sq->bus = ena_dev->bus;
327 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
328 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
330 io_sq->desc_addr.virt_addr,
331 io_sq->desc_addr.phys_addr,
332 io_sq->desc_addr.mem_handle,
335 if (!io_sq->desc_addr.virt_addr) {
336 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
338 io_sq->desc_addr.virt_addr,
339 io_sq->desc_addr.phys_addr,
340 io_sq->desc_addr.mem_handle);
343 if (!io_sq->desc_addr.virt_addr) {
344 ena_trc_err("memory allocation failed\n");
345 return ENA_COM_NO_MEM;
349 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
350 /* Allocate bounce buffers */
351 io_sq->bounce_buf_ctrl.buffer_size =
352 ena_dev->llq_info.desc_list_entry_size;
353 io_sq->bounce_buf_ctrl.buffers_num =
354 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
355 io_sq->bounce_buf_ctrl.next_to_use = 0;
357 size = io_sq->bounce_buf_ctrl.buffer_size *
358 io_sq->bounce_buf_ctrl.buffers_num;
360 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
362 io_sq->bounce_buf_ctrl.base_buffer,
365 if (!io_sq->bounce_buf_ctrl.base_buffer)
366 io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
368 if (!io_sq->bounce_buf_ctrl.base_buffer) {
369 ena_trc_err("bounce buffer memory allocation failed\n");
370 return ENA_COM_NO_MEM;
373 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
374 sizeof(io_sq->llq_info));
376 /* Initiate the first bounce buffer */
377 io_sq->llq_buf_ctrl.curr_bounce_buf =
378 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
379 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
380 0x0, io_sq->llq_info.desc_list_entry_size);
381 io_sq->llq_buf_ctrl.descs_left_in_line =
382 io_sq->llq_info.descs_num_before_header;
383 io_sq->disable_meta_caching =
384 io_sq->llq_info.disable_meta_caching;
386 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
387 io_sq->entries_in_tx_burst_left =
388 io_sq->llq_info.max_entries_in_tx_burst;
392 io_sq->next_to_comp = 0;
398 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
399 struct ena_com_create_io_ctx *ctx,
400 struct ena_com_io_cq *io_cq)
405 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
407 /* Use the basic completion descriptor for Rx */
408 io_cq->cdesc_entry_size_in_bytes =
409 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
410 sizeof(struct ena_eth_io_tx_cdesc) :
411 sizeof(struct ena_eth_io_rx_cdesc_base);
413 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
414 io_cq->bus = ena_dev->bus;
416 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
418 io_cq->cdesc_addr.virt_addr,
419 io_cq->cdesc_addr.phys_addr,
420 io_cq->cdesc_addr.mem_handle,
423 if (!io_cq->cdesc_addr.virt_addr) {
424 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
426 io_cq->cdesc_addr.virt_addr,
427 io_cq->cdesc_addr.phys_addr,
428 io_cq->cdesc_addr.mem_handle);
431 if (!io_cq->cdesc_addr.virt_addr) {
432 ena_trc_err("memory allocation failed\n");
433 return ENA_COM_NO_MEM;
442 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
443 struct ena_admin_acq_entry *cqe)
445 struct ena_comp_ctx *comp_ctx;
448 cmd_id = cqe->acq_common_descriptor.command &
449 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
451 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
452 if (unlikely(!comp_ctx)) {
453 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
454 admin_queue->running_state = false;
458 comp_ctx->status = ENA_CMD_COMPLETED;
459 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
461 if (comp_ctx->user_cqe)
462 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
464 if (!admin_queue->polling)
465 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
468 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
470 struct ena_admin_acq_entry *cqe = NULL;
475 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
476 phase = admin_queue->cq.phase;
478 cqe = &admin_queue->cq.entries[head_masked];
480 /* Go over all the completions */
481 while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
482 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
483 /* Do not read the rest of the completion entry before the
484 * phase bit was validated
487 ena_com_handle_single_admin_completion(admin_queue, cqe);
491 if (unlikely(head_masked == admin_queue->q_depth)) {
496 cqe = &admin_queue->cq.entries[head_masked];
499 admin_queue->cq.head += comp_num;
500 admin_queue->cq.phase = phase;
501 admin_queue->sq.head += comp_num;
502 admin_queue->stats.completed_cmd += comp_num;
505 static int ena_com_comp_status_to_errno(u8 comp_status)
507 if (unlikely(comp_status != 0))
508 ena_trc_err("admin command failed[%u]\n", comp_status);
510 switch (comp_status) {
511 case ENA_ADMIN_SUCCESS:
513 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
514 return ENA_COM_NO_MEM;
515 case ENA_ADMIN_UNSUPPORTED_OPCODE:
516 return ENA_COM_UNSUPPORTED;
517 case ENA_ADMIN_BAD_OPCODE:
518 case ENA_ADMIN_MALFORMED_REQUEST:
519 case ENA_ADMIN_ILLEGAL_PARAMETER:
520 case ENA_ADMIN_UNKNOWN_ERROR:
521 return ENA_COM_INVAL;
522 case ENA_ADMIN_RESOURCE_BUSY:
523 return ENA_COM_TRY_AGAIN;
526 return ENA_COM_INVAL;
529 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
531 delay_us = ENA_MAX32(ENA_MIN_ADMIN_POLL_US, delay_us);
532 delay_us = ENA_MIN32(delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
533 ENA_USLEEP(delay_us);
536 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
537 struct ena_com_admin_queue *admin_queue)
539 unsigned long flags = 0;
544 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
547 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
548 ena_com_handle_admin_completion(admin_queue);
549 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
551 if (comp_ctx->status != ENA_CMD_SUBMITTED)
554 if (ENA_TIME_EXPIRE(timeout)) {
555 ena_trc_err("Wait for completion (polling) timeout\n");
556 /* ENA didn't have any completion */
557 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
558 admin_queue->stats.no_completion++;
559 admin_queue->running_state = false;
560 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
562 ret = ENA_COM_TIMER_EXPIRED;
566 ena_delay_exponential_backoff_us(exp++,
567 admin_queue->ena_dev->ena_min_poll_delay_us);
570 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
571 ena_trc_err("Command was aborted\n");
572 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
573 admin_queue->stats.aborted_cmd++;
574 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
575 ret = ENA_COM_NO_DEVICE;
579 ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
580 "Invalid comp status %d\n", comp_ctx->status);
582 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
584 comp_ctxt_release(admin_queue, comp_ctx);
589 * Set the LLQ configurations of the firmware
591 * The driver provides only the enabled feature values to the device,
592 * which in turn, checks if they are supported.
594 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
596 struct ena_com_admin_queue *admin_queue;
597 struct ena_admin_set_feat_cmd cmd;
598 struct ena_admin_set_feat_resp resp;
599 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
602 memset(&cmd, 0x0, sizeof(cmd));
603 admin_queue = &ena_dev->admin_queue;
605 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
606 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
608 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
609 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
610 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
611 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
613 if (llq_info->disable_meta_caching)
614 cmd.u.llq.accel_mode.u.set.enabled_flags |=
615 BIT(ENA_ADMIN_DISABLE_META_CACHING);
617 if (llq_info->max_entries_in_tx_burst)
618 cmd.u.llq.accel_mode.u.set.enabled_flags |=
619 BIT(ENA_ADMIN_LIMIT_TX_BURST);
621 ret = ena_com_execute_admin_command(admin_queue,
622 (struct ena_admin_aq_entry *)&cmd,
624 (struct ena_admin_acq_entry *)&resp,
628 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
633 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
634 struct ena_admin_feature_llq_desc *llq_features,
635 struct ena_llq_configurations *llq_default_cfg)
637 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
641 memset(llq_info, 0, sizeof(*llq_info));
643 supported_feat = llq_features->header_location_ctrl_supported;
645 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
646 llq_info->header_location_ctrl =
647 llq_default_cfg->llq_header_location;
649 ena_trc_err("Invalid header location control, supported: 0x%x\n",
654 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
655 supported_feat = llq_features->descriptors_stride_ctrl_supported;
656 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
657 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
659 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
660 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
661 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
662 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
664 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
669 ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
670 llq_default_cfg->llq_stride_ctrl,
672 llq_info->desc_stride_ctrl);
675 llq_info->desc_stride_ctrl = 0;
678 supported_feat = llq_features->entry_size_ctrl_supported;
679 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
680 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
681 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
683 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
684 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
685 llq_info->desc_list_entry_size = 128;
686 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
687 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
688 llq_info->desc_list_entry_size = 192;
689 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
690 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
691 llq_info->desc_list_entry_size = 256;
693 ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
697 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
698 llq_default_cfg->llq_ring_entry_size,
700 llq_info->desc_list_entry_size);
702 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
703 /* The desc list entry size should be whole multiply of 8
704 * This requirement comes from __iowrite64_copy()
706 ena_trc_err("illegal entry size %d\n",
707 llq_info->desc_list_entry_size);
711 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
712 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
713 sizeof(struct ena_eth_io_tx_desc);
715 llq_info->descs_per_entry = 1;
717 supported_feat = llq_features->desc_num_before_header_supported;
718 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
719 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
721 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
722 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
723 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
724 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
725 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
726 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
727 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
728 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
730 ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
735 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
736 llq_default_cfg->llq_num_decs_before_header,
738 llq_info->descs_num_before_header);
740 /* Check for accelerated queue supported */
741 llq_info->disable_meta_caching =
742 llq_features->accel_mode.u.get.supported_flags &
743 BIT(ENA_ADMIN_DISABLE_META_CACHING);
745 if (llq_features->accel_mode.u.get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
746 llq_info->max_entries_in_tx_burst =
747 llq_features->accel_mode.u.get.max_tx_burst_size /
748 llq_default_cfg->llq_ring_entry_size_value;
750 rc = ena_com_set_llq(ena_dev);
752 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
757 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
758 struct ena_com_admin_queue *admin_queue)
760 unsigned long flags = 0;
763 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
764 admin_queue->completion_timeout);
766 /* In case the command wasn't completed find out the root cause.
767 * There might be 2 kinds of errors
768 * 1) No completion (timeout reached)
769 * 2) There is completion but the device didn't get any msi-x interrupt.
771 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
772 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
773 ena_com_handle_admin_completion(admin_queue);
774 admin_queue->stats.no_completion++;
775 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
777 if (comp_ctx->status == ENA_CMD_COMPLETED) {
778 ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
779 comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
780 /* Check if fallback to polling is enabled */
781 if (admin_queue->auto_polling)
782 admin_queue->polling = true;
784 ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
785 comp_ctx->cmd_opcode, comp_ctx->status);
787 /* Check if shifted to polling mode.
788 * This will happen if there is a completion without an interrupt
789 * and autopolling mode is enabled. Continuing normal execution in such case
791 if (!admin_queue->polling) {
792 admin_queue->running_state = false;
793 ret = ENA_COM_TIMER_EXPIRED;
798 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
800 comp_ctxt_release(admin_queue, comp_ctx);
804 /* This method read the hardware device register through posting writes
805 * and waiting for response
806 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
808 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
810 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
811 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
812 mmio_read->read_resp;
813 u32 mmio_read_reg, ret, i;
814 unsigned long flags = 0;
815 u32 timeout = mmio_read->reg_read_to;
820 timeout = ENA_REG_READ_TIMEOUT;
822 /* If readless is disabled, perform regular read */
823 if (!mmio_read->readless_supported)
824 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
826 ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
827 mmio_read->seq_num++;
829 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
830 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
831 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
832 mmio_read_reg |= mmio_read->seq_num &
833 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
835 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
836 ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
838 for (i = 0; i < timeout; i++) {
839 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
845 if (unlikely(i == timeout)) {
846 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
851 ret = ENA_MMIO_READ_TIMEOUT;
855 if (read_resp->reg_off != offset) {
856 ena_trc_err("Read failure: wrong offset provided\n");
857 ret = ENA_MMIO_READ_TIMEOUT;
859 ret = read_resp->reg_val;
862 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
867 /* There are two types to wait for completion.
868 * Polling mode - wait until the completion is available.
869 * Async mode - wait on wait queue until the completion is ready
870 * (or the timeout expired).
871 * It is expected that the IRQ called ena_com_handle_admin_completion
872 * to mark the completions.
874 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
875 struct ena_com_admin_queue *admin_queue)
877 if (admin_queue->polling)
878 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
881 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
885 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
886 struct ena_com_io_sq *io_sq)
888 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
889 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
890 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
894 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
896 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
897 direction = ENA_ADMIN_SQ_DIRECTION_TX;
899 direction = ENA_ADMIN_SQ_DIRECTION_RX;
901 destroy_cmd.sq.sq_identity |= (direction <<
902 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
903 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
905 destroy_cmd.sq.sq_idx = io_sq->idx;
906 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
908 ret = ena_com_execute_admin_command(admin_queue,
909 (struct ena_admin_aq_entry *)&destroy_cmd,
911 (struct ena_admin_acq_entry *)&destroy_resp,
912 sizeof(destroy_resp));
914 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
915 ena_trc_err("failed to destroy io sq error: %d\n", ret);
920 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
921 struct ena_com_io_sq *io_sq,
922 struct ena_com_io_cq *io_cq)
926 if (io_cq->cdesc_addr.virt_addr) {
927 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
929 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
931 io_cq->cdesc_addr.virt_addr,
932 io_cq->cdesc_addr.phys_addr,
933 io_cq->cdesc_addr.mem_handle);
935 io_cq->cdesc_addr.virt_addr = NULL;
938 if (io_sq->desc_addr.virt_addr) {
939 size = io_sq->desc_entry_size * io_sq->q_depth;
941 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
943 io_sq->desc_addr.virt_addr,
944 io_sq->desc_addr.phys_addr,
945 io_sq->desc_addr.mem_handle);
947 io_sq->desc_addr.virt_addr = NULL;
950 if (io_sq->bounce_buf_ctrl.base_buffer) {
951 ENA_MEM_FREE(ena_dev->dmadev,
952 io_sq->bounce_buf_ctrl.base_buffer,
953 (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
954 io_sq->bounce_buf_ctrl.base_buffer = NULL;
958 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
962 ena_time_t timeout_stamp;
964 /* Convert timeout from resolution of 100ms to us resolution. */
965 timeout_stamp = ENA_GET_SYSTEM_TIMEOUT(100 * 1000 * timeout);
968 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
970 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
971 ena_trc_err("Reg read timeout occurred\n");
972 return ENA_COM_TIMER_EXPIRED;
975 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
979 if (ENA_TIME_EXPIRE(timeout_stamp))
980 return ENA_COM_TIMER_EXPIRED;
982 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
986 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
987 enum ena_admin_aq_feature_id feature_id)
989 u32 feature_mask = 1 << feature_id;
991 /* Device attributes is always supported */
992 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
993 !(ena_dev->supported_features & feature_mask))
999 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
1000 struct ena_admin_get_feat_resp *get_resp,
1001 enum ena_admin_aq_feature_id feature_id,
1002 dma_addr_t control_buf_dma_addr,
1003 u32 control_buff_size,
1006 struct ena_com_admin_queue *admin_queue;
1007 struct ena_admin_get_feat_cmd get_cmd;
1010 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1011 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
1012 return ENA_COM_UNSUPPORTED;
1015 memset(&get_cmd, 0x0, sizeof(get_cmd));
1016 admin_queue = &ena_dev->admin_queue;
1018 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1020 if (control_buff_size)
1021 get_cmd.aq_common_descriptor.flags =
1022 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1024 get_cmd.aq_common_descriptor.flags = 0;
1026 ret = ena_com_mem_addr_set(ena_dev,
1027 &get_cmd.control_buffer.address,
1028 control_buf_dma_addr);
1029 if (unlikely(ret)) {
1030 ena_trc_err("memory address set failed\n");
1034 get_cmd.control_buffer.length = control_buff_size;
1035 get_cmd.feat_common.feature_version = feature_ver;
1036 get_cmd.feat_common.feature_id = feature_id;
1038 ret = ena_com_execute_admin_command(admin_queue,
1039 (struct ena_admin_aq_entry *)
1042 (struct ena_admin_acq_entry *)
1047 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1053 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1054 struct ena_admin_get_feat_resp *get_resp,
1055 enum ena_admin_aq_feature_id feature_id,
1058 return ena_com_get_feature_ex(ena_dev,
1066 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1068 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1069 (ena_dev->rss).hash_key;
1071 ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1072 /* The key is stored in the device in uint32_t array
1073 * as well as the API requires the key to be passed in this
1074 * format. Thus the size of our array should be divided by 4
1076 hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t);
1079 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1081 struct ena_rss *rss = &ena_dev->rss;
1083 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1084 sizeof(*rss->hash_key),
1086 rss->hash_key_dma_addr,
1087 rss->hash_key_mem_handle);
1089 if (unlikely(!rss->hash_key))
1090 return ENA_COM_NO_MEM;
1095 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1097 struct ena_rss *rss = &ena_dev->rss;
1100 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1101 sizeof(*rss->hash_key),
1103 rss->hash_key_dma_addr,
1104 rss->hash_key_mem_handle);
1105 rss->hash_key = NULL;
1108 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1110 struct ena_rss *rss = &ena_dev->rss;
1112 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1113 sizeof(*rss->hash_ctrl),
1115 rss->hash_ctrl_dma_addr,
1116 rss->hash_ctrl_mem_handle);
1118 if (unlikely(!rss->hash_ctrl))
1119 return ENA_COM_NO_MEM;
1124 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1126 struct ena_rss *rss = &ena_dev->rss;
1129 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1130 sizeof(*rss->hash_ctrl),
1132 rss->hash_ctrl_dma_addr,
1133 rss->hash_ctrl_mem_handle);
1134 rss->hash_ctrl = NULL;
1137 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1140 struct ena_rss *rss = &ena_dev->rss;
1141 struct ena_admin_get_feat_resp get_resp;
1145 ret = ena_com_get_feature(ena_dev, &get_resp,
1146 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1150 if ((get_resp.u.ind_table.min_size > log_size) ||
1151 (get_resp.u.ind_table.max_size < log_size)) {
1152 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1154 1 << get_resp.u.ind_table.min_size,
1155 1 << get_resp.u.ind_table.max_size);
1156 return ENA_COM_INVAL;
1159 tbl_size = (1ULL << log_size) *
1160 sizeof(struct ena_admin_rss_ind_table_entry);
1162 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1165 rss->rss_ind_tbl_dma_addr,
1166 rss->rss_ind_tbl_mem_handle);
1167 if (unlikely(!rss->rss_ind_tbl))
1170 tbl_size = (1ULL << log_size) * sizeof(u16);
1171 rss->host_rss_ind_tbl =
1172 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1173 if (unlikely(!rss->host_rss_ind_tbl))
1176 rss->tbl_log_size = log_size;
1181 tbl_size = (1ULL << log_size) *
1182 sizeof(struct ena_admin_rss_ind_table_entry);
1184 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1187 rss->rss_ind_tbl_dma_addr,
1188 rss->rss_ind_tbl_mem_handle);
1189 rss->rss_ind_tbl = NULL;
1191 rss->tbl_log_size = 0;
1192 return ENA_COM_NO_MEM;
1195 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1197 struct ena_rss *rss = &ena_dev->rss;
1198 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1199 sizeof(struct ena_admin_rss_ind_table_entry);
1201 if (rss->rss_ind_tbl)
1202 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1205 rss->rss_ind_tbl_dma_addr,
1206 rss->rss_ind_tbl_mem_handle);
1207 rss->rss_ind_tbl = NULL;
1209 if (rss->host_rss_ind_tbl)
1210 ENA_MEM_FREE(ena_dev->dmadev,
1211 rss->host_rss_ind_tbl,
1212 ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1213 rss->host_rss_ind_tbl = NULL;
1216 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1217 struct ena_com_io_sq *io_sq, u16 cq_idx)
1219 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1220 struct ena_admin_aq_create_sq_cmd create_cmd;
1221 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1225 memset(&create_cmd, 0x0, sizeof(create_cmd));
1227 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1229 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1230 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1232 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1234 create_cmd.sq_identity |= (direction <<
1235 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1236 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1238 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1239 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1241 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1242 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1243 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1245 create_cmd.sq_caps_3 |=
1246 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1248 create_cmd.cq_idx = cq_idx;
1249 create_cmd.sq_depth = io_sq->q_depth;
1251 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1252 ret = ena_com_mem_addr_set(ena_dev,
1254 io_sq->desc_addr.phys_addr);
1255 if (unlikely(ret)) {
1256 ena_trc_err("memory address set failed\n");
1261 ret = ena_com_execute_admin_command(admin_queue,
1262 (struct ena_admin_aq_entry *)&create_cmd,
1264 (struct ena_admin_acq_entry *)&cmd_completion,
1265 sizeof(cmd_completion));
1266 if (unlikely(ret)) {
1267 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1271 io_sq->idx = cmd_completion.sq_idx;
1273 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1274 (uintptr_t)cmd_completion.sq_doorbell_offset);
1276 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1277 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1278 + cmd_completion.llq_headers_offset);
1280 io_sq->desc_addr.pbuf_dev_addr =
1281 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1282 cmd_completion.llq_descriptors_offset);
1285 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1290 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1292 struct ena_rss *rss = &ena_dev->rss;
1293 struct ena_com_io_sq *io_sq;
1297 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1298 qid = rss->host_rss_ind_tbl[i];
1299 if (qid >= ENA_TOTAL_NUM_QUEUES)
1300 return ENA_COM_INVAL;
1302 io_sq = &ena_dev->io_sq_queues[qid];
1304 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1305 return ENA_COM_INVAL;
1307 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1313 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1314 u16 intr_delay_resolution)
1316 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1318 if (unlikely(!intr_delay_resolution)) {
1319 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1320 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1324 ena_dev->intr_moder_rx_interval =
1325 ena_dev->intr_moder_rx_interval *
1326 prev_intr_delay_resolution /
1327 intr_delay_resolution;
1330 ena_dev->intr_moder_tx_interval =
1331 ena_dev->intr_moder_tx_interval *
1332 prev_intr_delay_resolution /
1333 intr_delay_resolution;
1335 ena_dev->intr_delay_resolution = intr_delay_resolution;
1338 /*****************************************************************************/
1339 /******************************* API ******************************/
1340 /*****************************************************************************/
1342 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1343 struct ena_admin_aq_entry *cmd,
1345 struct ena_admin_acq_entry *comp,
1348 struct ena_comp_ctx *comp_ctx;
1351 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1353 if (IS_ERR(comp_ctx)) {
1354 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1355 ena_trc_dbg("Failed to submit command [%ld]\n",
1358 ena_trc_err("Failed to submit command [%ld]\n",
1361 return PTR_ERR(comp_ctx);
1364 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1365 if (unlikely(ret)) {
1366 if (admin_queue->running_state)
1367 ena_trc_err("Failed to process command. ret = %d\n",
1370 ena_trc_dbg("Failed to process command. ret = %d\n",
1376 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1377 struct ena_com_io_cq *io_cq)
1379 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1380 struct ena_admin_aq_create_cq_cmd create_cmd;
1381 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1384 memset(&create_cmd, 0x0, sizeof(create_cmd));
1386 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1388 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1389 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1390 create_cmd.cq_caps_1 |=
1391 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1393 create_cmd.msix_vector = io_cq->msix_vector;
1394 create_cmd.cq_depth = io_cq->q_depth;
1396 ret = ena_com_mem_addr_set(ena_dev,
1398 io_cq->cdesc_addr.phys_addr);
1399 if (unlikely(ret)) {
1400 ena_trc_err("memory address set failed\n");
1404 ret = ena_com_execute_admin_command(admin_queue,
1405 (struct ena_admin_aq_entry *)&create_cmd,
1407 (struct ena_admin_acq_entry *)&cmd_completion,
1408 sizeof(cmd_completion));
1409 if (unlikely(ret)) {
1410 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1414 io_cq->idx = cmd_completion.cq_idx;
1416 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1417 cmd_completion.cq_interrupt_unmask_register_offset);
1419 if (cmd_completion.cq_head_db_register_offset)
1420 io_cq->cq_head_db_reg =
1421 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1422 cmd_completion.cq_head_db_register_offset);
1424 if (cmd_completion.numa_node_register_offset)
1425 io_cq->numa_node_cfg_reg =
1426 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1427 cmd_completion.numa_node_register_offset);
1429 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1434 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1435 struct ena_com_io_sq **io_sq,
1436 struct ena_com_io_cq **io_cq)
1438 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1439 ena_trc_err("Invalid queue number %d but the max is %d\n",
1440 qid, ENA_TOTAL_NUM_QUEUES);
1441 return ENA_COM_INVAL;
1444 *io_sq = &ena_dev->io_sq_queues[qid];
1445 *io_cq = &ena_dev->io_cq_queues[qid];
1450 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1452 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1453 struct ena_comp_ctx *comp_ctx;
1456 if (!admin_queue->comp_ctx)
1459 for (i = 0; i < admin_queue->q_depth; i++) {
1460 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1461 if (unlikely(!comp_ctx))
1464 comp_ctx->status = ENA_CMD_ABORTED;
1466 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1470 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1472 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1473 unsigned long flags = 0;
1476 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1477 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1478 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1479 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1480 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1482 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1485 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1486 struct ena_com_io_cq *io_cq)
1488 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1489 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1490 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1493 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1495 destroy_cmd.cq_idx = io_cq->idx;
1496 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1498 ret = ena_com_execute_admin_command(admin_queue,
1499 (struct ena_admin_aq_entry *)&destroy_cmd,
1500 sizeof(destroy_cmd),
1501 (struct ena_admin_acq_entry *)&destroy_resp,
1502 sizeof(destroy_resp));
1504 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1505 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1510 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1512 return ena_dev->admin_queue.running_state;
1515 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1517 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1518 unsigned long flags = 0;
1520 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1521 ena_dev->admin_queue.running_state = state;
1522 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1525 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1527 u16 depth = ena_dev->aenq.q_depth;
1529 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1531 /* Init head_db to mark that all entries in the queue
1532 * are initially available
1534 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1537 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1539 struct ena_com_admin_queue *admin_queue;
1540 struct ena_admin_set_feat_cmd cmd;
1541 struct ena_admin_set_feat_resp resp;
1542 struct ena_admin_get_feat_resp get_resp;
1545 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1547 ena_trc_info("Can't get aenq configuration\n");
1551 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1552 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1553 get_resp.u.aenq.supported_groups,
1555 return ENA_COM_UNSUPPORTED;
1558 memset(&cmd, 0x0, sizeof(cmd));
1559 admin_queue = &ena_dev->admin_queue;
1561 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1562 cmd.aq_common_descriptor.flags = 0;
1563 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1564 cmd.u.aenq.enabled_groups = groups_flag;
1566 ret = ena_com_execute_admin_command(admin_queue,
1567 (struct ena_admin_aq_entry *)&cmd,
1569 (struct ena_admin_acq_entry *)&resp,
1573 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1578 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1580 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1583 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1584 ena_trc_err("Reg read timeout occurred\n");
1585 return ENA_COM_TIMER_EXPIRED;
1588 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1589 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1591 ena_trc_dbg("ENA dma width: %d\n", width);
1593 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1594 ena_trc_err("DMA width illegal value: %d\n", width);
1595 return ENA_COM_INVAL;
1598 ena_dev->dma_addr_bits = width;
1603 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1607 u32 ctrl_ver_masked;
1609 /* Make sure the ENA version and the controller version are at least
1610 * as the driver expects
1612 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1613 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1614 ENA_REGS_CONTROLLER_VERSION_OFF);
1616 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1617 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1618 ena_trc_err("Reg read timeout occurred\n");
1619 return ENA_COM_TIMER_EXPIRED;
1622 ena_trc_info("ena device version: %d.%d\n",
1623 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1624 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1625 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1627 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1628 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1629 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1630 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1631 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1632 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1633 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1634 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1637 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1638 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1639 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1641 /* Validate the ctrl version without the implementation ID */
1642 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1643 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1650 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1652 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1653 struct ena_com_admin_cq *cq = &admin_queue->cq;
1654 struct ena_com_admin_sq *sq = &admin_queue->sq;
1655 struct ena_com_aenq *aenq = &ena_dev->aenq;
1658 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1659 if (admin_queue->comp_ctx)
1660 ENA_MEM_FREE(ena_dev->dmadev,
1661 admin_queue->comp_ctx,
1662 (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1663 admin_queue->comp_ctx = NULL;
1664 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1666 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1667 sq->dma_addr, sq->mem_handle);
1670 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1672 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1673 cq->dma_addr, cq->mem_handle);
1676 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1677 if (ena_dev->aenq.entries)
1678 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1679 aenq->dma_addr, aenq->mem_handle);
1680 aenq->entries = NULL;
1681 ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1684 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1689 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1691 ENA_REG_WRITE32(ena_dev->bus, mask_value,
1692 ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1693 ena_dev->admin_queue.polling = polling;
1696 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1698 return ena_dev->admin_queue.polling;
1701 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1704 ena_dev->admin_queue.auto_polling = polling;
1707 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1709 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1711 ENA_SPINLOCK_INIT(mmio_read->lock);
1712 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1713 sizeof(*mmio_read->read_resp),
1714 mmio_read->read_resp,
1715 mmio_read->read_resp_dma_addr,
1716 mmio_read->read_resp_mem_handle);
1717 if (unlikely(!mmio_read->read_resp))
1720 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1722 mmio_read->read_resp->req_id = 0x0;
1723 mmio_read->seq_num = 0x0;
1724 mmio_read->readless_supported = true;
1729 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1730 return ENA_COM_NO_MEM;
1733 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1735 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1737 mmio_read->readless_supported = readless_supported;
1740 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1742 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1744 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1745 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1747 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1748 sizeof(*mmio_read->read_resp),
1749 mmio_read->read_resp,
1750 mmio_read->read_resp_dma_addr,
1751 mmio_read->read_resp_mem_handle);
1753 mmio_read->read_resp = NULL;
1754 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1757 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1759 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1760 u32 addr_low, addr_high;
1762 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1763 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1765 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1766 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1769 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1770 struct ena_aenq_handlers *aenq_handlers)
1772 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1773 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1776 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1778 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1779 ena_trc_err("Reg read timeout occurred\n");
1780 return ENA_COM_TIMER_EXPIRED;
1783 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1784 ena_trc_err("Device isn't ready, abort com init\n");
1785 return ENA_COM_NO_DEVICE;
1788 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1790 admin_queue->bus = ena_dev->bus;
1791 admin_queue->q_dmadev = ena_dev->dmadev;
1792 admin_queue->polling = false;
1793 admin_queue->curr_cmd_id = 0;
1795 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1797 ENA_SPINLOCK_INIT(admin_queue->q_lock);
1799 ret = ena_com_init_comp_ctxt(admin_queue);
1803 ret = ena_com_admin_init_sq(admin_queue);
1807 ret = ena_com_admin_init_cq(admin_queue);
1811 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1812 ENA_REGS_AQ_DB_OFF);
1814 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1815 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1817 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1818 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1820 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1821 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1823 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1824 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1827 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1828 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1829 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1830 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1833 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1834 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1835 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1836 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1838 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1839 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1840 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1844 admin_queue->ena_dev = ena_dev;
1845 admin_queue->running_state = true;
1849 ena_com_admin_destroy(ena_dev);
1854 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1855 struct ena_com_create_io_ctx *ctx)
1857 struct ena_com_io_sq *io_sq;
1858 struct ena_com_io_cq *io_cq;
1861 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1862 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1863 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1864 return ENA_COM_INVAL;
1867 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1868 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1870 memset(io_sq, 0x0, sizeof(*io_sq));
1871 memset(io_cq, 0x0, sizeof(*io_cq));
1874 io_cq->q_depth = ctx->queue_size;
1875 io_cq->direction = ctx->direction;
1876 io_cq->qid = ctx->qid;
1878 io_cq->msix_vector = ctx->msix_vector;
1880 io_sq->q_depth = ctx->queue_size;
1881 io_sq->direction = ctx->direction;
1882 io_sq->qid = ctx->qid;
1884 io_sq->mem_queue_type = ctx->mem_queue_type;
1886 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1887 /* header length is limited to 8 bits */
1888 io_sq->tx_max_header_size =
1889 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1891 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1894 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1898 ret = ena_com_create_io_cq(ena_dev, io_cq);
1902 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1909 ena_com_destroy_io_cq(ena_dev, io_cq);
1911 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1915 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1917 struct ena_com_io_sq *io_sq;
1918 struct ena_com_io_cq *io_cq;
1920 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1921 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1922 qid, ENA_TOTAL_NUM_QUEUES);
1926 io_sq = &ena_dev->io_sq_queues[qid];
1927 io_cq = &ena_dev->io_cq_queues[qid];
1929 ena_com_destroy_io_sq(ena_dev, io_sq);
1930 ena_com_destroy_io_cq(ena_dev, io_cq);
1932 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1935 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1936 struct ena_admin_get_feat_resp *resp)
1938 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1941 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1942 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1944 struct ena_admin_get_feat_resp get_resp;
1947 rc = ena_com_get_feature(ena_dev, &get_resp,
1948 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1952 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1953 sizeof(get_resp.u.dev_attr));
1954 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1956 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1957 rc = ena_com_get_feature(ena_dev, &get_resp,
1958 ENA_ADMIN_MAX_QUEUES_EXT,
1959 ENA_FEATURE_MAX_QUEUE_EXT_VER);
1963 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1966 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1967 sizeof(get_resp.u.max_queue_ext));
1968 ena_dev->tx_max_header_size =
1969 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1971 rc = ena_com_get_feature(ena_dev, &get_resp,
1972 ENA_ADMIN_MAX_QUEUES_NUM, 0);
1973 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1974 sizeof(get_resp.u.max_queue));
1975 ena_dev->tx_max_header_size =
1976 get_resp.u.max_queue.max_header_size;
1982 rc = ena_com_get_feature(ena_dev, &get_resp,
1983 ENA_ADMIN_AENQ_CONFIG, 0);
1987 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1988 sizeof(get_resp.u.aenq));
1990 rc = ena_com_get_feature(ena_dev, &get_resp,
1991 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1995 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1996 sizeof(get_resp.u.offload));
1998 /* Driver hints isn't mandatory admin command. So in case the
1999 * command isn't supported set driver hints to 0
2001 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2004 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2005 sizeof(get_resp.u.hw_hints));
2006 else if (rc == ENA_COM_UNSUPPORTED)
2007 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2011 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2013 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2014 sizeof(get_resp.u.llq));
2015 else if (rc == ENA_COM_UNSUPPORTED)
2016 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2020 rc = ena_com_get_feature(ena_dev, &get_resp,
2021 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2023 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2024 sizeof(get_resp.u.ind_table));
2025 else if (rc == ENA_COM_UNSUPPORTED)
2026 memset(&get_feat_ctx->ind_table, 0x0,
2027 sizeof(get_feat_ctx->ind_table));
2034 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2036 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2039 /* ena_handle_specific_aenq_event:
2040 * return the handler that is relevant to the specific event group
2042 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2045 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2047 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2048 return aenq_handlers->handlers[group];
2050 return aenq_handlers->unimplemented_handler;
2053 /* ena_aenq_intr_handler:
2054 * handles the aenq incoming events.
2055 * pop events from the queue and apply the specific handler
2057 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2059 struct ena_admin_aenq_entry *aenq_e;
2060 struct ena_admin_aenq_common_desc *aenq_common;
2061 struct ena_com_aenq *aenq = &dev->aenq;
2063 ena_aenq_handler handler_cb;
2064 u16 masked_head, processed = 0;
2067 masked_head = aenq->head & (aenq->q_depth - 1);
2068 phase = aenq->phase;
2069 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2070 aenq_common = &aenq_e->aenq_common_desc;
2072 /* Go over all the events */
2073 while ((READ_ONCE8(aenq_common->flags) &
2074 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2075 /* Make sure the phase bit (ownership) is as expected before
2076 * reading the rest of the descriptor.
2080 timestamp = (u64)aenq_common->timestamp_low |
2081 ((u64)aenq_common->timestamp_high << 32);
2082 ENA_TOUCH(timestamp); /* In case debug is disabled */
2083 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2085 aenq_common->syndrom,
2088 /* Handle specific event*/
2089 handler_cb = ena_com_get_specific_aenq_cb(dev,
2090 aenq_common->group);
2091 handler_cb(data, aenq_e); /* call the actual event handler*/
2093 /* Get next event entry */
2097 if (unlikely(masked_head == aenq->q_depth)) {
2101 aenq_e = &aenq->entries[masked_head];
2102 aenq_common = &aenq_e->aenq_common_desc;
2105 aenq->head += processed;
2106 aenq->phase = phase;
2108 /* Don't update aenq doorbell if there weren't any processed events */
2112 /* write the aenq doorbell after all AENQ descriptors were read */
2114 ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2115 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2116 #ifndef MMIOWB_NOT_DEFINED
2121 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2122 enum ena_regs_reset_reason_types reset_reason)
2124 u32 stat, timeout, cap, reset_val;
2127 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2128 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2130 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2131 (cap == ENA_MMIO_READ_TIMEOUT))) {
2132 ena_trc_err("Reg read32 timeout occurred\n");
2133 return ENA_COM_TIMER_EXPIRED;
2136 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2137 ena_trc_err("Device isn't ready, can't reset device\n");
2138 return ENA_COM_INVAL;
2141 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2142 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2144 ena_trc_err("Invalid timeout value\n");
2145 return ENA_COM_INVAL;
2149 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2150 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2151 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2152 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2154 /* Write again the MMIO read request address */
2155 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2157 rc = wait_for_reset_state(ena_dev, timeout,
2158 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2160 ena_trc_err("Reset indication didn't turn on\n");
2165 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2166 rc = wait_for_reset_state(ena_dev, timeout, 0);
2168 ena_trc_err("Reset indication didn't turn off\n");
2172 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2173 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2175 /* the resolution of timeout reg is 100ms */
2176 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2178 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2183 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2184 struct ena_com_stats_ctx *ctx,
2185 enum ena_admin_get_stats_type type)
2187 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2188 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2189 struct ena_com_admin_queue *admin_queue;
2192 admin_queue = &ena_dev->admin_queue;
2194 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2195 get_cmd->aq_common_descriptor.flags = 0;
2196 get_cmd->type = type;
2198 ret = ena_com_execute_admin_command(admin_queue,
2199 (struct ena_admin_aq_entry *)get_cmd,
2201 (struct ena_admin_acq_entry *)get_resp,
2205 ena_trc_err("Failed to get stats. error: %d\n", ret);
2210 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2211 struct ena_admin_basic_stats *stats)
2213 struct ena_com_stats_ctx ctx;
2216 memset(&ctx, 0x0, sizeof(ctx));
2217 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2218 if (likely(ret == 0))
2219 memcpy(stats, &ctx.get_resp.basic_stats,
2220 sizeof(ctx.get_resp.basic_stats));
2225 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2227 struct ena_com_admin_queue *admin_queue;
2228 struct ena_admin_set_feat_cmd cmd;
2229 struct ena_admin_set_feat_resp resp;
2232 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2233 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2234 return ENA_COM_UNSUPPORTED;
2237 memset(&cmd, 0x0, sizeof(cmd));
2238 admin_queue = &ena_dev->admin_queue;
2240 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2241 cmd.aq_common_descriptor.flags = 0;
2242 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2243 cmd.u.mtu.mtu = mtu;
2245 ret = ena_com_execute_admin_command(admin_queue,
2246 (struct ena_admin_aq_entry *)&cmd,
2248 (struct ena_admin_acq_entry *)&resp,
2252 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2257 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2258 struct ena_admin_feature_offload_desc *offload)
2261 struct ena_admin_get_feat_resp resp;
2263 ret = ena_com_get_feature(ena_dev, &resp,
2264 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2265 if (unlikely(ret)) {
2266 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2270 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2275 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2277 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2278 struct ena_rss *rss = &ena_dev->rss;
2279 struct ena_admin_set_feat_cmd cmd;
2280 struct ena_admin_set_feat_resp resp;
2281 struct ena_admin_get_feat_resp get_resp;
2284 if (!ena_com_check_supported_feature_id(ena_dev,
2285 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2286 ena_trc_dbg("Feature %d isn't supported\n",
2287 ENA_ADMIN_RSS_HASH_FUNCTION);
2288 return ENA_COM_UNSUPPORTED;
2291 /* Validate hash function is supported */
2292 ret = ena_com_get_feature(ena_dev, &get_resp,
2293 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2297 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2298 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2300 return ENA_COM_UNSUPPORTED;
2303 memset(&cmd, 0x0, sizeof(cmd));
2305 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2306 cmd.aq_common_descriptor.flags =
2307 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2308 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2309 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2310 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2312 ret = ena_com_mem_addr_set(ena_dev,
2313 &cmd.control_buffer.address,
2314 rss->hash_key_dma_addr);
2315 if (unlikely(ret)) {
2316 ena_trc_err("memory address set failed\n");
2320 cmd.control_buffer.length = sizeof(*rss->hash_key);
2322 ret = ena_com_execute_admin_command(admin_queue,
2323 (struct ena_admin_aq_entry *)&cmd,
2325 (struct ena_admin_acq_entry *)&resp,
2327 if (unlikely(ret)) {
2328 ena_trc_err("Failed to set hash function %d. error: %d\n",
2329 rss->hash_func, ret);
2330 return ENA_COM_INVAL;
2336 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2337 enum ena_admin_hash_functions func,
2338 const u8 *key, u16 key_len, u32 init_val)
2340 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2341 struct ena_admin_get_feat_resp get_resp;
2342 enum ena_admin_hash_functions old_func;
2343 struct ena_rss *rss = &ena_dev->rss;
2346 hash_key = rss->hash_key;
2348 /* Make sure size is a mult of DWs */
2349 if (unlikely(key_len & 0x3))
2350 return ENA_COM_INVAL;
2352 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2353 ENA_ADMIN_RSS_HASH_FUNCTION,
2354 rss->hash_key_dma_addr,
2355 sizeof(*rss->hash_key), 0);
2359 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2360 ena_trc_err("Flow hash function %d isn't supported\n", func);
2361 return ENA_COM_UNSUPPORTED;
2365 case ENA_ADMIN_TOEPLITZ:
2367 if (key_len != sizeof(hash_key->key)) {
2368 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2369 key_len, sizeof(hash_key->key));
2370 return ENA_COM_INVAL;
2372 memcpy(hash_key->key, key, key_len);
2373 rss->hash_init_val = init_val;
2374 hash_key->keys_num = key_len / sizeof(u32);
2377 case ENA_ADMIN_CRC32:
2378 rss->hash_init_val = init_val;
2381 ena_trc_err("Invalid hash function (%d)\n", func);
2382 return ENA_COM_INVAL;
2385 old_func = rss->hash_func;
2386 rss->hash_func = func;
2387 rc = ena_com_set_hash_function(ena_dev);
2389 /* Restore the old function */
2391 rss->hash_func = old_func;
2396 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2397 enum ena_admin_hash_functions *func,
2400 struct ena_rss *rss = &ena_dev->rss;
2401 struct ena_admin_get_feat_resp get_resp;
2402 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2406 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2407 ENA_ADMIN_RSS_HASH_FUNCTION,
2408 rss->hash_key_dma_addr,
2409 sizeof(*rss->hash_key), 0);
2413 /* ENA_FFS returns 1 in case the lsb is set */
2414 rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2419 *func = rss->hash_func;
2422 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2427 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2428 enum ena_admin_flow_hash_proto proto,
2431 struct ena_rss *rss = &ena_dev->rss;
2432 struct ena_admin_get_feat_resp get_resp;
2435 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2436 ENA_ADMIN_RSS_HASH_INPUT,
2437 rss->hash_ctrl_dma_addr,
2438 sizeof(*rss->hash_ctrl), 0);
2443 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2448 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2450 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2451 struct ena_rss *rss = &ena_dev->rss;
2452 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2453 struct ena_admin_set_feat_cmd cmd;
2454 struct ena_admin_set_feat_resp resp;
2457 if (!ena_com_check_supported_feature_id(ena_dev,
2458 ENA_ADMIN_RSS_HASH_INPUT)) {
2459 ena_trc_dbg("Feature %d isn't supported\n",
2460 ENA_ADMIN_RSS_HASH_INPUT);
2461 return ENA_COM_UNSUPPORTED;
2464 memset(&cmd, 0x0, sizeof(cmd));
2466 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2467 cmd.aq_common_descriptor.flags =
2468 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2469 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2470 cmd.u.flow_hash_input.enabled_input_sort =
2471 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2472 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2474 ret = ena_com_mem_addr_set(ena_dev,
2475 &cmd.control_buffer.address,
2476 rss->hash_ctrl_dma_addr);
2477 if (unlikely(ret)) {
2478 ena_trc_err("memory address set failed\n");
2481 cmd.control_buffer.length = sizeof(*hash_ctrl);
2483 ret = ena_com_execute_admin_command(admin_queue,
2484 (struct ena_admin_aq_entry *)&cmd,
2486 (struct ena_admin_acq_entry *)&resp,
2489 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2494 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2496 struct ena_rss *rss = &ena_dev->rss;
2497 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2499 u16 available_fields = 0;
2502 /* Get the supported hash input */
2503 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2507 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2508 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2509 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2511 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2512 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2513 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2515 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2516 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2517 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2519 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2520 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2521 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2523 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2524 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2526 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2527 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2529 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2530 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2532 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2533 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2535 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2536 available_fields = hash_ctrl->selected_fields[i].fields &
2537 hash_ctrl->supported_fields[i].fields;
2538 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2539 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2540 i, hash_ctrl->supported_fields[i].fields,
2541 hash_ctrl->selected_fields[i].fields);
2542 return ENA_COM_UNSUPPORTED;
2546 rc = ena_com_set_hash_ctrl(ena_dev);
2548 /* In case of failure, restore the old hash ctrl */
2550 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2555 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2556 enum ena_admin_flow_hash_proto proto,
2559 struct ena_rss *rss = &ena_dev->rss;
2560 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2561 u16 supported_fields;
2564 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2565 ena_trc_err("Invalid proto num (%u)\n", proto);
2566 return ENA_COM_INVAL;
2569 /* Get the ctrl table */
2570 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2574 /* Make sure all the fields are supported */
2575 supported_fields = hash_ctrl->supported_fields[proto].fields;
2576 if ((hash_fields & supported_fields) != hash_fields) {
2577 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2578 proto, hash_fields, supported_fields);
2581 hash_ctrl->selected_fields[proto].fields = hash_fields;
2583 rc = ena_com_set_hash_ctrl(ena_dev);
2585 /* In case of failure, restore the old hash ctrl */
2587 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2592 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2593 u16 entry_idx, u16 entry_value)
2595 struct ena_rss *rss = &ena_dev->rss;
2597 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2598 return ENA_COM_INVAL;
2600 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2601 return ENA_COM_INVAL;
2603 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2608 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2610 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2611 struct ena_rss *rss = &ena_dev->rss;
2612 struct ena_admin_set_feat_cmd cmd;
2613 struct ena_admin_set_feat_resp resp;
2616 if (!ena_com_check_supported_feature_id(ena_dev,
2617 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2618 ena_trc_dbg("Feature %d isn't supported\n",
2619 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2620 return ENA_COM_UNSUPPORTED;
2623 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2625 ena_trc_err("Failed to convert host indirection table to device table\n");
2629 memset(&cmd, 0x0, sizeof(cmd));
2631 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2632 cmd.aq_common_descriptor.flags =
2633 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2634 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2635 cmd.u.ind_table.size = rss->tbl_log_size;
2636 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2638 ret = ena_com_mem_addr_set(ena_dev,
2639 &cmd.control_buffer.address,
2640 rss->rss_ind_tbl_dma_addr);
2641 if (unlikely(ret)) {
2642 ena_trc_err("memory address set failed\n");
2646 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2647 sizeof(struct ena_admin_rss_ind_table_entry);
2649 ret = ena_com_execute_admin_command(admin_queue,
2650 (struct ena_admin_aq_entry *)&cmd,
2652 (struct ena_admin_acq_entry *)&resp,
2656 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2661 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2663 struct ena_rss *rss = &ena_dev->rss;
2664 struct ena_admin_get_feat_resp get_resp;
2668 tbl_size = (1ULL << rss->tbl_log_size) *
2669 sizeof(struct ena_admin_rss_ind_table_entry);
2671 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2672 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2673 rss->rss_ind_tbl_dma_addr,
2681 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2682 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2687 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2691 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2693 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2697 rc = ena_com_hash_key_allocate(ena_dev);
2701 ena_com_hash_key_fill_default_key(ena_dev);
2703 rc = ena_com_hash_ctrl_init(ena_dev);
2710 ena_com_hash_key_destroy(ena_dev);
2712 ena_com_indirect_table_destroy(ena_dev);
2718 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2720 ena_com_indirect_table_destroy(ena_dev);
2721 ena_com_hash_key_destroy(ena_dev);
2722 ena_com_hash_ctrl_destroy(ena_dev);
2724 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2727 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2729 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2731 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2733 host_attr->host_info,
2734 host_attr->host_info_dma_addr,
2735 host_attr->host_info_dma_handle);
2736 if (unlikely(!host_attr->host_info))
2737 return ENA_COM_NO_MEM;
2739 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2740 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2741 (ENA_COMMON_SPEC_VERSION_MINOR));
2746 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2747 u32 debug_area_size)
2749 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2751 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2753 host_attr->debug_area_virt_addr,
2754 host_attr->debug_area_dma_addr,
2755 host_attr->debug_area_dma_handle);
2756 if (unlikely(!host_attr->debug_area_virt_addr)) {
2757 host_attr->debug_area_size = 0;
2758 return ENA_COM_NO_MEM;
2761 host_attr->debug_area_size = debug_area_size;
2766 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2768 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2770 if (host_attr->host_info) {
2771 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2773 host_attr->host_info,
2774 host_attr->host_info_dma_addr,
2775 host_attr->host_info_dma_handle);
2776 host_attr->host_info = NULL;
2780 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2782 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2784 if (host_attr->debug_area_virt_addr) {
2785 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2786 host_attr->debug_area_size,
2787 host_attr->debug_area_virt_addr,
2788 host_attr->debug_area_dma_addr,
2789 host_attr->debug_area_dma_handle);
2790 host_attr->debug_area_virt_addr = NULL;
2794 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2796 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2797 struct ena_com_admin_queue *admin_queue;
2798 struct ena_admin_set_feat_cmd cmd;
2799 struct ena_admin_set_feat_resp resp;
2803 /* Host attribute config is called before ena_com_get_dev_attr_feat
2804 * so ena_com can't check if the feature is supported.
2807 memset(&cmd, 0x0, sizeof(cmd));
2808 admin_queue = &ena_dev->admin_queue;
2810 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2811 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2813 ret = ena_com_mem_addr_set(ena_dev,
2814 &cmd.u.host_attr.debug_ba,
2815 host_attr->debug_area_dma_addr);
2816 if (unlikely(ret)) {
2817 ena_trc_err("memory address set failed\n");
2821 ret = ena_com_mem_addr_set(ena_dev,
2822 &cmd.u.host_attr.os_info_ba,
2823 host_attr->host_info_dma_addr);
2824 if (unlikely(ret)) {
2825 ena_trc_err("memory address set failed\n");
2829 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2831 ret = ena_com_execute_admin_command(admin_queue,
2832 (struct ena_admin_aq_entry *)&cmd,
2834 (struct ena_admin_acq_entry *)&resp,
2838 ena_trc_err("Failed to set host attributes: %d\n", ret);
2843 /* Interrupt moderation */
2844 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2846 return ena_com_check_supported_feature_id(ena_dev,
2847 ENA_ADMIN_INTERRUPT_MODERATION);
2850 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2851 u32 intr_delay_resolution,
2852 u32 *intr_moder_interval)
2854 if (!intr_delay_resolution) {
2855 ena_trc_err("Illegal interrupt delay granularity value\n");
2856 return ENA_COM_FAULT;
2859 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2865 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2866 u32 tx_coalesce_usecs)
2868 return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2869 ena_dev->intr_delay_resolution,
2870 &ena_dev->intr_moder_tx_interval);
2873 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2874 u32 rx_coalesce_usecs)
2876 return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2877 ena_dev->intr_delay_resolution,
2878 &ena_dev->intr_moder_rx_interval);
2881 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2883 struct ena_admin_get_feat_resp get_resp;
2884 u16 delay_resolution;
2887 rc = ena_com_get_feature(ena_dev, &get_resp,
2888 ENA_ADMIN_INTERRUPT_MODERATION, 0);
2891 if (rc == ENA_COM_UNSUPPORTED) {
2892 ena_trc_dbg("Feature %d isn't supported\n",
2893 ENA_ADMIN_INTERRUPT_MODERATION);
2896 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2900 /* no moderation supported, disable adaptive support */
2901 ena_com_disable_adaptive_moderation(ena_dev);
2905 /* if moderation is supported by device we set adaptive moderation */
2906 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2907 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2909 /* Disable adaptive moderation by default - can be enabled later */
2910 ena_com_disable_adaptive_moderation(ena_dev);
2915 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2917 return ena_dev->intr_moder_tx_interval;
2920 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2922 return ena_dev->intr_moder_rx_interval;
2925 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2926 struct ena_admin_feature_llq_desc *llq_features,
2927 struct ena_llq_configurations *llq_default_cfg)
2930 struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2932 if (!llq_features->max_llq_num) {
2933 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2937 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2941 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2942 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2944 if (ena_dev->tx_max_header_size == 0) {
2945 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2949 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;