drivers/net/ena/base/ena_com.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include "ena_com.h"
   7
   8 /*****************************************************************************/
   9 /*****************************************************************************/
  10
  11 /* Timeout in micro-sec */
  12 #define ADMIN_CMD_TIMEOUT_US (3000000)
  13
  14 #define ENA_ASYNC_QUEUE_DEPTH 16
  15 #define ENA_ADMIN_QUEUE_DEPTH 32
  16
  17 #define ENA_CTRL_MAJOR          0
  18 #define ENA_CTRL_MINOR          0
  19 #define ENA_CTRL_SUB_MINOR      1
  20
  21 #define MIN_ENA_CTRL_VER \
  22         (((ENA_CTRL_MAJOR) << \
  23         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  24         ((ENA_CTRL_MINOR) << \
  25         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  26         (ENA_CTRL_SUB_MINOR))
  27
  28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  30
  31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  32
  33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  34
  35 #define ENA_REGS_ADMIN_INTR_MASK 1
  36
  37 #define ENA_MIN_ADMIN_POLL_US 100
  38
  39 #define ENA_MAX_ADMIN_POLL_US 5000
  40
  41 /*****************************************************************************/
  42 /*****************************************************************************/
  43 /*****************************************************************************/
  44
  45 enum ena_cmd_status {
  46         ENA_CMD_SUBMITTED,
  47         ENA_CMD_COMPLETED,
  48         /* Abort - canceled by the driver */
  49         ENA_CMD_ABORTED,
  50 };
  51
  52 struct ena_comp_ctx {
  53         ena_wait_event_t wait_event;
  54         struct ena_admin_acq_entry *user_cqe;
  55         u32 comp_size;
  56         enum ena_cmd_status status;
  57         /* status from the device */
  58         u8 comp_status;
  59         u8 cmd_opcode;
  60         bool occupied;
  61 };
  62
  63 struct ena_com_stats_ctx {
  64         struct ena_admin_aq_get_stats_cmd get_cmd;
  65         struct ena_admin_acq_get_stats_resp get_resp;
  66 };
  67
  68 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  69                                        struct ena_common_mem_addr *ena_addr,
  70                                        dma_addr_t addr)
  71 {
  72         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  73                 ena_trc_err("dma address has more bits that the device supports\n");
  74                 return ENA_COM_INVAL;
  75         }
  76
  77         ena_addr->mem_addr_low = lower_32_bits(addr);
  78         ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
  79
  80         return 0;
  81 }
  82
  83 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
  84 {
  85         struct ena_com_admin_sq *sq = &queue->sq;
  86         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
  87
  88         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
  89                                sq->mem_handle);
  90
  91         if (!sq->entries) {
  92                 ena_trc_err("memory allocation failed\n");
  93                 return ENA_COM_NO_MEM;
  94         }
  95
  96         sq->head = 0;
  97         sq->tail = 0;
  98         sq->phase = 1;
  99
 100         sq->db_addr = NULL;
 101
 102         return 0;
 103 }
 104
 105 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 106 {
 107         struct ena_com_admin_cq *cq = &queue->cq;
 108         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 109
 110         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
 111                                cq->mem_handle);
 112
 113         if (!cq->entries)  {
 114                 ena_trc_err("memory allocation failed\n");
 115                 return ENA_COM_NO_MEM;
 116         }
 117
 118         cq->head = 0;
 119         cq->phase = 1;
 120
 121         return 0;
 122 }
 123
 124 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 125                                    struct ena_aenq_handlers *aenq_handlers)
 126 {
 127         struct ena_com_aenq *aenq = &dev->aenq;
 128         u32 addr_low, addr_high, aenq_caps;
 129         u16 size;
 130
 131         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 132         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 133         ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
 134                         aenq->entries,
 135                         aenq->dma_addr,
 136                         aenq->mem_handle);
 137
 138         if (!aenq->entries) {
 139                 ena_trc_err("memory allocation failed\n");
 140                 return ENA_COM_NO_MEM;
 141         }
 142
 143         aenq->head = aenq->q_depth;
 144         aenq->phase = 1;
 145
 146         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 147         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 148
 149         ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 150         ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 151
 152         aenq_caps = 0;
 153         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 154         aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
 155                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 156                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 157         ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 158
 159         if (unlikely(!aenq_handlers)) {
 160                 ena_trc_err("aenq handlers pointer is NULL\n");
 161                 return ENA_COM_INVAL;
 162         }
 163
 164         aenq->aenq_handlers = aenq_handlers;
 165
 166         return 0;
 167 }
 168
 169 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 170                                      struct ena_comp_ctx *comp_ctx)
 171 {
 172         comp_ctx->occupied = false;
 173         ATOMIC32_DEC(&queue->outstanding_cmds);
 174 }
 175
 176 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 177                                           u16 command_id, bool capture)
 178 {
 179         if (unlikely(command_id >= queue->q_depth)) {
 180                 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 181                             command_id, queue->q_depth);
 182                 return NULL;
 183         }
 184
 185         if (unlikely(!queue->comp_ctx)) {
 186                 ena_trc_err("Completion context is NULL\n");
 187                 return NULL;
 188         }
 189
 190         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 191                 ena_trc_err("Completion context is occupied\n");
 192                 return NULL;
 193         }
 194
 195         if (capture) {
 196                 ATOMIC32_INC(&queue->outstanding_cmds);
 197                 queue->comp_ctx[command_id].occupied = true;
 198         }
 199
 200         return &queue->comp_ctx[command_id];
 201 }
 202
 203 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 204                                                        struct ena_admin_aq_entry *cmd,
 205                                                        size_t cmd_size_in_bytes,
 206                                                        struct ena_admin_acq_entry *comp,
 207                                                        size_t comp_size_in_bytes)
 208 {
 209         struct ena_comp_ctx *comp_ctx;
 210         u16 tail_masked, cmd_id;
 211         u16 queue_size_mask;
 212         u16 cnt;
 213
 214         queue_size_mask = admin_queue->q_depth - 1;
 215
 216         tail_masked = admin_queue->sq.tail & queue_size_mask;
 217
 218         /* In case of queue FULL */
 219         cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
 220         if (cnt >= admin_queue->q_depth) {
 221                 ena_trc_dbg("admin queue is full.\n");
 222                 admin_queue->stats.out_of_space++;
 223                 return ERR_PTR(ENA_COM_NO_SPACE);
 224         }
 225
 226         cmd_id = admin_queue->curr_cmd_id;
 227
 228         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 229                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 230
 231         cmd->aq_common_descriptor.command_id |= cmd_id &
 232                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 233
 234         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 235         if (unlikely(!comp_ctx))
 236                 return ERR_PTR(ENA_COM_INVAL);
 237
 238         comp_ctx->status = ENA_CMD_SUBMITTED;
 239         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 240         comp_ctx->user_cqe = comp;
 241         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 242
 243         ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
 244
 245         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 246
 247         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 248                 queue_size_mask;
 249
 250         admin_queue->sq.tail++;
 251         admin_queue->stats.submitted_cmd++;
 252
 253         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 254                 admin_queue->sq.phase = !admin_queue->sq.phase;
 255
 256         ENA_DB_SYNC(&admin_queue->sq.mem_handle);
 257         ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
 258                         admin_queue->sq.db_addr);
 259
 260         return comp_ctx;
 261 }
 262
 263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 264 {
 265         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 266         struct ena_comp_ctx *comp_ctx;
 267         u16 i;
 268
 269         queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
 270         if (unlikely(!queue->comp_ctx)) {
 271                 ena_trc_err("memory allocation failed\n");
 272                 return ENA_COM_NO_MEM;
 273         }
 274
 275         for (i = 0; i < queue->q_depth; i++) {
 276                 comp_ctx = get_comp_ctxt(queue, i, false);
 277                 if (comp_ctx)
 278                         ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
 279         }
 280
 281         return 0;
 282 }
 283
 284 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 285                                                      struct ena_admin_aq_entry *cmd,
 286                                                      size_t cmd_size_in_bytes,
 287                                                      struct ena_admin_acq_entry *comp,
 288                                                      size_t comp_size_in_bytes)
 289 {
 290         unsigned long flags = 0;
 291         struct ena_comp_ctx *comp_ctx;
 292
 293         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 294         if (unlikely(!admin_queue->running_state)) {
 295                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 296                 return ERR_PTR(ENA_COM_NO_DEVICE);
 297         }
 298         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 299                                               cmd_size_in_bytes,
 300                                               comp,
 301                                               comp_size_in_bytes);
 302         if (IS_ERR(comp_ctx))
 303                 admin_queue->running_state = false;
 304         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 305
 306         return comp_ctx;
 307 }
 308
 309 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 310                               struct ena_com_create_io_ctx *ctx,
 311                               struct ena_com_io_sq *io_sq)
 312 {
 313         size_t size;
 314         int dev_node = 0;
 315
 316         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 317
 318         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 319         io_sq->desc_entry_size =
 320                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 321                 sizeof(struct ena_eth_io_tx_desc) :
 322                 sizeof(struct ena_eth_io_rx_desc);
 323
 324         size = io_sq->desc_entry_size * io_sq->q_depth;
 325         io_sq->bus = ena_dev->bus;
 326
 327         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 328                 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 329                                             size,
 330                                             io_sq->desc_addr.virt_addr,
 331                                             io_sq->desc_addr.phys_addr,
 332                                             io_sq->desc_addr.mem_handle,
 333                                             ctx->numa_node,
 334                                             dev_node);
 335                 if (!io_sq->desc_addr.virt_addr) {
 336                         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 337                                                size,
 338                                                io_sq->desc_addr.virt_addr,
 339                                                io_sq->desc_addr.phys_addr,
 340                                                io_sq->desc_addr.mem_handle);
 341                 }
 342
 343                 if (!io_sq->desc_addr.virt_addr) {
 344                         ena_trc_err("memory allocation failed\n");
 345                         return ENA_COM_NO_MEM;
 346                 }
 347         }
 348
 349         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 350                 /* Allocate bounce buffers */
 351                 io_sq->bounce_buf_ctrl.buffer_size =
 352                         ena_dev->llq_info.desc_list_entry_size;
 353                 io_sq->bounce_buf_ctrl.buffers_num =
 354                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 355                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 356
 357                 size = io_sq->bounce_buf_ctrl.buffer_size *
 358                         io_sq->bounce_buf_ctrl.buffers_num;
 359
 360                 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
 361                                    size,
 362                                    io_sq->bounce_buf_ctrl.base_buffer,
 363                                    ctx->numa_node,
 364                                    dev_node);
 365                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 366                         io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
 367
 368                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 369                         ena_trc_err("bounce buffer memory allocation failed\n");
 370                         return ENA_COM_NO_MEM;
 371                 }
 372
 373                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 374                        sizeof(io_sq->llq_info));
 375
 376                 /* Initiate the first bounce buffer */
 377                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 378                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 379                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 380                        0x0, io_sq->llq_info.desc_list_entry_size);
 381                 io_sq->llq_buf_ctrl.descs_left_in_line =
 382                         io_sq->llq_info.descs_num_before_header;
 383                 io_sq->disable_meta_caching =
 384                         io_sq->llq_info.disable_meta_caching;
 385
 386                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 387                         io_sq->entries_in_tx_burst_left =
 388                                 io_sq->llq_info.max_entries_in_tx_burst;
 389         }
 390
 391         io_sq->tail = 0;
 392         io_sq->next_to_comp = 0;
 393         io_sq->phase = 1;
 394
 395         return 0;
 396 }
 397
 398 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 399                               struct ena_com_create_io_ctx *ctx,
 400                               struct ena_com_io_cq *io_cq)
 401 {
 402         size_t size;
 403         int prev_node = 0;
 404
 405         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 406
 407         /* Use the basic completion descriptor for Rx */
 408         io_cq->cdesc_entry_size_in_bytes =
 409                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 410                 sizeof(struct ena_eth_io_tx_cdesc) :
 411                 sizeof(struct ena_eth_io_rx_cdesc_base);
 412
 413         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 414         io_cq->bus = ena_dev->bus;
 415
 416         ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 417                         size,
 418                         io_cq->cdesc_addr.virt_addr,
 419                         io_cq->cdesc_addr.phys_addr,
 420                         io_cq->cdesc_addr.mem_handle,
 421                         ctx->numa_node,
 422                         prev_node);
 423         if (!io_cq->cdesc_addr.virt_addr) {
 424                 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 425                                        size,
 426                                        io_cq->cdesc_addr.virt_addr,
 427                                        io_cq->cdesc_addr.phys_addr,
 428                                        io_cq->cdesc_addr.mem_handle);
 429         }
 430
 431         if (!io_cq->cdesc_addr.virt_addr) {
 432                 ena_trc_err("memory allocation failed\n");
 433                 return ENA_COM_NO_MEM;
 434         }
 435
 436         io_cq->phase = 1;
 437         io_cq->head = 0;
 438
 439         return 0;
 440 }
 441
 442 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 443                                                    struct ena_admin_acq_entry *cqe)
 444 {
 445         struct ena_comp_ctx *comp_ctx;
 446         u16 cmd_id;
 447
 448         cmd_id = cqe->acq_common_descriptor.command &
 449                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 450
 451         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 452         if (unlikely(!comp_ctx)) {
 453                 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
 454                 admin_queue->running_state = false;
 455                 return;
 456         }
 457
 458         comp_ctx->status = ENA_CMD_COMPLETED;
 459         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 460
 461         if (comp_ctx->user_cqe)
 462                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 463
 464         if (!admin_queue->polling)
 465                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
 466 }
 467
 468 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 469 {
 470         struct ena_admin_acq_entry *cqe = NULL;
 471         u16 comp_num = 0;
 472         u16 head_masked;
 473         u8 phase;
 474
 475         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 476         phase = admin_queue->cq.phase;
 477
 478         cqe = &admin_queue->cq.entries[head_masked];
 479
 480         /* Go over all the completions */
 481         while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
 482                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 483                 /* Do not read the rest of the completion entry before the
 484                  * phase bit was validated
 485                  */
 486                 dma_rmb();
 487                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 488
 489                 head_masked++;
 490                 comp_num++;
 491                 if (unlikely(head_masked == admin_queue->q_depth)) {
 492                         head_masked = 0;
 493                         phase = !phase;
 494                 }
 495
 496                 cqe = &admin_queue->cq.entries[head_masked];
 497         }
 498
 499         admin_queue->cq.head += comp_num;
 500         admin_queue->cq.phase = phase;
 501         admin_queue->sq.head += comp_num;
 502         admin_queue->stats.completed_cmd += comp_num;
 503 }
 504
 505 static int ena_com_comp_status_to_errno(u8 comp_status)
 506 {
 507         if (unlikely(comp_status != 0))
 508                 ena_trc_err("admin command failed[%u]\n", comp_status);
 509
 510         switch (comp_status) {
 511         case ENA_ADMIN_SUCCESS:
 512                 return ENA_COM_OK;
 513         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 514                 return ENA_COM_NO_MEM;
 515         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 516                 return ENA_COM_UNSUPPORTED;
 517         case ENA_ADMIN_BAD_OPCODE:
 518         case ENA_ADMIN_MALFORMED_REQUEST:
 519         case ENA_ADMIN_ILLEGAL_PARAMETER:
 520         case ENA_ADMIN_UNKNOWN_ERROR:
 521                 return ENA_COM_INVAL;
 522         case ENA_ADMIN_RESOURCE_BUSY:
 523                 return ENA_COM_TRY_AGAIN;
 524         }
 525
 526         return ENA_COM_INVAL;
 527 }
 528
 529 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
 530 {
 531         delay_us = ENA_MAX32(ENA_MIN_ADMIN_POLL_US, delay_us);
 532         delay_us = ENA_MIN32(delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
 533         ENA_USLEEP(delay_us);
 534 }
 535
 536 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 537                                                      struct ena_com_admin_queue *admin_queue)
 538 {
 539         unsigned long flags = 0;
 540         ena_time_t timeout;
 541         int ret;
 542         u32 exp = 0;
 543
 544         timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
 545
 546         while (1) {
 547                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 548                 ena_com_handle_admin_completion(admin_queue);
 549                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 550
 551                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 552                         break;
 553
 554                 if (ENA_TIME_EXPIRE(timeout)) {
 555                         ena_trc_err("Wait for completion (polling) timeout\n");
 556                         /* ENA didn't have any completion */
 557                         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 558                         admin_queue->stats.no_completion++;
 559                         admin_queue->running_state = false;
 560                         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 561
 562                         ret = ENA_COM_TIMER_EXPIRED;
 563                         goto err;
 564                 }
 565
 566                 ena_delay_exponential_backoff_us(exp++,
 567                                                  admin_queue->ena_dev->ena_min_poll_delay_us);
 568         }
 569
 570         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 571                 ena_trc_err("Command was aborted\n");
 572                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 573                 admin_queue->stats.aborted_cmd++;
 574                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 575                 ret = ENA_COM_NO_DEVICE;
 576                 goto err;
 577         }
 578
 579         ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
 580                  "Invalid comp status %d\n", comp_ctx->status);
 581
 582         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 583 err:
 584         comp_ctxt_release(admin_queue, comp_ctx);
 585         return ret;
 586 }
 587
 588 /**
 589  * Set the LLQ configurations of the firmware
 590  *
 591  * The driver provides only the enabled feature values to the device,
 592  * which in turn, checks if they are supported.
 593  */
 594 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 595 {
 596         struct ena_com_admin_queue *admin_queue;
 597         struct ena_admin_set_feat_cmd cmd;
 598         struct ena_admin_set_feat_resp resp;
 599         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 600         int ret;
 601
 602         memset(&cmd, 0x0, sizeof(cmd));
 603         admin_queue = &ena_dev->admin_queue;
 604
 605         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 606         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 607
 608         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 609         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 610         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 611         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 612
 613         cmd.u.llq.accel_mode.u.set.enabled_flags =
 614                 BIT(ENA_ADMIN_DISABLE_META_CACHING) |
 615                 BIT(ENA_ADMIN_LIMIT_TX_BURST);
 616
 617         ret = ena_com_execute_admin_command(admin_queue,
 618                                             (struct ena_admin_aq_entry *)&cmd,
 619                                             sizeof(cmd),
 620                                             (struct ena_admin_acq_entry *)&resp,
 621                                             sizeof(resp));
 622
 623         if (unlikely(ret))
 624                 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
 625
 626         return ret;
 627 }
 628
 629 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 630                                    struct ena_admin_feature_llq_desc *llq_features,
 631                                    struct ena_llq_configurations *llq_default_cfg)
 632 {
 633         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 634         struct ena_admin_accel_mode_get llq_accel_mode_get;
 635         u16 supported_feat;
 636         int rc;
 637
 638         memset(llq_info, 0, sizeof(*llq_info));
 639
 640         supported_feat = llq_features->header_location_ctrl_supported;
 641
 642         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 643                 llq_info->header_location_ctrl =
 644                         llq_default_cfg->llq_header_location;
 645         } else {
 646                 ena_trc_err("Invalid header location control, supported: 0x%x\n",
 647                             supported_feat);
 648                 return -EINVAL;
 649         }
 650
 651         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 652                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 653                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 654                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 655                 } else  {
 656                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 657                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 658                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 659                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 660                         } else {
 661                                 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 662                                             supported_feat);
 663                                 return -EINVAL;
 664                         }
 665
 666                         ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 667                                     llq_default_cfg->llq_stride_ctrl,
 668                                     supported_feat,
 669                                     llq_info->desc_stride_ctrl);
 670                 }
 671         } else {
 672                 llq_info->desc_stride_ctrl = 0;
 673         }
 674
 675         supported_feat = llq_features->entry_size_ctrl_supported;
 676         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 677                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 678                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 679         } else {
 680                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 681                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 682                         llq_info->desc_list_entry_size = 128;
 683                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 684                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 685                         llq_info->desc_list_entry_size = 192;
 686                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 687                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 688                         llq_info->desc_list_entry_size = 256;
 689                 } else {
 690                         ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
 691                         return -EINVAL;
 692                 }
 693
 694                 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 695                             llq_default_cfg->llq_ring_entry_size,
 696                             supported_feat,
 697                             llq_info->desc_list_entry_size);
 698         }
 699         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 700                 /* The desc list entry size should be whole multiply of 8
 701                  * This requirement comes from __iowrite64_copy()
 702                  */
 703                 ena_trc_err("illegal entry size %d\n",
 704                             llq_info->desc_list_entry_size);
 705                 return -EINVAL;
 706         }
 707
 708         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 709                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 710                         sizeof(struct ena_eth_io_tx_desc);
 711         else
 712                 llq_info->descs_per_entry = 1;
 713
 714         supported_feat = llq_features->desc_num_before_header_supported;
 715         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 716                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 717         } else {
 718                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 719                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 720                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 721                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 722                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 723                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 724                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 725                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 726                 } else {
 727                         ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
 728                                     supported_feat);
 729                         return -EINVAL;
 730                 }
 731
 732                 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 733                             llq_default_cfg->llq_num_decs_before_header,
 734                             supported_feat,
 735                             llq_info->descs_num_before_header);
 736         }
 737         /* Check for accelerated queue supported */
 738         llq_accel_mode_get = llq_features->accel_mode.u.get;
 739
 740         llq_info->disable_meta_caching =
 741                 !!(llq_accel_mode_get.supported_flags &
 742                    BIT(ENA_ADMIN_DISABLE_META_CACHING));
 743
 744         if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
 745                 llq_info->max_entries_in_tx_burst =
 746                         llq_accel_mode_get.max_tx_burst_size /
 747                         llq_default_cfg->llq_ring_entry_size_value;
 748
 749         rc = ena_com_set_llq(ena_dev);
 750         if (rc)
 751                 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
 752
 753         return rc;
 754 }
 755
 756 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 757                                                         struct ena_com_admin_queue *admin_queue)
 758 {
 759         unsigned long flags = 0;
 760         int ret;
 761
 762         ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
 763                             admin_queue->completion_timeout);
 764
 765         /* In case the command wasn't completed find out the root cause.
 766          * There might be 2 kinds of errors
 767          * 1) No completion (timeout reached)
 768          * 2) There is completion but the device didn't get any msi-x interrupt.
 769          */
 770         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 771                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 772                 ena_com_handle_admin_completion(admin_queue);
 773                 admin_queue->stats.no_completion++;
 774                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 775
 776                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 777                         ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 778                                     comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
 779                         /* Check if fallback to polling is enabled */
 780                         if (admin_queue->auto_polling)
 781                                 admin_queue->polling = true;
 782                 } else {
 783                         ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 784                                     comp_ctx->cmd_opcode, comp_ctx->status);
 785                 }
 786                 /* Check if shifted to polling mode.
 787                  * This will happen if there is a completion without an interrupt
 788                  * and autopolling mode is enabled. Continuing normal execution in such case
 789                  */
 790                 if (!admin_queue->polling) {
 791                         admin_queue->running_state = false;
 792                         ret = ENA_COM_TIMER_EXPIRED;
 793                         goto err;
 794                 }
 795         }
 796
 797         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 798 err:
 799         comp_ctxt_release(admin_queue, comp_ctx);
 800         return ret;
 801 }
 802
 803 /* This method read the hardware device register through posting writes
 804  * and waiting for response
 805  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 806  */
 807 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 808 {
 809         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 810         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 811                 mmio_read->read_resp;
 812         u32 mmio_read_reg, ret, i;
 813         unsigned long flags = 0;
 814         u32 timeout = mmio_read->reg_read_to;
 815
 816         ENA_MIGHT_SLEEP();
 817
 818         if (timeout == 0)
 819                 timeout = ENA_REG_READ_TIMEOUT;
 820
 821         /* If readless is disabled, perform regular read */
 822         if (!mmio_read->readless_supported)
 823                 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
 824
 825         ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
 826         mmio_read->seq_num++;
 827
 828         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 829         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 830                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 831         mmio_read_reg |= mmio_read->seq_num &
 832                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 833
 834         ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
 835                         ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 836
 837         for (i = 0; i < timeout; i++) {
 838                 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
 839                         break;
 840
 841                 ENA_UDELAY(1);
 842         }
 843
 844         if (unlikely(i == timeout)) {
 845                 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 846                             mmio_read->seq_num,
 847                             offset,
 848                             read_resp->req_id,
 849                             read_resp->reg_off);
 850                 ret = ENA_MMIO_READ_TIMEOUT;
 851                 goto err;
 852         }
 853
 854         if (read_resp->reg_off != offset) {
 855                 ena_trc_err("Read failure: wrong offset provided\n");
 856                 ret = ENA_MMIO_READ_TIMEOUT;
 857         } else {
 858                 ret = read_resp->reg_val;
 859         }
 860 err:
 861         ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
 862
 863         return ret;
 864 }
 865
 866 /* There are two types to wait for completion.
 867  * Polling mode - wait until the completion is available.
 868  * Async mode - wait on wait queue until the completion is ready
 869  * (or the timeout expired).
 870  * It is expected that the IRQ called ena_com_handle_admin_completion
 871  * to mark the completions.
 872  */
 873 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 874                                              struct ena_com_admin_queue *admin_queue)
 875 {
 876         if (admin_queue->polling)
 877                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 878                                                                  admin_queue);
 879
 880         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 881                                                             admin_queue);
 882 }
 883
 884 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 885                                  struct ena_com_io_sq *io_sq)
 886 {
 887         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 888         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 889         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 890         u8 direction;
 891         int ret;
 892
 893         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 894
 895         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 896                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 897         else
 898                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 899
 900         destroy_cmd.sq.sq_identity |= (direction <<
 901                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 902                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 903
 904         destroy_cmd.sq.sq_idx = io_sq->idx;
 905         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 906
 907         ret = ena_com_execute_admin_command(admin_queue,
 908                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 909                                             sizeof(destroy_cmd),
 910                                             (struct ena_admin_acq_entry *)&destroy_resp,
 911                                             sizeof(destroy_resp));
 912
 913         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
 914                 ena_trc_err("failed to destroy io sq error: %d\n", ret);
 915
 916         return ret;
 917 }
 918
 919 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 920                                   struct ena_com_io_sq *io_sq,
 921                                   struct ena_com_io_cq *io_cq)
 922 {
 923         size_t size;
 924
 925         if (io_cq->cdesc_addr.virt_addr) {
 926                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 927
 928                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 929                                       size,
 930                                       io_cq->cdesc_addr.virt_addr,
 931                                       io_cq->cdesc_addr.phys_addr,
 932                                       io_cq->cdesc_addr.mem_handle);
 933
 934                 io_cq->cdesc_addr.virt_addr = NULL;
 935         }
 936
 937         if (io_sq->desc_addr.virt_addr) {
 938                 size = io_sq->desc_entry_size * io_sq->q_depth;
 939
 940                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 941                                       size,
 942                                       io_sq->desc_addr.virt_addr,
 943                                       io_sq->desc_addr.phys_addr,
 944                                       io_sq->desc_addr.mem_handle);
 945
 946                 io_sq->desc_addr.virt_addr = NULL;
 947         }
 948
 949         if (io_sq->bounce_buf_ctrl.base_buffer) {
 950                 ENA_MEM_FREE(ena_dev->dmadev,
 951                              io_sq->bounce_buf_ctrl.base_buffer,
 952                              (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
 953                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 954         }
 955 }
 956
 957 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 958                                 u16 exp_state)
 959 {
 960         u32 val, exp = 0;
 961         ena_time_t timeout_stamp;
 962
 963         /* Convert timeout from resolution of 100ms to us resolution. */
 964         timeout_stamp = ENA_GET_SYSTEM_TIMEOUT(100 * 1000 * timeout);
 965
 966         while (1) {
 967                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 968
 969                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 970                         ena_trc_err("Reg read timeout occurred\n");
 971                         return ENA_COM_TIMER_EXPIRED;
 972                 }
 973
 974                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 975                         exp_state)
 976                         return 0;
 977
 978                 if (ENA_TIME_EXPIRE(timeout_stamp))
 979                         return ENA_COM_TIMER_EXPIRED;
 980
 981                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
 982         }
 983 }
 984
 985 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 986                                                enum ena_admin_aq_feature_id feature_id)
 987 {
 988         u32 feature_mask = 1 << feature_id;
 989
 990         /* Device attributes is always supported */
 991         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 992             !(ena_dev->supported_features & feature_mask))
 993                 return false;
 994
 995         return true;
 996 }
 997
 998 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 999                                   struct ena_admin_get_feat_resp *get_resp,
1000                                   enum ena_admin_aq_feature_id feature_id,
1001                                   dma_addr_t control_buf_dma_addr,
1002                                   u32 control_buff_size,
1003                                   u8 feature_ver)
1004 {
1005         struct ena_com_admin_queue *admin_queue;
1006         struct ena_admin_get_feat_cmd get_cmd;
1007         int ret;
1008
1009         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1010                 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
1011                 return ENA_COM_UNSUPPORTED;
1012         }
1013
1014         memset(&get_cmd, 0x0, sizeof(get_cmd));
1015         admin_queue = &ena_dev->admin_queue;
1016
1017         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1018
1019         if (control_buff_size)
1020                 get_cmd.aq_common_descriptor.flags =
1021                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1022         else
1023                 get_cmd.aq_common_descriptor.flags = 0;
1024
1025         ret = ena_com_mem_addr_set(ena_dev,
1026                                    &get_cmd.control_buffer.address,
1027                                    control_buf_dma_addr);
1028         if (unlikely(ret)) {
1029                 ena_trc_err("memory address set failed\n");
1030                 return ret;
1031         }
1032
1033         get_cmd.control_buffer.length = control_buff_size;
1034         get_cmd.feat_common.feature_version = feature_ver;
1035         get_cmd.feat_common.feature_id = feature_id;
1036
1037         ret = ena_com_execute_admin_command(admin_queue,
1038                                             (struct ena_admin_aq_entry *)
1039                                             &get_cmd,
1040                                             sizeof(get_cmd),
1041                                             (struct ena_admin_acq_entry *)
1042                                             get_resp,
1043                                             sizeof(*get_resp));
1044
1045         if (unlikely(ret))
1046                 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1047                             feature_id, ret);
1048
1049         return ret;
1050 }
1051
1052 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1053                                struct ena_admin_get_feat_resp *get_resp,
1054                                enum ena_admin_aq_feature_id feature_id,
1055                                u8 feature_ver)
1056 {
1057         return ena_com_get_feature_ex(ena_dev,
1058                                       get_resp,
1059                                       feature_id,
1060                                       0,
1061                                       0,
1062                                       feature_ver);
1063 }
1064
1065 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1066 {
1067         return ena_dev->rss.hash_func;
1068 }
1069
1070 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1071 {
1072         struct ena_admin_feature_rss_flow_hash_control *hash_key =
1073                 (ena_dev->rss).hash_key;
1074
1075         ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1076         /* The key is stored in the device in uint32_t array
1077          * as well as the API requires the key to be passed in this
1078          * format. Thus the size of our array should be divided by 4
1079          */
1080         hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t);
1081 }
1082
1083 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1084 {
1085         struct ena_rss *rss = &ena_dev->rss;
1086
1087         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1088                                sizeof(*rss->hash_key),
1089                                rss->hash_key,
1090                                rss->hash_key_dma_addr,
1091                                rss->hash_key_mem_handle);
1092
1093         if (unlikely(!rss->hash_key))
1094                 return ENA_COM_NO_MEM;
1095
1096         return 0;
1097 }
1098
1099 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1100 {
1101         struct ena_rss *rss = &ena_dev->rss;
1102
1103         if (rss->hash_key)
1104                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1105                                       sizeof(*rss->hash_key),
1106                                       rss->hash_key,
1107                                       rss->hash_key_dma_addr,
1108                                       rss->hash_key_mem_handle);
1109         rss->hash_key = NULL;
1110 }
1111
1112 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1113 {
1114         struct ena_rss *rss = &ena_dev->rss;
1115
1116         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1117                                sizeof(*rss->hash_ctrl),
1118                                rss->hash_ctrl,
1119                                rss->hash_ctrl_dma_addr,
1120                                rss->hash_ctrl_mem_handle);
1121
1122         if (unlikely(!rss->hash_ctrl))
1123                 return ENA_COM_NO_MEM;
1124
1125         return 0;
1126 }
1127
1128 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1129 {
1130         struct ena_rss *rss = &ena_dev->rss;
1131
1132         if (rss->hash_ctrl)
1133                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1134                                       sizeof(*rss->hash_ctrl),
1135                                       rss->hash_ctrl,
1136                                       rss->hash_ctrl_dma_addr,
1137                                       rss->hash_ctrl_mem_handle);
1138         rss->hash_ctrl = NULL;
1139 }
1140
1141 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1142                                            u16 log_size)
1143 {
1144         struct ena_rss *rss = &ena_dev->rss;
1145         struct ena_admin_get_feat_resp get_resp;
1146         size_t tbl_size;
1147         int ret;
1148
1149         ret = ena_com_get_feature(ena_dev, &get_resp,
1150                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1151         if (unlikely(ret))
1152                 return ret;
1153
1154         if ((get_resp.u.ind_table.min_size > log_size) ||
1155             (get_resp.u.ind_table.max_size < log_size)) {
1156                 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1157                             1 << log_size,
1158                             1 << get_resp.u.ind_table.min_size,
1159                             1 << get_resp.u.ind_table.max_size);
1160                 return ENA_COM_INVAL;
1161         }
1162
1163         tbl_size = (1ULL << log_size) *
1164                 sizeof(struct ena_admin_rss_ind_table_entry);
1165
1166         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1167                              tbl_size,
1168                              rss->rss_ind_tbl,
1169                              rss->rss_ind_tbl_dma_addr,
1170                              rss->rss_ind_tbl_mem_handle);
1171         if (unlikely(!rss->rss_ind_tbl))
1172                 goto mem_err1;
1173
1174         tbl_size = (1ULL << log_size) * sizeof(u16);
1175         rss->host_rss_ind_tbl =
1176                 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1177         if (unlikely(!rss->host_rss_ind_tbl))
1178                 goto mem_err2;
1179
1180         rss->tbl_log_size = log_size;
1181
1182         return 0;
1183
1184 mem_err2:
1185         tbl_size = (1ULL << log_size) *
1186                 sizeof(struct ena_admin_rss_ind_table_entry);
1187
1188         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1189                               tbl_size,
1190                               rss->rss_ind_tbl,
1191                               rss->rss_ind_tbl_dma_addr,
1192                               rss->rss_ind_tbl_mem_handle);
1193         rss->rss_ind_tbl = NULL;
1194 mem_err1:
1195         rss->tbl_log_size = 0;
1196         return ENA_COM_NO_MEM;
1197 }
1198
1199 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1200 {
1201         struct ena_rss *rss = &ena_dev->rss;
1202         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1203                 sizeof(struct ena_admin_rss_ind_table_entry);
1204
1205         if (rss->rss_ind_tbl)
1206                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1207                                       tbl_size,
1208                                       rss->rss_ind_tbl,
1209                                       rss->rss_ind_tbl_dma_addr,
1210                                       rss->rss_ind_tbl_mem_handle);
1211         rss->rss_ind_tbl = NULL;
1212
1213         if (rss->host_rss_ind_tbl)
1214                 ENA_MEM_FREE(ena_dev->dmadev,
1215                              rss->host_rss_ind_tbl,
1216                              ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1217         rss->host_rss_ind_tbl = NULL;
1218 }
1219
1220 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1221                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1222 {
1223         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1224         struct ena_admin_aq_create_sq_cmd create_cmd;
1225         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1226         u8 direction;
1227         int ret;
1228
1229         memset(&create_cmd, 0x0, sizeof(create_cmd));
1230
1231         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1232
1233         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1234                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1235         else
1236                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1237
1238         create_cmd.sq_identity |= (direction <<
1239                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1240                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1241
1242         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1243                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1244
1245         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1246                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1247                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1248
1249         create_cmd.sq_caps_3 |=
1250                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1251
1252         create_cmd.cq_idx = cq_idx;
1253         create_cmd.sq_depth = io_sq->q_depth;
1254
1255         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1256                 ret = ena_com_mem_addr_set(ena_dev,
1257                                            &create_cmd.sq_ba,
1258                                            io_sq->desc_addr.phys_addr);
1259                 if (unlikely(ret)) {
1260                         ena_trc_err("memory address set failed\n");
1261                         return ret;
1262                 }
1263         }
1264
1265         ret = ena_com_execute_admin_command(admin_queue,
1266                                             (struct ena_admin_aq_entry *)&create_cmd,
1267                                             sizeof(create_cmd),
1268                                             (struct ena_admin_acq_entry *)&cmd_completion,
1269                                             sizeof(cmd_completion));
1270         if (unlikely(ret)) {
1271                 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1272                 return ret;
1273         }
1274
1275         io_sq->idx = cmd_completion.sq_idx;
1276
1277         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1278                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1279
1280         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1281                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1282                                 + cmd_completion.llq_headers_offset);
1283
1284                 io_sq->desc_addr.pbuf_dev_addr =
1285                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1286                         cmd_completion.llq_descriptors_offset);
1287         }
1288
1289         ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1290
1291         return ret;
1292 }
1293
1294 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1295 {
1296         struct ena_rss *rss = &ena_dev->rss;
1297         struct ena_com_io_sq *io_sq;
1298         u16 qid;
1299         int i;
1300
1301         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1302                 qid = rss->host_rss_ind_tbl[i];
1303                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1304                         return ENA_COM_INVAL;
1305
1306                 io_sq = &ena_dev->io_sq_queues[qid];
1307
1308                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1309                         return ENA_COM_INVAL;
1310
1311                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1318                                                  u16 intr_delay_resolution)
1319 {
1320         u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1321
1322         if (unlikely(!intr_delay_resolution)) {
1323                 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1324                 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1325         }
1326
1327         /* update Rx */
1328         ena_dev->intr_moder_rx_interval =
1329                 ena_dev->intr_moder_rx_interval *
1330                 prev_intr_delay_resolution /
1331                 intr_delay_resolution;
1332
1333         /* update Tx */
1334         ena_dev->intr_moder_tx_interval =
1335                 ena_dev->intr_moder_tx_interval *
1336                 prev_intr_delay_resolution /
1337                 intr_delay_resolution;
1338
1339         ena_dev->intr_delay_resolution = intr_delay_resolution;
1340 }
1341
1342 /*****************************************************************************/
1343 /*******************************      API       ******************************/
1344 /*****************************************************************************/
1345
1346 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1347                                   struct ena_admin_aq_entry *cmd,
1348                                   size_t cmd_size,
1349                                   struct ena_admin_acq_entry *comp,
1350                                   size_t comp_size)
1351 {
1352         struct ena_comp_ctx *comp_ctx;
1353         int ret;
1354
1355         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1356                                             comp, comp_size);
1357         if (IS_ERR(comp_ctx)) {
1358                 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1359                         ena_trc_dbg("Failed to submit command [%ld]\n",
1360                                     PTR_ERR(comp_ctx));
1361                 else
1362                         ena_trc_err("Failed to submit command [%ld]\n",
1363                                     PTR_ERR(comp_ctx));
1364
1365                 return PTR_ERR(comp_ctx);
1366         }
1367
1368         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1369         if (unlikely(ret)) {
1370                 if (admin_queue->running_state)
1371                         ena_trc_err("Failed to process command. ret = %d\n",
1372                                     ret);
1373                 else
1374                         ena_trc_dbg("Failed to process command. ret = %d\n",
1375                                     ret);
1376         }
1377         return ret;
1378 }
1379
1380 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1381                          struct ena_com_io_cq *io_cq)
1382 {
1383         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1384         struct ena_admin_aq_create_cq_cmd create_cmd;
1385         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1386         int ret;
1387
1388         memset(&create_cmd, 0x0, sizeof(create_cmd));
1389
1390         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1391
1392         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1393                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1394         create_cmd.cq_caps_1 |=
1395                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1396
1397         create_cmd.msix_vector = io_cq->msix_vector;
1398         create_cmd.cq_depth = io_cq->q_depth;
1399
1400         ret = ena_com_mem_addr_set(ena_dev,
1401                                    &create_cmd.cq_ba,
1402                                    io_cq->cdesc_addr.phys_addr);
1403         if (unlikely(ret)) {
1404                 ena_trc_err("memory address set failed\n");
1405                 return ret;
1406         }
1407
1408         ret = ena_com_execute_admin_command(admin_queue,
1409                                             (struct ena_admin_aq_entry *)&create_cmd,
1410                                             sizeof(create_cmd),
1411                                             (struct ena_admin_acq_entry *)&cmd_completion,
1412                                             sizeof(cmd_completion));
1413         if (unlikely(ret)) {
1414                 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1415                 return ret;
1416         }
1417
1418         io_cq->idx = cmd_completion.cq_idx;
1419
1420         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1421                 cmd_completion.cq_interrupt_unmask_register_offset);
1422
1423         if (cmd_completion.cq_head_db_register_offset)
1424                 io_cq->cq_head_db_reg =
1425                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1426                         cmd_completion.cq_head_db_register_offset);
1427
1428         if (cmd_completion.numa_node_register_offset)
1429                 io_cq->numa_node_cfg_reg =
1430                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1431                         cmd_completion.numa_node_register_offset);
1432
1433         ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1434
1435         return ret;
1436 }
1437
1438 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1439                             struct ena_com_io_sq **io_sq,
1440                             struct ena_com_io_cq **io_cq)
1441 {
1442         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1443                 ena_trc_err("Invalid queue number %d but the max is %d\n",
1444                             qid, ENA_TOTAL_NUM_QUEUES);
1445                 return ENA_COM_INVAL;
1446         }
1447
1448         *io_sq = &ena_dev->io_sq_queues[qid];
1449         *io_cq = &ena_dev->io_cq_queues[qid];
1450
1451         return 0;
1452 }
1453
1454 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1455 {
1456         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1457         struct ena_comp_ctx *comp_ctx;
1458         u16 i;
1459
1460         if (!admin_queue->comp_ctx)
1461                 return;
1462
1463         for (i = 0; i < admin_queue->q_depth; i++) {
1464                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1465                 if (unlikely(!comp_ctx))
1466                         break;
1467
1468                 comp_ctx->status = ENA_CMD_ABORTED;
1469
1470                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1471         }
1472 }
1473
1474 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1475 {
1476         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1477         unsigned long flags = 0;
1478         u32 exp = 0;
1479
1480         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1481         while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1482                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1483                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1484                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1485         }
1486         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1487 }
1488
1489 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1490                           struct ena_com_io_cq *io_cq)
1491 {
1492         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1493         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1494         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1495         int ret;
1496
1497         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1498
1499         destroy_cmd.cq_idx = io_cq->idx;
1500         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1501
1502         ret = ena_com_execute_admin_command(admin_queue,
1503                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1504                                             sizeof(destroy_cmd),
1505                                             (struct ena_admin_acq_entry *)&destroy_resp,
1506                                             sizeof(destroy_resp));
1507
1508         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1509                 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1510
1511         return ret;
1512 }
1513
1514 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1515 {
1516         return ena_dev->admin_queue.running_state;
1517 }
1518
1519 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1520 {
1521         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1522         unsigned long flags = 0;
1523
1524         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1525         ena_dev->admin_queue.running_state = state;
1526         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1527 }
1528
1529 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1530 {
1531         u16 depth = ena_dev->aenq.q_depth;
1532
1533         ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1534
1535         /* Init head_db to mark that all entries in the queue
1536          * are initially available
1537          */
1538         ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1539 }
1540
1541 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1542 {
1543         struct ena_com_admin_queue *admin_queue;
1544         struct ena_admin_set_feat_cmd cmd;
1545         struct ena_admin_set_feat_resp resp;
1546         struct ena_admin_get_feat_resp get_resp;
1547         int ret;
1548
1549         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1550         if (ret) {
1551                 ena_trc_info("Can't get aenq configuration\n");
1552                 return ret;
1553         }
1554
1555         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1556                 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1557                              get_resp.u.aenq.supported_groups,
1558                              groups_flag);
1559                 return ENA_COM_UNSUPPORTED;
1560         }
1561
1562         memset(&cmd, 0x0, sizeof(cmd));
1563         admin_queue = &ena_dev->admin_queue;
1564
1565         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1566         cmd.aq_common_descriptor.flags = 0;
1567         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1568         cmd.u.aenq.enabled_groups = groups_flag;
1569
1570         ret = ena_com_execute_admin_command(admin_queue,
1571                                             (struct ena_admin_aq_entry *)&cmd,
1572                                             sizeof(cmd),
1573                                             (struct ena_admin_acq_entry *)&resp,
1574                                             sizeof(resp));
1575
1576         if (unlikely(ret))
1577                 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1578
1579         return ret;
1580 }
1581
1582 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1583 {
1584         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1585         int width;
1586
1587         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1588                 ena_trc_err("Reg read timeout occurred\n");
1589                 return ENA_COM_TIMER_EXPIRED;
1590         }
1591
1592         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1593                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1594
1595         ena_trc_dbg("ENA dma width: %d\n", width);
1596
1597         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1598                 ena_trc_err("DMA width illegal value: %d\n", width);
1599                 return ENA_COM_INVAL;
1600         }
1601
1602         ena_dev->dma_addr_bits = width;
1603
1604         return width;
1605 }
1606
1607 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1608 {
1609         u32 ver;
1610         u32 ctrl_ver;
1611         u32 ctrl_ver_masked;
1612
1613         /* Make sure the ENA version and the controller version are at least
1614          * as the driver expects
1615          */
1616         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1617         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1618                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1619
1620         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1621                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1622                 ena_trc_err("Reg read timeout occurred\n");
1623                 return ENA_COM_TIMER_EXPIRED;
1624         }
1625
1626         ena_trc_info("ena device version: %d.%d\n",
1627                      (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1628                      ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1629                      ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1630
1631         ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1632                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1633                      >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1634                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1635                      >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1636                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1637                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1638                      ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1639
1640         ctrl_ver_masked =
1641                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1642                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1643                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1644
1645         /* Validate the ctrl version without the implementation ID */
1646         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1647                 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1648                 return -1;
1649         }
1650
1651         return 0;
1652 }
1653
1654 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1655 {
1656         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1657         struct ena_com_admin_cq *cq = &admin_queue->cq;
1658         struct ena_com_admin_sq *sq = &admin_queue->sq;
1659         struct ena_com_aenq *aenq = &ena_dev->aenq;
1660         u16 size;
1661
1662         if (admin_queue->comp_ctx) {
1663                 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1664                 ENA_MEM_FREE(ena_dev->dmadev,
1665                              admin_queue->comp_ctx,
1666                              (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1667         }
1668
1669         admin_queue->comp_ctx = NULL;
1670         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1671         if (sq->entries)
1672                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1673                                       sq->dma_addr, sq->mem_handle);
1674         sq->entries = NULL;
1675
1676         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1677         if (cq->entries)
1678                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1679                                       cq->dma_addr, cq->mem_handle);
1680         cq->entries = NULL;
1681
1682         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1683         if (ena_dev->aenq.entries)
1684                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1685                                       aenq->dma_addr, aenq->mem_handle);
1686         aenq->entries = NULL;
1687         ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1688 }
1689
1690 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1691 {
1692         u32 mask_value = 0;
1693
1694         if (polling)
1695                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1696
1697         ENA_REG_WRITE32(ena_dev->bus, mask_value,
1698                         ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1699         ena_dev->admin_queue.polling = polling;
1700 }
1701
1702 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1703 {
1704         return ena_dev->admin_queue.polling;
1705 }
1706
1707 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1708                                          bool polling)
1709 {
1710         ena_dev->admin_queue.auto_polling = polling;
1711 }
1712
1713 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1714 {
1715         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1716
1717         ENA_SPINLOCK_INIT(mmio_read->lock);
1718         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1719                                sizeof(*mmio_read->read_resp),
1720                                mmio_read->read_resp,
1721                                mmio_read->read_resp_dma_addr,
1722                                mmio_read->read_resp_mem_handle);
1723         if (unlikely(!mmio_read->read_resp))
1724                 goto err;
1725
1726         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1727
1728         mmio_read->read_resp->req_id = 0x0;
1729         mmio_read->seq_num = 0x0;
1730         mmio_read->readless_supported = true;
1731
1732         return 0;
1733
1734 err:
1735                 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1736                 return ENA_COM_NO_MEM;
1737 }
1738
1739 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1740 {
1741         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1742
1743         mmio_read->readless_supported = readless_supported;
1744 }
1745
1746 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1747 {
1748         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1749
1750         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1751         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1752
1753         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1754                               sizeof(*mmio_read->read_resp),
1755                               mmio_read->read_resp,
1756                               mmio_read->read_resp_dma_addr,
1757                               mmio_read->read_resp_mem_handle);
1758
1759         mmio_read->read_resp = NULL;
1760         ENA_SPINLOCK_DESTROY(mmio_read->lock);
1761 }
1762
1763 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1764 {
1765         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1766         u32 addr_low, addr_high;
1767
1768         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1769         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1770
1771         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1772         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1773 }
1774
1775 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1776                        struct ena_aenq_handlers *aenq_handlers)
1777 {
1778         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1779         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1780         int ret;
1781
1782         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1783
1784         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1785                 ena_trc_err("Reg read timeout occurred\n");
1786                 return ENA_COM_TIMER_EXPIRED;
1787         }
1788
1789         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1790                 ena_trc_err("Device isn't ready, abort com init\n");
1791                 return ENA_COM_NO_DEVICE;
1792         }
1793
1794         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1795
1796         admin_queue->bus = ena_dev->bus;
1797         admin_queue->q_dmadev = ena_dev->dmadev;
1798         admin_queue->polling = false;
1799         admin_queue->curr_cmd_id = 0;
1800
1801         ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1802
1803         ENA_SPINLOCK_INIT(admin_queue->q_lock);
1804
1805         ret = ena_com_init_comp_ctxt(admin_queue);
1806         if (ret)
1807                 goto error;
1808
1809         ret = ena_com_admin_init_sq(admin_queue);
1810         if (ret)
1811                 goto error;
1812
1813         ret = ena_com_admin_init_cq(admin_queue);
1814         if (ret)
1815                 goto error;
1816
1817         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1818                 ENA_REGS_AQ_DB_OFF);
1819
1820         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1821         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1822
1823         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1824         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1825
1826         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1827         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1828
1829         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1830         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1831
1832         aq_caps = 0;
1833         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1834         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1835                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1836                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1837
1838         acq_caps = 0;
1839         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1840         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1841                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1842                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1843
1844         ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1845         ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1846         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1847         if (ret)
1848                 goto error;
1849
1850         admin_queue->ena_dev = ena_dev;
1851         admin_queue->running_state = true;
1852
1853         return 0;
1854 error:
1855         ena_com_admin_destroy(ena_dev);
1856
1857         return ret;
1858 }
1859
1860 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1861                             struct ena_com_create_io_ctx *ctx)
1862 {
1863         struct ena_com_io_sq *io_sq;
1864         struct ena_com_io_cq *io_cq;
1865         int ret;
1866
1867         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1868                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1869                             ctx->qid, ENA_TOTAL_NUM_QUEUES);
1870                 return ENA_COM_INVAL;
1871         }
1872
1873         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1874         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1875
1876         memset(io_sq, 0x0, sizeof(*io_sq));
1877         memset(io_cq, 0x0, sizeof(*io_cq));
1878
1879         /* Init CQ */
1880         io_cq->q_depth = ctx->queue_size;
1881         io_cq->direction = ctx->direction;
1882         io_cq->qid = ctx->qid;
1883
1884         io_cq->msix_vector = ctx->msix_vector;
1885
1886         io_sq->q_depth = ctx->queue_size;
1887         io_sq->direction = ctx->direction;
1888         io_sq->qid = ctx->qid;
1889
1890         io_sq->mem_queue_type = ctx->mem_queue_type;
1891
1892         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1893                 /* header length is limited to 8 bits */
1894                 io_sq->tx_max_header_size =
1895                         ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1896
1897         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1898         if (ret)
1899                 goto error;
1900         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1901         if (ret)
1902                 goto error;
1903
1904         ret = ena_com_create_io_cq(ena_dev, io_cq);
1905         if (ret)
1906                 goto error;
1907
1908         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1909         if (ret)
1910                 goto destroy_io_cq;
1911
1912         return 0;
1913
1914 destroy_io_cq:
1915         ena_com_destroy_io_cq(ena_dev, io_cq);
1916 error:
1917         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1918         return ret;
1919 }
1920
1921 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1922 {
1923         struct ena_com_io_sq *io_sq;
1924         struct ena_com_io_cq *io_cq;
1925
1926         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1927                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1928                             qid, ENA_TOTAL_NUM_QUEUES);
1929                 return;
1930         }
1931
1932         io_sq = &ena_dev->io_sq_queues[qid];
1933         io_cq = &ena_dev->io_cq_queues[qid];
1934
1935         ena_com_destroy_io_sq(ena_dev, io_sq);
1936         ena_com_destroy_io_cq(ena_dev, io_cq);
1937
1938         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1939 }
1940
1941 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1942                             struct ena_admin_get_feat_resp *resp)
1943 {
1944         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1945 }
1946
1947 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1948                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1949 {
1950         struct ena_admin_get_feat_resp get_resp;
1951         int rc;
1952
1953         rc = ena_com_get_feature(ena_dev, &get_resp,
1954                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1955         if (rc)
1956                 return rc;
1957
1958         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1959                sizeof(get_resp.u.dev_attr));
1960         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1961
1962         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1963                 rc = ena_com_get_feature(ena_dev, &get_resp,
1964                                          ENA_ADMIN_MAX_QUEUES_EXT,
1965                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
1966                 if (rc)
1967                         return rc;
1968
1969                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1970                         return -EINVAL;
1971
1972                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1973                        sizeof(get_resp.u.max_queue_ext));
1974                 ena_dev->tx_max_header_size =
1975                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1976         } else {
1977                 rc = ena_com_get_feature(ena_dev, &get_resp,
1978                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
1979                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1980                        sizeof(get_resp.u.max_queue));
1981                 ena_dev->tx_max_header_size =
1982                         get_resp.u.max_queue.max_header_size;
1983
1984                 if (rc)
1985                         return rc;
1986         }
1987
1988         rc = ena_com_get_feature(ena_dev, &get_resp,
1989                                  ENA_ADMIN_AENQ_CONFIG, 0);
1990         if (rc)
1991                 return rc;
1992
1993         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1994                sizeof(get_resp.u.aenq));
1995
1996         rc = ena_com_get_feature(ena_dev, &get_resp,
1997                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1998         if (rc)
1999                 return rc;
2000
2001         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
2002                sizeof(get_resp.u.offload));
2003
2004         /* Driver hints isn't mandatory admin command. So in case the
2005          * command isn't supported set driver hints to 0
2006          */
2007         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2008
2009         if (!rc)
2010                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2011                        sizeof(get_resp.u.hw_hints));
2012         else if (rc == ENA_COM_UNSUPPORTED)
2013                 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2014         else
2015                 return rc;
2016
2017         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2018         if (!rc)
2019                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2020                        sizeof(get_resp.u.llq));
2021         else if (rc == ENA_COM_UNSUPPORTED)
2022                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2023         else
2024                 return rc;
2025
2026         rc = ena_com_get_feature(ena_dev, &get_resp,
2027                                  ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2028         if (!rc)
2029                 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2030                        sizeof(get_resp.u.ind_table));
2031         else if (rc == ENA_COM_UNSUPPORTED)
2032                 memset(&get_feat_ctx->ind_table, 0x0,
2033                        sizeof(get_feat_ctx->ind_table));
2034         else
2035                 return rc;
2036
2037         return 0;
2038 }
2039
2040 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2041 {
2042         ena_com_handle_admin_completion(&ena_dev->admin_queue);
2043 }
2044
2045 /* ena_handle_specific_aenq_event:
2046  * return the handler that is relevant to the specific event group
2047  */
2048 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2049                                                      u16 group)
2050 {
2051         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2052
2053         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2054                 return aenq_handlers->handlers[group];
2055
2056         return aenq_handlers->unimplemented_handler;
2057 }
2058
2059 /* ena_aenq_intr_handler:
2060  * handles the aenq incoming events.
2061  * pop events from the queue and apply the specific handler
2062  */
2063 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2064 {
2065         struct ena_admin_aenq_entry *aenq_e;
2066         struct ena_admin_aenq_common_desc *aenq_common;
2067         struct ena_com_aenq *aenq  = &dev->aenq;
2068         u64 timestamp;
2069         ena_aenq_handler handler_cb;
2070         u16 masked_head, processed = 0;
2071         u8 phase;
2072
2073         masked_head = aenq->head & (aenq->q_depth - 1);
2074         phase = aenq->phase;
2075         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2076         aenq_common = &aenq_e->aenq_common_desc;
2077
2078         /* Go over all the events */
2079         while ((READ_ONCE8(aenq_common->flags) &
2080                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2081                 /* Make sure the phase bit (ownership) is as expected before
2082                  * reading the rest of the descriptor.
2083                  */
2084                 dma_rmb();
2085
2086                 timestamp = (u64)aenq_common->timestamp_low |
2087                         ((u64)aenq_common->timestamp_high << 32);
2088                 ENA_TOUCH(timestamp); /* In case debug is disabled */
2089                 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2090                             aenq_common->group,
2091                             aenq_common->syndrom,
2092                             timestamp);
2093
2094                 /* Handle specific event*/
2095                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2096                                                           aenq_common->group);
2097                 handler_cb(data, aenq_e); /* call the actual event handler*/
2098
2099                 /* Get next event entry */
2100                 masked_head++;
2101                 processed++;
2102
2103                 if (unlikely(masked_head == aenq->q_depth)) {
2104                         masked_head = 0;
2105                         phase = !phase;
2106                 }
2107                 aenq_e = &aenq->entries[masked_head];
2108                 aenq_common = &aenq_e->aenq_common_desc;
2109         }
2110
2111         aenq->head += processed;
2112         aenq->phase = phase;
2113
2114         /* Don't update aenq doorbell if there weren't any processed events */
2115         if (!processed)
2116                 return;
2117
2118         /* write the aenq doorbell after all AENQ descriptors were read */
2119         mb();
2120         ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2121                                 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2122         mmiowb();
2123 }
2124
2125 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2126                       enum ena_regs_reset_reason_types reset_reason)
2127 {
2128         u32 stat, timeout, cap, reset_val;
2129         int rc;
2130
2131         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2132         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2133
2134         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2135                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2136                 ena_trc_err("Reg read32 timeout occurred\n");
2137                 return ENA_COM_TIMER_EXPIRED;
2138         }
2139
2140         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2141                 ena_trc_err("Device isn't ready, can't reset device\n");
2142                 return ENA_COM_INVAL;
2143         }
2144
2145         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2146                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2147         if (timeout == 0) {
2148                 ena_trc_err("Invalid timeout value\n");
2149                 return ENA_COM_INVAL;
2150         }
2151
2152         /* start reset */
2153         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2154         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2155                         ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2156         ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2157
2158         /* Write again the MMIO read request address */
2159         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2160
2161         rc = wait_for_reset_state(ena_dev, timeout,
2162                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2163         if (rc != 0) {
2164                 ena_trc_err("Reset indication didn't turn on\n");
2165                 return rc;
2166         }
2167
2168         /* reset done */
2169         ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2170         rc = wait_for_reset_state(ena_dev, timeout, 0);
2171         if (rc != 0) {
2172                 ena_trc_err("Reset indication didn't turn off\n");
2173                 return rc;
2174         }
2175
2176         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2177                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2178         if (timeout)
2179                 /* the resolution of timeout reg is 100ms */
2180                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2181         else
2182                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2183
2184         return 0;
2185 }
2186
2187 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2188                              struct ena_com_stats_ctx *ctx,
2189                              enum ena_admin_get_stats_type type)
2190 {
2191         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2192         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2193         struct ena_com_admin_queue *admin_queue;
2194         int ret;
2195
2196         admin_queue = &ena_dev->admin_queue;
2197
2198         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2199         get_cmd->aq_common_descriptor.flags = 0;
2200         get_cmd->type = type;
2201
2202         ret =  ena_com_execute_admin_command(admin_queue,
2203                                              (struct ena_admin_aq_entry *)get_cmd,
2204                                              sizeof(*get_cmd),
2205                                              (struct ena_admin_acq_entry *)get_resp,
2206                                              sizeof(*get_resp));
2207
2208         if (unlikely(ret))
2209                 ena_trc_err("Failed to get stats. error: %d\n", ret);
2210
2211         return ret;
2212 }
2213
2214 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
2215                           struct ena_admin_eni_stats *stats)
2216 {
2217         struct ena_com_stats_ctx ctx;
2218         int ret;
2219
2220         memset(&ctx, 0x0, sizeof(ctx));
2221         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
2222         if (likely(ret == 0))
2223                 memcpy(stats, &ctx.get_resp.u.eni_stats,
2224                        sizeof(ctx.get_resp.u.eni_stats));
2225
2226         return ret;
2227 }
2228
2229 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2230                                 struct ena_admin_basic_stats *stats)
2231 {
2232         struct ena_com_stats_ctx ctx;
2233         int ret;
2234
2235         memset(&ctx, 0x0, sizeof(ctx));
2236         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2237         if (likely(ret == 0))
2238                 memcpy(stats, &ctx.get_resp.u.basic_stats,
2239                        sizeof(ctx.get_resp.u.basic_stats));
2240
2241         return ret;
2242 }
2243
2244 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2245 {
2246         struct ena_com_admin_queue *admin_queue;
2247         struct ena_admin_set_feat_cmd cmd;
2248         struct ena_admin_set_feat_resp resp;
2249         int ret;
2250
2251         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2252                 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2253                 return ENA_COM_UNSUPPORTED;
2254         }
2255
2256         memset(&cmd, 0x0, sizeof(cmd));
2257         admin_queue = &ena_dev->admin_queue;
2258
2259         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2260         cmd.aq_common_descriptor.flags = 0;
2261         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2262         cmd.u.mtu.mtu = mtu;
2263
2264         ret = ena_com_execute_admin_command(admin_queue,
2265                                             (struct ena_admin_aq_entry *)&cmd,
2266                                             sizeof(cmd),
2267                                             (struct ena_admin_acq_entry *)&resp,
2268                                             sizeof(resp));
2269
2270         if (unlikely(ret))
2271                 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2272
2273         return ret;
2274 }
2275
2276 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2277                                  struct ena_admin_feature_offload_desc *offload)
2278 {
2279         int ret;
2280         struct ena_admin_get_feat_resp resp;
2281
2282         ret = ena_com_get_feature(ena_dev, &resp,
2283                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2284         if (unlikely(ret)) {
2285                 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2286                 return ret;
2287         }
2288
2289         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2290
2291         return 0;
2292 }
2293
2294 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2295 {
2296         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2297         struct ena_rss *rss = &ena_dev->rss;
2298         struct ena_admin_set_feat_cmd cmd;
2299         struct ena_admin_set_feat_resp resp;
2300         struct ena_admin_get_feat_resp get_resp;
2301         int ret;
2302
2303         if (!ena_com_check_supported_feature_id(ena_dev,
2304                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2305                 ena_trc_dbg("Feature %d isn't supported\n",
2306                             ENA_ADMIN_RSS_HASH_FUNCTION);
2307                 return ENA_COM_UNSUPPORTED;
2308         }
2309
2310         /* Validate hash function is supported */
2311         ret = ena_com_get_feature(ena_dev, &get_resp,
2312                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2313         if (unlikely(ret))
2314                 return ret;
2315
2316         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2317                 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2318                             rss->hash_func);
2319                 return ENA_COM_UNSUPPORTED;
2320         }
2321
2322         memset(&cmd, 0x0, sizeof(cmd));
2323
2324         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2325         cmd.aq_common_descriptor.flags =
2326                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2327         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2328         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2329         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2330
2331         ret = ena_com_mem_addr_set(ena_dev,
2332                                    &cmd.control_buffer.address,
2333                                    rss->hash_key_dma_addr);
2334         if (unlikely(ret)) {
2335                 ena_trc_err("memory address set failed\n");
2336                 return ret;
2337         }
2338
2339         cmd.control_buffer.length = sizeof(*rss->hash_key);
2340
2341         ret = ena_com_execute_admin_command(admin_queue,
2342                                             (struct ena_admin_aq_entry *)&cmd,
2343                                             sizeof(cmd),
2344                                             (struct ena_admin_acq_entry *)&resp,
2345                                             sizeof(resp));
2346         if (unlikely(ret)) {
2347                 ena_trc_err("Failed to set hash function %d. error: %d\n",
2348                             rss->hash_func, ret);
2349                 return ENA_COM_INVAL;
2350         }
2351
2352         return 0;
2353 }
2354
2355 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2356                                enum ena_admin_hash_functions func,
2357                                const u8 *key, u16 key_len, u32 init_val)
2358 {
2359         struct ena_admin_feature_rss_flow_hash_control *hash_key;
2360         struct ena_admin_get_feat_resp get_resp;
2361         enum ena_admin_hash_functions old_func;
2362         struct ena_rss *rss = &ena_dev->rss;
2363         int rc;
2364
2365         hash_key = rss->hash_key;
2366
2367         /* Make sure size is a mult of DWs */
2368         if (unlikely(key_len & 0x3))
2369                 return ENA_COM_INVAL;
2370
2371         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2372                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2373                                     rss->hash_key_dma_addr,
2374                                     sizeof(*rss->hash_key), 0);
2375         if (unlikely(rc))
2376                 return rc;
2377
2378         if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2379                 ena_trc_err("Flow hash function %d isn't supported\n", func);
2380                 return ENA_COM_UNSUPPORTED;
2381         }
2382
2383         switch (func) {
2384         case ENA_ADMIN_TOEPLITZ:
2385                 if (key) {
2386                         if (key_len != sizeof(hash_key->key)) {
2387                                 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2388                                              key_len, sizeof(hash_key->key));
2389                                 return ENA_COM_INVAL;
2390                         }
2391                         memcpy(hash_key->key, key, key_len);
2392                         rss->hash_init_val = init_val;
2393                         hash_key->keys_num = key_len / sizeof(u32);
2394                 }
2395                 break;
2396         case ENA_ADMIN_CRC32:
2397                 rss->hash_init_val = init_val;
2398                 break;
2399         default:
2400                 ena_trc_err("Invalid hash function (%d)\n", func);
2401                 return ENA_COM_INVAL;
2402         }
2403
2404         old_func = rss->hash_func;
2405         rss->hash_func = func;
2406         rc = ena_com_set_hash_function(ena_dev);
2407
2408         /* Restore the old function */
2409         if (unlikely(rc))
2410                 rss->hash_func = old_func;
2411
2412         return rc;
2413 }
2414
2415 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2416                               enum ena_admin_hash_functions *func)
2417 {
2418         struct ena_rss *rss = &ena_dev->rss;
2419         struct ena_admin_get_feat_resp get_resp;
2420         int rc;
2421
2422         if (unlikely(!func))
2423                 return ENA_COM_INVAL;
2424
2425         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2426                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2427                                     rss->hash_key_dma_addr,
2428                                     sizeof(*rss->hash_key), 0);
2429         if (unlikely(rc))
2430                 return rc;
2431
2432         /* ENA_FFS() returns 1 in case the lsb is set */
2433         rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2434         if (rss->hash_func)
2435                 rss->hash_func--;
2436
2437         *func = rss->hash_func;
2438
2439         return 0;
2440 }
2441
2442 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2443 {
2444         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2445                 ena_dev->rss.hash_key;
2446
2447         if (key)
2448                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2449
2450         return 0;
2451 }
2452
2453 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2454                           enum ena_admin_flow_hash_proto proto,
2455                           u16 *fields)
2456 {
2457         struct ena_rss *rss = &ena_dev->rss;
2458         struct ena_admin_get_feat_resp get_resp;
2459         int rc;
2460
2461         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2462                                     ENA_ADMIN_RSS_HASH_INPUT,
2463                                     rss->hash_ctrl_dma_addr,
2464                                     sizeof(*rss->hash_ctrl), 0);
2465         if (unlikely(rc))
2466                 return rc;
2467
2468         if (fields)
2469                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2470
2471         return 0;
2472 }
2473
2474 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2475 {
2476         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2477         struct ena_rss *rss = &ena_dev->rss;
2478         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2479         struct ena_admin_set_feat_cmd cmd;
2480         struct ena_admin_set_feat_resp resp;
2481         int ret;
2482
2483         if (!ena_com_check_supported_feature_id(ena_dev,
2484                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2485                 ena_trc_dbg("Feature %d isn't supported\n",
2486                             ENA_ADMIN_RSS_HASH_INPUT);
2487                 return ENA_COM_UNSUPPORTED;
2488         }
2489
2490         memset(&cmd, 0x0, sizeof(cmd));
2491
2492         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2493         cmd.aq_common_descriptor.flags =
2494                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2495         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2496         cmd.u.flow_hash_input.enabled_input_sort =
2497                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2498                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2499
2500         ret = ena_com_mem_addr_set(ena_dev,
2501                                    &cmd.control_buffer.address,
2502                                    rss->hash_ctrl_dma_addr);
2503         if (unlikely(ret)) {
2504                 ena_trc_err("memory address set failed\n");
2505                 return ret;
2506         }
2507         cmd.control_buffer.length = sizeof(*hash_ctrl);
2508
2509         ret = ena_com_execute_admin_command(admin_queue,
2510                                             (struct ena_admin_aq_entry *)&cmd,
2511                                             sizeof(cmd),
2512                                             (struct ena_admin_acq_entry *)&resp,
2513                                             sizeof(resp));
2514         if (unlikely(ret))
2515                 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2516
2517         return ret;
2518 }
2519
2520 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2521 {
2522         struct ena_rss *rss = &ena_dev->rss;
2523         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2524                 rss->hash_ctrl;
2525         u16 available_fields = 0;
2526         int rc, i;
2527
2528         /* Get the supported hash input */
2529         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2530         if (unlikely(rc))
2531                 return rc;
2532
2533         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2534                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2535                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2536
2537         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2538                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2539                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2540
2541         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2542                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2543                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2544
2545         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2546                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2547                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2548
2549         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2550                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2551
2552         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2553                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2554
2555         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2556                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2557
2558         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2559                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2560
2561         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2562                 available_fields = hash_ctrl->selected_fields[i].fields &
2563                                 hash_ctrl->supported_fields[i].fields;
2564                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2565                         ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2566                                     i, hash_ctrl->supported_fields[i].fields,
2567                                     hash_ctrl->selected_fields[i].fields);
2568                         return ENA_COM_UNSUPPORTED;
2569                 }
2570         }
2571
2572         rc = ena_com_set_hash_ctrl(ena_dev);
2573
2574         /* In case of failure, restore the old hash ctrl */
2575         if (unlikely(rc))
2576                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2577
2578         return rc;
2579 }
2580
2581 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2582                            enum ena_admin_flow_hash_proto proto,
2583                            u16 hash_fields)
2584 {
2585         struct ena_rss *rss = &ena_dev->rss;
2586         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2587         u16 supported_fields;
2588         int rc;
2589
2590         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2591                 ena_trc_err("Invalid proto num (%u)\n", proto);
2592                 return ENA_COM_INVAL;
2593         }
2594
2595         /* Get the ctrl table */
2596         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2597         if (unlikely(rc))
2598                 return rc;
2599
2600         /* Make sure all the fields are supported */
2601         supported_fields = hash_ctrl->supported_fields[proto].fields;
2602         if ((hash_fields & supported_fields) != hash_fields) {
2603                 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2604                             proto, hash_fields, supported_fields);
2605         }
2606
2607         hash_ctrl->selected_fields[proto].fields = hash_fields;
2608
2609         rc = ena_com_set_hash_ctrl(ena_dev);
2610
2611         /* In case of failure, restore the old hash ctrl */
2612         if (unlikely(rc))
2613                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2614
2615         return 0;
2616 }
2617
2618 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2619                                       u16 entry_idx, u16 entry_value)
2620 {
2621         struct ena_rss *rss = &ena_dev->rss;
2622
2623         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2624                 return ENA_COM_INVAL;
2625
2626         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2627                 return ENA_COM_INVAL;
2628
2629         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2630
2631         return 0;
2632 }
2633
2634 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2635 {
2636         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2637         struct ena_rss *rss = &ena_dev->rss;
2638         struct ena_admin_set_feat_cmd cmd;
2639         struct ena_admin_set_feat_resp resp;
2640         int ret;
2641
2642         if (!ena_com_check_supported_feature_id(ena_dev,
2643                                                 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2644                 ena_trc_dbg("Feature %d isn't supported\n",
2645                             ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2646                 return ENA_COM_UNSUPPORTED;
2647         }
2648
2649         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2650         if (ret) {
2651                 ena_trc_err("Failed to convert host indirection table to device table\n");
2652                 return ret;
2653         }
2654
2655         memset(&cmd, 0x0, sizeof(cmd));
2656
2657         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2658         cmd.aq_common_descriptor.flags =
2659                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2660         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2661         cmd.u.ind_table.size = rss->tbl_log_size;
2662         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2663
2664         ret = ena_com_mem_addr_set(ena_dev,
2665                                    &cmd.control_buffer.address,
2666                                    rss->rss_ind_tbl_dma_addr);
2667         if (unlikely(ret)) {
2668                 ena_trc_err("memory address set failed\n");
2669                 return ret;
2670         }
2671
2672         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2673                 sizeof(struct ena_admin_rss_ind_table_entry);
2674
2675         ret = ena_com_execute_admin_command(admin_queue,
2676                                             (struct ena_admin_aq_entry *)&cmd,
2677                                             sizeof(cmd),
2678                                             (struct ena_admin_acq_entry *)&resp,
2679                                             sizeof(resp));
2680
2681         if (unlikely(ret))
2682                 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2683
2684         return ret;
2685 }
2686
2687 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2688 {
2689         struct ena_rss *rss = &ena_dev->rss;
2690         struct ena_admin_get_feat_resp get_resp;
2691         u32 tbl_size;
2692         int i, rc;
2693
2694         tbl_size = (1ULL << rss->tbl_log_size) *
2695                 sizeof(struct ena_admin_rss_ind_table_entry);
2696
2697         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2698                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2699                                     rss->rss_ind_tbl_dma_addr,
2700                                     tbl_size, 0);
2701         if (unlikely(rc))
2702                 return rc;
2703
2704         if (!ind_tbl)
2705                 return 0;
2706
2707         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2708                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2709
2710         return 0;
2711 }
2712
2713 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2714 {
2715         int rc;
2716
2717         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2718
2719         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2720         if (unlikely(rc))
2721                 goto err_indr_tbl;
2722
2723         rc = ena_com_hash_key_allocate(ena_dev);
2724         if (unlikely(rc))
2725                 goto err_hash_key;
2726
2727         ena_com_hash_key_fill_default_key(ena_dev);
2728
2729         rc = ena_com_hash_ctrl_init(ena_dev);
2730         if (unlikely(rc))
2731                 goto err_hash_ctrl;
2732
2733         return 0;
2734
2735 err_hash_ctrl:
2736         ena_com_hash_key_destroy(ena_dev);
2737 err_hash_key:
2738         ena_com_indirect_table_destroy(ena_dev);
2739 err_indr_tbl:
2740
2741         return rc;
2742 }
2743
2744 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2745 {
2746         ena_com_indirect_table_destroy(ena_dev);
2747         ena_com_hash_key_destroy(ena_dev);
2748         ena_com_hash_ctrl_destroy(ena_dev);
2749
2750         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2751 }
2752
2753 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2754 {
2755         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2756
2757         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2758                                SZ_4K,
2759                                host_attr->host_info,
2760                                host_attr->host_info_dma_addr,
2761                                host_attr->host_info_dma_handle);
2762         if (unlikely(!host_attr->host_info))
2763                 return ENA_COM_NO_MEM;
2764
2765         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2766                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2767                 (ENA_COMMON_SPEC_VERSION_MINOR));
2768
2769         return 0;
2770 }
2771
2772 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2773                                 u32 debug_area_size)
2774 {
2775         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2776
2777         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2778                                debug_area_size,
2779                                host_attr->debug_area_virt_addr,
2780                                host_attr->debug_area_dma_addr,
2781                                host_attr->debug_area_dma_handle);
2782         if (unlikely(!host_attr->debug_area_virt_addr)) {
2783                 host_attr->debug_area_size = 0;
2784                 return ENA_COM_NO_MEM;
2785         }
2786
2787         host_attr->debug_area_size = debug_area_size;
2788
2789         return 0;
2790 }
2791
2792 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2793 {
2794         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2795
2796         if (host_attr->host_info) {
2797                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2798                                       SZ_4K,
2799                                       host_attr->host_info,
2800                                       host_attr->host_info_dma_addr,
2801                                       host_attr->host_info_dma_handle);
2802                 host_attr->host_info = NULL;
2803         }
2804 }
2805
2806 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2807 {
2808         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2809
2810         if (host_attr->debug_area_virt_addr) {
2811                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2812                                       host_attr->debug_area_size,
2813                                       host_attr->debug_area_virt_addr,
2814                                       host_attr->debug_area_dma_addr,
2815                                       host_attr->debug_area_dma_handle);
2816                 host_attr->debug_area_virt_addr = NULL;
2817         }
2818 }
2819
2820 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2821 {
2822         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2823         struct ena_com_admin_queue *admin_queue;
2824         struct ena_admin_set_feat_cmd cmd;
2825         struct ena_admin_set_feat_resp resp;
2826
2827         int ret;
2828
2829         /* Host attribute config is called before ena_com_get_dev_attr_feat
2830          * so ena_com can't check if the feature is supported.
2831          */
2832
2833         memset(&cmd, 0x0, sizeof(cmd));
2834         admin_queue = &ena_dev->admin_queue;
2835
2836         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2837         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2838
2839         ret = ena_com_mem_addr_set(ena_dev,
2840                                    &cmd.u.host_attr.debug_ba,
2841                                    host_attr->debug_area_dma_addr);
2842         if (unlikely(ret)) {
2843                 ena_trc_err("memory address set failed\n");
2844                 return ret;
2845         }
2846
2847         ret = ena_com_mem_addr_set(ena_dev,
2848                                    &cmd.u.host_attr.os_info_ba,
2849                                    host_attr->host_info_dma_addr);
2850         if (unlikely(ret)) {
2851                 ena_trc_err("memory address set failed\n");
2852                 return ret;
2853         }
2854
2855         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2856
2857         ret = ena_com_execute_admin_command(admin_queue,
2858                                             (struct ena_admin_aq_entry *)&cmd,
2859                                             sizeof(cmd),
2860                                             (struct ena_admin_acq_entry *)&resp,
2861                                             sizeof(resp));
2862
2863         if (unlikely(ret))
2864                 ena_trc_err("Failed to set host attributes: %d\n", ret);
2865
2866         return ret;
2867 }
2868
2869 /* Interrupt moderation */
2870 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2871 {
2872         return ena_com_check_supported_feature_id(ena_dev,
2873                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2874 }
2875
2876 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2877                                                           u32 intr_delay_resolution,
2878                                                           u32 *intr_moder_interval)
2879 {
2880         if (!intr_delay_resolution) {
2881                 ena_trc_err("Illegal interrupt delay granularity value\n");
2882                 return ENA_COM_FAULT;
2883         }
2884
2885         *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2886
2887         return 0;
2888 }
2889
2890
2891 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2892                                                       u32 tx_coalesce_usecs)
2893 {
2894         return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2895                                                               ena_dev->intr_delay_resolution,
2896                                                               &ena_dev->intr_moder_tx_interval);
2897 }
2898
2899 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2900                                                       u32 rx_coalesce_usecs)
2901 {
2902         return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2903                                                               ena_dev->intr_delay_resolution,
2904                                                               &ena_dev->intr_moder_rx_interval);
2905 }
2906
2907 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2908 {
2909         struct ena_admin_get_feat_resp get_resp;
2910         u16 delay_resolution;
2911         int rc;
2912
2913         rc = ena_com_get_feature(ena_dev, &get_resp,
2914                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2915
2916         if (rc) {
2917                 if (rc == ENA_COM_UNSUPPORTED) {
2918                         ena_trc_dbg("Feature %d isn't supported\n",
2919                                     ENA_ADMIN_INTERRUPT_MODERATION);
2920                         rc = 0;
2921                 } else {
2922                         ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2923                                     rc);
2924                 }
2925
2926                 /* no moderation supported, disable adaptive support */
2927                 ena_com_disable_adaptive_moderation(ena_dev);
2928                 return rc;
2929         }
2930
2931         /* if moderation is supported by device we set adaptive moderation */
2932         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2933         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2934
2935         /* Disable adaptive moderation by default - can be enabled later */
2936         ena_com_disable_adaptive_moderation(ena_dev);
2937
2938         return 0;
2939 }
2940
2941 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2942 {
2943         return ena_dev->intr_moder_tx_interval;
2944 }
2945
2946 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2947 {
2948         return ena_dev->intr_moder_rx_interval;
2949 }
2950
2951 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2952                             struct ena_admin_feature_llq_desc *llq_features,
2953                             struct ena_llq_configurations *llq_default_cfg)
2954 {
2955         int rc;
2956         struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2957
2958         if (!llq_features->max_llq_num) {
2959                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2960                 return 0;
2961         }
2962
2963         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2964         if (rc)
2965                 return rc;
2966
2967         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2968                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2969
2970         if (ena_dev->tx_max_header_size == 0) {
2971                 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2972                 return -EINVAL;
2973         }
2974
2975         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2976
2977         return 0;
2978 }