drivers/net/ena/base/ena_com.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include "ena_com.h"
   7
   8 /*****************************************************************************/
   9 /*****************************************************************************/
  10
  11 /* Timeout in micro-sec */
  12 #define ADMIN_CMD_TIMEOUT_US (3000000)
  13
  14 #define ENA_ASYNC_QUEUE_DEPTH 16
  15 #define ENA_ADMIN_QUEUE_DEPTH 32
  16
  17 #define ENA_CTRL_MAJOR          0
  18 #define ENA_CTRL_MINOR          0
  19 #define ENA_CTRL_SUB_MINOR      1
  20
  21 #define MIN_ENA_CTRL_VER \
  22         (((ENA_CTRL_MAJOR) << \
  23         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  24         ((ENA_CTRL_MINOR) << \
  25         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  26         (ENA_CTRL_SUB_MINOR))
  27
  28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  30
  31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  32
  33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  34
  35 #define ENA_REGS_ADMIN_INTR_MASK 1
  36
  37 #define ENA_MIN_ADMIN_POLL_US 100
  38
  39 #define ENA_MAX_ADMIN_POLL_US 5000
  40
  41 /*****************************************************************************/
  42 /*****************************************************************************/
  43 /*****************************************************************************/
  44
  45 enum ena_cmd_status {
  46         ENA_CMD_SUBMITTED,
  47         ENA_CMD_COMPLETED,
  48         /* Abort - canceled by the driver */
  49         ENA_CMD_ABORTED,
  50 };
  51
  52 struct ena_comp_ctx {
  53         ena_wait_event_t wait_event;
  54         struct ena_admin_acq_entry *user_cqe;
  55         u32 comp_size;
  56         enum ena_cmd_status status;
  57         /* status from the device */
  58         u8 comp_status;
  59         u8 cmd_opcode;
  60         bool occupied;
  61 };
  62
  63 struct ena_com_stats_ctx {
  64         struct ena_admin_aq_get_stats_cmd get_cmd;
  65         struct ena_admin_acq_get_stats_resp get_resp;
  66 };
  67
  68 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  69                                        struct ena_common_mem_addr *ena_addr,
  70                                        dma_addr_t addr)
  71 {
  72         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  73                 ena_trc_err("dma address has more bits that the device supports\n");
  74                 return ENA_COM_INVAL;
  75         }
  76
  77         ena_addr->mem_addr_low = lower_32_bits(addr);
  78         ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
  79
  80         return 0;
  81 }
  82
  83 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
  84 {
  85         struct ena_com_admin_sq *sq = &queue->sq;
  86         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
  87
  88         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
  89                                sq->mem_handle);
  90
  91         if (!sq->entries) {
  92                 ena_trc_err("memory allocation failed\n");
  93                 return ENA_COM_NO_MEM;
  94         }
  95
  96         sq->head = 0;
  97         sq->tail = 0;
  98         sq->phase = 1;
  99
 100         sq->db_addr = NULL;
 101
 102         return 0;
 103 }
 104
 105 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 106 {
 107         struct ena_com_admin_cq *cq = &queue->cq;
 108         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 109
 110         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
 111                                cq->mem_handle);
 112
 113         if (!cq->entries)  {
 114                 ena_trc_err("memory allocation failed\n");
 115                 return ENA_COM_NO_MEM;
 116         }
 117
 118         cq->head = 0;
 119         cq->phase = 1;
 120
 121         return 0;
 122 }
 123
 124 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 125                                    struct ena_aenq_handlers *aenq_handlers)
 126 {
 127         struct ena_com_aenq *aenq = &dev->aenq;
 128         u32 addr_low, addr_high, aenq_caps;
 129         u16 size;
 130
 131         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 132         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 133         ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
 134                         aenq->entries,
 135                         aenq->dma_addr,
 136                         aenq->mem_handle);
 137
 138         if (!aenq->entries) {
 139                 ena_trc_err("memory allocation failed\n");
 140                 return ENA_COM_NO_MEM;
 141         }
 142
 143         aenq->head = aenq->q_depth;
 144         aenq->phase = 1;
 145
 146         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 147         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 148
 149         ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 150         ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 151
 152         aenq_caps = 0;
 153         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 154         aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
 155                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 156                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 157         ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 158
 159         if (unlikely(!aenq_handlers)) {
 160                 ena_trc_err("aenq handlers pointer is NULL\n");
 161                 return ENA_COM_INVAL;
 162         }
 163
 164         aenq->aenq_handlers = aenq_handlers;
 165
 166         return 0;
 167 }
 168
 169 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 170                                      struct ena_comp_ctx *comp_ctx)
 171 {
 172         comp_ctx->occupied = false;
 173         ATOMIC32_DEC(&queue->outstanding_cmds);
 174 }
 175
 176 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 177                                           u16 command_id, bool capture)
 178 {
 179         if (unlikely(command_id >= queue->q_depth)) {
 180                 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 181                             command_id, queue->q_depth);
 182                 return NULL;
 183         }
 184
 185         if (unlikely(!queue->comp_ctx)) {
 186                 ena_trc_err("Completion context is NULL\n");
 187                 return NULL;
 188         }
 189
 190         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 191                 ena_trc_err("Completion context is occupied\n");
 192                 return NULL;
 193         }
 194
 195         if (capture) {
 196                 ATOMIC32_INC(&queue->outstanding_cmds);
 197                 queue->comp_ctx[command_id].occupied = true;
 198         }
 199
 200         return &queue->comp_ctx[command_id];
 201 }
 202
 203 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 204                                                        struct ena_admin_aq_entry *cmd,
 205                                                        size_t cmd_size_in_bytes,
 206                                                        struct ena_admin_acq_entry *comp,
 207                                                        size_t comp_size_in_bytes)
 208 {
 209         struct ena_comp_ctx *comp_ctx;
 210         u16 tail_masked, cmd_id;
 211         u16 queue_size_mask;
 212         u16 cnt;
 213
 214         queue_size_mask = admin_queue->q_depth - 1;
 215
 216         tail_masked = admin_queue->sq.tail & queue_size_mask;
 217
 218         /* In case of queue FULL */
 219         cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
 220         if (cnt >= admin_queue->q_depth) {
 221                 ena_trc_dbg("admin queue is full.\n");
 222                 admin_queue->stats.out_of_space++;
 223                 return ERR_PTR(ENA_COM_NO_SPACE);
 224         }
 225
 226         cmd_id = admin_queue->curr_cmd_id;
 227
 228         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 229                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 230
 231         cmd->aq_common_descriptor.command_id |= cmd_id &
 232                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 233
 234         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 235         if (unlikely(!comp_ctx))
 236                 return ERR_PTR(ENA_COM_INVAL);
 237
 238         comp_ctx->status = ENA_CMD_SUBMITTED;
 239         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 240         comp_ctx->user_cqe = comp;
 241         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 242
 243         ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
 244
 245         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 246
 247         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 248                 queue_size_mask;
 249
 250         admin_queue->sq.tail++;
 251         admin_queue->stats.submitted_cmd++;
 252
 253         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 254                 admin_queue->sq.phase = !admin_queue->sq.phase;
 255
 256         ENA_DB_SYNC(&admin_queue->sq.mem_handle);
 257         ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
 258                         admin_queue->sq.db_addr);
 259
 260         return comp_ctx;
 261 }
 262
 263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 264 {
 265         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 266         struct ena_comp_ctx *comp_ctx;
 267         u16 i;
 268
 269         queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
 270         if (unlikely(!queue->comp_ctx)) {
 271                 ena_trc_err("memory allocation failed\n");
 272                 return ENA_COM_NO_MEM;
 273         }
 274
 275         for (i = 0; i < queue->q_depth; i++) {
 276                 comp_ctx = get_comp_ctxt(queue, i, false);
 277                 if (comp_ctx)
 278                         ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
 279         }
 280
 281         return 0;
 282 }
 283
 284 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 285                                                      struct ena_admin_aq_entry *cmd,
 286                                                      size_t cmd_size_in_bytes,
 287                                                      struct ena_admin_acq_entry *comp,
 288                                                      size_t comp_size_in_bytes)
 289 {
 290         unsigned long flags = 0;
 291         struct ena_comp_ctx *comp_ctx;
 292
 293         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 294         if (unlikely(!admin_queue->running_state)) {
 295                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 296                 return ERR_PTR(ENA_COM_NO_DEVICE);
 297         }
 298         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 299                                               cmd_size_in_bytes,
 300                                               comp,
 301                                               comp_size_in_bytes);
 302         if (IS_ERR(comp_ctx))
 303                 admin_queue->running_state = false;
 304         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 305
 306         return comp_ctx;
 307 }
 308
 309 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 310                               struct ena_com_create_io_ctx *ctx,
 311                               struct ena_com_io_sq *io_sq)
 312 {
 313         size_t size;
 314         int dev_node = 0;
 315
 316         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 317
 318         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 319         io_sq->desc_entry_size =
 320                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 321                 sizeof(struct ena_eth_io_tx_desc) :
 322                 sizeof(struct ena_eth_io_rx_desc);
 323
 324         size = io_sq->desc_entry_size * io_sq->q_depth;
 325         io_sq->bus = ena_dev->bus;
 326
 327         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 328                 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 329                                             size,
 330                                             io_sq->desc_addr.virt_addr,
 331                                             io_sq->desc_addr.phys_addr,
 332                                             io_sq->desc_addr.mem_handle,
 333                                             ctx->numa_node,
 334                                             dev_node);
 335                 if (!io_sq->desc_addr.virt_addr) {
 336                         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 337                                                size,
 338                                                io_sq->desc_addr.virt_addr,
 339                                                io_sq->desc_addr.phys_addr,
 340                                                io_sq->desc_addr.mem_handle);
 341                 }
 342
 343                 if (!io_sq->desc_addr.virt_addr) {
 344                         ena_trc_err("memory allocation failed\n");
 345                         return ENA_COM_NO_MEM;
 346                 }
 347         }
 348
 349         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 350                 /* Allocate bounce buffers */
 351                 io_sq->bounce_buf_ctrl.buffer_size =
 352                         ena_dev->llq_info.desc_list_entry_size;
 353                 io_sq->bounce_buf_ctrl.buffers_num =
 354                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 355                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 356
 357                 size = io_sq->bounce_buf_ctrl.buffer_size *
 358                         io_sq->bounce_buf_ctrl.buffers_num;
 359
 360                 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
 361                                    size,
 362                                    io_sq->bounce_buf_ctrl.base_buffer,
 363                                    ctx->numa_node,
 364                                    dev_node);
 365                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 366                         io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
 367
 368                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 369                         ena_trc_err("bounce buffer memory allocation failed\n");
 370                         return ENA_COM_NO_MEM;
 371                 }
 372
 373                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 374                        sizeof(io_sq->llq_info));
 375
 376                 /* Initiate the first bounce buffer */
 377                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 378                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 379                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 380                        0x0, io_sq->llq_info.desc_list_entry_size);
 381                 io_sq->llq_buf_ctrl.descs_left_in_line =
 382                         io_sq->llq_info.descs_num_before_header;
 383                 io_sq->disable_meta_caching =
 384                         io_sq->llq_info.disable_meta_caching;
 385
 386                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 387                         io_sq->entries_in_tx_burst_left =
 388                                 io_sq->llq_info.max_entries_in_tx_burst;
 389         }
 390
 391         io_sq->tail = 0;
 392         io_sq->next_to_comp = 0;
 393         io_sq->phase = 1;
 394
 395         return 0;
 396 }
 397
 398 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 399                               struct ena_com_create_io_ctx *ctx,
 400                               struct ena_com_io_cq *io_cq)
 401 {
 402         size_t size;
 403         int prev_node = 0;
 404
 405         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 406
 407         /* Use the basic completion descriptor for Rx */
 408         io_cq->cdesc_entry_size_in_bytes =
 409                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 410                 sizeof(struct ena_eth_io_tx_cdesc) :
 411                 sizeof(struct ena_eth_io_rx_cdesc_base);
 412
 413         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 414         io_cq->bus = ena_dev->bus;
 415
 416         ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 417                         size,
 418                         io_cq->cdesc_addr.virt_addr,
 419                         io_cq->cdesc_addr.phys_addr,
 420                         io_cq->cdesc_addr.mem_handle,
 421                         ctx->numa_node,
 422                         prev_node);
 423         if (!io_cq->cdesc_addr.virt_addr) {
 424                 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 425                                        size,
 426                                        io_cq->cdesc_addr.virt_addr,
 427                                        io_cq->cdesc_addr.phys_addr,
 428                                        io_cq->cdesc_addr.mem_handle);
 429         }
 430
 431         if (!io_cq->cdesc_addr.virt_addr) {
 432                 ena_trc_err("memory allocation failed\n");
 433                 return ENA_COM_NO_MEM;
 434         }
 435
 436         io_cq->phase = 1;
 437         io_cq->head = 0;
 438
 439         return 0;
 440 }
 441
 442 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 443                                                    struct ena_admin_acq_entry *cqe)
 444 {
 445         struct ena_comp_ctx *comp_ctx;
 446         u16 cmd_id;
 447
 448         cmd_id = cqe->acq_common_descriptor.command &
 449                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 450
 451         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 452         if (unlikely(!comp_ctx)) {
 453                 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
 454                 admin_queue->running_state = false;
 455                 return;
 456         }
 457
 458         comp_ctx->status = ENA_CMD_COMPLETED;
 459         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 460
 461         if (comp_ctx->user_cqe)
 462                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 463
 464         if (!admin_queue->polling)
 465                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
 466 }
 467
 468 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 469 {
 470         struct ena_admin_acq_entry *cqe = NULL;
 471         u16 comp_num = 0;
 472         u16 head_masked;
 473         u8 phase;
 474
 475         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 476         phase = admin_queue->cq.phase;
 477
 478         cqe = &admin_queue->cq.entries[head_masked];
 479
 480         /* Go over all the completions */
 481         while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
 482                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 483                 /* Do not read the rest of the completion entry before the
 484                  * phase bit was validated
 485                  */
 486                 dma_rmb();
 487                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 488
 489                 head_masked++;
 490                 comp_num++;
 491                 if (unlikely(head_masked == admin_queue->q_depth)) {
 492                         head_masked = 0;
 493                         phase = !phase;
 494                 }
 495
 496                 cqe = &admin_queue->cq.entries[head_masked];
 497         }
 498
 499         admin_queue->cq.head += comp_num;
 500         admin_queue->cq.phase = phase;
 501         admin_queue->sq.head += comp_num;
 502         admin_queue->stats.completed_cmd += comp_num;
 503 }
 504
 505 static int ena_com_comp_status_to_errno(u8 comp_status)
 506 {
 507         if (unlikely(comp_status != 0))
 508                 ena_trc_err("admin command failed[%u]\n", comp_status);
 509
 510         switch (comp_status) {
 511         case ENA_ADMIN_SUCCESS:
 512                 return ENA_COM_OK;
 513         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 514                 return ENA_COM_NO_MEM;
 515         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 516                 return ENA_COM_UNSUPPORTED;
 517         case ENA_ADMIN_BAD_OPCODE:
 518         case ENA_ADMIN_MALFORMED_REQUEST:
 519         case ENA_ADMIN_ILLEGAL_PARAMETER:
 520         case ENA_ADMIN_UNKNOWN_ERROR:
 521                 return ENA_COM_INVAL;
 522         case ENA_ADMIN_RESOURCE_BUSY:
 523                 return ENA_COM_TRY_AGAIN;
 524         }
 525
 526         return ENA_COM_INVAL;
 527 }
 528
 529 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
 530 {
 531         delay_us = ENA_MAX32(ENA_MIN_ADMIN_POLL_US, delay_us);
 532         delay_us = ENA_MIN32(delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
 533         ENA_USLEEP(delay_us);
 534 }
 535
 536 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 537                                                      struct ena_com_admin_queue *admin_queue)
 538 {
 539         unsigned long flags = 0;
 540         ena_time_t timeout;
 541         int ret;
 542         u32 exp = 0;
 543
 544         timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
 545
 546         while (1) {
 547                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 548                 ena_com_handle_admin_completion(admin_queue);
 549                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 550
 551                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 552                         break;
 553
 554                 if (ENA_TIME_EXPIRE(timeout)) {
 555                         ena_trc_err("Wait for completion (polling) timeout\n");
 556                         /* ENA didn't have any completion */
 557                         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 558                         admin_queue->stats.no_completion++;
 559                         admin_queue->running_state = false;
 560                         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 561
 562                         ret = ENA_COM_TIMER_EXPIRED;
 563                         goto err;
 564                 }
 565
 566                 ena_delay_exponential_backoff_us(exp++,
 567                                                  admin_queue->ena_dev->ena_min_poll_delay_us);
 568         }
 569
 570         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 571                 ena_trc_err("Command was aborted\n");
 572                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 573                 admin_queue->stats.aborted_cmd++;
 574                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 575                 ret = ENA_COM_NO_DEVICE;
 576                 goto err;
 577         }
 578
 579         ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
 580                  "Invalid comp status %d\n", comp_ctx->status);
 581
 582         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 583 err:
 584         comp_ctxt_release(admin_queue, comp_ctx);
 585         return ret;
 586 }
 587
 588 /**
 589  * Set the LLQ configurations of the firmware
 590  *
 591  * The driver provides only the enabled feature values to the device,
 592  * which in turn, checks if they are supported.
 593  */
 594 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 595 {
 596         struct ena_com_admin_queue *admin_queue;
 597         struct ena_admin_set_feat_cmd cmd;
 598         struct ena_admin_set_feat_resp resp;
 599         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 600         int ret;
 601
 602         memset(&cmd, 0x0, sizeof(cmd));
 603         admin_queue = &ena_dev->admin_queue;
 604
 605         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 606         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 607
 608         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 609         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 610         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 611         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 612
 613         cmd.u.llq.accel_mode.u.set.enabled_flags =
 614                 BIT(ENA_ADMIN_DISABLE_META_CACHING) |
 615                 BIT(ENA_ADMIN_LIMIT_TX_BURST);
 616
 617         ret = ena_com_execute_admin_command(admin_queue,
 618                                             (struct ena_admin_aq_entry *)&cmd,
 619                                             sizeof(cmd),
 620                                             (struct ena_admin_acq_entry *)&resp,
 621                                             sizeof(resp));
 622
 623         if (unlikely(ret))
 624                 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
 625
 626         return ret;
 627 }
 628
 629 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 630                                    struct ena_admin_feature_llq_desc *llq_features,
 631                                    struct ena_llq_configurations *llq_default_cfg)
 632 {
 633         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 634         struct ena_admin_accel_mode_get llq_accel_mode_get;
 635         u16 supported_feat;
 636         int rc;
 637
 638         memset(llq_info, 0, sizeof(*llq_info));
 639
 640         supported_feat = llq_features->header_location_ctrl_supported;
 641
 642         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 643                 llq_info->header_location_ctrl =
 644                         llq_default_cfg->llq_header_location;
 645         } else {
 646                 ena_trc_err("Invalid header location control, supported: 0x%x\n",
 647                             supported_feat);
 648                 return -EINVAL;
 649         }
 650
 651         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 652                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 653                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 654                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 655                 } else  {
 656                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 657                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 658                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 659                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 660                         } else {
 661                                 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 662                                             supported_feat);
 663                                 return -EINVAL;
 664                         }
 665
 666                         ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 667                                     llq_default_cfg->llq_stride_ctrl,
 668                                     supported_feat,
 669                                     llq_info->desc_stride_ctrl);
 670                 }
 671         } else {
 672                 llq_info->desc_stride_ctrl = 0;
 673         }
 674
 675         supported_feat = llq_features->entry_size_ctrl_supported;
 676         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 677                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 678                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 679         } else {
 680                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 681                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 682                         llq_info->desc_list_entry_size = 128;
 683                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 684                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 685                         llq_info->desc_list_entry_size = 192;
 686                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 687                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 688                         llq_info->desc_list_entry_size = 256;
 689                 } else {
 690                         ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
 691                         return -EINVAL;
 692                 }
 693
 694                 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 695                             llq_default_cfg->llq_ring_entry_size,
 696                             supported_feat,
 697                             llq_info->desc_list_entry_size);
 698         }
 699         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 700                 /* The desc list entry size should be whole multiply of 8
 701                  * This requirement comes from __iowrite64_copy()
 702                  */
 703                 ena_trc_err("illegal entry size %d\n",
 704                             llq_info->desc_list_entry_size);
 705                 return -EINVAL;
 706         }
 707
 708         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 709                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 710                         sizeof(struct ena_eth_io_tx_desc);
 711         else
 712                 llq_info->descs_per_entry = 1;
 713
 714         supported_feat = llq_features->desc_num_before_header_supported;
 715         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 716                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 717         } else {
 718                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 719                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 720                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 721                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 722                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 723                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 724                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 725                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 726                 } else {
 727                         ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
 728                                     supported_feat);
 729                         return -EINVAL;
 730                 }
 731
 732                 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 733                             llq_default_cfg->llq_num_decs_before_header,
 734                             supported_feat,
 735                             llq_info->descs_num_before_header);
 736         }
 737         /* Check for accelerated queue supported */
 738         llq_accel_mode_get = llq_features->accel_mode.u.get;
 739
 740         llq_info->disable_meta_caching =
 741                 !!(llq_accel_mode_get.supported_flags &
 742                    BIT(ENA_ADMIN_DISABLE_META_CACHING));
 743
 744         if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
 745                 llq_info->max_entries_in_tx_burst =
 746                         llq_accel_mode_get.max_tx_burst_size /
 747                         llq_default_cfg->llq_ring_entry_size_value;
 748
 749         rc = ena_com_set_llq(ena_dev);
 750         if (rc)
 751                 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
 752
 753         return rc;
 754 }
 755
 756 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 757                                                         struct ena_com_admin_queue *admin_queue)
 758 {
 759         unsigned long flags = 0;
 760         int ret;
 761
 762         ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
 763                             admin_queue->completion_timeout);
 764
 765         /* In case the command wasn't completed find out the root cause.
 766          * There might be 2 kinds of errors
 767          * 1) No completion (timeout reached)
 768          * 2) There is completion but the device didn't get any msi-x interrupt.
 769          */
 770         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 771                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 772                 ena_com_handle_admin_completion(admin_queue);
 773                 admin_queue->stats.no_completion++;
 774                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 775
 776                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 777                         ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 778                                     comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
 779                         /* Check if fallback to polling is enabled */
 780                         if (admin_queue->auto_polling)
 781                                 admin_queue->polling = true;
 782                 } else {
 783                         ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 784                                     comp_ctx->cmd_opcode, comp_ctx->status);
 785                 }
 786                 /* Check if shifted to polling mode.
 787                  * This will happen if there is a completion without an interrupt
 788                  * and autopolling mode is enabled. Continuing normal execution in such case
 789                  */
 790                 if (!admin_queue->polling) {
 791                         admin_queue->running_state = false;
 792                         ret = ENA_COM_TIMER_EXPIRED;
 793                         goto err;
 794                 }
 795         }
 796
 797         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 798 err:
 799         comp_ctxt_release(admin_queue, comp_ctx);
 800         return ret;
 801 }
 802
 803 /* This method read the hardware device register through posting writes
 804  * and waiting for response
 805  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 806  */
 807 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 808 {
 809         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 810         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 811                 mmio_read->read_resp;
 812         u32 mmio_read_reg, ret, i;
 813         unsigned long flags = 0;
 814         u32 timeout = mmio_read->reg_read_to;
 815
 816         ENA_MIGHT_SLEEP();
 817
 818         if (timeout == 0)
 819                 timeout = ENA_REG_READ_TIMEOUT;
 820
 821         /* If readless is disabled, perform regular read */
 822         if (!mmio_read->readless_supported)
 823                 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
 824
 825         ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
 826         mmio_read->seq_num++;
 827
 828         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 829         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 830                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 831         mmio_read_reg |= mmio_read->seq_num &
 832                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 833
 834         ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
 835                         ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 836
 837         for (i = 0; i < timeout; i++) {
 838                 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
 839                         break;
 840
 841                 ENA_UDELAY(1);
 842         }
 843
 844         if (unlikely(i == timeout)) {
 845                 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 846                             mmio_read->seq_num,
 847                             offset,
 848                             read_resp->req_id,
 849                             read_resp->reg_off);
 850                 ret = ENA_MMIO_READ_TIMEOUT;
 851                 goto err;
 852         }
 853
 854         if (read_resp->reg_off != offset) {
 855                 ena_trc_err("Read failure: wrong offset provided\n");
 856                 ret = ENA_MMIO_READ_TIMEOUT;
 857         } else {
 858                 ret = read_resp->reg_val;
 859         }
 860 err:
 861         ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
 862
 863         return ret;
 864 }
 865
 866 /* There are two types to wait for completion.
 867  * Polling mode - wait until the completion is available.
 868  * Async mode - wait on wait queue until the completion is ready
 869  * (or the timeout expired).
 870  * It is expected that the IRQ called ena_com_handle_admin_completion
 871  * to mark the completions.
 872  */
 873 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 874                                              struct ena_com_admin_queue *admin_queue)
 875 {
 876         if (admin_queue->polling)
 877                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 878                                                                  admin_queue);
 879
 880         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 881                                                             admin_queue);
 882 }
 883
 884 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 885                                  struct ena_com_io_sq *io_sq)
 886 {
 887         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 888         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 889         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 890         u8 direction;
 891         int ret;
 892
 893         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 894
 895         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 896                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 897         else
 898                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 899
 900         destroy_cmd.sq.sq_identity |= (direction <<
 901                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 902                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 903
 904         destroy_cmd.sq.sq_idx = io_sq->idx;
 905         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 906
 907         ret = ena_com_execute_admin_command(admin_queue,
 908                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 909                                             sizeof(destroy_cmd),
 910                                             (struct ena_admin_acq_entry *)&destroy_resp,
 911                                             sizeof(destroy_resp));
 912
 913         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
 914                 ena_trc_err("failed to destroy io sq error: %d\n", ret);
 915
 916         return ret;
 917 }
 918
 919 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 920                                   struct ena_com_io_sq *io_sq,
 921                                   struct ena_com_io_cq *io_cq)
 922 {
 923         size_t size;
 924
 925         if (io_cq->cdesc_addr.virt_addr) {
 926                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 927
 928                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 929                                       size,
 930                                       io_cq->cdesc_addr.virt_addr,
 931                                       io_cq->cdesc_addr.phys_addr,
 932                                       io_cq->cdesc_addr.mem_handle);
 933
 934                 io_cq->cdesc_addr.virt_addr = NULL;
 935         }
 936
 937         if (io_sq->desc_addr.virt_addr) {
 938                 size = io_sq->desc_entry_size * io_sq->q_depth;
 939
 940                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 941                                       size,
 942                                       io_sq->desc_addr.virt_addr,
 943                                       io_sq->desc_addr.phys_addr,
 944                                       io_sq->desc_addr.mem_handle);
 945
 946                 io_sq->desc_addr.virt_addr = NULL;
 947         }
 948
 949         if (io_sq->bounce_buf_ctrl.base_buffer) {
 950                 ENA_MEM_FREE(ena_dev->dmadev,
 951                              io_sq->bounce_buf_ctrl.base_buffer,
 952                              (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
 953                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 954         }
 955 }
 956
 957 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 958                                 u16 exp_state)
 959 {
 960         u32 val, exp = 0;
 961         ena_time_t timeout_stamp;
 962
 963         /* Convert timeout from resolution of 100ms to us resolution. */
 964         timeout_stamp = ENA_GET_SYSTEM_TIMEOUT(100 * 1000 * timeout);
 965
 966         while (1) {
 967                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 968
 969                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 970                         ena_trc_err("Reg read timeout occurred\n");
 971                         return ENA_COM_TIMER_EXPIRED;
 972                 }
 973
 974                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 975                         exp_state)
 976                         return 0;
 977
 978                 if (ENA_TIME_EXPIRE(timeout_stamp))
 979                         return ENA_COM_TIMER_EXPIRED;
 980
 981                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
 982         }
 983 }
 984
 985 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 986                                                enum ena_admin_aq_feature_id feature_id)
 987 {
 988         u32 feature_mask = 1 << feature_id;
 989
 990         /* Device attributes is always supported */
 991         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 992             !(ena_dev->supported_features & feature_mask))
 993                 return false;
 994
 995         return true;
 996 }
 997
 998 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 999                                   struct ena_admin_get_feat_resp *get_resp,
1000                                   enum ena_admin_aq_feature_id feature_id,
1001                                   dma_addr_t control_buf_dma_addr,
1002                                   u32 control_buff_size,
1003                                   u8 feature_ver)
1004 {
1005         struct ena_com_admin_queue *admin_queue;
1006         struct ena_admin_get_feat_cmd get_cmd;
1007         int ret;
1008
1009         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1010                 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
1011                 return ENA_COM_UNSUPPORTED;
1012         }
1013
1014         memset(&get_cmd, 0x0, sizeof(get_cmd));
1015         admin_queue = &ena_dev->admin_queue;
1016
1017         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1018
1019         if (control_buff_size)
1020                 get_cmd.aq_common_descriptor.flags =
1021                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1022         else
1023                 get_cmd.aq_common_descriptor.flags = 0;
1024
1025         ret = ena_com_mem_addr_set(ena_dev,
1026                                    &get_cmd.control_buffer.address,
1027                                    control_buf_dma_addr);
1028         if (unlikely(ret)) {
1029                 ena_trc_err("memory address set failed\n");
1030                 return ret;
1031         }
1032
1033         get_cmd.control_buffer.length = control_buff_size;
1034         get_cmd.feat_common.feature_version = feature_ver;
1035         get_cmd.feat_common.feature_id = feature_id;
1036
1037         ret = ena_com_execute_admin_command(admin_queue,
1038                                             (struct ena_admin_aq_entry *)
1039                                             &get_cmd,
1040                                             sizeof(get_cmd),
1041                                             (struct ena_admin_acq_entry *)
1042                                             get_resp,
1043                                             sizeof(*get_resp));
1044
1045         if (unlikely(ret))
1046                 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1047                             feature_id, ret);
1048
1049         return ret;
1050 }
1051
1052 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1053                                struct ena_admin_get_feat_resp *get_resp,
1054                                enum ena_admin_aq_feature_id feature_id,
1055                                u8 feature_ver)
1056 {
1057         return ena_com_get_feature_ex(ena_dev,
1058                                       get_resp,
1059                                       feature_id,
1060                                       0,
1061                                       0,
1062                                       feature_ver);
1063 }
1064
1065 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1066 {
1067         return ena_dev->rss.hash_func;
1068 }
1069
1070 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1071 {
1072         struct ena_admin_feature_rss_flow_hash_control *hash_key =
1073                 (ena_dev->rss).hash_key;
1074
1075         ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1076         /* The key buffer is stored in the device in an array of
1077          * uint32 elements.
1078          */
1079         hash_key->keys_num = ENA_ADMIN_RSS_KEY_PARTS;
1080 }
1081
1082 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1083 {
1084         struct ena_rss *rss = &ena_dev->rss;
1085
1086         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1087                                sizeof(*rss->hash_key),
1088                                rss->hash_key,
1089                                rss->hash_key_dma_addr,
1090                                rss->hash_key_mem_handle);
1091
1092         if (unlikely(!rss->hash_key))
1093                 return ENA_COM_NO_MEM;
1094
1095         return 0;
1096 }
1097
1098 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1099 {
1100         struct ena_rss *rss = &ena_dev->rss;
1101
1102         if (rss->hash_key)
1103                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1104                                       sizeof(*rss->hash_key),
1105                                       rss->hash_key,
1106                                       rss->hash_key_dma_addr,
1107                                       rss->hash_key_mem_handle);
1108         rss->hash_key = NULL;
1109 }
1110
1111 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1112 {
1113         struct ena_rss *rss = &ena_dev->rss;
1114
1115         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1116                                sizeof(*rss->hash_ctrl),
1117                                rss->hash_ctrl,
1118                                rss->hash_ctrl_dma_addr,
1119                                rss->hash_ctrl_mem_handle);
1120
1121         if (unlikely(!rss->hash_ctrl))
1122                 return ENA_COM_NO_MEM;
1123
1124         return 0;
1125 }
1126
1127 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1128 {
1129         struct ena_rss *rss = &ena_dev->rss;
1130
1131         if (rss->hash_ctrl)
1132                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1133                                       sizeof(*rss->hash_ctrl),
1134                                       rss->hash_ctrl,
1135                                       rss->hash_ctrl_dma_addr,
1136                                       rss->hash_ctrl_mem_handle);
1137         rss->hash_ctrl = NULL;
1138 }
1139
1140 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1141                                            u16 log_size)
1142 {
1143         struct ena_rss *rss = &ena_dev->rss;
1144         struct ena_admin_get_feat_resp get_resp;
1145         size_t tbl_size;
1146         int ret;
1147
1148         ret = ena_com_get_feature(ena_dev, &get_resp,
1149                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1150         if (unlikely(ret))
1151                 return ret;
1152
1153         if ((get_resp.u.ind_table.min_size > log_size) ||
1154             (get_resp.u.ind_table.max_size < log_size)) {
1155                 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1156                             1 << log_size,
1157                             1 << get_resp.u.ind_table.min_size,
1158                             1 << get_resp.u.ind_table.max_size);
1159                 return ENA_COM_INVAL;
1160         }
1161
1162         tbl_size = (1ULL << log_size) *
1163                 sizeof(struct ena_admin_rss_ind_table_entry);
1164
1165         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1166                              tbl_size,
1167                              rss->rss_ind_tbl,
1168                              rss->rss_ind_tbl_dma_addr,
1169                              rss->rss_ind_tbl_mem_handle);
1170         if (unlikely(!rss->rss_ind_tbl))
1171                 goto mem_err1;
1172
1173         tbl_size = (1ULL << log_size) * sizeof(u16);
1174         rss->host_rss_ind_tbl =
1175                 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1176         if (unlikely(!rss->host_rss_ind_tbl))
1177                 goto mem_err2;
1178
1179         rss->tbl_log_size = log_size;
1180
1181         return 0;
1182
1183 mem_err2:
1184         tbl_size = (1ULL << log_size) *
1185                 sizeof(struct ena_admin_rss_ind_table_entry);
1186
1187         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1188                               tbl_size,
1189                               rss->rss_ind_tbl,
1190                               rss->rss_ind_tbl_dma_addr,
1191                               rss->rss_ind_tbl_mem_handle);
1192         rss->rss_ind_tbl = NULL;
1193 mem_err1:
1194         rss->tbl_log_size = 0;
1195         return ENA_COM_NO_MEM;
1196 }
1197
1198 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1199 {
1200         struct ena_rss *rss = &ena_dev->rss;
1201         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1202                 sizeof(struct ena_admin_rss_ind_table_entry);
1203
1204         if (rss->rss_ind_tbl)
1205                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1206                                       tbl_size,
1207                                       rss->rss_ind_tbl,
1208                                       rss->rss_ind_tbl_dma_addr,
1209                                       rss->rss_ind_tbl_mem_handle);
1210         rss->rss_ind_tbl = NULL;
1211
1212         if (rss->host_rss_ind_tbl)
1213                 ENA_MEM_FREE(ena_dev->dmadev,
1214                              rss->host_rss_ind_tbl,
1215                              ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1216         rss->host_rss_ind_tbl = NULL;
1217 }
1218
1219 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1220                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1221 {
1222         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1223         struct ena_admin_aq_create_sq_cmd create_cmd;
1224         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1225         u8 direction;
1226         int ret;
1227
1228         memset(&create_cmd, 0x0, sizeof(create_cmd));
1229
1230         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1231
1232         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1233                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1234         else
1235                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1236
1237         create_cmd.sq_identity |= (direction <<
1238                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1239                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1240
1241         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1242                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1243
1244         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1245                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1246                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1247
1248         create_cmd.sq_caps_3 |=
1249                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1250
1251         create_cmd.cq_idx = cq_idx;
1252         create_cmd.sq_depth = io_sq->q_depth;
1253
1254         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1255                 ret = ena_com_mem_addr_set(ena_dev,
1256                                            &create_cmd.sq_ba,
1257                                            io_sq->desc_addr.phys_addr);
1258                 if (unlikely(ret)) {
1259                         ena_trc_err("memory address set failed\n");
1260                         return ret;
1261                 }
1262         }
1263
1264         ret = ena_com_execute_admin_command(admin_queue,
1265                                             (struct ena_admin_aq_entry *)&create_cmd,
1266                                             sizeof(create_cmd),
1267                                             (struct ena_admin_acq_entry *)&cmd_completion,
1268                                             sizeof(cmd_completion));
1269         if (unlikely(ret)) {
1270                 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1271                 return ret;
1272         }
1273
1274         io_sq->idx = cmd_completion.sq_idx;
1275
1276         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1277                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1278
1279         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1280                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1281                                 + cmd_completion.llq_headers_offset);
1282
1283                 io_sq->desc_addr.pbuf_dev_addr =
1284                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1285                         cmd_completion.llq_descriptors_offset);
1286         }
1287
1288         ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1289
1290         return ret;
1291 }
1292
1293 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1294 {
1295         struct ena_rss *rss = &ena_dev->rss;
1296         struct ena_com_io_sq *io_sq;
1297         u16 qid;
1298         int i;
1299
1300         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1301                 qid = rss->host_rss_ind_tbl[i];
1302                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1303                         return ENA_COM_INVAL;
1304
1305                 io_sq = &ena_dev->io_sq_queues[qid];
1306
1307                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1308                         return ENA_COM_INVAL;
1309
1310                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1311         }
1312
1313         return 0;
1314 }
1315
1316 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1317                                                  u16 intr_delay_resolution)
1318 {
1319         u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1320
1321         if (unlikely(!intr_delay_resolution)) {
1322                 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1323                 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1324         }
1325
1326         /* update Rx */
1327         ena_dev->intr_moder_rx_interval =
1328                 ena_dev->intr_moder_rx_interval *
1329                 prev_intr_delay_resolution /
1330                 intr_delay_resolution;
1331
1332         /* update Tx */
1333         ena_dev->intr_moder_tx_interval =
1334                 ena_dev->intr_moder_tx_interval *
1335                 prev_intr_delay_resolution /
1336                 intr_delay_resolution;
1337
1338         ena_dev->intr_delay_resolution = intr_delay_resolution;
1339 }
1340
1341 /*****************************************************************************/
1342 /*******************************      API       ******************************/
1343 /*****************************************************************************/
1344
1345 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1346                                   struct ena_admin_aq_entry *cmd,
1347                                   size_t cmd_size,
1348                                   struct ena_admin_acq_entry *comp,
1349                                   size_t comp_size)
1350 {
1351         struct ena_comp_ctx *comp_ctx;
1352         int ret;
1353
1354         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1355                                             comp, comp_size);
1356         if (IS_ERR(comp_ctx)) {
1357                 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1358                         ena_trc_dbg("Failed to submit command [%ld]\n",
1359                                     PTR_ERR(comp_ctx));
1360                 else
1361                         ena_trc_err("Failed to submit command [%ld]\n",
1362                                     PTR_ERR(comp_ctx));
1363
1364                 return PTR_ERR(comp_ctx);
1365         }
1366
1367         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1368         if (unlikely(ret)) {
1369                 if (admin_queue->running_state)
1370                         ena_trc_err("Failed to process command. ret = %d\n",
1371                                     ret);
1372                 else
1373                         ena_trc_dbg("Failed to process command. ret = %d\n",
1374                                     ret);
1375         }
1376         return ret;
1377 }
1378
1379 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1380                          struct ena_com_io_cq *io_cq)
1381 {
1382         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1383         struct ena_admin_aq_create_cq_cmd create_cmd;
1384         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1385         int ret;
1386
1387         memset(&create_cmd, 0x0, sizeof(create_cmd));
1388
1389         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1390
1391         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1392                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1393         create_cmd.cq_caps_1 |=
1394                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1395
1396         create_cmd.msix_vector = io_cq->msix_vector;
1397         create_cmd.cq_depth = io_cq->q_depth;
1398
1399         ret = ena_com_mem_addr_set(ena_dev,
1400                                    &create_cmd.cq_ba,
1401                                    io_cq->cdesc_addr.phys_addr);
1402         if (unlikely(ret)) {
1403                 ena_trc_err("memory address set failed\n");
1404                 return ret;
1405         }
1406
1407         ret = ena_com_execute_admin_command(admin_queue,
1408                                             (struct ena_admin_aq_entry *)&create_cmd,
1409                                             sizeof(create_cmd),
1410                                             (struct ena_admin_acq_entry *)&cmd_completion,
1411                                             sizeof(cmd_completion));
1412         if (unlikely(ret)) {
1413                 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1414                 return ret;
1415         }
1416
1417         io_cq->idx = cmd_completion.cq_idx;
1418
1419         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1420                 cmd_completion.cq_interrupt_unmask_register_offset);
1421
1422         if (cmd_completion.cq_head_db_register_offset)
1423                 io_cq->cq_head_db_reg =
1424                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1425                         cmd_completion.cq_head_db_register_offset);
1426
1427         if (cmd_completion.numa_node_register_offset)
1428                 io_cq->numa_node_cfg_reg =
1429                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1430                         cmd_completion.numa_node_register_offset);
1431
1432         ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1433
1434         return ret;
1435 }
1436
1437 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1438                             struct ena_com_io_sq **io_sq,
1439                             struct ena_com_io_cq **io_cq)
1440 {
1441         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1442                 ena_trc_err("Invalid queue number %d but the max is %d\n",
1443                             qid, ENA_TOTAL_NUM_QUEUES);
1444                 return ENA_COM_INVAL;
1445         }
1446
1447         *io_sq = &ena_dev->io_sq_queues[qid];
1448         *io_cq = &ena_dev->io_cq_queues[qid];
1449
1450         return 0;
1451 }
1452
1453 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1454 {
1455         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1456         struct ena_comp_ctx *comp_ctx;
1457         u16 i;
1458
1459         if (!admin_queue->comp_ctx)
1460                 return;
1461
1462         for (i = 0; i < admin_queue->q_depth; i++) {
1463                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1464                 if (unlikely(!comp_ctx))
1465                         break;
1466
1467                 comp_ctx->status = ENA_CMD_ABORTED;
1468
1469                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1470         }
1471 }
1472
1473 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1474 {
1475         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1476         unsigned long flags = 0;
1477         u32 exp = 0;
1478
1479         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1480         while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1481                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1482                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1483                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1484         }
1485         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1486 }
1487
1488 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1489                           struct ena_com_io_cq *io_cq)
1490 {
1491         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1492         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1493         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1494         int ret;
1495
1496         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1497
1498         destroy_cmd.cq_idx = io_cq->idx;
1499         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1500
1501         ret = ena_com_execute_admin_command(admin_queue,
1502                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1503                                             sizeof(destroy_cmd),
1504                                             (struct ena_admin_acq_entry *)&destroy_resp,
1505                                             sizeof(destroy_resp));
1506
1507         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1508                 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1509
1510         return ret;
1511 }
1512
1513 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1514 {
1515         return ena_dev->admin_queue.running_state;
1516 }
1517
1518 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1519 {
1520         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1521         unsigned long flags = 0;
1522
1523         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1524         ena_dev->admin_queue.running_state = state;
1525         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1526 }
1527
1528 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1529 {
1530         u16 depth = ena_dev->aenq.q_depth;
1531
1532         ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1533
1534         /* Init head_db to mark that all entries in the queue
1535          * are initially available
1536          */
1537         ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1538 }
1539
1540 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1541 {
1542         struct ena_com_admin_queue *admin_queue;
1543         struct ena_admin_set_feat_cmd cmd;
1544         struct ena_admin_set_feat_resp resp;
1545         struct ena_admin_get_feat_resp get_resp;
1546         int ret;
1547
1548         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1549         if (ret) {
1550                 ena_trc_info("Can't get aenq configuration\n");
1551                 return ret;
1552         }
1553
1554         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1555                 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1556                              get_resp.u.aenq.supported_groups,
1557                              groups_flag);
1558                 return ENA_COM_UNSUPPORTED;
1559         }
1560
1561         memset(&cmd, 0x0, sizeof(cmd));
1562         admin_queue = &ena_dev->admin_queue;
1563
1564         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1565         cmd.aq_common_descriptor.flags = 0;
1566         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1567         cmd.u.aenq.enabled_groups = groups_flag;
1568
1569         ret = ena_com_execute_admin_command(admin_queue,
1570                                             (struct ena_admin_aq_entry *)&cmd,
1571                                             sizeof(cmd),
1572                                             (struct ena_admin_acq_entry *)&resp,
1573                                             sizeof(resp));
1574
1575         if (unlikely(ret))
1576                 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1577
1578         return ret;
1579 }
1580
1581 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1582 {
1583         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1584         int width;
1585
1586         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1587                 ena_trc_err("Reg read timeout occurred\n");
1588                 return ENA_COM_TIMER_EXPIRED;
1589         }
1590
1591         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1592                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1593
1594         ena_trc_dbg("ENA dma width: %d\n", width);
1595
1596         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1597                 ena_trc_err("DMA width illegal value: %d\n", width);
1598                 return ENA_COM_INVAL;
1599         }
1600
1601         ena_dev->dma_addr_bits = width;
1602
1603         return width;
1604 }
1605
1606 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1607 {
1608         u32 ver;
1609         u32 ctrl_ver;
1610         u32 ctrl_ver_masked;
1611
1612         /* Make sure the ENA version and the controller version are at least
1613          * as the driver expects
1614          */
1615         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1616         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1617                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1618
1619         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1620                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1621                 ena_trc_err("Reg read timeout occurred\n");
1622                 return ENA_COM_TIMER_EXPIRED;
1623         }
1624
1625         ena_trc_info("ena device version: %d.%d\n",
1626                      (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1627                      ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1628                      ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1629
1630         ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1631                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1632                      >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1633                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1634                      >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1635                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1636                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1637                      ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1638
1639         ctrl_ver_masked =
1640                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1641                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1642                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1643
1644         /* Validate the ctrl version without the implementation ID */
1645         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1646                 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1647                 return -1;
1648         }
1649
1650         return 0;
1651 }
1652
1653 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1654 {
1655         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1656         struct ena_com_admin_cq *cq = &admin_queue->cq;
1657         struct ena_com_admin_sq *sq = &admin_queue->sq;
1658         struct ena_com_aenq *aenq = &ena_dev->aenq;
1659         u16 size;
1660
1661         if (admin_queue->comp_ctx) {
1662                 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1663                 ENA_MEM_FREE(ena_dev->dmadev,
1664                              admin_queue->comp_ctx,
1665                              (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1666         }
1667
1668         admin_queue->comp_ctx = NULL;
1669         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1670         if (sq->entries)
1671                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1672                                       sq->dma_addr, sq->mem_handle);
1673         sq->entries = NULL;
1674
1675         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1676         if (cq->entries)
1677                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1678                                       cq->dma_addr, cq->mem_handle);
1679         cq->entries = NULL;
1680
1681         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1682         if (ena_dev->aenq.entries)
1683                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1684                                       aenq->dma_addr, aenq->mem_handle);
1685         aenq->entries = NULL;
1686         ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1687 }
1688
1689 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1690 {
1691         u32 mask_value = 0;
1692
1693         if (polling)
1694                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1695
1696         ENA_REG_WRITE32(ena_dev->bus, mask_value,
1697                         ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1698         ena_dev->admin_queue.polling = polling;
1699 }
1700
1701 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1702 {
1703         return ena_dev->admin_queue.polling;
1704 }
1705
1706 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1707                                          bool polling)
1708 {
1709         ena_dev->admin_queue.auto_polling = polling;
1710 }
1711
1712 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1713 {
1714         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1715
1716         ENA_SPINLOCK_INIT(mmio_read->lock);
1717         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1718                                sizeof(*mmio_read->read_resp),
1719                                mmio_read->read_resp,
1720                                mmio_read->read_resp_dma_addr,
1721                                mmio_read->read_resp_mem_handle);
1722         if (unlikely(!mmio_read->read_resp))
1723                 goto err;
1724
1725         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1726
1727         mmio_read->read_resp->req_id = 0x0;
1728         mmio_read->seq_num = 0x0;
1729         mmio_read->readless_supported = true;
1730
1731         return 0;
1732
1733 err:
1734                 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1735                 return ENA_COM_NO_MEM;
1736 }
1737
1738 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1739 {
1740         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1741
1742         mmio_read->readless_supported = readless_supported;
1743 }
1744
1745 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1746 {
1747         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1748
1749         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1750         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1751
1752         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1753                               sizeof(*mmio_read->read_resp),
1754                               mmio_read->read_resp,
1755                               mmio_read->read_resp_dma_addr,
1756                               mmio_read->read_resp_mem_handle);
1757
1758         mmio_read->read_resp = NULL;
1759         ENA_SPINLOCK_DESTROY(mmio_read->lock);
1760 }
1761
1762 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1763 {
1764         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1765         u32 addr_low, addr_high;
1766
1767         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1768         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1769
1770         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1771         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1772 }
1773
1774 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1775                        struct ena_aenq_handlers *aenq_handlers)
1776 {
1777         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1778         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1779         int ret;
1780
1781         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1782
1783         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1784                 ena_trc_err("Reg read timeout occurred\n");
1785                 return ENA_COM_TIMER_EXPIRED;
1786         }
1787
1788         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1789                 ena_trc_err("Device isn't ready, abort com init\n");
1790                 return ENA_COM_NO_DEVICE;
1791         }
1792
1793         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1794
1795         admin_queue->bus = ena_dev->bus;
1796         admin_queue->q_dmadev = ena_dev->dmadev;
1797         admin_queue->polling = false;
1798         admin_queue->curr_cmd_id = 0;
1799
1800         ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1801
1802         ENA_SPINLOCK_INIT(admin_queue->q_lock);
1803
1804         ret = ena_com_init_comp_ctxt(admin_queue);
1805         if (ret)
1806                 goto error;
1807
1808         ret = ena_com_admin_init_sq(admin_queue);
1809         if (ret)
1810                 goto error;
1811
1812         ret = ena_com_admin_init_cq(admin_queue);
1813         if (ret)
1814                 goto error;
1815
1816         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1817                 ENA_REGS_AQ_DB_OFF);
1818
1819         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1820         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1821
1822         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1823         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1824
1825         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1826         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1827
1828         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1829         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1830
1831         aq_caps = 0;
1832         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1833         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1834                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1835                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1836
1837         acq_caps = 0;
1838         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1839         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1840                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1841                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1842
1843         ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1844         ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1845         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1846         if (ret)
1847                 goto error;
1848
1849         admin_queue->ena_dev = ena_dev;
1850         admin_queue->running_state = true;
1851
1852         return 0;
1853 error:
1854         ena_com_admin_destroy(ena_dev);
1855
1856         return ret;
1857 }
1858
1859 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1860                             struct ena_com_create_io_ctx *ctx)
1861 {
1862         struct ena_com_io_sq *io_sq;
1863         struct ena_com_io_cq *io_cq;
1864         int ret;
1865
1866         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1867                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1868                             ctx->qid, ENA_TOTAL_NUM_QUEUES);
1869                 return ENA_COM_INVAL;
1870         }
1871
1872         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1873         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1874
1875         memset(io_sq, 0x0, sizeof(*io_sq));
1876         memset(io_cq, 0x0, sizeof(*io_cq));
1877
1878         /* Init CQ */
1879         io_cq->q_depth = ctx->queue_size;
1880         io_cq->direction = ctx->direction;
1881         io_cq->qid = ctx->qid;
1882
1883         io_cq->msix_vector = ctx->msix_vector;
1884
1885         io_sq->q_depth = ctx->queue_size;
1886         io_sq->direction = ctx->direction;
1887         io_sq->qid = ctx->qid;
1888
1889         io_sq->mem_queue_type = ctx->mem_queue_type;
1890
1891         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1892                 /* header length is limited to 8 bits */
1893                 io_sq->tx_max_header_size =
1894                         ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1895
1896         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1897         if (ret)
1898                 goto error;
1899         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1900         if (ret)
1901                 goto error;
1902
1903         ret = ena_com_create_io_cq(ena_dev, io_cq);
1904         if (ret)
1905                 goto error;
1906
1907         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1908         if (ret)
1909                 goto destroy_io_cq;
1910
1911         return 0;
1912
1913 destroy_io_cq:
1914         ena_com_destroy_io_cq(ena_dev, io_cq);
1915 error:
1916         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1917         return ret;
1918 }
1919
1920 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1921 {
1922         struct ena_com_io_sq *io_sq;
1923         struct ena_com_io_cq *io_cq;
1924
1925         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1926                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1927                             qid, ENA_TOTAL_NUM_QUEUES);
1928                 return;
1929         }
1930
1931         io_sq = &ena_dev->io_sq_queues[qid];
1932         io_cq = &ena_dev->io_cq_queues[qid];
1933
1934         ena_com_destroy_io_sq(ena_dev, io_sq);
1935         ena_com_destroy_io_cq(ena_dev, io_cq);
1936
1937         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1938 }
1939
1940 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1941                             struct ena_admin_get_feat_resp *resp)
1942 {
1943         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1944 }
1945
1946 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1947                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1948 {
1949         struct ena_admin_get_feat_resp get_resp;
1950         int rc;
1951
1952         rc = ena_com_get_feature(ena_dev, &get_resp,
1953                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1954         if (rc)
1955                 return rc;
1956
1957         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1958                sizeof(get_resp.u.dev_attr));
1959         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1960
1961         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1962                 rc = ena_com_get_feature(ena_dev, &get_resp,
1963                                          ENA_ADMIN_MAX_QUEUES_EXT,
1964                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
1965                 if (rc)
1966                         return rc;
1967
1968                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1969                         return -EINVAL;
1970
1971                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1972                        sizeof(get_resp.u.max_queue_ext));
1973                 ena_dev->tx_max_header_size =
1974                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1975         } else {
1976                 rc = ena_com_get_feature(ena_dev, &get_resp,
1977                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
1978                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1979                        sizeof(get_resp.u.max_queue));
1980                 ena_dev->tx_max_header_size =
1981                         get_resp.u.max_queue.max_header_size;
1982
1983                 if (rc)
1984                         return rc;
1985         }
1986
1987         rc = ena_com_get_feature(ena_dev, &get_resp,
1988                                  ENA_ADMIN_AENQ_CONFIG, 0);
1989         if (rc)
1990                 return rc;
1991
1992         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1993                sizeof(get_resp.u.aenq));
1994
1995         rc = ena_com_get_feature(ena_dev, &get_resp,
1996                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1997         if (rc)
1998                 return rc;
1999
2000         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
2001                sizeof(get_resp.u.offload));
2002
2003         /* Driver hints isn't mandatory admin command. So in case the
2004          * command isn't supported set driver hints to 0
2005          */
2006         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2007
2008         if (!rc)
2009                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2010                        sizeof(get_resp.u.hw_hints));
2011         else if (rc == ENA_COM_UNSUPPORTED)
2012                 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2013         else
2014                 return rc;
2015
2016         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2017         if (!rc)
2018                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2019                        sizeof(get_resp.u.llq));
2020         else if (rc == ENA_COM_UNSUPPORTED)
2021                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2022         else
2023                 return rc;
2024
2025         rc = ena_com_get_feature(ena_dev, &get_resp,
2026                                  ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2027         if (!rc)
2028                 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2029                        sizeof(get_resp.u.ind_table));
2030         else if (rc == ENA_COM_UNSUPPORTED)
2031                 memset(&get_feat_ctx->ind_table, 0x0,
2032                        sizeof(get_feat_ctx->ind_table));
2033         else
2034                 return rc;
2035
2036         return 0;
2037 }
2038
2039 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2040 {
2041         ena_com_handle_admin_completion(&ena_dev->admin_queue);
2042 }
2043
2044 /* ena_handle_specific_aenq_event:
2045  * return the handler that is relevant to the specific event group
2046  */
2047 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2048                                                      u16 group)
2049 {
2050         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2051
2052         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2053                 return aenq_handlers->handlers[group];
2054
2055         return aenq_handlers->unimplemented_handler;
2056 }
2057
2058 /* ena_aenq_intr_handler:
2059  * handles the aenq incoming events.
2060  * pop events from the queue and apply the specific handler
2061  */
2062 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2063 {
2064         struct ena_admin_aenq_entry *aenq_e;
2065         struct ena_admin_aenq_common_desc *aenq_common;
2066         struct ena_com_aenq *aenq  = &dev->aenq;
2067         u64 timestamp;
2068         ena_aenq_handler handler_cb;
2069         u16 masked_head, processed = 0;
2070         u8 phase;
2071
2072         masked_head = aenq->head & (aenq->q_depth - 1);
2073         phase = aenq->phase;
2074         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2075         aenq_common = &aenq_e->aenq_common_desc;
2076
2077         /* Go over all the events */
2078         while ((READ_ONCE8(aenq_common->flags) &
2079                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2080                 /* Make sure the phase bit (ownership) is as expected before
2081                  * reading the rest of the descriptor.
2082                  */
2083                 dma_rmb();
2084
2085                 timestamp = (u64)aenq_common->timestamp_low |
2086                         ((u64)aenq_common->timestamp_high << 32);
2087                 ENA_TOUCH(timestamp); /* In case debug is disabled */
2088                 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2089                             aenq_common->group,
2090                             aenq_common->syndrom,
2091                             timestamp);
2092
2093                 /* Handle specific event*/
2094                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2095                                                           aenq_common->group);
2096                 handler_cb(data, aenq_e); /* call the actual event handler*/
2097
2098                 /* Get next event entry */
2099                 masked_head++;
2100                 processed++;
2101
2102                 if (unlikely(masked_head == aenq->q_depth)) {
2103                         masked_head = 0;
2104                         phase = !phase;
2105                 }
2106                 aenq_e = &aenq->entries[masked_head];
2107                 aenq_common = &aenq_e->aenq_common_desc;
2108         }
2109
2110         aenq->head += processed;
2111         aenq->phase = phase;
2112
2113         /* Don't update aenq doorbell if there weren't any processed events */
2114         if (!processed)
2115                 return;
2116
2117         /* write the aenq doorbell after all AENQ descriptors were read */
2118         mb();
2119         ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2120                                 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2121         mmiowb();
2122 }
2123
2124 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2125                       enum ena_regs_reset_reason_types reset_reason)
2126 {
2127         u32 stat, timeout, cap, reset_val;
2128         int rc;
2129
2130         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2131         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2132
2133         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2134                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2135                 ena_trc_err("Reg read32 timeout occurred\n");
2136                 return ENA_COM_TIMER_EXPIRED;
2137         }
2138
2139         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2140                 ena_trc_err("Device isn't ready, can't reset device\n");
2141                 return ENA_COM_INVAL;
2142         }
2143
2144         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2145                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2146         if (timeout == 0) {
2147                 ena_trc_err("Invalid timeout value\n");
2148                 return ENA_COM_INVAL;
2149         }
2150
2151         /* start reset */
2152         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2153         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2154                         ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2155         ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2156
2157         /* Write again the MMIO read request address */
2158         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2159
2160         rc = wait_for_reset_state(ena_dev, timeout,
2161                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2162         if (rc != 0) {
2163                 ena_trc_err("Reset indication didn't turn on\n");
2164                 return rc;
2165         }
2166
2167         /* reset done */
2168         ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2169         rc = wait_for_reset_state(ena_dev, timeout, 0);
2170         if (rc != 0) {
2171                 ena_trc_err("Reset indication didn't turn off\n");
2172                 return rc;
2173         }
2174
2175         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2176                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2177         if (timeout)
2178                 /* the resolution of timeout reg is 100ms */
2179                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2180         else
2181                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2182
2183         return 0;
2184 }
2185
2186 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2187                              struct ena_com_stats_ctx *ctx,
2188                              enum ena_admin_get_stats_type type)
2189 {
2190         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2191         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2192         struct ena_com_admin_queue *admin_queue;
2193         int ret;
2194
2195         admin_queue = &ena_dev->admin_queue;
2196
2197         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2198         get_cmd->aq_common_descriptor.flags = 0;
2199         get_cmd->type = type;
2200
2201         ret =  ena_com_execute_admin_command(admin_queue,
2202                                              (struct ena_admin_aq_entry *)get_cmd,
2203                                              sizeof(*get_cmd),
2204                                              (struct ena_admin_acq_entry *)get_resp,
2205                                              sizeof(*get_resp));
2206
2207         if (unlikely(ret))
2208                 ena_trc_err("Failed to get stats. error: %d\n", ret);
2209
2210         return ret;
2211 }
2212
2213 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
2214                           struct ena_admin_eni_stats *stats)
2215 {
2216         struct ena_com_stats_ctx ctx;
2217         int ret;
2218
2219         memset(&ctx, 0x0, sizeof(ctx));
2220         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
2221         if (likely(ret == 0))
2222                 memcpy(stats, &ctx.get_resp.u.eni_stats,
2223                        sizeof(ctx.get_resp.u.eni_stats));
2224
2225         return ret;
2226 }
2227
2228 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2229                                 struct ena_admin_basic_stats *stats)
2230 {
2231         struct ena_com_stats_ctx ctx;
2232         int ret;
2233
2234         memset(&ctx, 0x0, sizeof(ctx));
2235         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2236         if (likely(ret == 0))
2237                 memcpy(stats, &ctx.get_resp.u.basic_stats,
2238                        sizeof(ctx.get_resp.u.basic_stats));
2239
2240         return ret;
2241 }
2242
2243 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2244 {
2245         struct ena_com_admin_queue *admin_queue;
2246         struct ena_admin_set_feat_cmd cmd;
2247         struct ena_admin_set_feat_resp resp;
2248         int ret;
2249
2250         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2251                 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2252                 return ENA_COM_UNSUPPORTED;
2253         }
2254
2255         memset(&cmd, 0x0, sizeof(cmd));
2256         admin_queue = &ena_dev->admin_queue;
2257
2258         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2259         cmd.aq_common_descriptor.flags = 0;
2260         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2261         cmd.u.mtu.mtu = mtu;
2262
2263         ret = ena_com_execute_admin_command(admin_queue,
2264                                             (struct ena_admin_aq_entry *)&cmd,
2265                                             sizeof(cmd),
2266                                             (struct ena_admin_acq_entry *)&resp,
2267                                             sizeof(resp));
2268
2269         if (unlikely(ret))
2270                 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2271
2272         return ret;
2273 }
2274
2275 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2276                                  struct ena_admin_feature_offload_desc *offload)
2277 {
2278         int ret;
2279         struct ena_admin_get_feat_resp resp;
2280
2281         ret = ena_com_get_feature(ena_dev, &resp,
2282                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2283         if (unlikely(ret)) {
2284                 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2285                 return ret;
2286         }
2287
2288         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2289
2290         return 0;
2291 }
2292
2293 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2294 {
2295         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2296         struct ena_rss *rss = &ena_dev->rss;
2297         struct ena_admin_set_feat_cmd cmd;
2298         struct ena_admin_set_feat_resp resp;
2299         struct ena_admin_get_feat_resp get_resp;
2300         int ret;
2301
2302         if (!ena_com_check_supported_feature_id(ena_dev,
2303                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2304                 ena_trc_dbg("Feature %d isn't supported\n",
2305                             ENA_ADMIN_RSS_HASH_FUNCTION);
2306                 return ENA_COM_UNSUPPORTED;
2307         }
2308
2309         /* Validate hash function is supported */
2310         ret = ena_com_get_feature(ena_dev, &get_resp,
2311                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2312         if (unlikely(ret))
2313                 return ret;
2314
2315         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2316                 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2317                             rss->hash_func);
2318                 return ENA_COM_UNSUPPORTED;
2319         }
2320
2321         memset(&cmd, 0x0, sizeof(cmd));
2322
2323         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2324         cmd.aq_common_descriptor.flags =
2325                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2326         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2327         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2328         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2329
2330         ret = ena_com_mem_addr_set(ena_dev,
2331                                    &cmd.control_buffer.address,
2332                                    rss->hash_key_dma_addr);
2333         if (unlikely(ret)) {
2334                 ena_trc_err("memory address set failed\n");
2335                 return ret;
2336         }
2337
2338         cmd.control_buffer.length = sizeof(*rss->hash_key);
2339
2340         ret = ena_com_execute_admin_command(admin_queue,
2341                                             (struct ena_admin_aq_entry *)&cmd,
2342                                             sizeof(cmd),
2343                                             (struct ena_admin_acq_entry *)&resp,
2344                                             sizeof(resp));
2345         if (unlikely(ret)) {
2346                 ena_trc_err("Failed to set hash function %d. error: %d\n",
2347                             rss->hash_func, ret);
2348                 return ENA_COM_INVAL;
2349         }
2350
2351         return 0;
2352 }
2353
2354 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2355                                enum ena_admin_hash_functions func,
2356                                const u8 *key, u16 key_len, u32 init_val)
2357 {
2358         struct ena_admin_feature_rss_flow_hash_control *hash_key;
2359         struct ena_admin_get_feat_resp get_resp;
2360         enum ena_admin_hash_functions old_func;
2361         struct ena_rss *rss = &ena_dev->rss;
2362         int rc;
2363
2364         hash_key = rss->hash_key;
2365
2366         /* Make sure size is a mult of DWs */
2367         if (unlikely(key_len & 0x3))
2368                 return ENA_COM_INVAL;
2369
2370         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2371                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2372                                     rss->hash_key_dma_addr,
2373                                     sizeof(*rss->hash_key), 0);
2374         if (unlikely(rc))
2375                 return rc;
2376
2377         if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2378                 ena_trc_err("Flow hash function %d isn't supported\n", func);
2379                 return ENA_COM_UNSUPPORTED;
2380         }
2381
2382         switch (func) {
2383         case ENA_ADMIN_TOEPLITZ:
2384                 if (key) {
2385                         if (key_len != sizeof(hash_key->key)) {
2386                                 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2387                                              key_len, sizeof(hash_key->key));
2388                                 return ENA_COM_INVAL;
2389                         }
2390                         memcpy(hash_key->key, key, key_len);
2391                         rss->hash_init_val = init_val;
2392                         hash_key->keys_num = key_len / sizeof(u32);
2393                 }
2394                 break;
2395         case ENA_ADMIN_CRC32:
2396                 rss->hash_init_val = init_val;
2397                 break;
2398         default:
2399                 ena_trc_err("Invalid hash function (%d)\n", func);
2400                 return ENA_COM_INVAL;
2401         }
2402
2403         old_func = rss->hash_func;
2404         rss->hash_func = func;
2405         rc = ena_com_set_hash_function(ena_dev);
2406
2407         /* Restore the old function */
2408         if (unlikely(rc))
2409                 rss->hash_func = old_func;
2410
2411         return rc;
2412 }
2413
2414 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2415                               enum ena_admin_hash_functions *func)
2416 {
2417         struct ena_rss *rss = &ena_dev->rss;
2418         struct ena_admin_get_feat_resp get_resp;
2419         int rc;
2420
2421         if (unlikely(!func))
2422                 return ENA_COM_INVAL;
2423
2424         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2425                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2426                                     rss->hash_key_dma_addr,
2427                                     sizeof(*rss->hash_key), 0);
2428         if (unlikely(rc))
2429                 return rc;
2430
2431         /* ENA_FFS() returns 1 in case the lsb is set */
2432         rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2433         if (rss->hash_func)
2434                 rss->hash_func--;
2435
2436         *func = rss->hash_func;
2437
2438         return 0;
2439 }
2440
2441 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2442 {
2443         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2444                 ena_dev->rss.hash_key;
2445
2446         if (key)
2447                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2448
2449         return 0;
2450 }
2451
2452 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2453                           enum ena_admin_flow_hash_proto proto,
2454                           u16 *fields)
2455 {
2456         struct ena_rss *rss = &ena_dev->rss;
2457         struct ena_admin_get_feat_resp get_resp;
2458         int rc;
2459
2460         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2461                                     ENA_ADMIN_RSS_HASH_INPUT,
2462                                     rss->hash_ctrl_dma_addr,
2463                                     sizeof(*rss->hash_ctrl), 0);
2464         if (unlikely(rc))
2465                 return rc;
2466
2467         if (fields)
2468                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2469
2470         return 0;
2471 }
2472
2473 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2474 {
2475         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2476         struct ena_rss *rss = &ena_dev->rss;
2477         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2478         struct ena_admin_set_feat_cmd cmd;
2479         struct ena_admin_set_feat_resp resp;
2480         int ret;
2481
2482         if (!ena_com_check_supported_feature_id(ena_dev,
2483                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2484                 ena_trc_dbg("Feature %d isn't supported\n",
2485                             ENA_ADMIN_RSS_HASH_INPUT);
2486                 return ENA_COM_UNSUPPORTED;
2487         }
2488
2489         memset(&cmd, 0x0, sizeof(cmd));
2490
2491         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2492         cmd.aq_common_descriptor.flags =
2493                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2494         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2495         cmd.u.flow_hash_input.enabled_input_sort =
2496                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2497                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2498
2499         ret = ena_com_mem_addr_set(ena_dev,
2500                                    &cmd.control_buffer.address,
2501                                    rss->hash_ctrl_dma_addr);
2502         if (unlikely(ret)) {
2503                 ena_trc_err("memory address set failed\n");
2504                 return ret;
2505         }
2506         cmd.control_buffer.length = sizeof(*hash_ctrl);
2507
2508         ret = ena_com_execute_admin_command(admin_queue,
2509                                             (struct ena_admin_aq_entry *)&cmd,
2510                                             sizeof(cmd),
2511                                             (struct ena_admin_acq_entry *)&resp,
2512                                             sizeof(resp));
2513         if (unlikely(ret))
2514                 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2515
2516         return ret;
2517 }
2518
2519 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2520 {
2521         struct ena_rss *rss = &ena_dev->rss;
2522         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2523                 rss->hash_ctrl;
2524         u16 available_fields = 0;
2525         int rc, i;
2526
2527         /* Get the supported hash input */
2528         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2529         if (unlikely(rc))
2530                 return rc;
2531
2532         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2533                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2534                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2535
2536         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2537                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2538                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2539
2540         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2541                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2542                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2543
2544         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2545                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2546                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2547
2548         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2549                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2550
2551         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2552                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2553
2554         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2555                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2556
2557         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2558                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2559
2560         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2561                 available_fields = hash_ctrl->selected_fields[i].fields &
2562                                 hash_ctrl->supported_fields[i].fields;
2563                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2564                         ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2565                                     i, hash_ctrl->supported_fields[i].fields,
2566                                     hash_ctrl->selected_fields[i].fields);
2567                         return ENA_COM_UNSUPPORTED;
2568                 }
2569         }
2570
2571         rc = ena_com_set_hash_ctrl(ena_dev);
2572
2573         /* In case of failure, restore the old hash ctrl */
2574         if (unlikely(rc))
2575                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2576
2577         return rc;
2578 }
2579
2580 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2581                            enum ena_admin_flow_hash_proto proto,
2582                            u16 hash_fields)
2583 {
2584         struct ena_rss *rss = &ena_dev->rss;
2585         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2586         u16 supported_fields;
2587         int rc;
2588
2589         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2590                 ena_trc_err("Invalid proto num (%u)\n", proto);
2591                 return ENA_COM_INVAL;
2592         }
2593
2594         /* Get the ctrl table */
2595         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2596         if (unlikely(rc))
2597                 return rc;
2598
2599         /* Make sure all the fields are supported */
2600         supported_fields = hash_ctrl->supported_fields[proto].fields;
2601         if ((hash_fields & supported_fields) != hash_fields) {
2602                 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2603                             proto, hash_fields, supported_fields);
2604         }
2605
2606         hash_ctrl->selected_fields[proto].fields = hash_fields;
2607
2608         rc = ena_com_set_hash_ctrl(ena_dev);
2609
2610         /* In case of failure, restore the old hash ctrl */
2611         if (unlikely(rc))
2612                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2613
2614         return 0;
2615 }
2616
2617 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2618                                       u16 entry_idx, u16 entry_value)
2619 {
2620         struct ena_rss *rss = &ena_dev->rss;
2621
2622         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2623                 return ENA_COM_INVAL;
2624
2625         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2626                 return ENA_COM_INVAL;
2627
2628         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2629
2630         return 0;
2631 }
2632
2633 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2634 {
2635         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2636         struct ena_rss *rss = &ena_dev->rss;
2637         struct ena_admin_set_feat_cmd cmd;
2638         struct ena_admin_set_feat_resp resp;
2639         int ret;
2640
2641         if (!ena_com_check_supported_feature_id(ena_dev,
2642                                                 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2643                 ena_trc_dbg("Feature %d isn't supported\n",
2644                             ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2645                 return ENA_COM_UNSUPPORTED;
2646         }
2647
2648         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2649         if (ret) {
2650                 ena_trc_err("Failed to convert host indirection table to device table\n");
2651                 return ret;
2652         }
2653
2654         memset(&cmd, 0x0, sizeof(cmd));
2655
2656         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2657         cmd.aq_common_descriptor.flags =
2658                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2659         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2660         cmd.u.ind_table.size = rss->tbl_log_size;
2661         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2662
2663         ret = ena_com_mem_addr_set(ena_dev,
2664                                    &cmd.control_buffer.address,
2665                                    rss->rss_ind_tbl_dma_addr);
2666         if (unlikely(ret)) {
2667                 ena_trc_err("memory address set failed\n");
2668                 return ret;
2669         }
2670
2671         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2672                 sizeof(struct ena_admin_rss_ind_table_entry);
2673
2674         ret = ena_com_execute_admin_command(admin_queue,
2675                                             (struct ena_admin_aq_entry *)&cmd,
2676                                             sizeof(cmd),
2677                                             (struct ena_admin_acq_entry *)&resp,
2678                                             sizeof(resp));
2679
2680         if (unlikely(ret))
2681                 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2682
2683         return ret;
2684 }
2685
2686 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2687 {
2688         struct ena_rss *rss = &ena_dev->rss;
2689         struct ena_admin_get_feat_resp get_resp;
2690         u32 tbl_size;
2691         int i, rc;
2692
2693         tbl_size = (1ULL << rss->tbl_log_size) *
2694                 sizeof(struct ena_admin_rss_ind_table_entry);
2695
2696         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2697                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2698                                     rss->rss_ind_tbl_dma_addr,
2699                                     tbl_size, 0);
2700         if (unlikely(rc))
2701                 return rc;
2702
2703         if (!ind_tbl)
2704                 return 0;
2705
2706         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2707                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2708
2709         return 0;
2710 }
2711
2712 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2713 {
2714         int rc;
2715
2716         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2717
2718         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2719         if (unlikely(rc))
2720                 goto err_indr_tbl;
2721
2722         rc = ena_com_hash_key_allocate(ena_dev);
2723         if (unlikely(rc))
2724                 goto err_hash_key;
2725
2726         ena_com_hash_key_fill_default_key(ena_dev);
2727
2728         rc = ena_com_hash_ctrl_init(ena_dev);
2729         if (unlikely(rc))
2730                 goto err_hash_ctrl;
2731
2732         return 0;
2733
2734 err_hash_ctrl:
2735         ena_com_hash_key_destroy(ena_dev);
2736 err_hash_key:
2737         ena_com_indirect_table_destroy(ena_dev);
2738 err_indr_tbl:
2739
2740         return rc;
2741 }
2742
2743 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2744 {
2745         ena_com_indirect_table_destroy(ena_dev);
2746         ena_com_hash_key_destroy(ena_dev);
2747         ena_com_hash_ctrl_destroy(ena_dev);
2748
2749         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2750 }
2751
2752 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2753 {
2754         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2755
2756         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2757                                SZ_4K,
2758                                host_attr->host_info,
2759                                host_attr->host_info_dma_addr,
2760                                host_attr->host_info_dma_handle);
2761         if (unlikely(!host_attr->host_info))
2762                 return ENA_COM_NO_MEM;
2763
2764         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2765                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2766                 (ENA_COMMON_SPEC_VERSION_MINOR));
2767
2768         return 0;
2769 }
2770
2771 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2772                                 u32 debug_area_size)
2773 {
2774         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2775
2776         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2777                                debug_area_size,
2778                                host_attr->debug_area_virt_addr,
2779                                host_attr->debug_area_dma_addr,
2780                                host_attr->debug_area_dma_handle);
2781         if (unlikely(!host_attr->debug_area_virt_addr)) {
2782                 host_attr->debug_area_size = 0;
2783                 return ENA_COM_NO_MEM;
2784         }
2785
2786         host_attr->debug_area_size = debug_area_size;
2787
2788         return 0;
2789 }
2790
2791 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2792 {
2793         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2794
2795         if (host_attr->host_info) {
2796                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2797                                       SZ_4K,
2798                                       host_attr->host_info,
2799                                       host_attr->host_info_dma_addr,
2800                                       host_attr->host_info_dma_handle);
2801                 host_attr->host_info = NULL;
2802         }
2803 }
2804
2805 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2806 {
2807         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2808
2809         if (host_attr->debug_area_virt_addr) {
2810                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2811                                       host_attr->debug_area_size,
2812                                       host_attr->debug_area_virt_addr,
2813                                       host_attr->debug_area_dma_addr,
2814                                       host_attr->debug_area_dma_handle);
2815                 host_attr->debug_area_virt_addr = NULL;
2816         }
2817 }
2818
2819 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2820 {
2821         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2822         struct ena_com_admin_queue *admin_queue;
2823         struct ena_admin_set_feat_cmd cmd;
2824         struct ena_admin_set_feat_resp resp;
2825
2826         int ret;
2827
2828         /* Host attribute config is called before ena_com_get_dev_attr_feat
2829          * so ena_com can't check if the feature is supported.
2830          */
2831
2832         memset(&cmd, 0x0, sizeof(cmd));
2833         admin_queue = &ena_dev->admin_queue;
2834
2835         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2836         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2837
2838         ret = ena_com_mem_addr_set(ena_dev,
2839                                    &cmd.u.host_attr.debug_ba,
2840                                    host_attr->debug_area_dma_addr);
2841         if (unlikely(ret)) {
2842                 ena_trc_err("memory address set failed\n");
2843                 return ret;
2844         }
2845
2846         ret = ena_com_mem_addr_set(ena_dev,
2847                                    &cmd.u.host_attr.os_info_ba,
2848                                    host_attr->host_info_dma_addr);
2849         if (unlikely(ret)) {
2850                 ena_trc_err("memory address set failed\n");
2851                 return ret;
2852         }
2853
2854         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2855
2856         ret = ena_com_execute_admin_command(admin_queue,
2857                                             (struct ena_admin_aq_entry *)&cmd,
2858                                             sizeof(cmd),
2859                                             (struct ena_admin_acq_entry *)&resp,
2860                                             sizeof(resp));
2861
2862         if (unlikely(ret))
2863                 ena_trc_err("Failed to set host attributes: %d\n", ret);
2864
2865         return ret;
2866 }
2867
2868 /* Interrupt moderation */
2869 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2870 {
2871         return ena_com_check_supported_feature_id(ena_dev,
2872                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2873 }
2874
2875 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2876                                                           u32 intr_delay_resolution,
2877                                                           u32 *intr_moder_interval)
2878 {
2879         if (!intr_delay_resolution) {
2880                 ena_trc_err("Illegal interrupt delay granularity value\n");
2881                 return ENA_COM_FAULT;
2882         }
2883
2884         *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2885
2886         return 0;
2887 }
2888
2889
2890 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2891                                                       u32 tx_coalesce_usecs)
2892 {
2893         return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2894                                                               ena_dev->intr_delay_resolution,
2895                                                               &ena_dev->intr_moder_tx_interval);
2896 }
2897
2898 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2899                                                       u32 rx_coalesce_usecs)
2900 {
2901         return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2902                                                               ena_dev->intr_delay_resolution,
2903                                                               &ena_dev->intr_moder_rx_interval);
2904 }
2905
2906 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2907 {
2908         struct ena_admin_get_feat_resp get_resp;
2909         u16 delay_resolution;
2910         int rc;
2911
2912         rc = ena_com_get_feature(ena_dev, &get_resp,
2913                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2914
2915         if (rc) {
2916                 if (rc == ENA_COM_UNSUPPORTED) {
2917                         ena_trc_dbg("Feature %d isn't supported\n",
2918                                     ENA_ADMIN_INTERRUPT_MODERATION);
2919                         rc = 0;
2920                 } else {
2921                         ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2922                                     rc);
2923                 }
2924
2925                 /* no moderation supported, disable adaptive support */
2926                 ena_com_disable_adaptive_moderation(ena_dev);
2927                 return rc;
2928         }
2929
2930         /* if moderation is supported by device we set adaptive moderation */
2931         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2932         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2933
2934         /* Disable adaptive moderation by default - can be enabled later */
2935         ena_com_disable_adaptive_moderation(ena_dev);
2936
2937         return 0;
2938 }
2939
2940 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2941 {
2942         return ena_dev->intr_moder_tx_interval;
2943 }
2944
2945 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2946 {
2947         return ena_dev->intr_moder_rx_interval;
2948 }
2949
2950 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2951                             struct ena_admin_feature_llq_desc *llq_features,
2952                             struct ena_llq_configurations *llq_default_cfg)
2953 {
2954         int rc;
2955         struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2956
2957         if (!llq_features->max_llq_num) {
2958                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2959                 return 0;
2960         }
2961
2962         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2963         if (rc)
2964                 return rc;
2965
2966         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2967                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2968
2969         if (ena_dev->tx_max_header_size == 0) {
2970                 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2971                 return -EINVAL;
2972         }
2973
2974         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2975
2976         return 0;
2977 }