drivers/net/ena/base/ena_com.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include "ena_com.h"
   7
   8 /*****************************************************************************/
   9 /*****************************************************************************/
  10
  11 /* Timeout in micro-sec */
  12 #define ADMIN_CMD_TIMEOUT_US (3000000)
  13
  14 #define ENA_ASYNC_QUEUE_DEPTH 16
  15 #define ENA_ADMIN_QUEUE_DEPTH 32
  16
  17 #define ENA_CTRL_MAJOR          0
  18 #define ENA_CTRL_MINOR          0
  19 #define ENA_CTRL_SUB_MINOR      1
  20
  21 #define MIN_ENA_CTRL_VER \
  22         (((ENA_CTRL_MAJOR) << \
  23         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  24         ((ENA_CTRL_MINOR) << \
  25         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  26         (ENA_CTRL_SUB_MINOR))
  27
  28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  30
  31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  32
  33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  34
  35 #define ENA_REGS_ADMIN_INTR_MASK 1
  36
  37 #define ENA_POLL_MS     5
  38
  39 /*****************************************************************************/
  40 /*****************************************************************************/
  41 /*****************************************************************************/
  42
  43 enum ena_cmd_status {
  44         ENA_CMD_SUBMITTED,
  45         ENA_CMD_COMPLETED,
  46         /* Abort - canceled by the driver */
  47         ENA_CMD_ABORTED,
  48 };
  49
  50 struct ena_comp_ctx {
  51         ena_wait_event_t wait_event;
  52         struct ena_admin_acq_entry *user_cqe;
  53         u32 comp_size;
  54         enum ena_cmd_status status;
  55         /* status from the device */
  56         u8 comp_status;
  57         u8 cmd_opcode;
  58         bool occupied;
  59 };
  60
  61 struct ena_com_stats_ctx {
  62         struct ena_admin_aq_get_stats_cmd get_cmd;
  63         struct ena_admin_acq_get_stats_resp get_resp;
  64 };
  65
  66 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  67                                        struct ena_common_mem_addr *ena_addr,
  68                                        dma_addr_t addr)
  69 {
  70         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  71                 ena_trc_err("dma address has more bits that the device supports\n");
  72                 return ENA_COM_INVAL;
  73         }
  74
  75         ena_addr->mem_addr_low = lower_32_bits(addr);
  76         ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
  77
  78         return 0;
  79 }
  80
  81 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
  82 {
  83         struct ena_com_admin_sq *sq = &queue->sq;
  84         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
  85
  86         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
  87                                sq->mem_handle);
  88
  89         if (!sq->entries) {
  90                 ena_trc_err("memory allocation failed\n");
  91                 return ENA_COM_NO_MEM;
  92         }
  93
  94         sq->head = 0;
  95         sq->tail = 0;
  96         sq->phase = 1;
  97
  98         sq->db_addr = NULL;
  99
 100         return 0;
 101 }
 102
 103 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 104 {
 105         struct ena_com_admin_cq *cq = &queue->cq;
 106         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 107
 108         ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
 109                                cq->mem_handle);
 110
 111         if (!cq->entries)  {
 112                 ena_trc_err("memory allocation failed\n");
 113                 return ENA_COM_NO_MEM;
 114         }
 115
 116         cq->head = 0;
 117         cq->phase = 1;
 118
 119         return 0;
 120 }
 121
 122 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 123                                    struct ena_aenq_handlers *aenq_handlers)
 124 {
 125         struct ena_com_aenq *aenq = &dev->aenq;
 126         u32 addr_low, addr_high, aenq_caps;
 127         u16 size;
 128
 129         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 130         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 131         ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
 132                         aenq->entries,
 133                         aenq->dma_addr,
 134                         aenq->mem_handle);
 135
 136         if (!aenq->entries) {
 137                 ena_trc_err("memory allocation failed\n");
 138                 return ENA_COM_NO_MEM;
 139         }
 140
 141         aenq->head = aenq->q_depth;
 142         aenq->phase = 1;
 143
 144         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 145         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 146
 147         ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 148         ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 149
 150         aenq_caps = 0;
 151         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 152         aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
 153                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 154                 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 155         ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 156
 157         if (unlikely(!aenq_handlers)) {
 158                 ena_trc_err("aenq handlers pointer is NULL\n");
 159                 return ENA_COM_INVAL;
 160         }
 161
 162         aenq->aenq_handlers = aenq_handlers;
 163
 164         return 0;
 165 }
 166
 167 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 168                                      struct ena_comp_ctx *comp_ctx)
 169 {
 170         comp_ctx->occupied = false;
 171         ATOMIC32_DEC(&queue->outstanding_cmds);
 172 }
 173
 174 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 175                                           u16 command_id, bool capture)
 176 {
 177         if (unlikely(command_id >= queue->q_depth)) {
 178                 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 179                             command_id, queue->q_depth);
 180                 return NULL;
 181         }
 182
 183         if (unlikely(!queue->comp_ctx)) {
 184                 ena_trc_err("Completion context is NULL\n");
 185                 return NULL;
 186         }
 187
 188         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 189                 ena_trc_err("Completion context is occupied\n");
 190                 return NULL;
 191         }
 192
 193         if (capture) {
 194                 ATOMIC32_INC(&queue->outstanding_cmds);
 195                 queue->comp_ctx[command_id].occupied = true;
 196         }
 197
 198         return &queue->comp_ctx[command_id];
 199 }
 200
 201 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 202                                                        struct ena_admin_aq_entry *cmd,
 203                                                        size_t cmd_size_in_bytes,
 204                                                        struct ena_admin_acq_entry *comp,
 205                                                        size_t comp_size_in_bytes)
 206 {
 207         struct ena_comp_ctx *comp_ctx;
 208         u16 tail_masked, cmd_id;
 209         u16 queue_size_mask;
 210         u16 cnt;
 211
 212         queue_size_mask = admin_queue->q_depth - 1;
 213
 214         tail_masked = admin_queue->sq.tail & queue_size_mask;
 215
 216         /* In case of queue FULL */
 217         cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
 218         if (cnt >= admin_queue->q_depth) {
 219                 ena_trc_dbg("admin queue is full.\n");
 220                 admin_queue->stats.out_of_space++;
 221                 return ERR_PTR(ENA_COM_NO_SPACE);
 222         }
 223
 224         cmd_id = admin_queue->curr_cmd_id;
 225
 226         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 227                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 228
 229         cmd->aq_common_descriptor.command_id |= cmd_id &
 230                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 231
 232         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 233         if (unlikely(!comp_ctx))
 234                 return ERR_PTR(ENA_COM_INVAL);
 235
 236         comp_ctx->status = ENA_CMD_SUBMITTED;
 237         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 238         comp_ctx->user_cqe = comp;
 239         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 240
 241         ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
 242
 243         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 244
 245         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 246                 queue_size_mask;
 247
 248         admin_queue->sq.tail++;
 249         admin_queue->stats.submitted_cmd++;
 250
 251         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 252                 admin_queue->sq.phase = !admin_queue->sq.phase;
 253
 254         ENA_DB_SYNC(&admin_queue->sq.mem_handle);
 255         ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
 256                         admin_queue->sq.db_addr);
 257
 258         return comp_ctx;
 259 }
 260
 261 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 262 {
 263         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 264         struct ena_comp_ctx *comp_ctx;
 265         u16 i;
 266
 267         queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
 268         if (unlikely(!queue->comp_ctx)) {
 269                 ena_trc_err("memory allocation failed\n");
 270                 return ENA_COM_NO_MEM;
 271         }
 272
 273         for (i = 0; i < queue->q_depth; i++) {
 274                 comp_ctx = get_comp_ctxt(queue, i, false);
 275                 if (comp_ctx)
 276                         ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 283                                                      struct ena_admin_aq_entry *cmd,
 284                                                      size_t cmd_size_in_bytes,
 285                                                      struct ena_admin_acq_entry *comp,
 286                                                      size_t comp_size_in_bytes)
 287 {
 288         unsigned long flags = 0;
 289         struct ena_comp_ctx *comp_ctx;
 290
 291         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 292         if (unlikely(!admin_queue->running_state)) {
 293                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 294                 return ERR_PTR(ENA_COM_NO_DEVICE);
 295         }
 296         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 297                                               cmd_size_in_bytes,
 298                                               comp,
 299                                               comp_size_in_bytes);
 300         if (IS_ERR(comp_ctx))
 301                 admin_queue->running_state = false;
 302         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 303
 304         return comp_ctx;
 305 }
 306
 307 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 308                               struct ena_com_create_io_ctx *ctx,
 309                               struct ena_com_io_sq *io_sq)
 310 {
 311         size_t size;
 312         int dev_node = 0;
 313
 314         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 315
 316         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 317         io_sq->desc_entry_size =
 318                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 319                 sizeof(struct ena_eth_io_tx_desc) :
 320                 sizeof(struct ena_eth_io_rx_desc);
 321
 322         size = io_sq->desc_entry_size * io_sq->q_depth;
 323         io_sq->bus = ena_dev->bus;
 324
 325         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 326                 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 327                                             size,
 328                                             io_sq->desc_addr.virt_addr,
 329                                             io_sq->desc_addr.phys_addr,
 330                                             io_sq->desc_addr.mem_handle,
 331                                             ctx->numa_node,
 332                                             dev_node);
 333                 if (!io_sq->desc_addr.virt_addr) {
 334                         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 335                                                size,
 336                                                io_sq->desc_addr.virt_addr,
 337                                                io_sq->desc_addr.phys_addr,
 338                                                io_sq->desc_addr.mem_handle);
 339                 }
 340
 341                 if (!io_sq->desc_addr.virt_addr) {
 342                         ena_trc_err("memory allocation failed\n");
 343                         return ENA_COM_NO_MEM;
 344                 }
 345         }
 346
 347         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 348                 /* Allocate bounce buffers */
 349                 io_sq->bounce_buf_ctrl.buffer_size =
 350                         ena_dev->llq_info.desc_list_entry_size;
 351                 io_sq->bounce_buf_ctrl.buffers_num =
 352                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 353                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 354
 355                 size = io_sq->bounce_buf_ctrl.buffer_size *
 356                         io_sq->bounce_buf_ctrl.buffers_num;
 357
 358                 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
 359                                    size,
 360                                    io_sq->bounce_buf_ctrl.base_buffer,
 361                                    ctx->numa_node,
 362                                    dev_node);
 363                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 364                         io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
 365
 366                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 367                         ena_trc_err("bounce buffer memory allocation failed\n");
 368                         return ENA_COM_NO_MEM;
 369                 }
 370
 371                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 372                        sizeof(io_sq->llq_info));
 373
 374                 /* Initiate the first bounce buffer */
 375                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 376                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 377                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 378                        0x0, io_sq->llq_info.desc_list_entry_size);
 379                 io_sq->llq_buf_ctrl.descs_left_in_line =
 380                         io_sq->llq_info.descs_num_before_header;
 381                 io_sq->disable_meta_caching =
 382                         io_sq->llq_info.disable_meta_caching;
 383
 384                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 385                         io_sq->entries_in_tx_burst_left =
 386                                 io_sq->llq_info.max_entries_in_tx_burst;
 387         }
 388
 389         io_sq->tail = 0;
 390         io_sq->next_to_comp = 0;
 391         io_sq->phase = 1;
 392
 393         return 0;
 394 }
 395
 396 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 397                               struct ena_com_create_io_ctx *ctx,
 398                               struct ena_com_io_cq *io_cq)
 399 {
 400         size_t size;
 401         int prev_node = 0;
 402
 403         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 404
 405         /* Use the basic completion descriptor for Rx */
 406         io_cq->cdesc_entry_size_in_bytes =
 407                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 408                 sizeof(struct ena_eth_io_tx_cdesc) :
 409                 sizeof(struct ena_eth_io_rx_cdesc_base);
 410
 411         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 412         io_cq->bus = ena_dev->bus;
 413
 414         ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
 415                         size,
 416                         io_cq->cdesc_addr.virt_addr,
 417                         io_cq->cdesc_addr.phys_addr,
 418                         io_cq->cdesc_addr.mem_handle,
 419                         ctx->numa_node,
 420                         prev_node);
 421         if (!io_cq->cdesc_addr.virt_addr) {
 422                 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
 423                                        size,
 424                                        io_cq->cdesc_addr.virt_addr,
 425                                        io_cq->cdesc_addr.phys_addr,
 426                                        io_cq->cdesc_addr.mem_handle);
 427         }
 428
 429         if (!io_cq->cdesc_addr.virt_addr) {
 430                 ena_trc_err("memory allocation failed\n");
 431                 return ENA_COM_NO_MEM;
 432         }
 433
 434         io_cq->phase = 1;
 435         io_cq->head = 0;
 436
 437         return 0;
 438 }
 439
 440 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 441                                                    struct ena_admin_acq_entry *cqe)
 442 {
 443         struct ena_comp_ctx *comp_ctx;
 444         u16 cmd_id;
 445
 446         cmd_id = cqe->acq_common_descriptor.command &
 447                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 448
 449         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 450         if (unlikely(!comp_ctx)) {
 451                 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
 452                 admin_queue->running_state = false;
 453                 return;
 454         }
 455
 456         comp_ctx->status = ENA_CMD_COMPLETED;
 457         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 458
 459         if (comp_ctx->user_cqe)
 460                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 461
 462         if (!admin_queue->polling)
 463                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
 464 }
 465
 466 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 467 {
 468         struct ena_admin_acq_entry *cqe = NULL;
 469         u16 comp_num = 0;
 470         u16 head_masked;
 471         u8 phase;
 472
 473         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 474         phase = admin_queue->cq.phase;
 475
 476         cqe = &admin_queue->cq.entries[head_masked];
 477
 478         /* Go over all the completions */
 479         while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
 480                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 481                 /* Do not read the rest of the completion entry before the
 482                  * phase bit was validated
 483                  */
 484                 dma_rmb();
 485                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 486
 487                 head_masked++;
 488                 comp_num++;
 489                 if (unlikely(head_masked == admin_queue->q_depth)) {
 490                         head_masked = 0;
 491                         phase = !phase;
 492                 }
 493
 494                 cqe = &admin_queue->cq.entries[head_masked];
 495         }
 496
 497         admin_queue->cq.head += comp_num;
 498         admin_queue->cq.phase = phase;
 499         admin_queue->sq.head += comp_num;
 500         admin_queue->stats.completed_cmd += comp_num;
 501 }
 502
 503 static int ena_com_comp_status_to_errno(u8 comp_status)
 504 {
 505         if (unlikely(comp_status != 0))
 506                 ena_trc_err("admin command failed[%u]\n", comp_status);
 507
 508         switch (comp_status) {
 509         case ENA_ADMIN_SUCCESS:
 510                 return ENA_COM_OK;
 511         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 512                 return ENA_COM_NO_MEM;
 513         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 514                 return ENA_COM_UNSUPPORTED;
 515         case ENA_ADMIN_BAD_OPCODE:
 516         case ENA_ADMIN_MALFORMED_REQUEST:
 517         case ENA_ADMIN_ILLEGAL_PARAMETER:
 518         case ENA_ADMIN_UNKNOWN_ERROR:
 519                 return ENA_COM_INVAL;
 520         case ENA_ADMIN_RESOURCE_BUSY:
 521                 return ENA_COM_TRY_AGAIN;
 522         }
 523
 524         return ENA_COM_INVAL;
 525 }
 526
 527 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 528                                                      struct ena_com_admin_queue *admin_queue)
 529 {
 530         unsigned long flags = 0;
 531         ena_time_t timeout;
 532         int ret;
 533
 534         timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
 535
 536         while (1) {
 537                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 538                 ena_com_handle_admin_completion(admin_queue);
 539                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 540
 541                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 542                         break;
 543
 544                 if (ENA_TIME_EXPIRE(timeout)) {
 545                         ena_trc_err("Wait for completion (polling) timeout\n");
 546                         /* ENA didn't have any completion */
 547                         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 548                         admin_queue->stats.no_completion++;
 549                         admin_queue->running_state = false;
 550                         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 551
 552                         ret = ENA_COM_TIMER_EXPIRED;
 553                         goto err;
 554                 }
 555
 556                 ENA_MSLEEP(ENA_POLL_MS);
 557         }
 558
 559         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 560                 ena_trc_err("Command was aborted\n");
 561                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 562                 admin_queue->stats.aborted_cmd++;
 563                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 564                 ret = ENA_COM_NO_DEVICE;
 565                 goto err;
 566         }
 567
 568         ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
 569                  "Invalid comp status %d\n", comp_ctx->status);
 570
 571         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 572 err:
 573         comp_ctxt_release(admin_queue, comp_ctx);
 574         return ret;
 575 }
 576
 577 /**
 578  * Set the LLQ configurations of the firmware
 579  *
 580  * The driver provides only the enabled feature values to the device,
 581  * which in turn, checks if they are supported.
 582  */
 583 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 584 {
 585         struct ena_com_admin_queue *admin_queue;
 586         struct ena_admin_set_feat_cmd cmd;
 587         struct ena_admin_set_feat_resp resp;
 588         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 589         int ret;
 590
 591         memset(&cmd, 0x0, sizeof(cmd));
 592         admin_queue = &ena_dev->admin_queue;
 593
 594         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 595         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 596
 597         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 598         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 599         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 600         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 601
 602         if (llq_info->disable_meta_caching)
 603                 cmd.u.llq.accel_mode.u.set.enabled_flags |=
 604                         BIT(ENA_ADMIN_DISABLE_META_CACHING);
 605
 606         if (llq_info->max_entries_in_tx_burst)
 607                 cmd.u.llq.accel_mode.u.set.enabled_flags |=
 608                         BIT(ENA_ADMIN_LIMIT_TX_BURST);
 609
 610         ret = ena_com_execute_admin_command(admin_queue,
 611                                             (struct ena_admin_aq_entry *)&cmd,
 612                                             sizeof(cmd),
 613                                             (struct ena_admin_acq_entry *)&resp,
 614                                             sizeof(resp));
 615
 616         if (unlikely(ret))
 617                 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
 618
 619         return ret;
 620 }
 621
 622 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 623                                    struct ena_admin_feature_llq_desc *llq_features,
 624                                    struct ena_llq_configurations *llq_default_cfg)
 625 {
 626         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 627         u16 supported_feat;
 628         int rc;
 629
 630         memset(llq_info, 0, sizeof(*llq_info));
 631
 632         supported_feat = llq_features->header_location_ctrl_supported;
 633
 634         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 635                 llq_info->header_location_ctrl =
 636                         llq_default_cfg->llq_header_location;
 637         } else {
 638                 ena_trc_err("Invalid header location control, supported: 0x%x\n",
 639                             supported_feat);
 640                 return -EINVAL;
 641         }
 642
 643         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 644                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 645                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 646                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 647                 } else  {
 648                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 649                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 650                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 651                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 652                         } else {
 653                                 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 654                                             supported_feat);
 655                                 return -EINVAL;
 656                         }
 657
 658                         ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 659                                     llq_default_cfg->llq_stride_ctrl,
 660                                     supported_feat,
 661                                     llq_info->desc_stride_ctrl);
 662                 }
 663         } else {
 664                 llq_info->desc_stride_ctrl = 0;
 665         }
 666
 667         supported_feat = llq_features->entry_size_ctrl_supported;
 668         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 669                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 670                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 671         } else {
 672                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 673                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 674                         llq_info->desc_list_entry_size = 128;
 675                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 676                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 677                         llq_info->desc_list_entry_size = 192;
 678                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 679                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 680                         llq_info->desc_list_entry_size = 256;
 681                 } else {
 682                         ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
 683                         return -EINVAL;
 684                 }
 685
 686                 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 687                             llq_default_cfg->llq_ring_entry_size,
 688                             supported_feat,
 689                             llq_info->desc_list_entry_size);
 690         }
 691         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 692                 /* The desc list entry size should be whole multiply of 8
 693                  * This requirement comes from __iowrite64_copy()
 694                  */
 695                 ena_trc_err("illegal entry size %d\n",
 696                             llq_info->desc_list_entry_size);
 697                 return -EINVAL;
 698         }
 699
 700         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 701                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 702                         sizeof(struct ena_eth_io_tx_desc);
 703         else
 704                 llq_info->descs_per_entry = 1;
 705
 706         supported_feat = llq_features->desc_num_before_header_supported;
 707         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 708                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 709         } else {
 710                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 711                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 712                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 713                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 714                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 715                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 716                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 717                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 718                 } else {
 719                         ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
 720                                     supported_feat);
 721                         return -EINVAL;
 722                 }
 723
 724                 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 725                             llq_default_cfg->llq_num_decs_before_header,
 726                             supported_feat,
 727                             llq_info->descs_num_before_header);
 728         }
 729         /* Check for accelerated queue supported */
 730         llq_info->disable_meta_caching =
 731                 llq_features->accel_mode.u.get.supported_flags &
 732                 BIT(ENA_ADMIN_DISABLE_META_CACHING);
 733
 734         if (llq_features->accel_mode.u.get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
 735                 llq_info->max_entries_in_tx_burst =
 736                         llq_features->accel_mode.u.get.max_tx_burst_size /
 737                         llq_default_cfg->llq_ring_entry_size_value;
 738
 739         rc = ena_com_set_llq(ena_dev);
 740         if (rc)
 741                 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
 742
 743         return rc;
 744 }
 745
 746 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 747                                                         struct ena_com_admin_queue *admin_queue)
 748 {
 749         unsigned long flags = 0;
 750         int ret;
 751
 752         ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
 753                             admin_queue->completion_timeout);
 754
 755         /* In case the command wasn't completed find out the root cause.
 756          * There might be 2 kinds of errors
 757          * 1) No completion (timeout reached)
 758          * 2) There is completion but the device didn't get any msi-x interrupt.
 759          */
 760         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 761                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
 762                 ena_com_handle_admin_completion(admin_queue);
 763                 admin_queue->stats.no_completion++;
 764                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
 765
 766                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 767                         ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 768                                     comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
 769                         /* Check if fallback to polling is enabled */
 770                         if (admin_queue->auto_polling)
 771                                 admin_queue->polling = true;
 772                 } else {
 773                         ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 774                                     comp_ctx->cmd_opcode, comp_ctx->status);
 775                 }
 776                 /* Check if shifted to polling mode.
 777                  * This will happen if there is a completion without an interrupt
 778                  * and autopolling mode is enabled. Continuing normal execution in such case
 779                  */
 780                 if (!admin_queue->polling) {
 781                         admin_queue->running_state = false;
 782                         ret = ENA_COM_TIMER_EXPIRED;
 783                         goto err;
 784                 }
 785         }
 786
 787         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 788 err:
 789         comp_ctxt_release(admin_queue, comp_ctx);
 790         return ret;
 791 }
 792
 793 /* This method read the hardware device register through posting writes
 794  * and waiting for response
 795  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 796  */
 797 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 798 {
 799         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 800         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 801                 mmio_read->read_resp;
 802         u32 mmio_read_reg, ret, i;
 803         unsigned long flags = 0;
 804         u32 timeout = mmio_read->reg_read_to;
 805
 806         ENA_MIGHT_SLEEP();
 807
 808         if (timeout == 0)
 809                 timeout = ENA_REG_READ_TIMEOUT;
 810
 811         /* If readless is disabled, perform regular read */
 812         if (!mmio_read->readless_supported)
 813                 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
 814
 815         ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
 816         mmio_read->seq_num++;
 817
 818         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 819         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 820                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 821         mmio_read_reg |= mmio_read->seq_num &
 822                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 823
 824         ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
 825                         ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 826
 827         for (i = 0; i < timeout; i++) {
 828                 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
 829                         break;
 830
 831                 ENA_UDELAY(1);
 832         }
 833
 834         if (unlikely(i == timeout)) {
 835                 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 836                             mmio_read->seq_num,
 837                             offset,
 838                             read_resp->req_id,
 839                             read_resp->reg_off);
 840                 ret = ENA_MMIO_READ_TIMEOUT;
 841                 goto err;
 842         }
 843
 844         if (read_resp->reg_off != offset) {
 845                 ena_trc_err("Read failure: wrong offset provided\n");
 846                 ret = ENA_MMIO_READ_TIMEOUT;
 847         } else {
 848                 ret = read_resp->reg_val;
 849         }
 850 err:
 851         ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
 852
 853         return ret;
 854 }
 855
 856 /* There are two types to wait for completion.
 857  * Polling mode - wait until the completion is available.
 858  * Async mode - wait on wait queue until the completion is ready
 859  * (or the timeout expired).
 860  * It is expected that the IRQ called ena_com_handle_admin_completion
 861  * to mark the completions.
 862  */
 863 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 864                                              struct ena_com_admin_queue *admin_queue)
 865 {
 866         if (admin_queue->polling)
 867                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 868                                                                  admin_queue);
 869
 870         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 871                                                             admin_queue);
 872 }
 873
 874 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 875                                  struct ena_com_io_sq *io_sq)
 876 {
 877         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 878         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 879         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 880         u8 direction;
 881         int ret;
 882
 883         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 884
 885         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 886                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 887         else
 888                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 889
 890         destroy_cmd.sq.sq_identity |= (direction <<
 891                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 892                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 893
 894         destroy_cmd.sq.sq_idx = io_sq->idx;
 895         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 896
 897         ret = ena_com_execute_admin_command(admin_queue,
 898                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 899                                             sizeof(destroy_cmd),
 900                                             (struct ena_admin_acq_entry *)&destroy_resp,
 901                                             sizeof(destroy_resp));
 902
 903         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
 904                 ena_trc_err("failed to destroy io sq error: %d\n", ret);
 905
 906         return ret;
 907 }
 908
 909 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 910                                   struct ena_com_io_sq *io_sq,
 911                                   struct ena_com_io_cq *io_cq)
 912 {
 913         size_t size;
 914
 915         if (io_cq->cdesc_addr.virt_addr) {
 916                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 917
 918                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 919                                       size,
 920                                       io_cq->cdesc_addr.virt_addr,
 921                                       io_cq->cdesc_addr.phys_addr,
 922                                       io_cq->cdesc_addr.mem_handle);
 923
 924                 io_cq->cdesc_addr.virt_addr = NULL;
 925         }
 926
 927         if (io_sq->desc_addr.virt_addr) {
 928                 size = io_sq->desc_entry_size * io_sq->q_depth;
 929
 930                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
 931                                       size,
 932                                       io_sq->desc_addr.virt_addr,
 933                                       io_sq->desc_addr.phys_addr,
 934                                       io_sq->desc_addr.mem_handle);
 935
 936                 io_sq->desc_addr.virt_addr = NULL;
 937         }
 938
 939         if (io_sq->bounce_buf_ctrl.base_buffer) {
 940                 ENA_MEM_FREE(ena_dev->dmadev,
 941                              io_sq->bounce_buf_ctrl.base_buffer,
 942                              (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
 943                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 944         }
 945 }
 946
 947 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 948                                 u16 exp_state)
 949 {
 950         u32 val, i;
 951
 952         /* Convert timeout from resolution of 100ms to ENA_POLL_MS */
 953         timeout = (timeout * 100) / ENA_POLL_MS;
 954
 955         for (i = 0; i < timeout; i++) {
 956                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 957
 958                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 959                         ena_trc_err("Reg read timeout occurred\n");
 960                         return ENA_COM_TIMER_EXPIRED;
 961                 }
 962
 963                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 964                         exp_state)
 965                         return 0;
 966
 967                 ENA_MSLEEP(ENA_POLL_MS);
 968         }
 969
 970         return ENA_COM_TIMER_EXPIRED;
 971 }
 972
 973 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 974                                                enum ena_admin_aq_feature_id feature_id)
 975 {
 976         u32 feature_mask = 1 << feature_id;
 977
 978         /* Device attributes is always supported */
 979         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 980             !(ena_dev->supported_features & feature_mask))
 981                 return false;
 982
 983         return true;
 984 }
 985
 986 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 987                                   struct ena_admin_get_feat_resp *get_resp,
 988                                   enum ena_admin_aq_feature_id feature_id,
 989                                   dma_addr_t control_buf_dma_addr,
 990                                   u32 control_buff_size,
 991                                   u8 feature_ver)
 992 {
 993         struct ena_com_admin_queue *admin_queue;
 994         struct ena_admin_get_feat_cmd get_cmd;
 995         int ret;
 996
 997         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
 998                 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
 999                 return ENA_COM_UNSUPPORTED;
1000         }
1001
1002         memset(&get_cmd, 0x0, sizeof(get_cmd));
1003         admin_queue = &ena_dev->admin_queue;
1004
1005         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1006
1007         if (control_buff_size)
1008                 get_cmd.aq_common_descriptor.flags =
1009                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1010         else
1011                 get_cmd.aq_common_descriptor.flags = 0;
1012
1013         ret = ena_com_mem_addr_set(ena_dev,
1014                                    &get_cmd.control_buffer.address,
1015                                    control_buf_dma_addr);
1016         if (unlikely(ret)) {
1017                 ena_trc_err("memory address set failed\n");
1018                 return ret;
1019         }
1020
1021         get_cmd.control_buffer.length = control_buff_size;
1022         get_cmd.feat_common.feature_version = feature_ver;
1023         get_cmd.feat_common.feature_id = feature_id;
1024
1025         ret = ena_com_execute_admin_command(admin_queue,
1026                                             (struct ena_admin_aq_entry *)
1027                                             &get_cmd,
1028                                             sizeof(get_cmd),
1029                                             (struct ena_admin_acq_entry *)
1030                                             get_resp,
1031                                             sizeof(*get_resp));
1032
1033         if (unlikely(ret))
1034                 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1035                             feature_id, ret);
1036
1037         return ret;
1038 }
1039
1040 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1041                                struct ena_admin_get_feat_resp *get_resp,
1042                                enum ena_admin_aq_feature_id feature_id,
1043                                u8 feature_ver)
1044 {
1045         return ena_com_get_feature_ex(ena_dev,
1046                                       get_resp,
1047                                       feature_id,
1048                                       0,
1049                                       0,
1050                                       feature_ver);
1051 }
1052
1053 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1054 {
1055         struct ena_admin_feature_rss_flow_hash_control *hash_key =
1056                 (ena_dev->rss).hash_key;
1057
1058         ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1059         /* The key is stored in the device in uint32_t array
1060          * as well as the API requires the key to be passed in this
1061          * format. Thus the size of our array should be divided by 4
1062          */
1063         hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t);
1064 }
1065
1066 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1067 {
1068         struct ena_rss *rss = &ena_dev->rss;
1069
1070         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1071                                sizeof(*rss->hash_key),
1072                                rss->hash_key,
1073                                rss->hash_key_dma_addr,
1074                                rss->hash_key_mem_handle);
1075
1076         if (unlikely(!rss->hash_key))
1077                 return ENA_COM_NO_MEM;
1078
1079         return 0;
1080 }
1081
1082 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1083 {
1084         struct ena_rss *rss = &ena_dev->rss;
1085
1086         if (rss->hash_key)
1087                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1088                                       sizeof(*rss->hash_key),
1089                                       rss->hash_key,
1090                                       rss->hash_key_dma_addr,
1091                                       rss->hash_key_mem_handle);
1092         rss->hash_key = NULL;
1093 }
1094
1095 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1096 {
1097         struct ena_rss *rss = &ena_dev->rss;
1098
1099         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1100                                sizeof(*rss->hash_ctrl),
1101                                rss->hash_ctrl,
1102                                rss->hash_ctrl_dma_addr,
1103                                rss->hash_ctrl_mem_handle);
1104
1105         if (unlikely(!rss->hash_ctrl))
1106                 return ENA_COM_NO_MEM;
1107
1108         return 0;
1109 }
1110
1111 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1112 {
1113         struct ena_rss *rss = &ena_dev->rss;
1114
1115         if (rss->hash_ctrl)
1116                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1117                                       sizeof(*rss->hash_ctrl),
1118                                       rss->hash_ctrl,
1119                                       rss->hash_ctrl_dma_addr,
1120                                       rss->hash_ctrl_mem_handle);
1121         rss->hash_ctrl = NULL;
1122 }
1123
1124 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1125                                            u16 log_size)
1126 {
1127         struct ena_rss *rss = &ena_dev->rss;
1128         struct ena_admin_get_feat_resp get_resp;
1129         size_t tbl_size;
1130         int ret;
1131
1132         ret = ena_com_get_feature(ena_dev, &get_resp,
1133                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1134         if (unlikely(ret))
1135                 return ret;
1136
1137         if ((get_resp.u.ind_table.min_size > log_size) ||
1138             (get_resp.u.ind_table.max_size < log_size)) {
1139                 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1140                             1 << log_size,
1141                             1 << get_resp.u.ind_table.min_size,
1142                             1 << get_resp.u.ind_table.max_size);
1143                 return ENA_COM_INVAL;
1144         }
1145
1146         tbl_size = (1ULL << log_size) *
1147                 sizeof(struct ena_admin_rss_ind_table_entry);
1148
1149         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1150                              tbl_size,
1151                              rss->rss_ind_tbl,
1152                              rss->rss_ind_tbl_dma_addr,
1153                              rss->rss_ind_tbl_mem_handle);
1154         if (unlikely(!rss->rss_ind_tbl))
1155                 goto mem_err1;
1156
1157         tbl_size = (1ULL << log_size) * sizeof(u16);
1158         rss->host_rss_ind_tbl =
1159                 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1160         if (unlikely(!rss->host_rss_ind_tbl))
1161                 goto mem_err2;
1162
1163         rss->tbl_log_size = log_size;
1164
1165         return 0;
1166
1167 mem_err2:
1168         tbl_size = (1ULL << log_size) *
1169                 sizeof(struct ena_admin_rss_ind_table_entry);
1170
1171         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1172                               tbl_size,
1173                               rss->rss_ind_tbl,
1174                               rss->rss_ind_tbl_dma_addr,
1175                               rss->rss_ind_tbl_mem_handle);
1176         rss->rss_ind_tbl = NULL;
1177 mem_err1:
1178         rss->tbl_log_size = 0;
1179         return ENA_COM_NO_MEM;
1180 }
1181
1182 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1183 {
1184         struct ena_rss *rss = &ena_dev->rss;
1185         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1186                 sizeof(struct ena_admin_rss_ind_table_entry);
1187
1188         if (rss->rss_ind_tbl)
1189                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1190                                       tbl_size,
1191                                       rss->rss_ind_tbl,
1192                                       rss->rss_ind_tbl_dma_addr,
1193                                       rss->rss_ind_tbl_mem_handle);
1194         rss->rss_ind_tbl = NULL;
1195
1196         if (rss->host_rss_ind_tbl)
1197                 ENA_MEM_FREE(ena_dev->dmadev,
1198                              rss->host_rss_ind_tbl,
1199                              ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1200         rss->host_rss_ind_tbl = NULL;
1201 }
1202
1203 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1204                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1205 {
1206         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1207         struct ena_admin_aq_create_sq_cmd create_cmd;
1208         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1209         u8 direction;
1210         int ret;
1211
1212         memset(&create_cmd, 0x0, sizeof(create_cmd));
1213
1214         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1215
1216         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1217                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1218         else
1219                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1220
1221         create_cmd.sq_identity |= (direction <<
1222                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1223                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1224
1225         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1226                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1227
1228         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1229                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1230                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1231
1232         create_cmd.sq_caps_3 |=
1233                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1234
1235         create_cmd.cq_idx = cq_idx;
1236         create_cmd.sq_depth = io_sq->q_depth;
1237
1238         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1239                 ret = ena_com_mem_addr_set(ena_dev,
1240                                            &create_cmd.sq_ba,
1241                                            io_sq->desc_addr.phys_addr);
1242                 if (unlikely(ret)) {
1243                         ena_trc_err("memory address set failed\n");
1244                         return ret;
1245                 }
1246         }
1247
1248         ret = ena_com_execute_admin_command(admin_queue,
1249                                             (struct ena_admin_aq_entry *)&create_cmd,
1250                                             sizeof(create_cmd),
1251                                             (struct ena_admin_acq_entry *)&cmd_completion,
1252                                             sizeof(cmd_completion));
1253         if (unlikely(ret)) {
1254                 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1255                 return ret;
1256         }
1257
1258         io_sq->idx = cmd_completion.sq_idx;
1259
1260         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1261                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1262
1263         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1264                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1265                                 + cmd_completion.llq_headers_offset);
1266
1267                 io_sq->desc_addr.pbuf_dev_addr =
1268                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1269                         cmd_completion.llq_descriptors_offset);
1270         }
1271
1272         ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1273
1274         return ret;
1275 }
1276
1277 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1278 {
1279         struct ena_rss *rss = &ena_dev->rss;
1280         struct ena_com_io_sq *io_sq;
1281         u16 qid;
1282         int i;
1283
1284         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1285                 qid = rss->host_rss_ind_tbl[i];
1286                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1287                         return ENA_COM_INVAL;
1288
1289                 io_sq = &ena_dev->io_sq_queues[qid];
1290
1291                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1292                         return ENA_COM_INVAL;
1293
1294                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1301                                                  u16 intr_delay_resolution)
1302 {
1303         u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1304
1305         if (unlikely(!intr_delay_resolution)) {
1306                 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1307                 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1308         }
1309
1310         /* update Rx */
1311         ena_dev->intr_moder_rx_interval =
1312                 ena_dev->intr_moder_rx_interval *
1313                 prev_intr_delay_resolution /
1314                 intr_delay_resolution;
1315
1316         /* update Tx */
1317         ena_dev->intr_moder_tx_interval =
1318                 ena_dev->intr_moder_tx_interval *
1319                 prev_intr_delay_resolution /
1320                 intr_delay_resolution;
1321
1322         ena_dev->intr_delay_resolution = intr_delay_resolution;
1323 }
1324
1325 /*****************************************************************************/
1326 /*******************************      API       ******************************/
1327 /*****************************************************************************/
1328
1329 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1330                                   struct ena_admin_aq_entry *cmd,
1331                                   size_t cmd_size,
1332                                   struct ena_admin_acq_entry *comp,
1333                                   size_t comp_size)
1334 {
1335         struct ena_comp_ctx *comp_ctx;
1336         int ret;
1337
1338         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1339                                             comp, comp_size);
1340         if (IS_ERR(comp_ctx)) {
1341                 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1342                         ena_trc_dbg("Failed to submit command [%ld]\n",
1343                                     PTR_ERR(comp_ctx));
1344                 else
1345                         ena_trc_err("Failed to submit command [%ld]\n",
1346                                     PTR_ERR(comp_ctx));
1347
1348                 return PTR_ERR(comp_ctx);
1349         }
1350
1351         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1352         if (unlikely(ret)) {
1353                 if (admin_queue->running_state)
1354                         ena_trc_err("Failed to process command. ret = %d\n",
1355                                     ret);
1356                 else
1357                         ena_trc_dbg("Failed to process command. ret = %d\n",
1358                                     ret);
1359         }
1360         return ret;
1361 }
1362
1363 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1364                          struct ena_com_io_cq *io_cq)
1365 {
1366         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1367         struct ena_admin_aq_create_cq_cmd create_cmd;
1368         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1369         int ret;
1370
1371         memset(&create_cmd, 0x0, sizeof(create_cmd));
1372
1373         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1374
1375         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1376                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1377         create_cmd.cq_caps_1 |=
1378                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1379
1380         create_cmd.msix_vector = io_cq->msix_vector;
1381         create_cmd.cq_depth = io_cq->q_depth;
1382
1383         ret = ena_com_mem_addr_set(ena_dev,
1384                                    &create_cmd.cq_ba,
1385                                    io_cq->cdesc_addr.phys_addr);
1386         if (unlikely(ret)) {
1387                 ena_trc_err("memory address set failed\n");
1388                 return ret;
1389         }
1390
1391         ret = ena_com_execute_admin_command(admin_queue,
1392                                             (struct ena_admin_aq_entry *)&create_cmd,
1393                                             sizeof(create_cmd),
1394                                             (struct ena_admin_acq_entry *)&cmd_completion,
1395                                             sizeof(cmd_completion));
1396         if (unlikely(ret)) {
1397                 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1398                 return ret;
1399         }
1400
1401         io_cq->idx = cmd_completion.cq_idx;
1402
1403         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1404                 cmd_completion.cq_interrupt_unmask_register_offset);
1405
1406         if (cmd_completion.cq_head_db_register_offset)
1407                 io_cq->cq_head_db_reg =
1408                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1409                         cmd_completion.cq_head_db_register_offset);
1410
1411         if (cmd_completion.numa_node_register_offset)
1412                 io_cq->numa_node_cfg_reg =
1413                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1414                         cmd_completion.numa_node_register_offset);
1415
1416         ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1417
1418         return ret;
1419 }
1420
1421 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1422                             struct ena_com_io_sq **io_sq,
1423                             struct ena_com_io_cq **io_cq)
1424 {
1425         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1426                 ena_trc_err("Invalid queue number %d but the max is %d\n",
1427                             qid, ENA_TOTAL_NUM_QUEUES);
1428                 return ENA_COM_INVAL;
1429         }
1430
1431         *io_sq = &ena_dev->io_sq_queues[qid];
1432         *io_cq = &ena_dev->io_cq_queues[qid];
1433
1434         return 0;
1435 }
1436
1437 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1438 {
1439         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1440         struct ena_comp_ctx *comp_ctx;
1441         u16 i;
1442
1443         if (!admin_queue->comp_ctx)
1444                 return;
1445
1446         for (i = 0; i < admin_queue->q_depth; i++) {
1447                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1448                 if (unlikely(!comp_ctx))
1449                         break;
1450
1451                 comp_ctx->status = ENA_CMD_ABORTED;
1452
1453                 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1454         }
1455 }
1456
1457 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1458 {
1459         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1460         unsigned long flags = 0;
1461
1462         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1463         while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1464                 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1465                 ENA_MSLEEP(ENA_POLL_MS);
1466                 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1467         }
1468         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1469 }
1470
1471 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1472                           struct ena_com_io_cq *io_cq)
1473 {
1474         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1475         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1476         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1477         int ret;
1478
1479         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1480
1481         destroy_cmd.cq_idx = io_cq->idx;
1482         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1483
1484         ret = ena_com_execute_admin_command(admin_queue,
1485                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1486                                             sizeof(destroy_cmd),
1487                                             (struct ena_admin_acq_entry *)&destroy_resp,
1488                                             sizeof(destroy_resp));
1489
1490         if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1491                 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1492
1493         return ret;
1494 }
1495
1496 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1497 {
1498         return ena_dev->admin_queue.running_state;
1499 }
1500
1501 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1502 {
1503         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1504         unsigned long flags = 0;
1505
1506         ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1507         ena_dev->admin_queue.running_state = state;
1508         ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1509 }
1510
1511 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1512 {
1513         u16 depth = ena_dev->aenq.q_depth;
1514
1515         ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1516
1517         /* Init head_db to mark that all entries in the queue
1518          * are initially available
1519          */
1520         ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1521 }
1522
1523 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1524 {
1525         struct ena_com_admin_queue *admin_queue;
1526         struct ena_admin_set_feat_cmd cmd;
1527         struct ena_admin_set_feat_resp resp;
1528         struct ena_admin_get_feat_resp get_resp;
1529         int ret;
1530
1531         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1532         if (ret) {
1533                 ena_trc_info("Can't get aenq configuration\n");
1534                 return ret;
1535         }
1536
1537         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1538                 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1539                              get_resp.u.aenq.supported_groups,
1540                              groups_flag);
1541                 return ENA_COM_UNSUPPORTED;
1542         }
1543
1544         memset(&cmd, 0x0, sizeof(cmd));
1545         admin_queue = &ena_dev->admin_queue;
1546
1547         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1548         cmd.aq_common_descriptor.flags = 0;
1549         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1550         cmd.u.aenq.enabled_groups = groups_flag;
1551
1552         ret = ena_com_execute_admin_command(admin_queue,
1553                                             (struct ena_admin_aq_entry *)&cmd,
1554                                             sizeof(cmd),
1555                                             (struct ena_admin_acq_entry *)&resp,
1556                                             sizeof(resp));
1557
1558         if (unlikely(ret))
1559                 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1560
1561         return ret;
1562 }
1563
1564 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1565 {
1566         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1567         int width;
1568
1569         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1570                 ena_trc_err("Reg read timeout occurred\n");
1571                 return ENA_COM_TIMER_EXPIRED;
1572         }
1573
1574         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1575                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1576
1577         ena_trc_dbg("ENA dma width: %d\n", width);
1578
1579         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1580                 ena_trc_err("DMA width illegal value: %d\n", width);
1581                 return ENA_COM_INVAL;
1582         }
1583
1584         ena_dev->dma_addr_bits = width;
1585
1586         return width;
1587 }
1588
1589 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1590 {
1591         u32 ver;
1592         u32 ctrl_ver;
1593         u32 ctrl_ver_masked;
1594
1595         /* Make sure the ENA version and the controller version are at least
1596          * as the driver expects
1597          */
1598         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1599         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1600                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1601
1602         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1603                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1604                 ena_trc_err("Reg read timeout occurred\n");
1605                 return ENA_COM_TIMER_EXPIRED;
1606         }
1607
1608         ena_trc_info("ena device version: %d.%d\n",
1609                      (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1610                      ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1611                      ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1612
1613         ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1614                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1615                      >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1616                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1617                      >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1618                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1619                      (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1620                      ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1621
1622         ctrl_ver_masked =
1623                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1624                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1625                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1626
1627         /* Validate the ctrl version without the implementation ID */
1628         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1629                 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1630                 return -1;
1631         }
1632
1633         return 0;
1634 }
1635
1636 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1637 {
1638         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1639         struct ena_com_admin_cq *cq = &admin_queue->cq;
1640         struct ena_com_admin_sq *sq = &admin_queue->sq;
1641         struct ena_com_aenq *aenq = &ena_dev->aenq;
1642         u16 size;
1643
1644         ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1645         if (admin_queue->comp_ctx)
1646                 ENA_MEM_FREE(ena_dev->dmadev,
1647                              admin_queue->comp_ctx,
1648                              (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1649         admin_queue->comp_ctx = NULL;
1650         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1651         if (sq->entries)
1652                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1653                                       sq->dma_addr, sq->mem_handle);
1654         sq->entries = NULL;
1655
1656         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1657         if (cq->entries)
1658                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1659                                       cq->dma_addr, cq->mem_handle);
1660         cq->entries = NULL;
1661
1662         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1663         if (ena_dev->aenq.entries)
1664                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1665                                       aenq->dma_addr, aenq->mem_handle);
1666         aenq->entries = NULL;
1667         ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1668 }
1669
1670 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1671 {
1672         u32 mask_value = 0;
1673
1674         if (polling)
1675                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1676
1677         ENA_REG_WRITE32(ena_dev->bus, mask_value,
1678                         ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1679         ena_dev->admin_queue.polling = polling;
1680 }
1681
1682 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev)
1683 {
1684         return ena_dev->admin_queue.polling;
1685 }
1686
1687 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1688                                          bool polling)
1689 {
1690         ena_dev->admin_queue.auto_polling = polling;
1691 }
1692
1693 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1694 {
1695         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1696
1697         ENA_SPINLOCK_INIT(mmio_read->lock);
1698         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1699                                sizeof(*mmio_read->read_resp),
1700                                mmio_read->read_resp,
1701                                mmio_read->read_resp_dma_addr,
1702                                mmio_read->read_resp_mem_handle);
1703         if (unlikely(!mmio_read->read_resp))
1704                 goto err;
1705
1706         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1707
1708         mmio_read->read_resp->req_id = 0x0;
1709         mmio_read->seq_num = 0x0;
1710         mmio_read->readless_supported = true;
1711
1712         return 0;
1713
1714 err:
1715                 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1716                 return ENA_COM_NO_MEM;
1717 }
1718
1719 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1720 {
1721         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1722
1723         mmio_read->readless_supported = readless_supported;
1724 }
1725
1726 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1727 {
1728         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1729
1730         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1731         ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1732
1733         ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1734                               sizeof(*mmio_read->read_resp),
1735                               mmio_read->read_resp,
1736                               mmio_read->read_resp_dma_addr,
1737                               mmio_read->read_resp_mem_handle);
1738
1739         mmio_read->read_resp = NULL;
1740         ENA_SPINLOCK_DESTROY(mmio_read->lock);
1741 }
1742
1743 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1744 {
1745         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1746         u32 addr_low, addr_high;
1747
1748         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1749         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1750
1751         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1752         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1753 }
1754
1755 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1756                        struct ena_aenq_handlers *aenq_handlers)
1757 {
1758         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1759         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1760         int ret;
1761
1762         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1763
1764         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1765                 ena_trc_err("Reg read timeout occurred\n");
1766                 return ENA_COM_TIMER_EXPIRED;
1767         }
1768
1769         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1770                 ena_trc_err("Device isn't ready, abort com init\n");
1771                 return ENA_COM_NO_DEVICE;
1772         }
1773
1774         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1775
1776         admin_queue->bus = ena_dev->bus;
1777         admin_queue->q_dmadev = ena_dev->dmadev;
1778         admin_queue->polling = false;
1779         admin_queue->curr_cmd_id = 0;
1780
1781         ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1782
1783         ENA_SPINLOCK_INIT(admin_queue->q_lock);
1784
1785         ret = ena_com_init_comp_ctxt(admin_queue);
1786         if (ret)
1787                 goto error;
1788
1789         ret = ena_com_admin_init_sq(admin_queue);
1790         if (ret)
1791                 goto error;
1792
1793         ret = ena_com_admin_init_cq(admin_queue);
1794         if (ret)
1795                 goto error;
1796
1797         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1798                 ENA_REGS_AQ_DB_OFF);
1799
1800         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1801         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1802
1803         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1804         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1805
1806         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1807         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1808
1809         ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1810         ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1811
1812         aq_caps = 0;
1813         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1814         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1815                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1816                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1817
1818         acq_caps = 0;
1819         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1820         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1821                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1822                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1823
1824         ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1825         ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1826         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1827         if (ret)
1828                 goto error;
1829
1830         admin_queue->running_state = true;
1831
1832         return 0;
1833 error:
1834         ena_com_admin_destroy(ena_dev);
1835
1836         return ret;
1837 }
1838
1839 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1840                             struct ena_com_create_io_ctx *ctx)
1841 {
1842         struct ena_com_io_sq *io_sq;
1843         struct ena_com_io_cq *io_cq;
1844         int ret;
1845
1846         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1847                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1848                             ctx->qid, ENA_TOTAL_NUM_QUEUES);
1849                 return ENA_COM_INVAL;
1850         }
1851
1852         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1853         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1854
1855         memset(io_sq, 0x0, sizeof(*io_sq));
1856         memset(io_cq, 0x0, sizeof(*io_cq));
1857
1858         /* Init CQ */
1859         io_cq->q_depth = ctx->queue_size;
1860         io_cq->direction = ctx->direction;
1861         io_cq->qid = ctx->qid;
1862
1863         io_cq->msix_vector = ctx->msix_vector;
1864
1865         io_sq->q_depth = ctx->queue_size;
1866         io_sq->direction = ctx->direction;
1867         io_sq->qid = ctx->qid;
1868
1869         io_sq->mem_queue_type = ctx->mem_queue_type;
1870
1871         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1872                 /* header length is limited to 8 bits */
1873                 io_sq->tx_max_header_size =
1874                         ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1875
1876         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1877         if (ret)
1878                 goto error;
1879         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1880         if (ret)
1881                 goto error;
1882
1883         ret = ena_com_create_io_cq(ena_dev, io_cq);
1884         if (ret)
1885                 goto error;
1886
1887         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1888         if (ret)
1889                 goto destroy_io_cq;
1890
1891         return 0;
1892
1893 destroy_io_cq:
1894         ena_com_destroy_io_cq(ena_dev, io_cq);
1895 error:
1896         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1897         return ret;
1898 }
1899
1900 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1901 {
1902         struct ena_com_io_sq *io_sq;
1903         struct ena_com_io_cq *io_cq;
1904
1905         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1906                 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1907                             qid, ENA_TOTAL_NUM_QUEUES);
1908                 return;
1909         }
1910
1911         io_sq = &ena_dev->io_sq_queues[qid];
1912         io_cq = &ena_dev->io_cq_queues[qid];
1913
1914         ena_com_destroy_io_sq(ena_dev, io_sq);
1915         ena_com_destroy_io_cq(ena_dev, io_cq);
1916
1917         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1918 }
1919
1920 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1921                             struct ena_admin_get_feat_resp *resp)
1922 {
1923         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1924 }
1925
1926 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1927                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1928 {
1929         struct ena_admin_get_feat_resp get_resp;
1930         int rc;
1931
1932         rc = ena_com_get_feature(ena_dev, &get_resp,
1933                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1934         if (rc)
1935                 return rc;
1936
1937         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1938                sizeof(get_resp.u.dev_attr));
1939         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1940
1941         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1942                 rc = ena_com_get_feature(ena_dev, &get_resp,
1943                                          ENA_ADMIN_MAX_QUEUES_EXT,
1944                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
1945                 if (rc)
1946                         return rc;
1947
1948                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1949                         return -EINVAL;
1950
1951                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1952                        sizeof(get_resp.u.max_queue_ext));
1953                 ena_dev->tx_max_header_size =
1954                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1955         } else {
1956                 rc = ena_com_get_feature(ena_dev, &get_resp,
1957                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
1958                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1959                        sizeof(get_resp.u.max_queue));
1960                 ena_dev->tx_max_header_size =
1961                         get_resp.u.max_queue.max_header_size;
1962
1963                 if (rc)
1964                         return rc;
1965         }
1966
1967         rc = ena_com_get_feature(ena_dev, &get_resp,
1968                                  ENA_ADMIN_AENQ_CONFIG, 0);
1969         if (rc)
1970                 return rc;
1971
1972         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1973                sizeof(get_resp.u.aenq));
1974
1975         rc = ena_com_get_feature(ena_dev, &get_resp,
1976                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1977         if (rc)
1978                 return rc;
1979
1980         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1981                sizeof(get_resp.u.offload));
1982
1983         /* Driver hints isn't mandatory admin command. So in case the
1984          * command isn't supported set driver hints to 0
1985          */
1986         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
1987
1988         if (!rc)
1989                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1990                        sizeof(get_resp.u.hw_hints));
1991         else if (rc == ENA_COM_UNSUPPORTED)
1992                 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1993         else
1994                 return rc;
1995
1996         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
1997         if (!rc)
1998                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
1999                        sizeof(get_resp.u.llq));
2000         else if (rc == ENA_COM_UNSUPPORTED)
2001                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2002         else
2003                 return rc;
2004
2005         rc = ena_com_get_feature(ena_dev, &get_resp,
2006                                  ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2007         if (!rc)
2008                 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2009                        sizeof(get_resp.u.ind_table));
2010         else if (rc == ENA_COM_UNSUPPORTED)
2011                 memset(&get_feat_ctx->ind_table, 0x0,
2012                        sizeof(get_feat_ctx->ind_table));
2013         else
2014                 return rc;
2015
2016         return 0;
2017 }
2018
2019 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2020 {
2021         ena_com_handle_admin_completion(&ena_dev->admin_queue);
2022 }
2023
2024 /* ena_handle_specific_aenq_event:
2025  * return the handler that is relevant to the specific event group
2026  */
2027 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2028                                                      u16 group)
2029 {
2030         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2031
2032         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2033                 return aenq_handlers->handlers[group];
2034
2035         return aenq_handlers->unimplemented_handler;
2036 }
2037
2038 /* ena_aenq_intr_handler:
2039  * handles the aenq incoming events.
2040  * pop events from the queue and apply the specific handler
2041  */
2042 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2043 {
2044         struct ena_admin_aenq_entry *aenq_e;
2045         struct ena_admin_aenq_common_desc *aenq_common;
2046         struct ena_com_aenq *aenq  = &dev->aenq;
2047         u64 timestamp;
2048         ena_aenq_handler handler_cb;
2049         u16 masked_head, processed = 0;
2050         u8 phase;
2051
2052         masked_head = aenq->head & (aenq->q_depth - 1);
2053         phase = aenq->phase;
2054         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2055         aenq_common = &aenq_e->aenq_common_desc;
2056
2057         /* Go over all the events */
2058         while ((READ_ONCE8(aenq_common->flags) &
2059                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2060                 /* Make sure the phase bit (ownership) is as expected before
2061                  * reading the rest of the descriptor.
2062                  */
2063                 dma_rmb();
2064
2065                 timestamp = (u64)aenq_common->timestamp_low |
2066                         ((u64)aenq_common->timestamp_high << 32);
2067                 ENA_TOUCH(timestamp); /* In case debug is disabled */
2068                 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2069                             aenq_common->group,
2070                             aenq_common->syndrom,
2071                             timestamp);
2072
2073                 /* Handle specific event*/
2074                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2075                                                           aenq_common->group);
2076                 handler_cb(data, aenq_e); /* call the actual event handler*/
2077
2078                 /* Get next event entry */
2079                 masked_head++;
2080                 processed++;
2081
2082                 if (unlikely(masked_head == aenq->q_depth)) {
2083                         masked_head = 0;
2084                         phase = !phase;
2085                 }
2086                 aenq_e = &aenq->entries[masked_head];
2087                 aenq_common = &aenq_e->aenq_common_desc;
2088         }
2089
2090         aenq->head += processed;
2091         aenq->phase = phase;
2092
2093         /* Don't update aenq doorbell if there weren't any processed events */
2094         if (!processed)
2095                 return;
2096
2097         /* write the aenq doorbell after all AENQ descriptors were read */
2098         mb();
2099         ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2100                                 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2101 #ifndef MMIOWB_NOT_DEFINED
2102         mmiowb();
2103 #endif
2104 }
2105
2106 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2107                       enum ena_regs_reset_reason_types reset_reason)
2108 {
2109         u32 stat, timeout, cap, reset_val;
2110         int rc;
2111
2112         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2113         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2114
2115         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2116                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2117                 ena_trc_err("Reg read32 timeout occurred\n");
2118                 return ENA_COM_TIMER_EXPIRED;
2119         }
2120
2121         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2122                 ena_trc_err("Device isn't ready, can't reset device\n");
2123                 return ENA_COM_INVAL;
2124         }
2125
2126         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2127                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2128         if (timeout == 0) {
2129                 ena_trc_err("Invalid timeout value\n");
2130                 return ENA_COM_INVAL;
2131         }
2132
2133         /* start reset */
2134         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2135         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2136                         ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2137         ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2138
2139         /* Write again the MMIO read request address */
2140         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2141
2142         rc = wait_for_reset_state(ena_dev, timeout,
2143                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2144         if (rc != 0) {
2145                 ena_trc_err("Reset indication didn't turn on\n");
2146                 return rc;
2147         }
2148
2149         /* reset done */
2150         ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2151         rc = wait_for_reset_state(ena_dev, timeout, 0);
2152         if (rc != 0) {
2153                 ena_trc_err("Reset indication didn't turn off\n");
2154                 return rc;
2155         }
2156
2157         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2158                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2159         if (timeout)
2160                 /* the resolution of timeout reg is 100ms */
2161                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2162         else
2163                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2164
2165         return 0;
2166 }
2167
2168 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2169                              struct ena_com_stats_ctx *ctx,
2170                              enum ena_admin_get_stats_type type)
2171 {
2172         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2173         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2174         struct ena_com_admin_queue *admin_queue;
2175         int ret;
2176
2177         admin_queue = &ena_dev->admin_queue;
2178
2179         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2180         get_cmd->aq_common_descriptor.flags = 0;
2181         get_cmd->type = type;
2182
2183         ret =  ena_com_execute_admin_command(admin_queue,
2184                                              (struct ena_admin_aq_entry *)get_cmd,
2185                                              sizeof(*get_cmd),
2186                                              (struct ena_admin_acq_entry *)get_resp,
2187                                              sizeof(*get_resp));
2188
2189         if (unlikely(ret))
2190                 ena_trc_err("Failed to get stats. error: %d\n", ret);
2191
2192         return ret;
2193 }
2194
2195 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2196                                 struct ena_admin_basic_stats *stats)
2197 {
2198         struct ena_com_stats_ctx ctx;
2199         int ret;
2200
2201         memset(&ctx, 0x0, sizeof(ctx));
2202         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2203         if (likely(ret == 0))
2204                 memcpy(stats, &ctx.get_resp.basic_stats,
2205                        sizeof(ctx.get_resp.basic_stats));
2206
2207         return ret;
2208 }
2209
2210 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2211 {
2212         struct ena_com_admin_queue *admin_queue;
2213         struct ena_admin_set_feat_cmd cmd;
2214         struct ena_admin_set_feat_resp resp;
2215         int ret;
2216
2217         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2218                 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2219                 return ENA_COM_UNSUPPORTED;
2220         }
2221
2222         memset(&cmd, 0x0, sizeof(cmd));
2223         admin_queue = &ena_dev->admin_queue;
2224
2225         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2226         cmd.aq_common_descriptor.flags = 0;
2227         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2228         cmd.u.mtu.mtu = mtu;
2229
2230         ret = ena_com_execute_admin_command(admin_queue,
2231                                             (struct ena_admin_aq_entry *)&cmd,
2232                                             sizeof(cmd),
2233                                             (struct ena_admin_acq_entry *)&resp,
2234                                             sizeof(resp));
2235
2236         if (unlikely(ret))
2237                 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2238
2239         return ret;
2240 }
2241
2242 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2243                                  struct ena_admin_feature_offload_desc *offload)
2244 {
2245         int ret;
2246         struct ena_admin_get_feat_resp resp;
2247
2248         ret = ena_com_get_feature(ena_dev, &resp,
2249                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2250         if (unlikely(ret)) {
2251                 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2252                 return ret;
2253         }
2254
2255         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2256
2257         return 0;
2258 }
2259
2260 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2261 {
2262         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2263         struct ena_rss *rss = &ena_dev->rss;
2264         struct ena_admin_set_feat_cmd cmd;
2265         struct ena_admin_set_feat_resp resp;
2266         struct ena_admin_get_feat_resp get_resp;
2267         int ret;
2268
2269         if (!ena_com_check_supported_feature_id(ena_dev,
2270                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2271                 ena_trc_dbg("Feature %d isn't supported\n",
2272                             ENA_ADMIN_RSS_HASH_FUNCTION);
2273                 return ENA_COM_UNSUPPORTED;
2274         }
2275
2276         /* Validate hash function is supported */
2277         ret = ena_com_get_feature(ena_dev, &get_resp,
2278                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2279         if (unlikely(ret))
2280                 return ret;
2281
2282         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2283                 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2284                             rss->hash_func);
2285                 return ENA_COM_UNSUPPORTED;
2286         }
2287
2288         memset(&cmd, 0x0, sizeof(cmd));
2289
2290         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2291         cmd.aq_common_descriptor.flags =
2292                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2293         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2294         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2295         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2296
2297         ret = ena_com_mem_addr_set(ena_dev,
2298                                    &cmd.control_buffer.address,
2299                                    rss->hash_key_dma_addr);
2300         if (unlikely(ret)) {
2301                 ena_trc_err("memory address set failed\n");
2302                 return ret;
2303         }
2304
2305         cmd.control_buffer.length = sizeof(*rss->hash_key);
2306
2307         ret = ena_com_execute_admin_command(admin_queue,
2308                                             (struct ena_admin_aq_entry *)&cmd,
2309                                             sizeof(cmd),
2310                                             (struct ena_admin_acq_entry *)&resp,
2311                                             sizeof(resp));
2312         if (unlikely(ret)) {
2313                 ena_trc_err("Failed to set hash function %d. error: %d\n",
2314                             rss->hash_func, ret);
2315                 return ENA_COM_INVAL;
2316         }
2317
2318         return 0;
2319 }
2320
2321 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2322                                enum ena_admin_hash_functions func,
2323                                const u8 *key, u16 key_len, u32 init_val)
2324 {
2325         struct ena_admin_feature_rss_flow_hash_control *hash_key;
2326         struct ena_admin_get_feat_resp get_resp;
2327         enum ena_admin_hash_functions old_func;
2328         struct ena_rss *rss = &ena_dev->rss;
2329         int rc;
2330
2331         hash_key = rss->hash_key;
2332
2333         /* Make sure size is a mult of DWs */
2334         if (unlikely(key_len & 0x3))
2335                 return ENA_COM_INVAL;
2336
2337         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2338                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2339                                     rss->hash_key_dma_addr,
2340                                     sizeof(*rss->hash_key), 0);
2341         if (unlikely(rc))
2342                 return rc;
2343
2344         if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2345                 ena_trc_err("Flow hash function %d isn't supported\n", func);
2346                 return ENA_COM_UNSUPPORTED;
2347         }
2348
2349         switch (func) {
2350         case ENA_ADMIN_TOEPLITZ:
2351                 if (key) {
2352                         if (key_len != sizeof(hash_key->key)) {
2353                                 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2354                                              key_len, sizeof(hash_key->key));
2355                                 return ENA_COM_INVAL;
2356                         }
2357                         memcpy(hash_key->key, key, key_len);
2358                         rss->hash_init_val = init_val;
2359                         hash_key->keys_num = key_len / sizeof(u32);
2360                 }
2361                 break;
2362         case ENA_ADMIN_CRC32:
2363                 rss->hash_init_val = init_val;
2364                 break;
2365         default:
2366                 ena_trc_err("Invalid hash function (%d)\n", func);
2367                 return ENA_COM_INVAL;
2368         }
2369
2370         old_func = rss->hash_func;
2371         rss->hash_func = func;
2372         rc = ena_com_set_hash_function(ena_dev);
2373
2374         /* Restore the old function */
2375         if (unlikely(rc))
2376                 rss->hash_func = old_func;
2377
2378         return rc;
2379 }
2380
2381 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2382                               enum ena_admin_hash_functions *func,
2383                               u8 *key)
2384 {
2385         struct ena_rss *rss = &ena_dev->rss;
2386         struct ena_admin_get_feat_resp get_resp;
2387         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2388                 rss->hash_key;
2389         int rc;
2390
2391         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2392                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2393                                     rss->hash_key_dma_addr,
2394                                     sizeof(*rss->hash_key), 0);
2395         if (unlikely(rc))
2396                 return rc;
2397
2398         /* ENA_FFS returns 1 in case the lsb is set */
2399         rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2400         if (rss->hash_func)
2401                 rss->hash_func--;
2402
2403         if (func)
2404                 *func = rss->hash_func;
2405
2406         if (key)
2407                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2408
2409         return 0;
2410 }
2411
2412 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2413                           enum ena_admin_flow_hash_proto proto,
2414                           u16 *fields)
2415 {
2416         struct ena_rss *rss = &ena_dev->rss;
2417         struct ena_admin_get_feat_resp get_resp;
2418         int rc;
2419
2420         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2421                                     ENA_ADMIN_RSS_HASH_INPUT,
2422                                     rss->hash_ctrl_dma_addr,
2423                                     sizeof(*rss->hash_ctrl), 0);
2424         if (unlikely(rc))
2425                 return rc;
2426
2427         if (fields)
2428                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2429
2430         return 0;
2431 }
2432
2433 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2434 {
2435         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2436         struct ena_rss *rss = &ena_dev->rss;
2437         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2438         struct ena_admin_set_feat_cmd cmd;
2439         struct ena_admin_set_feat_resp resp;
2440         int ret;
2441
2442         if (!ena_com_check_supported_feature_id(ena_dev,
2443                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2444                 ena_trc_dbg("Feature %d isn't supported\n",
2445                             ENA_ADMIN_RSS_HASH_INPUT);
2446                 return ENA_COM_UNSUPPORTED;
2447         }
2448
2449         memset(&cmd, 0x0, sizeof(cmd));
2450
2451         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2452         cmd.aq_common_descriptor.flags =
2453                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2454         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2455         cmd.u.flow_hash_input.enabled_input_sort =
2456                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2457                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2458
2459         ret = ena_com_mem_addr_set(ena_dev,
2460                                    &cmd.control_buffer.address,
2461                                    rss->hash_ctrl_dma_addr);
2462         if (unlikely(ret)) {
2463                 ena_trc_err("memory address set failed\n");
2464                 return ret;
2465         }
2466         cmd.control_buffer.length = sizeof(*hash_ctrl);
2467
2468         ret = ena_com_execute_admin_command(admin_queue,
2469                                             (struct ena_admin_aq_entry *)&cmd,
2470                                             sizeof(cmd),
2471                                             (struct ena_admin_acq_entry *)&resp,
2472                                             sizeof(resp));
2473         if (unlikely(ret))
2474                 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2475
2476         return ret;
2477 }
2478
2479 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2480 {
2481         struct ena_rss *rss = &ena_dev->rss;
2482         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2483                 rss->hash_ctrl;
2484         u16 available_fields = 0;
2485         int rc, i;
2486
2487         /* Get the supported hash input */
2488         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2489         if (unlikely(rc))
2490                 return rc;
2491
2492         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2493                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2494                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2495
2496         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2497                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2498                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2499
2500         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2501                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2502                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2503
2504         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2505                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2506                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2507
2508         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2509                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2510
2511         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2512                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2513
2514         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2515                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2516
2517         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2518                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2519
2520         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2521                 available_fields = hash_ctrl->selected_fields[i].fields &
2522                                 hash_ctrl->supported_fields[i].fields;
2523                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2524                         ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2525                                     i, hash_ctrl->supported_fields[i].fields,
2526                                     hash_ctrl->selected_fields[i].fields);
2527                         return ENA_COM_UNSUPPORTED;
2528                 }
2529         }
2530
2531         rc = ena_com_set_hash_ctrl(ena_dev);
2532
2533         /* In case of failure, restore the old hash ctrl */
2534         if (unlikely(rc))
2535                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2536
2537         return rc;
2538 }
2539
2540 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2541                            enum ena_admin_flow_hash_proto proto,
2542                            u16 hash_fields)
2543 {
2544         struct ena_rss *rss = &ena_dev->rss;
2545         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2546         u16 supported_fields;
2547         int rc;
2548
2549         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2550                 ena_trc_err("Invalid proto num (%u)\n", proto);
2551                 return ENA_COM_INVAL;
2552         }
2553
2554         /* Get the ctrl table */
2555         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2556         if (unlikely(rc))
2557                 return rc;
2558
2559         /* Make sure all the fields are supported */
2560         supported_fields = hash_ctrl->supported_fields[proto].fields;
2561         if ((hash_fields & supported_fields) != hash_fields) {
2562                 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2563                             proto, hash_fields, supported_fields);
2564         }
2565
2566         hash_ctrl->selected_fields[proto].fields = hash_fields;
2567
2568         rc = ena_com_set_hash_ctrl(ena_dev);
2569
2570         /* In case of failure, restore the old hash ctrl */
2571         if (unlikely(rc))
2572                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2573
2574         return 0;
2575 }
2576
2577 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2578                                       u16 entry_idx, u16 entry_value)
2579 {
2580         struct ena_rss *rss = &ena_dev->rss;
2581
2582         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2583                 return ENA_COM_INVAL;
2584
2585         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2586                 return ENA_COM_INVAL;
2587
2588         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2589
2590         return 0;
2591 }
2592
2593 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2594 {
2595         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2596         struct ena_rss *rss = &ena_dev->rss;
2597         struct ena_admin_set_feat_cmd cmd;
2598         struct ena_admin_set_feat_resp resp;
2599         int ret;
2600
2601         if (!ena_com_check_supported_feature_id(ena_dev,
2602                                                 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2603                 ena_trc_dbg("Feature %d isn't supported\n",
2604                             ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2605                 return ENA_COM_UNSUPPORTED;
2606         }
2607
2608         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2609         if (ret) {
2610                 ena_trc_err("Failed to convert host indirection table to device table\n");
2611                 return ret;
2612         }
2613
2614         memset(&cmd, 0x0, sizeof(cmd));
2615
2616         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2617         cmd.aq_common_descriptor.flags =
2618                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2619         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2620         cmd.u.ind_table.size = rss->tbl_log_size;
2621         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2622
2623         ret = ena_com_mem_addr_set(ena_dev,
2624                                    &cmd.control_buffer.address,
2625                                    rss->rss_ind_tbl_dma_addr);
2626         if (unlikely(ret)) {
2627                 ena_trc_err("memory address set failed\n");
2628                 return ret;
2629         }
2630
2631         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2632                 sizeof(struct ena_admin_rss_ind_table_entry);
2633
2634         ret = ena_com_execute_admin_command(admin_queue,
2635                                             (struct ena_admin_aq_entry *)&cmd,
2636                                             sizeof(cmd),
2637                                             (struct ena_admin_acq_entry *)&resp,
2638                                             sizeof(resp));
2639
2640         if (unlikely(ret))
2641                 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2642
2643         return ret;
2644 }
2645
2646 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2647 {
2648         struct ena_rss *rss = &ena_dev->rss;
2649         struct ena_admin_get_feat_resp get_resp;
2650         u32 tbl_size;
2651         int i, rc;
2652
2653         tbl_size = (1ULL << rss->tbl_log_size) *
2654                 sizeof(struct ena_admin_rss_ind_table_entry);
2655
2656         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2657                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2658                                     rss->rss_ind_tbl_dma_addr,
2659                                     tbl_size, 0);
2660         if (unlikely(rc))
2661                 return rc;
2662
2663         if (!ind_tbl)
2664                 return 0;
2665
2666         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2667                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2668
2669         return 0;
2670 }
2671
2672 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2673 {
2674         int rc;
2675
2676         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2677
2678         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2679         if (unlikely(rc))
2680                 goto err_indr_tbl;
2681
2682         rc = ena_com_hash_key_allocate(ena_dev);
2683         if (unlikely(rc))
2684                 goto err_hash_key;
2685
2686         ena_com_hash_key_fill_default_key(ena_dev);
2687
2688         rc = ena_com_hash_ctrl_init(ena_dev);
2689         if (unlikely(rc))
2690                 goto err_hash_ctrl;
2691
2692         return 0;
2693
2694 err_hash_ctrl:
2695         ena_com_hash_key_destroy(ena_dev);
2696 err_hash_key:
2697         ena_com_indirect_table_destroy(ena_dev);
2698 err_indr_tbl:
2699
2700         return rc;
2701 }
2702
2703 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2704 {
2705         ena_com_indirect_table_destroy(ena_dev);
2706         ena_com_hash_key_destroy(ena_dev);
2707         ena_com_hash_ctrl_destroy(ena_dev);
2708
2709         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2710 }
2711
2712 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2713 {
2714         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2715
2716         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2717                                SZ_4K,
2718                                host_attr->host_info,
2719                                host_attr->host_info_dma_addr,
2720                                host_attr->host_info_dma_handle);
2721         if (unlikely(!host_attr->host_info))
2722                 return ENA_COM_NO_MEM;
2723
2724         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2725                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2726                 (ENA_COMMON_SPEC_VERSION_MINOR));
2727
2728         return 0;
2729 }
2730
2731 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2732                                 u32 debug_area_size)
2733 {
2734         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2735
2736         ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2737                                debug_area_size,
2738                                host_attr->debug_area_virt_addr,
2739                                host_attr->debug_area_dma_addr,
2740                                host_attr->debug_area_dma_handle);
2741         if (unlikely(!host_attr->debug_area_virt_addr)) {
2742                 host_attr->debug_area_size = 0;
2743                 return ENA_COM_NO_MEM;
2744         }
2745
2746         host_attr->debug_area_size = debug_area_size;
2747
2748         return 0;
2749 }
2750
2751 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2752 {
2753         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2754
2755         if (host_attr->host_info) {
2756                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2757                                       SZ_4K,
2758                                       host_attr->host_info,
2759                                       host_attr->host_info_dma_addr,
2760                                       host_attr->host_info_dma_handle);
2761                 host_attr->host_info = NULL;
2762         }
2763 }
2764
2765 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2766 {
2767         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2768
2769         if (host_attr->debug_area_virt_addr) {
2770                 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2771                                       host_attr->debug_area_size,
2772                                       host_attr->debug_area_virt_addr,
2773                                       host_attr->debug_area_dma_addr,
2774                                       host_attr->debug_area_dma_handle);
2775                 host_attr->debug_area_virt_addr = NULL;
2776         }
2777 }
2778
2779 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2780 {
2781         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2782         struct ena_com_admin_queue *admin_queue;
2783         struct ena_admin_set_feat_cmd cmd;
2784         struct ena_admin_set_feat_resp resp;
2785
2786         int ret;
2787
2788         /* Host attribute config is called before ena_com_get_dev_attr_feat
2789          * so ena_com can't check if the feature is supported.
2790          */
2791
2792         memset(&cmd, 0x0, sizeof(cmd));
2793         admin_queue = &ena_dev->admin_queue;
2794
2795         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2796         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2797
2798         ret = ena_com_mem_addr_set(ena_dev,
2799                                    &cmd.u.host_attr.debug_ba,
2800                                    host_attr->debug_area_dma_addr);
2801         if (unlikely(ret)) {
2802                 ena_trc_err("memory address set failed\n");
2803                 return ret;
2804         }
2805
2806         ret = ena_com_mem_addr_set(ena_dev,
2807                                    &cmd.u.host_attr.os_info_ba,
2808                                    host_attr->host_info_dma_addr);
2809         if (unlikely(ret)) {
2810                 ena_trc_err("memory address set failed\n");
2811                 return ret;
2812         }
2813
2814         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2815
2816         ret = ena_com_execute_admin_command(admin_queue,
2817                                             (struct ena_admin_aq_entry *)&cmd,
2818                                             sizeof(cmd),
2819                                             (struct ena_admin_acq_entry *)&resp,
2820                                             sizeof(resp));
2821
2822         if (unlikely(ret))
2823                 ena_trc_err("Failed to set host attributes: %d\n", ret);
2824
2825         return ret;
2826 }
2827
2828 /* Interrupt moderation */
2829 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2830 {
2831         return ena_com_check_supported_feature_id(ena_dev,
2832                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2833 }
2834
2835 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2836                                                           u32 intr_delay_resolution,
2837                                                           u32 *intr_moder_interval)
2838 {
2839         if (!intr_delay_resolution) {
2840                 ena_trc_err("Illegal interrupt delay granularity value\n");
2841                 return ENA_COM_FAULT;
2842         }
2843
2844         *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2845
2846         return 0;
2847 }
2848
2849
2850 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2851                                                       u32 tx_coalesce_usecs)
2852 {
2853         return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2854                                                               ena_dev->intr_delay_resolution,
2855                                                               &ena_dev->intr_moder_tx_interval);
2856 }
2857
2858 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2859                                                       u32 rx_coalesce_usecs)
2860 {
2861         return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2862                                                               ena_dev->intr_delay_resolution,
2863                                                               &ena_dev->intr_moder_rx_interval);
2864 }
2865
2866 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2867 {
2868         struct ena_admin_get_feat_resp get_resp;
2869         u16 delay_resolution;
2870         int rc;
2871
2872         rc = ena_com_get_feature(ena_dev, &get_resp,
2873                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2874
2875         if (rc) {
2876                 if (rc == ENA_COM_UNSUPPORTED) {
2877                         ena_trc_dbg("Feature %d isn't supported\n",
2878                                     ENA_ADMIN_INTERRUPT_MODERATION);
2879                         rc = 0;
2880                 } else {
2881                         ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2882                                     rc);
2883                 }
2884
2885                 /* no moderation supported, disable adaptive support */
2886                 ena_com_disable_adaptive_moderation(ena_dev);
2887                 return rc;
2888         }
2889
2890         /* if moderation is supported by device we set adaptive moderation */
2891         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2892         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2893
2894         /* Disable adaptive moderation by default - can be enabled later */
2895         ena_com_disable_adaptive_moderation(ena_dev);
2896
2897         return 0;
2898 }
2899
2900 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2901 {
2902         return ena_dev->intr_moder_tx_interval;
2903 }
2904
2905 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2906 {
2907         return ena_dev->intr_moder_rx_interval;
2908 }
2909
2910 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2911                             struct ena_admin_feature_llq_desc *llq_features,
2912                             struct ena_llq_configurations *llq_default_cfg)
2913 {
2914         int rc;
2915         struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);;
2916
2917         if (!llq_features->max_llq_num) {
2918                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2919                 return 0;
2920         }
2921
2922         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2923         if (rc)
2924                 return rc;
2925
2926         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2927                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2928
2929         if (ena_dev->tx_max_header_size == 0) {
2930                 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2931                 return -EINVAL;
2932         }
2933
2934         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2935
2936         return 0;
2937 }