1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
9 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
10 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
12 #define ENA_ADMIN_RSS_KEY_PARTS 10
14 enum ena_admin_aq_opcode {
15 ENA_ADMIN_CREATE_SQ = 1,
16 ENA_ADMIN_DESTROY_SQ = 2,
17 ENA_ADMIN_CREATE_CQ = 3,
18 ENA_ADMIN_DESTROY_CQ = 4,
19 ENA_ADMIN_GET_FEATURE = 8,
20 ENA_ADMIN_SET_FEATURE = 9,
21 ENA_ADMIN_GET_STATS = 11,
24 enum ena_admin_aq_completion_status {
25 ENA_ADMIN_SUCCESS = 0,
26 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
27 ENA_ADMIN_BAD_OPCODE = 2,
28 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
29 ENA_ADMIN_MALFORMED_REQUEST = 4,
30 /* Additional status is provided in ACQ entry extended_status */
31 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
32 ENA_ADMIN_UNKNOWN_ERROR = 6,
33 ENA_ADMIN_RESOURCE_BUSY = 7,
36 enum ena_admin_aq_feature_id {
37 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
38 ENA_ADMIN_MAX_QUEUES_NUM = 2,
39 ENA_ADMIN_HW_HINTS = 3,
41 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
42 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
43 ENA_ADMIN_MAX_QUEUES_EXT = 7,
44 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
45 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
46 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
48 ENA_ADMIN_RSS_HASH_INPUT = 18,
49 ENA_ADMIN_INTERRUPT_MODERATION = 20,
50 ENA_ADMIN_AENQ_CONFIG = 26,
51 ENA_ADMIN_LINK_CONFIG = 27,
52 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
53 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
56 enum ena_admin_placement_policy_type {
57 /* descriptors and headers are in host memory */
58 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
59 /* descriptors and headers are in device memory (a.k.a Low Latency
62 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
65 enum ena_admin_link_types {
66 ENA_ADMIN_LINK_SPEED_1G = 0x1,
67 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
68 ENA_ADMIN_LINK_SPEED_5G = 0x4,
69 ENA_ADMIN_LINK_SPEED_10G = 0x8,
70 ENA_ADMIN_LINK_SPEED_25G = 0x10,
71 ENA_ADMIN_LINK_SPEED_40G = 0x20,
72 ENA_ADMIN_LINK_SPEED_50G = 0x40,
73 ENA_ADMIN_LINK_SPEED_100G = 0x80,
74 ENA_ADMIN_LINK_SPEED_200G = 0x100,
75 ENA_ADMIN_LINK_SPEED_400G = 0x200,
78 enum ena_admin_completion_policy_type {
79 /* completion queue entry for each sq descriptor */
80 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
81 /* completion queue entry upon request in sq descriptor */
82 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
83 /* current queue head pointer is updated in OS memory upon sq
86 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
87 /* current queue head pointer is updated in OS memory for each sq
90 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
93 /* basic stats return ena_admin_basic_stats while extanded stats return a
94 * buffer (string format) with additional statistics per queue and per
97 enum ena_admin_get_stats_type {
98 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
99 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
100 /* extra HW stats for specific network interface */
101 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
104 enum ena_admin_get_stats_scope {
105 ENA_ADMIN_SPECIFIC_QUEUE = 0,
106 ENA_ADMIN_ETH_TRAFFIC = 1,
109 struct ena_admin_aq_common_desc {
115 /* as appears in ena_admin_aq_opcode */
119 * 1 : ctrl_data - control buffer address valid
120 * 2 : ctrl_data_indirect - control buffer address
121 * points to list of pages with addresses of control
128 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
129 * page list chunk. Used also at the end of indirect mode page list chunks,
132 struct ena_admin_ctrl_buff_info {
135 struct ena_common_mem_addr address;
138 struct ena_admin_sq {
142 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
149 struct ena_admin_aq_entry {
150 struct ena_admin_aq_common_desc aq_common_descriptor;
153 uint32_t inline_data_w1[3];
155 struct ena_admin_ctrl_buff_info control_buffer;
158 uint32_t inline_data_w4[12];
161 struct ena_admin_acq_common_desc {
162 /* command identifier to associate it with the aq descriptor
175 uint16_t extended_status;
177 /* indicates to the driver which AQ entry has been consumed by the
178 * device and could be reused
180 uint16_t sq_head_indx;
183 struct ena_admin_acq_entry {
184 struct ena_admin_acq_common_desc acq_common_descriptor;
186 uint32_t response_specific_data[14];
189 struct ena_admin_aq_create_sq_cmd {
190 struct ena_admin_aq_common_desc aq_common_descriptor;
192 /* 4:0 : reserved0_w1
193 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
197 uint8_t reserved8_w1;
199 /* 3:0 : placement_policy - Describing where the SQ
200 * descriptor ring and the SQ packet headers reside:
201 * 0x1 - descriptors and headers are in OS memory,
202 * 0x3 - descriptors and headers in device memory
203 * (a.k.a Low Latency Queue)
204 * 6:4 : completion_policy - Describing what policy
205 * to use for generation completion entry (cqe) in
206 * the CQ associated with this SQ: 0x0 - cqe for each
207 * sq descriptor, 0x1 - cqe upon request in sq
208 * descriptor, 0x2 - current queue head pointer is
209 * updated in OS memory upon sq descriptor request
210 * 0x3 - current queue head pointer is updated in OS
211 * memory for each sq descriptor
216 /* 0 : is_physically_contiguous - Described if the
217 * queue ring memory is allocated in physical
218 * contiguous pages or split.
219 * 7:1 : reserved17_w1
223 /* associated completion queue id. This CQ must be created prior to
228 /* submission queue depth in entries */
231 /* SQ physical base address in OS memory. This field should not be
232 * used for Low Latency queues. Has to be page aligned.
234 struct ena_common_mem_addr sq_ba;
236 /* specifies queue head writeback location in OS memory. Valid if
237 * completion_policy is set to completion_policy_head_on_demand or
238 * completion_policy_head. Has to be cache aligned
240 struct ena_common_mem_addr sq_head_writeback;
242 uint32_t reserved0_w7;
244 uint32_t reserved0_w8;
247 enum ena_admin_sq_direction {
248 ENA_ADMIN_SQ_DIRECTION_TX = 1,
249 ENA_ADMIN_SQ_DIRECTION_RX = 2,
252 struct ena_admin_acq_create_sq_resp_desc {
253 struct ena_admin_acq_common_desc acq_common_desc;
259 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
260 uint32_t sq_doorbell_offset;
262 /* low latency queue ring base address as an offset to PCIe MMIO
265 uint32_t llq_descriptors_offset;
267 /* low latency queue headers' memory as an offset to PCIe MMIO
270 uint32_t llq_headers_offset;
273 struct ena_admin_aq_destroy_sq_cmd {
274 struct ena_admin_aq_common_desc aq_common_descriptor;
276 struct ena_admin_sq sq;
279 struct ena_admin_acq_destroy_sq_resp_desc {
280 struct ena_admin_acq_common_desc acq_common_desc;
283 struct ena_admin_aq_create_cq_cmd {
284 struct ena_admin_aq_common_desc aq_common_descriptor;
287 * 5 : interrupt_mode_enabled - if set, cq operates
288 * in interrupt mode, otherwise - polling
293 /* 4:0 : cq_entry_size_words - size of CQ entry in
294 * 32-bit words, valid values: 4, 8.
299 /* completion queue depth in # of entries. must be power of 2 */
302 /* msix vector assigned to this cq */
303 uint32_t msix_vector;
305 /* cq physical base address in OS memory. CQ must be physically
308 struct ena_common_mem_addr cq_ba;
311 struct ena_admin_acq_create_cq_resp_desc {
312 struct ena_admin_acq_common_desc acq_common_desc;
316 /* actual cq depth in number of entries */
317 uint16_t cq_actual_depth;
319 uint32_t numa_node_register_offset;
321 uint32_t cq_head_db_register_offset;
323 uint32_t cq_interrupt_unmask_register_offset;
326 struct ena_admin_aq_destroy_cq_cmd {
327 struct ena_admin_aq_common_desc aq_common_descriptor;
334 struct ena_admin_acq_destroy_cq_resp_desc {
335 struct ena_admin_acq_common_desc acq_common_desc;
338 /* ENA AQ Get Statistics command. Extended statistics are placed in control
339 * buffer pointed by AQ entry
341 struct ena_admin_aq_get_stats_cmd {
342 struct ena_admin_aq_common_desc aq_common_descriptor;
345 /* command specific inline data */
346 uint32_t inline_data_w1[3];
348 struct ena_admin_ctrl_buff_info control_buffer;
351 /* stats type as defined in enum ena_admin_get_stats_type */
354 /* stats scope defined in enum ena_admin_get_stats_scope */
359 /* queue id. used when scope is specific_queue */
362 /* device id, value 0xFFFF means mine. only privileged device can get
363 * stats of other device
368 /* Basic Statistics Command. */
369 struct ena_admin_basic_stats {
370 uint32_t tx_bytes_low;
372 uint32_t tx_bytes_high;
374 uint32_t tx_pkts_low;
376 uint32_t tx_pkts_high;
378 uint32_t rx_bytes_low;
380 uint32_t rx_bytes_high;
382 uint32_t rx_pkts_low;
384 uint32_t rx_pkts_high;
386 uint32_t rx_drops_low;
388 uint32_t rx_drops_high;
390 uint32_t tx_drops_low;
392 uint32_t tx_drops_high;
395 /* ENI Statistics Command. */
396 struct ena_admin_eni_stats {
397 /* The number of packets shaped due to inbound aggregate BW
398 * allowance being exceeded
400 uint64_t bw_in_allowance_exceeded;
402 /* The number of packets shaped due to outbound aggregate BW
403 * allowance being exceeded
405 uint64_t bw_out_allowance_exceeded;
407 /* The number of packets shaped due to PPS allowance being exceeded */
408 uint64_t pps_allowance_exceeded;
410 /* The number of packets shaped due to connection tracking
411 * allowance being exceeded and leading to failure in establishment
414 uint64_t conntrack_allowance_exceeded;
416 /* The number of packets shaped due to linklocal packet rate
417 * allowance being exceeded
419 uint64_t linklocal_allowance_exceeded;
422 struct ena_admin_acq_get_stats_resp {
423 struct ena_admin_acq_common_desc acq_common_desc;
428 struct ena_admin_basic_stats basic_stats;
430 struct ena_admin_eni_stats eni_stats;
434 struct ena_admin_get_set_feature_common_desc {
435 /* 1:0 : select - 0x1 - current value; 0x3 - default
441 /* as appears in ena_admin_aq_feature_id */
444 /* The driver specifies the max feature version it supports and the
445 * device responds with the currently supported feature version. The
446 * field is zero based
448 uint8_t feature_version;
453 struct ena_admin_device_attr_feature_desc {
456 uint32_t device_version;
458 /* bitmap of ena_admin_aq_feature_id */
459 uint32_t supported_features;
463 /* Indicates how many bits are used physical address access. */
464 uint32_t phys_addr_width;
466 /* Indicates how many bits are used virtual address access. */
467 uint32_t virt_addr_width;
469 /* unicast MAC address (in Network byte order) */
472 uint8_t reserved7[2];
477 enum ena_admin_llq_header_location {
478 /* header is in descriptor list */
479 ENA_ADMIN_INLINE_HEADER = 1,
480 /* header in a separate ring, implies 16B descriptor list entry */
481 ENA_ADMIN_HEADER_RING = 2,
484 enum ena_admin_llq_ring_entry_size {
485 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
486 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
487 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
490 enum ena_admin_llq_num_descs_before_header {
491 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
492 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
493 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
494 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
495 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
498 /* packet descriptor list entry always starts with one or more descriptors,
499 * followed by a header. The rest of the descriptors are located in the
500 * beginning of the subsequent entry. Stride refers to how the rest of the
501 * descriptors are placed. This field is relevant only for inline header
504 enum ena_admin_llq_stride_ctrl {
505 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
506 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
509 enum ena_admin_accel_mode_feat {
510 ENA_ADMIN_DISABLE_META_CACHING = 0,
511 ENA_ADMIN_LIMIT_TX_BURST = 1,
514 struct ena_admin_accel_mode_get {
515 /* bit field of enum ena_admin_accel_mode_feat */
516 uint16_t supported_flags;
518 /* maximum burst size between two doorbells. The size is in bytes */
519 uint16_t max_tx_burst_size;
522 struct ena_admin_accel_mode_set {
523 /* bit field of enum ena_admin_accel_mode_feat */
524 uint16_t enabled_flags;
529 struct ena_admin_accel_mode_req {
533 struct ena_admin_accel_mode_get get;
535 struct ena_admin_accel_mode_set set;
539 struct ena_admin_feature_llq_desc {
540 uint32_t max_llq_num;
542 uint32_t max_llq_depth;
544 /* specify the header locations the device supports. bitfield of
545 * enum ena_admin_llq_header_location.
547 uint16_t header_location_ctrl_supported;
549 /* the header location the driver selected to use. */
550 uint16_t header_location_ctrl_enabled;
552 /* if inline header is specified - this is the size of descriptor
553 * list entry. If header in a separate ring is specified - this is
554 * the size of header ring entry. bitfield of enum
555 * ena_admin_llq_ring_entry_size. specify the entry sizes the device
558 uint16_t entry_size_ctrl_supported;
560 /* the entry size the driver selected to use. */
561 uint16_t entry_size_ctrl_enabled;
563 /* valid only if inline header is specified. First entry associated
564 * with the packet includes descriptors and header. Rest of the
565 * entries occupied by descriptors. This parameter defines the max
566 * number of descriptors precedding the header in the first entry.
567 * The field is bitfield of enum
568 * ena_admin_llq_num_descs_before_header and specify the values the
571 uint16_t desc_num_before_header_supported;
573 /* the desire field the driver selected to use */
574 uint16_t desc_num_before_header_enabled;
576 /* valid only if inline was chosen. bitfield of enum
577 * ena_admin_llq_stride_ctrl
579 uint16_t descriptors_stride_ctrl_supported;
581 /* the stride control the driver selected to use */
582 uint16_t descriptors_stride_ctrl_enabled;
587 /* accelerated low latency queues requirement. Driver needs to
588 * support those requirements in order to use accelerated LLQ
590 struct ena_admin_accel_mode_req accel_mode;
593 struct ena_admin_queue_ext_feature_fields {
594 uint32_t max_tx_sq_num;
596 uint32_t max_tx_cq_num;
598 uint32_t max_rx_sq_num;
600 uint32_t max_rx_cq_num;
602 uint32_t max_tx_sq_depth;
604 uint32_t max_tx_cq_depth;
606 uint32_t max_rx_sq_depth;
608 uint32_t max_rx_cq_depth;
610 uint32_t max_tx_header_size;
612 /* Maximum Descriptors number, including meta descriptor, allowed for
615 uint16_t max_per_packet_tx_descs;
617 /* Maximum Descriptors number allowed for a single Rx packet */
618 uint16_t max_per_packet_rx_descs;
621 struct ena_admin_queue_feature_desc {
624 uint32_t max_sq_depth;
628 uint32_t max_cq_depth;
630 uint32_t max_legacy_llq_num;
632 uint32_t max_legacy_llq_depth;
634 uint32_t max_header_size;
636 /* Maximum Descriptors number, including meta descriptor, allowed for
639 uint16_t max_packet_tx_descs;
641 /* Maximum Descriptors number allowed for a single Rx packet */
642 uint16_t max_packet_rx_descs;
645 struct ena_admin_set_feature_mtu_desc {
650 struct ena_admin_get_extra_properties_strings_desc {
654 struct ena_admin_get_extra_properties_flags_desc {
658 struct ena_admin_set_feature_host_attr_desc {
659 /* host OS info base address in OS memory. host info is 4KB of
660 * physically contiguous
662 struct ena_common_mem_addr os_info_ba;
664 /* host debug area base address in OS memory. debug area must be
665 * physically contiguous
667 struct ena_common_mem_addr debug_ba;
669 /* debug area size */
670 uint32_t debug_area_size;
673 struct ena_admin_feature_intr_moder_desc {
674 /* interrupt delay granularity in usec */
675 uint16_t intr_delay_resolution;
680 struct ena_admin_get_feature_link_desc {
681 /* Link speed in Mb */
684 /* bit field of enum ena_admin_link types */
688 * 1 : duplex - Full Duplex
694 struct ena_admin_feature_aenq_desc {
695 /* bitmask for AENQ groups the device can report */
696 uint32_t supported_groups;
698 /* bitmask for AENQ groups to report */
699 uint32_t enabled_groups;
702 struct ena_admin_feature_offload_desc {
703 /* 0 : TX_L3_csum_ipv4
704 * 1 : TX_L4_ipv4_csum_part - The checksum field
705 * should be initialized with pseudo header checksum
706 * 2 : TX_L4_ipv4_csum_full
707 * 3 : TX_L4_ipv6_csum_part - The checksum field
708 * should be initialized with pseudo header checksum
709 * 4 : TX_L4_ipv6_csum_full
716 /* Receive side supported stateless offload
717 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
718 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
719 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
720 * 3 : RX_hash - Hash calculation
722 uint32_t rx_supported;
727 enum ena_admin_hash_functions {
728 ENA_ADMIN_TOEPLITZ = 1,
732 struct ena_admin_feature_rss_flow_hash_control {
737 uint32_t key[ENA_ADMIN_RSS_KEY_PARTS];
740 struct ena_admin_feature_rss_flow_hash_function {
741 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
742 uint32_t supported_func;
744 /* 7:0 : selected_func - bitmask of
745 * ena_admin_hash_functions
747 uint32_t selected_func;
753 /* RSS flow hash protocols */
754 enum ena_admin_flow_hash_proto {
755 ENA_ADMIN_RSS_TCP4 = 0,
756 ENA_ADMIN_RSS_UDP4 = 1,
757 ENA_ADMIN_RSS_TCP6 = 2,
758 ENA_ADMIN_RSS_UDP6 = 3,
759 ENA_ADMIN_RSS_IP4 = 4,
760 ENA_ADMIN_RSS_IP6 = 5,
761 ENA_ADMIN_RSS_IP4_FRAG = 6,
762 ENA_ADMIN_RSS_NOT_IP = 7,
763 /* TCPv6 with extension header */
764 ENA_ADMIN_RSS_TCP6_EX = 8,
765 /* IPv6 with extension header */
766 ENA_ADMIN_RSS_IP6_EX = 9,
767 ENA_ADMIN_RSS_PROTO_NUM = 16,
770 /* RSS flow hash fields */
771 enum ena_admin_flow_hash_fields {
772 /* Ethernet Dest Addr */
773 ENA_ADMIN_RSS_L2_DA = BIT(0),
774 /* Ethernet Src Addr */
775 ENA_ADMIN_RSS_L2_SA = BIT(1),
776 /* ipv4/6 Dest Addr */
777 ENA_ADMIN_RSS_L3_DA = BIT(2),
778 /* ipv4/6 Src Addr */
779 ENA_ADMIN_RSS_L3_SA = BIT(3),
780 /* tcp/udp Dest Port */
781 ENA_ADMIN_RSS_L4_DP = BIT(4),
782 /* tcp/udp Src Port */
783 ENA_ADMIN_RSS_L4_SP = BIT(5),
786 struct ena_admin_proto_input {
787 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
793 struct ena_admin_feature_rss_hash_control {
794 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
796 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
798 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
800 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
803 struct ena_admin_feature_rss_flow_hash_input {
804 /* supported hash input sorting
805 * 1 : L3_sort - support swap L3 addresses if DA is
807 * 2 : L4_sort - support swap L4 ports if DP smaller
810 uint16_t supported_input_sort;
812 /* enabled hash input sorting
813 * 1 : enable_L3_sort - enable swap L3 addresses if
815 * 2 : enable_L4_sort - enable swap L4 ports if DP
818 uint16_t enabled_input_sort;
821 enum ena_admin_os_type {
822 ENA_ADMIN_OS_LINUX = 1,
823 ENA_ADMIN_OS_WIN = 2,
824 ENA_ADMIN_OS_DPDK = 3,
825 ENA_ADMIN_OS_FREEBSD = 4,
826 ENA_ADMIN_OS_IPXE = 5,
827 ENA_ADMIN_OS_ESXI = 6,
828 ENA_ADMIN_OS_GROUPS_NUM = 6,
831 struct ena_admin_host_info {
832 /* defined in enum ena_admin_os_type */
835 /* os distribution string format */
836 uint8_t os_dist_str[128];
838 /* OS distribution numeric format */
841 /* kernel version string format */
842 uint8_t kernel_ver_str[32];
844 /* Kernel version numeric format */
850 * 31:24 : module_type
852 uint32_t driver_version;
854 /* features bitmap */
855 uint32_t supported_network_features[2];
857 /* ENA spec version of driver */
858 uint16_t ena_spec_version;
860 /* ENA device's Bus, Device and Function
872 /* 0 : mutable_rss_table_size
874 * 2 : interrupt_moderation
875 * 3 : map_rx_buf_bidirectional
876 * 4 : rss_configurable_function_key
879 uint32_t driver_supported_features;
882 struct ena_admin_rss_ind_table_entry {
888 struct ena_admin_feature_rss_ind_table {
889 /* min supported table size (2^min_size) */
892 /* max supported table size (2^max_size) */
895 /* table size (2^size) */
898 /* 0 : one_entry_update - The ENA device supports
899 * setting a single RSS table entry
905 /* index of the inline entry. 0xFFFFFFFF means invalid */
906 uint32_t inline_index;
908 /* used for updating single entry, ignored when setting the entire
909 * table through the control buffer.
911 struct ena_admin_rss_ind_table_entry inline_entry;
914 /* When hint value is 0, driver should use it's own predefined value */
915 struct ena_admin_ena_hw_hints {
917 uint16_t mmio_read_timeout;
920 uint16_t driver_watchdog_timeout;
922 /* Per packet tx completion timeout. value in ms */
923 uint16_t missing_tx_completion_timeout;
925 uint16_t missed_tx_completion_count_threshold_to_reset;
928 uint16_t admin_completion_tx_timeout;
930 uint16_t netdev_wd_timeout;
932 uint16_t max_tx_sgl_size;
934 uint16_t max_rx_sgl_size;
936 uint16_t reserved[8];
939 struct ena_admin_get_feat_cmd {
940 struct ena_admin_aq_common_desc aq_common_descriptor;
942 struct ena_admin_ctrl_buff_info control_buffer;
944 struct ena_admin_get_set_feature_common_desc feat_common;
949 struct ena_admin_queue_ext_feature_desc {
953 uint8_t reserved1[3];
956 struct ena_admin_queue_ext_feature_fields max_queue_ext;
962 struct ena_admin_get_feat_resp {
963 struct ena_admin_acq_common_desc acq_common_desc;
968 struct ena_admin_device_attr_feature_desc dev_attr;
970 struct ena_admin_feature_llq_desc llq;
972 struct ena_admin_queue_feature_desc max_queue;
974 struct ena_admin_queue_ext_feature_desc max_queue_ext;
976 struct ena_admin_feature_aenq_desc aenq;
978 struct ena_admin_get_feature_link_desc link;
980 struct ena_admin_feature_offload_desc offload;
982 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
984 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
986 struct ena_admin_feature_rss_ind_table ind_table;
988 struct ena_admin_feature_intr_moder_desc intr_moderation;
990 struct ena_admin_ena_hw_hints hw_hints;
992 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
994 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
998 struct ena_admin_set_feat_cmd {
999 struct ena_admin_aq_common_desc aq_common_descriptor;
1001 struct ena_admin_ctrl_buff_info control_buffer;
1003 struct ena_admin_get_set_feature_common_desc feat_common;
1009 struct ena_admin_set_feature_mtu_desc mtu;
1011 /* host attributes */
1012 struct ena_admin_set_feature_host_attr_desc host_attr;
1014 /* AENQ configuration */
1015 struct ena_admin_feature_aenq_desc aenq;
1017 /* rss flow hash function */
1018 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1020 /* rss flow hash input */
1021 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1023 /* rss indirection table */
1024 struct ena_admin_feature_rss_ind_table ind_table;
1026 /* LLQ configuration */
1027 struct ena_admin_feature_llq_desc llq;
1031 struct ena_admin_set_feat_resp {
1032 struct ena_admin_acq_common_desc acq_common_desc;
1039 struct ena_admin_aenq_common_desc {
1045 * 7:1 : reserved - MBZ
1049 uint8_t reserved1[3];
1051 uint32_t timestamp_low;
1053 uint32_t timestamp_high;
1056 /* asynchronous event notification groups */
1057 enum ena_admin_aenq_group {
1058 ENA_ADMIN_LINK_CHANGE = 0,
1059 ENA_ADMIN_FATAL_ERROR = 1,
1060 ENA_ADMIN_WARNING = 2,
1061 ENA_ADMIN_NOTIFICATION = 3,
1062 ENA_ADMIN_KEEP_ALIVE = 4,
1063 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
1066 enum ena_admin_aenq_notification_syndrom {
1067 ENA_ADMIN_SUSPEND = 0,
1068 ENA_ADMIN_RESUME = 1,
1069 ENA_ADMIN_UPDATE_HINTS = 2,
1072 struct ena_admin_aenq_entry {
1073 struct ena_admin_aenq_common_desc aenq_common_desc;
1075 /* command specific inline data */
1076 uint32_t inline_data_w4[12];
1079 struct ena_admin_aenq_link_change_desc {
1080 struct ena_admin_aenq_common_desc aenq_common_desc;
1082 /* 0 : link_status */
1086 struct ena_admin_aenq_keep_alive_desc {
1087 struct ena_admin_aenq_common_desc aenq_common_desc;
1089 uint32_t rx_drops_low;
1091 uint32_t rx_drops_high;
1093 uint32_t tx_drops_low;
1095 uint32_t tx_drops_high;
1098 struct ena_admin_ena_mmio_req_read_less_resp {
1103 /* value is valid when poll is cleared */
1107 /* aq_common_desc */
1108 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1109 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1110 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1111 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1112 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1113 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1116 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1117 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1119 /* acq_common_desc */
1120 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1121 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1123 /* aq_create_sq_cmd */
1124 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1125 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1126 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1127 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1128 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1129 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1131 /* aq_create_cq_cmd */
1132 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1133 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1134 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1136 /* get_set_feature_common_desc */
1137 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1139 /* get_feature_link_desc */
1140 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1141 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1142 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1144 /* feature_offload_desc */
1145 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1146 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1147 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1148 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1149 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1150 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1151 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1152 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1153 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1154 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1155 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1156 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1157 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1158 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1159 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1160 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1161 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1162 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1163 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1164 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1165 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1166 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1168 /* feature_rss_flow_hash_function */
1169 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1170 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1172 /* feature_rss_flow_hash_input */
1173 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1174 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1175 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1176 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1177 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1178 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1179 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1180 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1183 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1184 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1185 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1186 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1187 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1188 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1189 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1190 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1191 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1192 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1193 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1194 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1195 #define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0)
1196 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1197 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1198 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1199 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1200 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT 3
1201 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK BIT(3)
1202 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1203 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1205 /* feature_rss_ind_table */
1206 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1208 /* aenq_common_desc */
1209 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1211 /* aenq_link_change_desc */
1212 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1214 #if !defined(DEFS_LINUX_MAINLINE)
1215 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1217 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1220 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1222 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1225 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1227 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1230 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1232 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1235 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1237 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1240 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1242 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1245 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1247 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1250 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1252 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1255 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1257 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1260 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1262 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1265 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1267 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1270 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1272 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1275 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1277 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1280 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1282 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1285 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1287 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1290 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1292 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1295 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1297 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1300 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1302 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1305 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1307 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1310 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1312 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1315 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1317 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1320 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1322 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1325 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1327 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1330 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1332 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1335 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1337 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1340 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1342 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1345 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1347 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1350 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1352 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1355 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1357 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1360 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1362 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1365 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1367 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1370 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1372 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1375 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1377 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1380 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1382 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1385 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1387 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1390 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1392 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1395 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1397 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1400 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1402 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1405 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1407 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1410 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1412 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1415 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1417 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1420 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1422 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1425 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1427 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1430 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1432 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1435 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1437 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1440 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1442 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1445 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1447 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1450 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1452 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1455 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1457 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1460 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1462 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1465 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1467 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1470 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1472 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1475 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1477 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1480 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1482 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1485 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1487 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1490 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1492 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1495 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1497 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1500 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1502 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1505 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1507 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1510 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1512 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1515 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1517 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1520 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1522 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1525 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1527 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1530 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1532 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1535 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1537 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1540 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1542 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1545 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1547 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1550 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1552 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1555 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1557 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1560 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1562 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1565 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1567 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1570 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1572 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1575 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1577 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1580 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1582 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1585 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1587 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1590 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1592 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1595 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1597 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1600 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1602 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1605 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1607 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1610 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1612 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1615 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1617 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1620 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1622 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1625 static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p)
1627 return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1630 static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val)
1632 p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1635 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1637 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1640 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1642 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1645 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1647 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1650 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1652 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1655 static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p)
1657 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT;
1660 static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val)
1662 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK;
1665 static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p)
1667 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT;
1670 static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val)
1672 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
1675 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1677 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1680 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1682 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1685 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1687 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1690 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1692 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1695 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1697 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1700 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1702 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1705 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1706 #endif /* _ENA_ADMIN_H_ */