1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
9 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
10 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
12 enum ena_admin_aq_opcode {
13 ENA_ADMIN_CREATE_SQ = 1,
14 ENA_ADMIN_DESTROY_SQ = 2,
15 ENA_ADMIN_CREATE_CQ = 3,
16 ENA_ADMIN_DESTROY_CQ = 4,
17 ENA_ADMIN_GET_FEATURE = 8,
18 ENA_ADMIN_SET_FEATURE = 9,
19 ENA_ADMIN_GET_STATS = 11,
22 enum ena_admin_aq_completion_status {
23 ENA_ADMIN_SUCCESS = 0,
24 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
25 ENA_ADMIN_BAD_OPCODE = 2,
26 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
27 ENA_ADMIN_MALFORMED_REQUEST = 4,
28 /* Additional status is provided in ACQ entry extended_status */
29 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
30 ENA_ADMIN_UNKNOWN_ERROR = 6,
31 ENA_ADMIN_RESOURCE_BUSY = 7,
34 enum ena_admin_aq_feature_id {
35 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
36 ENA_ADMIN_MAX_QUEUES_NUM = 2,
37 ENA_ADMIN_HW_HINTS = 3,
39 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
40 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
41 ENA_ADMIN_MAX_QUEUES_EXT = 7,
42 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
43 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
44 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
46 ENA_ADMIN_RSS_HASH_INPUT = 18,
47 ENA_ADMIN_INTERRUPT_MODERATION = 20,
48 ENA_ADMIN_AENQ_CONFIG = 26,
49 ENA_ADMIN_LINK_CONFIG = 27,
50 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
51 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
54 enum ena_admin_placement_policy_type {
55 /* descriptors and headers are in host memory */
56 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
57 /* descriptors and headers are in device memory (a.k.a Low Latency
60 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
63 enum ena_admin_link_types {
64 ENA_ADMIN_LINK_SPEED_1G = 0x1,
65 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
66 ENA_ADMIN_LINK_SPEED_5G = 0x4,
67 ENA_ADMIN_LINK_SPEED_10G = 0x8,
68 ENA_ADMIN_LINK_SPEED_25G = 0x10,
69 ENA_ADMIN_LINK_SPEED_40G = 0x20,
70 ENA_ADMIN_LINK_SPEED_50G = 0x40,
71 ENA_ADMIN_LINK_SPEED_100G = 0x80,
72 ENA_ADMIN_LINK_SPEED_200G = 0x100,
73 ENA_ADMIN_LINK_SPEED_400G = 0x200,
76 enum ena_admin_completion_policy_type {
77 /* completion queue entry for each sq descriptor */
78 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
79 /* completion queue entry upon request in sq descriptor */
80 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
81 /* current queue head pointer is updated in OS memory upon sq
84 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
85 /* current queue head pointer is updated in OS memory for each sq
88 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
91 /* basic stats return ena_admin_basic_stats while extanded stats return a
92 * buffer (string format) with additional statistics per queue and per
95 enum ena_admin_get_stats_type {
96 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
97 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
100 enum ena_admin_get_stats_scope {
101 ENA_ADMIN_SPECIFIC_QUEUE = 0,
102 ENA_ADMIN_ETH_TRAFFIC = 1,
105 struct ena_admin_aq_common_desc {
111 /* as appears in ena_admin_aq_opcode */
115 * 1 : ctrl_data - control buffer address valid
116 * 2 : ctrl_data_indirect - control buffer address
117 * points to list of pages with addresses of control
124 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
125 * page list chunk. Used also at the end of indirect mode page list chunks,
128 struct ena_admin_ctrl_buff_info {
131 struct ena_common_mem_addr address;
134 struct ena_admin_sq {
138 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
145 struct ena_admin_aq_entry {
146 struct ena_admin_aq_common_desc aq_common_descriptor;
149 uint32_t inline_data_w1[3];
151 struct ena_admin_ctrl_buff_info control_buffer;
154 uint32_t inline_data_w4[12];
157 struct ena_admin_acq_common_desc {
158 /* command identifier to associate it with the aq descriptor
171 uint16_t extended_status;
173 /* indicates to the driver which AQ entry has been consumed by the
174 * device and could be reused
176 uint16_t sq_head_indx;
179 struct ena_admin_acq_entry {
180 struct ena_admin_acq_common_desc acq_common_descriptor;
182 uint32_t response_specific_data[14];
185 struct ena_admin_aq_create_sq_cmd {
186 struct ena_admin_aq_common_desc aq_common_descriptor;
188 /* 4:0 : reserved0_w1
189 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
193 uint8_t reserved8_w1;
195 /* 3:0 : placement_policy - Describing where the SQ
196 * descriptor ring and the SQ packet headers reside:
197 * 0x1 - descriptors and headers are in OS memory,
198 * 0x3 - descriptors and headers in device memory
199 * (a.k.a Low Latency Queue)
200 * 6:4 : completion_policy - Describing what policy
201 * to use for generation completion entry (cqe) in
202 * the CQ associated with this SQ: 0x0 - cqe for each
203 * sq descriptor, 0x1 - cqe upon request in sq
204 * descriptor, 0x2 - current queue head pointer is
205 * updated in OS memory upon sq descriptor request
206 * 0x3 - current queue head pointer is updated in OS
207 * memory for each sq descriptor
212 /* 0 : is_physically_contiguous - Described if the
213 * queue ring memory is allocated in physical
214 * contiguous pages or split.
215 * 7:1 : reserved17_w1
219 /* associated completion queue id. This CQ must be created prior to
224 /* submission queue depth in entries */
227 /* SQ physical base address in OS memory. This field should not be
228 * used for Low Latency queues. Has to be page aligned.
230 struct ena_common_mem_addr sq_ba;
232 /* specifies queue head writeback location in OS memory. Valid if
233 * completion_policy is set to completion_policy_head_on_demand or
234 * completion_policy_head. Has to be cache aligned
236 struct ena_common_mem_addr sq_head_writeback;
238 uint32_t reserved0_w7;
240 uint32_t reserved0_w8;
243 enum ena_admin_sq_direction {
244 ENA_ADMIN_SQ_DIRECTION_TX = 1,
245 ENA_ADMIN_SQ_DIRECTION_RX = 2,
248 struct ena_admin_acq_create_sq_resp_desc {
249 struct ena_admin_acq_common_desc acq_common_desc;
255 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
256 uint32_t sq_doorbell_offset;
258 /* low latency queue ring base address as an offset to PCIe MMIO
261 uint32_t llq_descriptors_offset;
263 /* low latency queue headers' memory as an offset to PCIe MMIO
266 uint32_t llq_headers_offset;
269 struct ena_admin_aq_destroy_sq_cmd {
270 struct ena_admin_aq_common_desc aq_common_descriptor;
272 struct ena_admin_sq sq;
275 struct ena_admin_acq_destroy_sq_resp_desc {
276 struct ena_admin_acq_common_desc acq_common_desc;
279 struct ena_admin_aq_create_cq_cmd {
280 struct ena_admin_aq_common_desc aq_common_descriptor;
283 * 5 : interrupt_mode_enabled - if set, cq operates
284 * in interrupt mode, otherwise - polling
289 /* 4:0 : cq_entry_size_words - size of CQ entry in
290 * 32-bit words, valid values: 4, 8.
295 /* completion queue depth in # of entries. must be power of 2 */
298 /* msix vector assigned to this cq */
299 uint32_t msix_vector;
301 /* cq physical base address in OS memory. CQ must be physically
304 struct ena_common_mem_addr cq_ba;
307 struct ena_admin_acq_create_cq_resp_desc {
308 struct ena_admin_acq_common_desc acq_common_desc;
312 /* actual cq depth in number of entries */
313 uint16_t cq_actual_depth;
315 uint32_t numa_node_register_offset;
317 uint32_t cq_head_db_register_offset;
319 uint32_t cq_interrupt_unmask_register_offset;
322 struct ena_admin_aq_destroy_cq_cmd {
323 struct ena_admin_aq_common_desc aq_common_descriptor;
330 struct ena_admin_acq_destroy_cq_resp_desc {
331 struct ena_admin_acq_common_desc acq_common_desc;
334 /* ENA AQ Get Statistics command. Extended statistics are placed in control
335 * buffer pointed by AQ entry
337 struct ena_admin_aq_get_stats_cmd {
338 struct ena_admin_aq_common_desc aq_common_descriptor;
341 /* command specific inline data */
342 uint32_t inline_data_w1[3];
344 struct ena_admin_ctrl_buff_info control_buffer;
347 /* stats type as defined in enum ena_admin_get_stats_type */
350 /* stats scope defined in enum ena_admin_get_stats_scope */
355 /* queue id. used when scope is specific_queue */
358 /* device id, value 0xFFFF means mine. only privileged device can get
359 * stats of other device
364 /* Basic Statistics Command. */
365 struct ena_admin_basic_stats {
366 uint32_t tx_bytes_low;
368 uint32_t tx_bytes_high;
370 uint32_t tx_pkts_low;
372 uint32_t tx_pkts_high;
374 uint32_t rx_bytes_low;
376 uint32_t rx_bytes_high;
378 uint32_t rx_pkts_low;
380 uint32_t rx_pkts_high;
382 uint32_t rx_drops_low;
384 uint32_t rx_drops_high;
387 struct ena_admin_acq_get_stats_resp {
388 struct ena_admin_acq_common_desc acq_common_desc;
390 struct ena_admin_basic_stats basic_stats;
393 struct ena_admin_get_set_feature_common_desc {
394 /* 1:0 : select - 0x1 - current value; 0x3 - default
400 /* as appears in ena_admin_aq_feature_id */
403 /* The driver specifies the max feature version it supports and the
404 * device responds with the currently supported feature version. The
405 * field is zero based
407 uint8_t feature_version;
412 struct ena_admin_device_attr_feature_desc {
415 uint32_t device_version;
417 /* bitmap of ena_admin_aq_feature_id */
418 uint32_t supported_features;
422 /* Indicates how many bits are used physical address access. */
423 uint32_t phys_addr_width;
425 /* Indicates how many bits are used virtual address access. */
426 uint32_t virt_addr_width;
428 /* unicast MAC address (in Network byte order) */
431 uint8_t reserved7[2];
436 enum ena_admin_llq_header_location {
437 /* header is in descriptor list */
438 ENA_ADMIN_INLINE_HEADER = 1,
439 /* header in a separate ring, implies 16B descriptor list entry */
440 ENA_ADMIN_HEADER_RING = 2,
443 enum ena_admin_llq_ring_entry_size {
444 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
445 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
446 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
449 enum ena_admin_llq_num_descs_before_header {
450 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
451 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
452 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
453 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
454 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
457 /* packet descriptor list entry always starts with one or more descriptors,
458 * followed by a header. The rest of the descriptors are located in the
459 * beginning of the subsequent entry. Stride refers to how the rest of the
460 * descriptors are placed. This field is relevant only for inline header
463 enum ena_admin_llq_stride_ctrl {
464 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
465 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
468 struct ena_admin_feature_llq_desc {
469 uint32_t max_llq_num;
471 uint32_t max_llq_depth;
473 /* specify the header locations the device supports. bitfield of
474 * enum ena_admin_llq_header_location.
476 uint16_t header_location_ctrl_supported;
478 /* the header location the driver selected to use. */
479 uint16_t header_location_ctrl_enabled;
481 /* if inline header is specified - this is the size of descriptor
482 * list entry. If header in a separate ring is specified - this is
483 * the size of header ring entry. bitfield of enum
484 * ena_admin_llq_ring_entry_size. specify the entry sizes the device
487 uint16_t entry_size_ctrl_supported;
489 /* the entry size the driver selected to use. */
490 uint16_t entry_size_ctrl_enabled;
492 /* valid only if inline header is specified. First entry associated
493 * with the packet includes descriptors and header. Rest of the
494 * entries occupied by descriptors. This parameter defines the max
495 * number of descriptors precedding the header in the first entry.
496 * The field is bitfield of enum
497 * ena_admin_llq_num_descs_before_header and specify the values the
500 uint16_t desc_num_before_header_supported;
502 /* the desire field the driver selected to use */
503 uint16_t desc_num_before_header_enabled;
505 /* valid only if inline was chosen. bitfield of enum
506 * ena_admin_llq_stride_ctrl
508 uint16_t descriptors_stride_ctrl_supported;
510 /* the stride control the driver selected to use */
511 uint16_t descriptors_stride_ctrl_enabled;
513 /* Maximum size in bytes taken by llq entries in a single tx burst.
514 * Set to 0 when there is no such limit.
516 uint32_t max_tx_burst_size;
519 struct ena_admin_queue_ext_feature_fields {
520 uint32_t max_tx_sq_num;
522 uint32_t max_tx_cq_num;
524 uint32_t max_rx_sq_num;
526 uint32_t max_rx_cq_num;
528 uint32_t max_tx_sq_depth;
530 uint32_t max_tx_cq_depth;
532 uint32_t max_rx_sq_depth;
534 uint32_t max_rx_cq_depth;
536 uint32_t max_tx_header_size;
538 /* Maximum Descriptors number, including meta descriptor, allowed for
541 uint16_t max_per_packet_tx_descs;
543 /* Maximum Descriptors number allowed for a single Rx packet */
544 uint16_t max_per_packet_rx_descs;
547 struct ena_admin_queue_feature_desc {
550 uint32_t max_sq_depth;
554 uint32_t max_cq_depth;
556 uint32_t max_legacy_llq_num;
558 uint32_t max_legacy_llq_depth;
560 uint32_t max_header_size;
562 /* Maximum Descriptors number, including meta descriptor, allowed for
565 uint16_t max_packet_tx_descs;
567 /* Maximum Descriptors number allowed for a single Rx packet */
568 uint16_t max_packet_rx_descs;
571 struct ena_admin_set_feature_mtu_desc {
576 struct ena_admin_get_extra_properties_strings_desc {
580 struct ena_admin_get_extra_properties_flags_desc {
584 struct ena_admin_set_feature_host_attr_desc {
585 /* host OS info base address in OS memory. host info is 4KB of
586 * physically contiguous
588 struct ena_common_mem_addr os_info_ba;
590 /* host debug area base address in OS memory. debug area must be
591 * physically contiguous
593 struct ena_common_mem_addr debug_ba;
595 /* debug area size */
596 uint32_t debug_area_size;
599 struct ena_admin_feature_intr_moder_desc {
600 /* interrupt delay granularity in usec */
601 uint16_t intr_delay_resolution;
606 struct ena_admin_get_feature_link_desc {
607 /* Link speed in Mb */
610 /* bit field of enum ena_admin_link types */
614 * 1 : duplex - Full Duplex
620 struct ena_admin_feature_aenq_desc {
621 /* bitmask for AENQ groups the device can report */
622 uint32_t supported_groups;
624 /* bitmask for AENQ groups to report */
625 uint32_t enabled_groups;
628 struct ena_admin_feature_offload_desc {
629 /* 0 : TX_L3_csum_ipv4
630 * 1 : TX_L4_ipv4_csum_part - The checksum field
631 * should be initialized with pseudo header checksum
632 * 2 : TX_L4_ipv4_csum_full
633 * 3 : TX_L4_ipv6_csum_part - The checksum field
634 * should be initialized with pseudo header checksum
635 * 4 : TX_L4_ipv6_csum_full
642 /* Receive side supported stateless offload
643 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
644 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
645 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
646 * 3 : RX_hash - Hash calculation
648 uint32_t rx_supported;
653 enum ena_admin_hash_functions {
654 ENA_ADMIN_TOEPLITZ = 1,
658 struct ena_admin_feature_rss_flow_hash_control {
666 struct ena_admin_feature_rss_flow_hash_function {
667 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
668 uint32_t supported_func;
670 /* 7:0 : selected_func - bitmask of
671 * ena_admin_hash_functions
673 uint32_t selected_func;
679 /* RSS flow hash protocols */
680 enum ena_admin_flow_hash_proto {
681 ENA_ADMIN_RSS_TCP4 = 0,
682 ENA_ADMIN_RSS_UDP4 = 1,
683 ENA_ADMIN_RSS_TCP6 = 2,
684 ENA_ADMIN_RSS_UDP6 = 3,
685 ENA_ADMIN_RSS_IP4 = 4,
686 ENA_ADMIN_RSS_IP6 = 5,
687 ENA_ADMIN_RSS_IP4_FRAG = 6,
688 ENA_ADMIN_RSS_NOT_IP = 7,
689 /* TCPv6 with extension header */
690 ENA_ADMIN_RSS_TCP6_EX = 8,
691 /* IPv6 with extension header */
692 ENA_ADMIN_RSS_IP6_EX = 9,
693 ENA_ADMIN_RSS_PROTO_NUM = 16,
696 /* RSS flow hash fields */
697 enum ena_admin_flow_hash_fields {
698 /* Ethernet Dest Addr */
699 ENA_ADMIN_RSS_L2_DA = BIT(0),
700 /* Ethernet Src Addr */
701 ENA_ADMIN_RSS_L2_SA = BIT(1),
702 /* ipv4/6 Dest Addr */
703 ENA_ADMIN_RSS_L3_DA = BIT(2),
704 /* ipv4/6 Src Addr */
705 ENA_ADMIN_RSS_L3_SA = BIT(3),
706 /* tcp/udp Dest Port */
707 ENA_ADMIN_RSS_L4_DP = BIT(4),
708 /* tcp/udp Src Port */
709 ENA_ADMIN_RSS_L4_SP = BIT(5),
712 struct ena_admin_proto_input {
713 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
719 struct ena_admin_feature_rss_hash_control {
720 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
722 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
724 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
726 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
729 struct ena_admin_feature_rss_flow_hash_input {
730 /* supported hash input sorting
731 * 1 : L3_sort - support swap L3 addresses if DA is
733 * 2 : L4_sort - support swap L4 ports if DP smaller
736 uint16_t supported_input_sort;
738 /* enabled hash input sorting
739 * 1 : enable_L3_sort - enable swap L3 addresses if
741 * 2 : enable_L4_sort - enable swap L4 ports if DP
744 uint16_t enabled_input_sort;
747 enum ena_admin_os_type {
748 ENA_ADMIN_OS_LINUX = 1,
749 ENA_ADMIN_OS_WIN = 2,
750 ENA_ADMIN_OS_DPDK = 3,
751 ENA_ADMIN_OS_FREEBSD = 4,
752 ENA_ADMIN_OS_IPXE = 5,
753 ENA_ADMIN_OS_ESXI = 6,
754 ENA_ADMIN_OS_GROUPS_NUM = 6,
757 struct ena_admin_host_info {
758 /* defined in enum ena_admin_os_type */
761 /* os distribution string format */
762 uint8_t os_dist_str[128];
764 /* OS distribution numeric format */
767 /* kernel version string format */
768 uint8_t kernel_ver_str[32];
770 /* Kernel version numeric format */
776 * 31:24 : module_type
778 uint32_t driver_version;
780 /* features bitmap */
781 uint32_t supported_network_features[2];
783 /* ENA spec version of driver */
784 uint16_t ena_spec_version;
786 /* ENA device's Bus, Device and Function
799 struct ena_admin_rss_ind_table_entry {
805 struct ena_admin_feature_rss_ind_table {
806 /* min supported table size (2^min_size) */
809 /* max supported table size (2^max_size) */
812 /* table size (2^size) */
815 /* 0 : one_entry_update - The FW supports setting a
816 * single RSS table entry
822 /* index of the inline entry. 0xFFFFFFFF means invalid */
823 uint32_t inline_index;
825 /* used for updating single entry, ignored when setting the entire
826 * table through the control buffer.
828 struct ena_admin_rss_ind_table_entry inline_entry;
831 /* When hint value is 0, driver should use it's own predefined value */
832 struct ena_admin_ena_hw_hints {
834 uint16_t mmio_read_timeout;
837 uint16_t driver_watchdog_timeout;
839 /* Per packet tx completion timeout. value in ms */
840 uint16_t missing_tx_completion_timeout;
842 uint16_t missed_tx_completion_count_threshold_to_reset;
845 uint16_t admin_completion_tx_timeout;
847 uint16_t netdev_wd_timeout;
849 uint16_t max_tx_sgl_size;
851 uint16_t max_rx_sgl_size;
853 uint16_t reserved[8];
856 struct ena_admin_get_feat_cmd {
857 struct ena_admin_aq_common_desc aq_common_descriptor;
859 struct ena_admin_ctrl_buff_info control_buffer;
861 struct ena_admin_get_set_feature_common_desc feat_common;
866 struct ena_admin_queue_ext_feature_desc {
870 uint8_t reserved1[3];
873 struct ena_admin_queue_ext_feature_fields max_queue_ext;
879 struct ena_admin_get_feat_resp {
880 struct ena_admin_acq_common_desc acq_common_desc;
885 struct ena_admin_device_attr_feature_desc dev_attr;
887 struct ena_admin_feature_llq_desc llq;
889 struct ena_admin_queue_feature_desc max_queue;
891 struct ena_admin_queue_ext_feature_desc max_queue_ext;
893 struct ena_admin_feature_aenq_desc aenq;
895 struct ena_admin_get_feature_link_desc link;
897 struct ena_admin_feature_offload_desc offload;
899 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
901 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
903 struct ena_admin_feature_rss_ind_table ind_table;
905 struct ena_admin_feature_intr_moder_desc intr_moderation;
907 struct ena_admin_ena_hw_hints hw_hints;
909 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
911 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
915 struct ena_admin_set_feat_cmd {
916 struct ena_admin_aq_common_desc aq_common_descriptor;
918 struct ena_admin_ctrl_buff_info control_buffer;
920 struct ena_admin_get_set_feature_common_desc feat_common;
926 struct ena_admin_set_feature_mtu_desc mtu;
928 /* host attributes */
929 struct ena_admin_set_feature_host_attr_desc host_attr;
931 /* AENQ configuration */
932 struct ena_admin_feature_aenq_desc aenq;
934 /* rss flow hash function */
935 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
937 /* rss flow hash input */
938 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
940 /* rss indirection table */
941 struct ena_admin_feature_rss_ind_table ind_table;
943 /* LLQ configuration */
944 struct ena_admin_feature_llq_desc llq;
948 struct ena_admin_set_feat_resp {
949 struct ena_admin_acq_common_desc acq_common_desc;
956 struct ena_admin_aenq_common_desc {
962 * 7:1 : reserved - MBZ
966 uint8_t reserved1[3];
968 uint32_t timestamp_low;
970 uint32_t timestamp_high;
973 /* asynchronous event notification groups */
974 enum ena_admin_aenq_group {
975 ENA_ADMIN_LINK_CHANGE = 0,
976 ENA_ADMIN_FATAL_ERROR = 1,
977 ENA_ADMIN_WARNING = 2,
978 ENA_ADMIN_NOTIFICATION = 3,
979 ENA_ADMIN_KEEP_ALIVE = 4,
980 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
983 enum ena_admin_aenq_notification_syndrom {
984 ENA_ADMIN_SUSPEND = 0,
985 ENA_ADMIN_RESUME = 1,
986 ENA_ADMIN_UPDATE_HINTS = 2,
989 struct ena_admin_aenq_entry {
990 struct ena_admin_aenq_common_desc aenq_common_desc;
992 /* command specific inline data */
993 uint32_t inline_data_w4[12];
996 struct ena_admin_aenq_link_change_desc {
997 struct ena_admin_aenq_common_desc aenq_common_desc;
999 /* 0 : link_status */
1003 struct ena_admin_aenq_keep_alive_desc {
1004 struct ena_admin_aenq_common_desc aenq_common_desc;
1006 uint32_t rx_drops_low;
1008 uint32_t rx_drops_high;
1011 struct ena_admin_ena_mmio_req_read_less_resp {
1016 /* value is valid when poll is cleared */
1020 /* aq_common_desc */
1021 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1022 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1023 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1024 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1025 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1026 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1029 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1030 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1032 /* acq_common_desc */
1033 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1034 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1036 /* aq_create_sq_cmd */
1037 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1038 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1039 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1040 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1041 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1042 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1044 /* aq_create_cq_cmd */
1045 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1046 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1047 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1049 /* get_set_feature_common_desc */
1050 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1052 /* get_feature_link_desc */
1053 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1054 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1055 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1057 /* feature_offload_desc */
1058 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1059 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1060 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1061 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1062 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1063 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1064 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1065 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1066 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1067 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1068 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1069 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1070 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1071 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1072 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1073 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1074 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1075 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1076 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1077 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1078 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1079 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1081 /* feature_rss_flow_hash_function */
1082 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1083 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1085 /* feature_rss_flow_hash_input */
1086 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1087 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1088 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1089 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1090 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1091 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1092 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1093 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1096 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1097 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1098 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1099 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1100 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1101 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1102 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1103 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1104 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1105 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1106 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1107 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1109 /* feature_rss_ind_table */
1110 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1112 /* aenq_common_desc */
1113 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1115 /* aenq_link_change_desc */
1116 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1118 #if !defined(DEFS_LINUX_MAINLINE)
1119 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1121 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1124 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1126 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1129 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1131 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1134 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1136 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1139 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1141 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1144 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1146 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1149 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1151 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1154 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1156 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1159 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1161 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1164 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1166 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1169 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1171 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1174 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1176 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1179 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1181 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1184 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1186 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1189 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1191 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1194 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1196 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1199 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1201 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1204 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1206 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1209 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1211 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1214 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1216 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1219 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1221 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1224 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1226 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1229 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1231 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1234 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1236 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1239 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1241 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1244 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1246 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1249 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1251 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1254 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1256 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1259 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1261 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1264 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1266 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1269 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1271 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1274 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1276 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1279 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1281 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1284 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1286 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1289 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1291 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1294 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1296 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1299 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1301 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1304 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1306 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1309 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1311 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1314 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1316 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1319 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1321 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1324 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1326 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1329 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1331 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1334 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1336 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1339 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1341 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1344 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1346 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1349 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1351 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1354 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1356 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1359 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1361 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1364 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1366 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1369 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1371 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1374 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1376 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1379 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1381 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1384 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1386 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1389 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1391 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1394 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1396 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1399 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1401 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1404 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1406 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1409 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1411 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1414 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1416 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1419 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1421 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1424 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1426 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1429 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1431 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1434 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1436 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1439 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1441 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1444 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1446 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1449 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1451 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1454 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1456 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1459 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1461 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1464 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1466 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1469 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1471 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1474 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1476 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1479 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1481 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1484 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1486 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1489 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1491 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1494 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1496 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1499 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1501 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1504 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1506 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1509 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1511 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1514 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1516 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1519 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1521 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1524 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1526 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1529 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1531 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1534 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1536 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1539 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1541 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1544 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1546 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1549 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1551 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1554 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1556 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1559 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1560 #endif /*_ENA_ADMIN_H_ */