4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
37 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
39 enum ena_admin_aq_opcode {
40 ENA_ADMIN_CREATE_SQ = 1,
41 ENA_ADMIN_DESTROY_SQ = 2,
42 ENA_ADMIN_CREATE_CQ = 3,
43 ENA_ADMIN_DESTROY_CQ = 4,
44 ENA_ADMIN_GET_FEATURE = 8,
45 ENA_ADMIN_SET_FEATURE = 9,
46 ENA_ADMIN_GET_STATS = 11,
49 enum ena_admin_aq_completion_status {
50 ENA_ADMIN_SUCCESS = 0,
51 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
52 ENA_ADMIN_BAD_OPCODE = 2,
53 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
54 ENA_ADMIN_MALFORMED_REQUEST = 4,
55 /* Additional status is provided in ACQ entry extended_status */
56 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
57 ENA_ADMIN_UNKNOWN_ERROR = 6,
58 ENA_ADMIN_RESOURCE_BUSY = 7,
61 enum ena_admin_aq_feature_id {
62 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
63 ENA_ADMIN_MAX_QUEUES_NUM = 2,
64 ENA_ADMIN_HW_HINTS = 3,
66 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
67 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
68 ENA_ADMIN_MAX_QUEUES_EXT = 7,
69 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
70 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
71 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
73 ENA_ADMIN_RSS_HASH_INPUT = 18,
74 ENA_ADMIN_INTERRUPT_MODERATION = 20,
75 ENA_ADMIN_AENQ_CONFIG = 26,
76 ENA_ADMIN_LINK_CONFIG = 27,
77 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
78 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
81 enum ena_admin_placement_policy_type {
82 /* descriptors and headers are in host memory */
83 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
84 /* descriptors and headers are in device memory (a.k.a Low Latency
87 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
90 enum ena_admin_link_types {
91 ENA_ADMIN_LINK_SPEED_1G = 0x1,
92 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
93 ENA_ADMIN_LINK_SPEED_5G = 0x4,
94 ENA_ADMIN_LINK_SPEED_10G = 0x8,
95 ENA_ADMIN_LINK_SPEED_25G = 0x10,
96 ENA_ADMIN_LINK_SPEED_40G = 0x20,
97 ENA_ADMIN_LINK_SPEED_50G = 0x40,
98 ENA_ADMIN_LINK_SPEED_100G = 0x80,
99 ENA_ADMIN_LINK_SPEED_200G = 0x100,
100 ENA_ADMIN_LINK_SPEED_400G = 0x200,
103 enum ena_admin_completion_policy_type {
104 /* completion queue entry for each sq descriptor */
105 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
106 /* completion queue entry upon request in sq descriptor */
107 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
108 /* current queue head pointer is updated in OS memory upon sq
111 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
112 /* current queue head pointer is updated in OS memory for each sq
115 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
118 /* basic stats return ena_admin_basic_stats while extanded stats return a
119 * buffer (string format) with additional statistics per queue and per
122 enum ena_admin_get_stats_type {
123 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
124 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
127 enum ena_admin_get_stats_scope {
128 ENA_ADMIN_SPECIFIC_QUEUE = 0,
129 ENA_ADMIN_ETH_TRAFFIC = 1,
132 struct ena_admin_aq_common_desc {
138 /* as appears in ena_admin_aq_opcode */
142 * 1 : ctrl_data - control buffer address valid
143 * 2 : ctrl_data_indirect - control buffer address
144 * points to list of pages with addresses of control
151 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
152 * page list chunk. Used also at the end of indirect mode page list chunks,
155 struct ena_admin_ctrl_buff_info {
158 struct ena_common_mem_addr address;
161 struct ena_admin_sq {
165 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
172 struct ena_admin_aq_entry {
173 struct ena_admin_aq_common_desc aq_common_descriptor;
176 uint32_t inline_data_w1[3];
178 struct ena_admin_ctrl_buff_info control_buffer;
181 uint32_t inline_data_w4[12];
184 struct ena_admin_acq_common_desc {
185 /* command identifier to associate it with the aq descriptor
198 uint16_t extended_status;
200 /* indicates to the driver which AQ entry has been consumed by the
201 * device and could be reused
203 uint16_t sq_head_indx;
206 struct ena_admin_acq_entry {
207 struct ena_admin_acq_common_desc acq_common_descriptor;
209 uint32_t response_specific_data[14];
212 struct ena_admin_aq_create_sq_cmd {
213 struct ena_admin_aq_common_desc aq_common_descriptor;
215 /* 4:0 : reserved0_w1
216 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
220 uint8_t reserved8_w1;
222 /* 3:0 : placement_policy - Describing where the SQ
223 * descriptor ring and the SQ packet headers reside:
224 * 0x1 - descriptors and headers are in OS memory,
225 * 0x3 - descriptors and headers in device memory
226 * (a.k.a Low Latency Queue)
227 * 6:4 : completion_policy - Describing what policy
228 * to use for generation completion entry (cqe) in
229 * the CQ associated with this SQ: 0x0 - cqe for each
230 * sq descriptor, 0x1 - cqe upon request in sq
231 * descriptor, 0x2 - current queue head pointer is
232 * updated in OS memory upon sq descriptor request
233 * 0x3 - current queue head pointer is updated in OS
234 * memory for each sq descriptor
239 /* 0 : is_physically_contiguous - Described if the
240 * queue ring memory is allocated in physical
241 * contiguous pages or split.
242 * 7:1 : reserved17_w1
246 /* associated completion queue id. This CQ must be created prior to
251 /* submission queue depth in entries */
254 /* SQ physical base address in OS memory. This field should not be
255 * used for Low Latency queues. Has to be page aligned.
257 struct ena_common_mem_addr sq_ba;
259 /* specifies queue head writeback location in OS memory. Valid if
260 * completion_policy is set to completion_policy_head_on_demand or
261 * completion_policy_head. Has to be cache aligned
263 struct ena_common_mem_addr sq_head_writeback;
265 uint32_t reserved0_w7;
267 uint32_t reserved0_w8;
270 enum ena_admin_sq_direction {
271 ENA_ADMIN_SQ_DIRECTION_TX = 1,
272 ENA_ADMIN_SQ_DIRECTION_RX = 2,
275 struct ena_admin_acq_create_sq_resp_desc {
276 struct ena_admin_acq_common_desc acq_common_desc;
282 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
283 uint32_t sq_doorbell_offset;
285 /* low latency queue ring base address as an offset to PCIe MMIO
288 uint32_t llq_descriptors_offset;
290 /* low latency queue headers' memory as an offset to PCIe MMIO
293 uint32_t llq_headers_offset;
296 struct ena_admin_aq_destroy_sq_cmd {
297 struct ena_admin_aq_common_desc aq_common_descriptor;
299 struct ena_admin_sq sq;
302 struct ena_admin_acq_destroy_sq_resp_desc {
303 struct ena_admin_acq_common_desc acq_common_desc;
306 struct ena_admin_aq_create_cq_cmd {
307 struct ena_admin_aq_common_desc aq_common_descriptor;
310 * 5 : interrupt_mode_enabled - if set, cq operates
311 * in interrupt mode, otherwise - polling
316 /* 4:0 : cq_entry_size_words - size of CQ entry in
317 * 32-bit words, valid values: 4, 8.
322 /* completion queue depth in # of entries. must be power of 2 */
325 /* msix vector assigned to this cq */
326 uint32_t msix_vector;
328 /* cq physical base address in OS memory. CQ must be physically
331 struct ena_common_mem_addr cq_ba;
334 struct ena_admin_acq_create_cq_resp_desc {
335 struct ena_admin_acq_common_desc acq_common_desc;
339 /* actual cq depth in number of entries */
340 uint16_t cq_actual_depth;
342 uint32_t numa_node_register_offset;
344 uint32_t cq_head_db_register_offset;
346 uint32_t cq_interrupt_unmask_register_offset;
349 struct ena_admin_aq_destroy_cq_cmd {
350 struct ena_admin_aq_common_desc aq_common_descriptor;
357 struct ena_admin_acq_destroy_cq_resp_desc {
358 struct ena_admin_acq_common_desc acq_common_desc;
361 /* ENA AQ Get Statistics command. Extended statistics are placed in control
362 * buffer pointed by AQ entry
364 struct ena_admin_aq_get_stats_cmd {
365 struct ena_admin_aq_common_desc aq_common_descriptor;
368 /* command specific inline data */
369 uint32_t inline_data_w1[3];
371 struct ena_admin_ctrl_buff_info control_buffer;
374 /* stats type as defined in enum ena_admin_get_stats_type */
377 /* stats scope defined in enum ena_admin_get_stats_scope */
382 /* queue id. used when scope is specific_queue */
385 /* device id, value 0xFFFF means mine. only privileged device can get
386 * stats of other device
391 /* Basic Statistics Command. */
392 struct ena_admin_basic_stats {
393 uint32_t tx_bytes_low;
395 uint32_t tx_bytes_high;
397 uint32_t tx_pkts_low;
399 uint32_t tx_pkts_high;
401 uint32_t rx_bytes_low;
403 uint32_t rx_bytes_high;
405 uint32_t rx_pkts_low;
407 uint32_t rx_pkts_high;
409 uint32_t rx_drops_low;
411 uint32_t rx_drops_high;
414 struct ena_admin_acq_get_stats_resp {
415 struct ena_admin_acq_common_desc acq_common_desc;
417 struct ena_admin_basic_stats basic_stats;
420 struct ena_admin_get_set_feature_common_desc {
421 /* 1:0 : select - 0x1 - current value; 0x3 - default
427 /* as appears in ena_admin_aq_feature_id */
430 /* The driver specifies the max feature version it supports and the
431 * device responds with the currently supported feature version. The
432 * field is zero based
434 uint8_t feature_version;
439 struct ena_admin_device_attr_feature_desc {
442 uint32_t device_version;
444 /* bitmap of ena_admin_aq_feature_id */
445 uint32_t supported_features;
449 /* Indicates how many bits are used physical address access. */
450 uint32_t phys_addr_width;
452 /* Indicates how many bits are used virtual address access. */
453 uint32_t virt_addr_width;
455 /* unicast MAC address (in Network byte order) */
458 uint8_t reserved7[2];
463 enum ena_admin_llq_header_location {
464 /* header is in descriptor list */
465 ENA_ADMIN_INLINE_HEADER = 1,
466 /* header in a separate ring, implies 16B descriptor list entry */
467 ENA_ADMIN_HEADER_RING = 2,
470 enum ena_admin_llq_ring_entry_size {
471 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
472 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
473 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
476 enum ena_admin_llq_num_descs_before_header {
477 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
478 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
479 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
480 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
481 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
484 /* packet descriptor list entry always starts with one or more descriptors,
485 * followed by a header. The rest of the descriptors are located in the
486 * beginning of the subsequent entry. Stride refers to how the rest of the
487 * descriptors are placed. This field is relevant only for inline header
490 enum ena_admin_llq_stride_ctrl {
491 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
492 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
495 struct ena_admin_feature_llq_desc {
496 uint32_t max_llq_num;
498 uint32_t max_llq_depth;
500 /* specify the header locations the device supports. bitfield of
501 * enum ena_admin_llq_header_location.
503 uint16_t header_location_ctrl_supported;
505 /* the header location the driver selected to use. */
506 uint16_t header_location_ctrl_enabled;
508 /* if inline header is specified - this is the size of descriptor
509 * list entry. If header in a separate ring is specified - this is
510 * the size of header ring entry. bitfield of enum
511 * ena_admin_llq_ring_entry_size. specify the entry sizes the device
514 uint16_t entry_size_ctrl_supported;
516 /* the entry size the driver selected to use. */
517 uint16_t entry_size_ctrl_enabled;
519 /* valid only if inline header is specified. First entry associated
520 * with the packet includes descriptors and header. Rest of the
521 * entries occupied by descriptors. This parameter defines the max
522 * number of descriptors precedding the header in the first entry.
523 * The field is bitfield of enum
524 * ena_admin_llq_num_descs_before_header and specify the values the
527 uint16_t desc_num_before_header_supported;
529 /* the desire field the driver selected to use */
530 uint16_t desc_num_before_header_enabled;
532 /* valid only if inline was chosen. bitfield of enum
533 * ena_admin_llq_stride_ctrl
535 uint16_t descriptors_stride_ctrl_supported;
537 /* the stride control the driver selected to use */
538 uint16_t descriptors_stride_ctrl_enabled;
540 /* Maximum size in bytes taken by llq entries in a single tx burst.
541 * Set to 0 when there is no such limit.
543 uint32_t max_tx_burst_size;
546 struct ena_admin_queue_ext_feature_fields {
547 uint32_t max_tx_sq_num;
549 uint32_t max_tx_cq_num;
551 uint32_t max_rx_sq_num;
553 uint32_t max_rx_cq_num;
555 uint32_t max_tx_sq_depth;
557 uint32_t max_tx_cq_depth;
559 uint32_t max_rx_sq_depth;
561 uint32_t max_rx_cq_depth;
563 uint32_t max_tx_header_size;
565 /* Maximum Descriptors number, including meta descriptor, allowed for
568 uint16_t max_per_packet_tx_descs;
570 /* Maximum Descriptors number allowed for a single Rx packet */
571 uint16_t max_per_packet_rx_descs;
574 struct ena_admin_queue_feature_desc {
577 uint32_t max_sq_depth;
581 uint32_t max_cq_depth;
583 uint32_t max_legacy_llq_num;
585 uint32_t max_legacy_llq_depth;
587 uint32_t max_header_size;
589 /* Maximum Descriptors number, including meta descriptor, allowed for
592 uint16_t max_packet_tx_descs;
594 /* Maximum Descriptors number allowed for a single Rx packet */
595 uint16_t max_packet_rx_descs;
598 struct ena_admin_set_feature_mtu_desc {
603 struct ena_admin_get_extra_properties_strings_desc {
607 struct ena_admin_get_extra_properties_flags_desc {
611 struct ena_admin_set_feature_host_attr_desc {
612 /* host OS info base address in OS memory. host info is 4KB of
613 * physically contiguous
615 struct ena_common_mem_addr os_info_ba;
617 /* host debug area base address in OS memory. debug area must be
618 * physically contiguous
620 struct ena_common_mem_addr debug_ba;
622 /* debug area size */
623 uint32_t debug_area_size;
626 struct ena_admin_feature_intr_moder_desc {
627 /* interrupt delay granularity in usec */
628 uint16_t intr_delay_resolution;
633 struct ena_admin_get_feature_link_desc {
634 /* Link speed in Mb */
637 /* bit field of enum ena_admin_link types */
641 * 1 : duplex - Full Duplex
647 struct ena_admin_feature_aenq_desc {
648 /* bitmask for AENQ groups the device can report */
649 uint32_t supported_groups;
651 /* bitmask for AENQ groups to report */
652 uint32_t enabled_groups;
655 struct ena_admin_feature_offload_desc {
656 /* 0 : TX_L3_csum_ipv4
657 * 1 : TX_L4_ipv4_csum_part - The checksum field
658 * should be initialized with pseudo header checksum
659 * 2 : TX_L4_ipv4_csum_full
660 * 3 : TX_L4_ipv6_csum_part - The checksum field
661 * should be initialized with pseudo header checksum
662 * 4 : TX_L4_ipv6_csum_full
669 /* Receive side supported stateless offload
670 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
671 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
672 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
673 * 3 : RX_hash - Hash calculation
675 uint32_t rx_supported;
680 enum ena_admin_hash_functions {
681 ENA_ADMIN_TOEPLITZ = 1,
685 struct ena_admin_feature_rss_flow_hash_control {
693 struct ena_admin_feature_rss_flow_hash_function {
694 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
695 uint32_t supported_func;
697 /* 7:0 : selected_func - bitmask of
698 * ena_admin_hash_functions
700 uint32_t selected_func;
706 /* RSS flow hash protocols */
707 enum ena_admin_flow_hash_proto {
708 ENA_ADMIN_RSS_TCP4 = 0,
709 ENA_ADMIN_RSS_UDP4 = 1,
710 ENA_ADMIN_RSS_TCP6 = 2,
711 ENA_ADMIN_RSS_UDP6 = 3,
712 ENA_ADMIN_RSS_IP4 = 4,
713 ENA_ADMIN_RSS_IP6 = 5,
714 ENA_ADMIN_RSS_IP4_FRAG = 6,
715 ENA_ADMIN_RSS_NOT_IP = 7,
716 /* TCPv6 with extension header */
717 ENA_ADMIN_RSS_TCP6_EX = 8,
718 /* IPv6 with extension header */
719 ENA_ADMIN_RSS_IP6_EX = 9,
720 ENA_ADMIN_RSS_PROTO_NUM = 16,
723 /* RSS flow hash fields */
724 enum ena_admin_flow_hash_fields {
725 /* Ethernet Dest Addr */
726 ENA_ADMIN_RSS_L2_DA = BIT(0),
727 /* Ethernet Src Addr */
728 ENA_ADMIN_RSS_L2_SA = BIT(1),
729 /* ipv4/6 Dest Addr */
730 ENA_ADMIN_RSS_L3_DA = BIT(2),
731 /* ipv4/6 Src Addr */
732 ENA_ADMIN_RSS_L3_SA = BIT(3),
733 /* tcp/udp Dest Port */
734 ENA_ADMIN_RSS_L4_DP = BIT(4),
735 /* tcp/udp Src Port */
736 ENA_ADMIN_RSS_L4_SP = BIT(5),
739 struct ena_admin_proto_input {
740 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
746 struct ena_admin_feature_rss_hash_control {
747 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
749 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
751 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
753 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
756 struct ena_admin_feature_rss_flow_hash_input {
757 /* supported hash input sorting
758 * 1 : L3_sort - support swap L3 addresses if DA is
760 * 2 : L4_sort - support swap L4 ports if DP smaller
763 uint16_t supported_input_sort;
765 /* enabled hash input sorting
766 * 1 : enable_L3_sort - enable swap L3 addresses if
768 * 2 : enable_L4_sort - enable swap L4 ports if DP
771 uint16_t enabled_input_sort;
774 enum ena_admin_os_type {
775 ENA_ADMIN_OS_LINUX = 1,
776 ENA_ADMIN_OS_WIN = 2,
777 ENA_ADMIN_OS_DPDK = 3,
778 ENA_ADMIN_OS_FREEBSD = 4,
779 ENA_ADMIN_OS_IPXE = 5,
780 ENA_ADMIN_OS_ESXI = 6,
781 ENA_ADMIN_OS_GROUPS_NUM = 6,
784 struct ena_admin_host_info {
785 /* defined in enum ena_admin_os_type */
788 /* os distribution string format */
789 uint8_t os_dist_str[128];
791 /* OS distribution numeric format */
794 /* kernel version string format */
795 uint8_t kernel_ver_str[32];
797 /* Kernel version numeric format */
803 * 31:24 : module_type
805 uint32_t driver_version;
807 /* features bitmap */
808 uint32_t supported_network_features[2];
810 /* ENA spec version of driver */
811 uint16_t ena_spec_version;
813 /* ENA device's Bus, Device and Function
826 struct ena_admin_rss_ind_table_entry {
832 struct ena_admin_feature_rss_ind_table {
833 /* min supported table size (2^min_size) */
836 /* max supported table size (2^max_size) */
839 /* table size (2^size) */
842 /* 0 : one_entry_update - The FW supports setting a
843 * single RSS table entry
849 /* index of the inline entry. 0xFFFFFFFF means invalid */
850 uint32_t inline_index;
852 /* used for updating single entry, ignored when setting the entire
853 * table through the control buffer.
855 struct ena_admin_rss_ind_table_entry inline_entry;
858 /* When hint value is 0, driver should use it's own predefined value */
859 struct ena_admin_ena_hw_hints {
861 uint16_t mmio_read_timeout;
864 uint16_t driver_watchdog_timeout;
866 /* Per packet tx completion timeout. value in ms */
867 uint16_t missing_tx_completion_timeout;
869 uint16_t missed_tx_completion_count_threshold_to_reset;
872 uint16_t admin_completion_tx_timeout;
874 uint16_t netdev_wd_timeout;
876 uint16_t max_tx_sgl_size;
878 uint16_t max_rx_sgl_size;
880 uint16_t reserved[8];
883 struct ena_admin_get_feat_cmd {
884 struct ena_admin_aq_common_desc aq_common_descriptor;
886 struct ena_admin_ctrl_buff_info control_buffer;
888 struct ena_admin_get_set_feature_common_desc feat_common;
893 struct ena_admin_queue_ext_feature_desc {
897 uint8_t reserved1[3];
900 struct ena_admin_queue_ext_feature_fields max_queue_ext;
906 struct ena_admin_get_feat_resp {
907 struct ena_admin_acq_common_desc acq_common_desc;
912 struct ena_admin_device_attr_feature_desc dev_attr;
914 struct ena_admin_feature_llq_desc llq;
916 struct ena_admin_queue_feature_desc max_queue;
918 struct ena_admin_queue_ext_feature_desc max_queue_ext;
920 struct ena_admin_feature_aenq_desc aenq;
922 struct ena_admin_get_feature_link_desc link;
924 struct ena_admin_feature_offload_desc offload;
926 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
928 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
930 struct ena_admin_feature_rss_ind_table ind_table;
932 struct ena_admin_feature_intr_moder_desc intr_moderation;
934 struct ena_admin_ena_hw_hints hw_hints;
936 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
938 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
942 struct ena_admin_set_feat_cmd {
943 struct ena_admin_aq_common_desc aq_common_descriptor;
945 struct ena_admin_ctrl_buff_info control_buffer;
947 struct ena_admin_get_set_feature_common_desc feat_common;
953 struct ena_admin_set_feature_mtu_desc mtu;
955 /* host attributes */
956 struct ena_admin_set_feature_host_attr_desc host_attr;
958 /* AENQ configuration */
959 struct ena_admin_feature_aenq_desc aenq;
961 /* rss flow hash function */
962 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
964 /* rss flow hash input */
965 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
967 /* rss indirection table */
968 struct ena_admin_feature_rss_ind_table ind_table;
970 /* LLQ configuration */
971 struct ena_admin_feature_llq_desc llq;
975 struct ena_admin_set_feat_resp {
976 struct ena_admin_acq_common_desc acq_common_desc;
983 struct ena_admin_aenq_common_desc {
989 * 7:1 : reserved - MBZ
993 uint8_t reserved1[3];
995 uint32_t timestamp_low;
997 uint32_t timestamp_high;
1000 /* asynchronous event notification groups */
1001 enum ena_admin_aenq_group {
1002 ENA_ADMIN_LINK_CHANGE = 0,
1003 ENA_ADMIN_FATAL_ERROR = 1,
1004 ENA_ADMIN_WARNING = 2,
1005 ENA_ADMIN_NOTIFICATION = 3,
1006 ENA_ADMIN_KEEP_ALIVE = 4,
1007 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
1010 enum ena_admin_aenq_notification_syndrom {
1011 ENA_ADMIN_SUSPEND = 0,
1012 ENA_ADMIN_RESUME = 1,
1013 ENA_ADMIN_UPDATE_HINTS = 2,
1016 struct ena_admin_aenq_entry {
1017 struct ena_admin_aenq_common_desc aenq_common_desc;
1019 /* command specific inline data */
1020 uint32_t inline_data_w4[12];
1023 struct ena_admin_aenq_link_change_desc {
1024 struct ena_admin_aenq_common_desc aenq_common_desc;
1026 /* 0 : link_status */
1030 struct ena_admin_aenq_keep_alive_desc {
1031 struct ena_admin_aenq_common_desc aenq_common_desc;
1033 uint32_t rx_drops_low;
1035 uint32_t rx_drops_high;
1038 struct ena_admin_ena_mmio_req_read_less_resp {
1043 /* value is valid when poll is cleared */
1047 /* aq_common_desc */
1048 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1049 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1050 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1051 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1052 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1053 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1056 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1057 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1059 /* acq_common_desc */
1060 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1061 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1063 /* aq_create_sq_cmd */
1064 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1065 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1066 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1067 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1068 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1069 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1071 /* aq_create_cq_cmd */
1072 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1073 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1074 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1076 /* get_set_feature_common_desc */
1077 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1079 /* get_feature_link_desc */
1080 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1081 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1082 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1084 /* feature_offload_desc */
1085 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1086 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1087 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1088 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1089 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1090 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1091 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1092 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1093 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1094 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1095 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1096 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1097 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1098 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1099 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1100 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1101 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1102 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1103 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1104 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1105 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1106 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1108 /* feature_rss_flow_hash_function */
1109 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1110 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1112 /* feature_rss_flow_hash_input */
1113 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1114 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1115 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1116 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1117 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1118 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1119 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1120 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1123 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1124 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1125 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1126 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1127 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1128 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1129 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1130 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1131 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1132 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1133 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1134 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1136 /* feature_rss_ind_table */
1137 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1139 /* aenq_common_desc */
1140 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1142 /* aenq_link_change_desc */
1143 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1145 #if !defined(DEFS_LINUX_MAINLINE)
1146 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1148 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1151 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1153 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1156 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1158 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1161 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1163 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1166 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1168 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1171 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1173 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1176 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1178 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1181 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1183 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1186 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1188 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1191 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1193 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1196 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1198 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1201 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1203 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1206 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1208 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1211 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1213 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1216 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1218 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1221 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1223 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1226 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1228 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1231 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1233 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1236 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1238 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1241 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1243 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1246 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1248 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1251 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1253 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1256 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1258 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1261 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1263 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1266 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1268 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1271 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1273 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1276 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1278 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1281 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1283 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1286 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1288 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1291 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1293 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1296 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1298 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1301 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1303 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1306 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1308 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1311 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1313 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1316 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1318 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1321 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1323 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1326 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1328 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1331 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1333 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1336 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1338 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1341 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1343 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1346 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1348 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1351 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1353 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1356 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1358 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1361 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1363 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1366 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1368 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1371 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1373 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1376 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1378 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1381 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1383 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1386 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1388 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1391 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1393 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1396 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1398 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1401 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1403 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1406 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1408 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1411 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1413 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1416 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1418 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1421 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1423 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1426 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1428 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1431 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1433 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1436 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1438 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1441 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1443 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1446 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1448 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1451 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1453 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1456 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1458 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1461 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1463 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1466 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1468 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1471 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1473 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1476 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1478 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1481 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1483 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1486 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1488 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1491 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1493 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1496 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1498 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1501 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1503 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1506 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1508 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1511 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1513 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1516 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1518 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1521 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1523 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1526 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1528 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1531 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1533 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1536 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1538 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1541 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1543 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1546 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1548 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1551 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1553 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1556 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1558 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1561 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1563 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1566 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1568 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1571 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1573 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1576 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1578 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1581 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1583 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1586 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1587 #endif /*_ENA_ADMIN_H_ */