drivers/net/ena/base/ena_defs/ena_admin_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _ENA_ADMIN_H_
   7 #define _ENA_ADMIN_H_
   8
   9 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
  10 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT     32
  11
  12 enum ena_admin_aq_opcode {
  13         ENA_ADMIN_CREATE_SQ                         = 1,
  14         ENA_ADMIN_DESTROY_SQ                        = 2,
  15         ENA_ADMIN_CREATE_CQ                         = 3,
  16         ENA_ADMIN_DESTROY_CQ                        = 4,
  17         ENA_ADMIN_GET_FEATURE                       = 8,
  18         ENA_ADMIN_SET_FEATURE                       = 9,
  19         ENA_ADMIN_GET_STATS                         = 11,
  20 };
  21
  22 enum ena_admin_aq_completion_status {
  23         ENA_ADMIN_SUCCESS                           = 0,
  24         ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
  25         ENA_ADMIN_BAD_OPCODE                        = 2,
  26         ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
  27         ENA_ADMIN_MALFORMED_REQUEST                 = 4,
  28         /* Additional status is provided in ACQ entry extended_status */
  29         ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
  30         ENA_ADMIN_UNKNOWN_ERROR                     = 6,
  31         ENA_ADMIN_RESOURCE_BUSY                     = 7,
  32 };
  33
  34 enum ena_admin_aq_feature_id {
  35         ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
  36         ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
  37         ENA_ADMIN_HW_HINTS                          = 3,
  38         ENA_ADMIN_LLQ                               = 4,
  39         ENA_ADMIN_EXTRA_PROPERTIES_STRINGS          = 5,
  40         ENA_ADMIN_EXTRA_PROPERTIES_FLAGS            = 6,
  41         ENA_ADMIN_MAX_QUEUES_EXT                    = 7,
  42         ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
  43         ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
  44         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,
  45         ENA_ADMIN_MTU                               = 14,
  46         ENA_ADMIN_RSS_HASH_INPUT                    = 18,
  47         ENA_ADMIN_INTERRUPT_MODERATION              = 20,
  48         ENA_ADMIN_AENQ_CONFIG                       = 26,
  49         ENA_ADMIN_LINK_CONFIG                       = 27,
  50         ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
  51         ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
  52 };
  53
  54 enum ena_admin_placement_policy_type {
  55         /* descriptors and headers are in host memory */
  56         ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
  57         /* descriptors and headers are in device memory (a.k.a Low Latency
  58          * Queue)
  59          */
  60         ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
  61 };
  62
  63 enum ena_admin_link_types {
  64         ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
  65         ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
  66         ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
  67         ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
  68         ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
  69         ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
  70         ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
  71         ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
  72         ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
  73         ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
  74 };
  75
  76 enum ena_admin_completion_policy_type {
  77         /* completion queue entry for each sq descriptor */
  78         ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
  79         /* completion queue entry upon request in sq descriptor */
  80         ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
  81         /* current queue head pointer is updated in OS memory upon sq
  82          * descriptor request
  83          */
  84         ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
  85         /* current queue head pointer is updated in OS memory for each sq
  86          * descriptor
  87          */
  88         ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
  89 };
  90
  91 /* basic stats return ena_admin_basic_stats while extanded stats return a
  92  * buffer (string format) with additional statistics per queue and per
  93  * device id
  94  */
  95 enum ena_admin_get_stats_type {
  96         ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
  97         ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
  98 };
  99
 100 enum ena_admin_get_stats_scope {
 101         ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
 102         ENA_ADMIN_ETH_TRAFFIC                       = 1,
 103 };
 104
 105 struct ena_admin_aq_common_desc {
 106         /* 11:0 : command_id
 107          * 15:12 : reserved12
 108          */
 109         uint16_t command_id;
 110
 111         /* as appears in ena_admin_aq_opcode */
 112         uint8_t opcode;
 113
 114         /* 0 : phase
 115          * 1 : ctrl_data - control buffer address valid
 116          * 2 : ctrl_data_indirect - control buffer address
 117          *    points to list of pages with addresses of control
 118          *    buffers
 119          * 7:3 : reserved3
 120          */
 121         uint8_t flags;
 122 };
 123
 124 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
 125  * page list chunk. Used also at the end of indirect mode page list chunks,
 126  * for chaining.
 127  */
 128 struct ena_admin_ctrl_buff_info {
 129         uint32_t length;
 130
 131         struct ena_common_mem_addr address;
 132 };
 133
 134 struct ena_admin_sq {
 135         uint16_t sq_idx;
 136
 137         /* 4:0 : reserved
 138          * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
 139          */
 140         uint8_t sq_identity;
 141
 142         uint8_t reserved1;
 143 };
 144
 145 struct ena_admin_aq_entry {
 146         struct ena_admin_aq_common_desc aq_common_descriptor;
 147
 148         union {
 149                 uint32_t inline_data_w1[3];
 150
 151                 struct ena_admin_ctrl_buff_info control_buffer;
 152         } u;
 153
 154         uint32_t inline_data_w4[12];
 155 };
 156
 157 struct ena_admin_acq_common_desc {
 158         /* command identifier to associate it with the aq descriptor
 159          * 11:0 : command_id
 160          * 15:12 : reserved12
 161          */
 162         uint16_t command;
 163
 164         uint8_t status;
 165
 166         /* 0 : phase
 167          * 7:1 : reserved1
 168          */
 169         uint8_t flags;
 170
 171         uint16_t extended_status;
 172
 173         /* indicates to the driver which AQ entry has been consumed by the
 174          *    device and could be reused
 175          */
 176         uint16_t sq_head_indx;
 177 };
 178
 179 struct ena_admin_acq_entry {
 180         struct ena_admin_acq_common_desc acq_common_descriptor;
 181
 182         uint32_t response_specific_data[14];
 183 };
 184
 185 struct ena_admin_aq_create_sq_cmd {
 186         struct ena_admin_aq_common_desc aq_common_descriptor;
 187
 188         /* 4:0 : reserved0_w1
 189          * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
 190          */
 191         uint8_t sq_identity;
 192
 193         uint8_t reserved8_w1;
 194
 195         /* 3:0 : placement_policy - Describing where the SQ
 196          *    descriptor ring and the SQ packet headers reside:
 197          *    0x1 - descriptors and headers are in OS memory,
 198          *    0x3 - descriptors and headers in device memory
 199          *    (a.k.a Low Latency Queue)
 200          * 6:4 : completion_policy - Describing what policy
 201          *    to use for generation completion entry (cqe) in
 202          *    the CQ associated with this SQ: 0x0 - cqe for each
 203          *    sq descriptor, 0x1 - cqe upon request in sq
 204          *    descriptor, 0x2 - current queue head pointer is
 205          *    updated in OS memory upon sq descriptor request
 206          *    0x3 - current queue head pointer is updated in OS
 207          *    memory for each sq descriptor
 208          * 7 : reserved15_w1
 209          */
 210         uint8_t sq_caps_2;
 211
 212         /* 0 : is_physically_contiguous - Described if the
 213          *    queue ring memory is allocated in physical
 214          *    contiguous pages or split.
 215          * 7:1 : reserved17_w1
 216          */
 217         uint8_t sq_caps_3;
 218
 219         /* associated completion queue id. This CQ must be created prior to
 220          *    SQ creation
 221          */
 222         uint16_t cq_idx;
 223
 224         /* submission queue depth in entries */
 225         uint16_t sq_depth;
 226
 227         /* SQ physical base address in OS memory. This field should not be
 228          * used for Low Latency queues. Has to be page aligned.
 229          */
 230         struct ena_common_mem_addr sq_ba;
 231
 232         /* specifies queue head writeback location in OS memory. Valid if
 233          * completion_policy is set to completion_policy_head_on_demand or
 234          * completion_policy_head. Has to be cache aligned
 235          */
 236         struct ena_common_mem_addr sq_head_writeback;
 237
 238         uint32_t reserved0_w7;
 239
 240         uint32_t reserved0_w8;
 241 };
 242
 243 enum ena_admin_sq_direction {
 244         ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
 245         ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
 246 };
 247
 248 struct ena_admin_acq_create_sq_resp_desc {
 249         struct ena_admin_acq_common_desc acq_common_desc;
 250
 251         uint16_t sq_idx;
 252
 253         uint16_t reserved;
 254
 255         /* queue doorbell address as an offset to PCIe MMIO REG BAR */
 256         uint32_t sq_doorbell_offset;
 257
 258         /* low latency queue ring base address as an offset to PCIe MMIO
 259          * LLQ_MEM BAR
 260          */
 261         uint32_t llq_descriptors_offset;
 262
 263         /* low latency queue headers' memory as an offset to PCIe MMIO
 264          * LLQ_MEM BAR
 265          */
 266         uint32_t llq_headers_offset;
 267 };
 268
 269 struct ena_admin_aq_destroy_sq_cmd {
 270         struct ena_admin_aq_common_desc aq_common_descriptor;
 271
 272         struct ena_admin_sq sq;
 273 };
 274
 275 struct ena_admin_acq_destroy_sq_resp_desc {
 276         struct ena_admin_acq_common_desc acq_common_desc;
 277 };
 278
 279 struct ena_admin_aq_create_cq_cmd {
 280         struct ena_admin_aq_common_desc aq_common_descriptor;
 281
 282         /* 4:0 : reserved5
 283          * 5 : interrupt_mode_enabled - if set, cq operates
 284          *    in interrupt mode, otherwise - polling
 285          * 7:6 : reserved6
 286          */
 287         uint8_t cq_caps_1;
 288
 289         /* 4:0 : cq_entry_size_words - size of CQ entry in
 290          *    32-bit words, valid values: 4, 8.
 291          * 7:5 : reserved7
 292          */
 293         uint8_t cq_caps_2;
 294
 295         /* completion queue depth in # of entries. must be power of 2 */
 296         uint16_t cq_depth;
 297
 298         /* msix vector assigned to this cq */
 299         uint32_t msix_vector;
 300
 301         /* cq physical base address in OS memory. CQ must be physically
 302          * contiguous
 303          */
 304         struct ena_common_mem_addr cq_ba;
 305 };
 306
 307 struct ena_admin_acq_create_cq_resp_desc {
 308         struct ena_admin_acq_common_desc acq_common_desc;
 309
 310         uint16_t cq_idx;
 311
 312         /* actual cq depth in number of entries */
 313         uint16_t cq_actual_depth;
 314
 315         uint32_t numa_node_register_offset;
 316
 317         uint32_t cq_head_db_register_offset;
 318
 319         uint32_t cq_interrupt_unmask_register_offset;
 320 };
 321
 322 struct ena_admin_aq_destroy_cq_cmd {
 323         struct ena_admin_aq_common_desc aq_common_descriptor;
 324
 325         uint16_t cq_idx;
 326
 327         uint16_t reserved1;
 328 };
 329
 330 struct ena_admin_acq_destroy_cq_resp_desc {
 331         struct ena_admin_acq_common_desc acq_common_desc;
 332 };
 333
 334 /* ENA AQ Get Statistics command. Extended statistics are placed in control
 335  * buffer pointed by AQ entry
 336  */
 337 struct ena_admin_aq_get_stats_cmd {
 338         struct ena_admin_aq_common_desc aq_common_descriptor;
 339
 340         union {
 341                 /* command specific inline data */
 342                 uint32_t inline_data_w1[3];
 343
 344                 struct ena_admin_ctrl_buff_info control_buffer;
 345         } u;
 346
 347         /* stats type as defined in enum ena_admin_get_stats_type */
 348         uint8_t type;
 349
 350         /* stats scope defined in enum ena_admin_get_stats_scope */
 351         uint8_t scope;
 352
 353         uint16_t reserved3;
 354
 355         /* queue id. used when scope is specific_queue */
 356         uint16_t queue_idx;
 357
 358         /* device id, value 0xFFFF means mine. only privileged device can get
 359          *    stats of other device
 360          */
 361         uint16_t device_id;
 362 };
 363
 364 /* Basic Statistics Command. */
 365 struct ena_admin_basic_stats {
 366         uint32_t tx_bytes_low;
 367
 368         uint32_t tx_bytes_high;
 369
 370         uint32_t tx_pkts_low;
 371
 372         uint32_t tx_pkts_high;
 373
 374         uint32_t rx_bytes_low;
 375
 376         uint32_t rx_bytes_high;
 377
 378         uint32_t rx_pkts_low;
 379
 380         uint32_t rx_pkts_high;
 381
 382         uint32_t rx_drops_low;
 383
 384         uint32_t rx_drops_high;
 385
 386         uint32_t tx_drops_low;
 387
 388         uint32_t tx_drops_high;
 389 };
 390
 391 struct ena_admin_acq_get_stats_resp {
 392         struct ena_admin_acq_common_desc acq_common_desc;
 393
 394         struct ena_admin_basic_stats basic_stats;
 395 };
 396
 397 struct ena_admin_get_set_feature_common_desc {
 398         /* 1:0 : select - 0x1 - current value; 0x3 - default
 399          *    value
 400          * 7:3 : reserved3
 401          */
 402         uint8_t flags;
 403
 404         /* as appears in ena_admin_aq_feature_id */
 405         uint8_t feature_id;
 406
 407         /* The driver specifies the max feature version it supports and the
 408          *    device responds with the currently supported feature version. The
 409          *    field is zero based
 410          */
 411         uint8_t feature_version;
 412
 413         uint8_t reserved8;
 414 };
 415
 416 struct ena_admin_device_attr_feature_desc {
 417         uint32_t impl_id;
 418
 419         uint32_t device_version;
 420
 421         /* bitmap of ena_admin_aq_feature_id */
 422         uint32_t supported_features;
 423
 424         uint32_t reserved3;
 425
 426         /* Indicates how many bits are used physical address access. */
 427         uint32_t phys_addr_width;
 428
 429         /* Indicates how many bits are used virtual address access. */
 430         uint32_t virt_addr_width;
 431
 432         /* unicast MAC address (in Network byte order) */
 433         uint8_t mac_addr[6];
 434
 435         uint8_t reserved7[2];
 436
 437         uint32_t max_mtu;
 438 };
 439
 440 enum ena_admin_llq_header_location {
 441         /* header is in descriptor list */
 442         ENA_ADMIN_INLINE_HEADER                     = 1,
 443         /* header in a separate ring, implies 16B descriptor list entry */
 444         ENA_ADMIN_HEADER_RING                       = 2,
 445 };
 446
 447 enum ena_admin_llq_ring_entry_size {
 448         ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
 449         ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
 450         ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
 451 };
 452
 453 enum ena_admin_llq_num_descs_before_header {
 454         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
 455         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
 456         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
 457         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
 458         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
 459 };
 460
 461 /* packet descriptor list entry always starts with one or more descriptors,
 462  * followed by a header. The rest of the descriptors are located in the
 463  * beginning of the subsequent entry. Stride refers to how the rest of the
 464  * descriptors are placed. This field is relevant only for inline header
 465  * mode
 466  */
 467 enum ena_admin_llq_stride_ctrl {
 468         ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
 469         ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
 470 };
 471
 472 struct ena_admin_feature_llq_desc {
 473         uint32_t max_llq_num;
 474
 475         uint32_t max_llq_depth;
 476
 477         /*  specify the header locations the device supports. bitfield of
 478          *    enum ena_admin_llq_header_location.
 479          */
 480         uint16_t header_location_ctrl_supported;
 481
 482         /* the header location the driver selected to use. */
 483         uint16_t header_location_ctrl_enabled;
 484
 485         /* if inline header is specified - this is the size of descriptor
 486          *    list entry. If header in a separate ring is specified - this is
 487          *    the size of header ring entry. bitfield of enum
 488          *    ena_admin_llq_ring_entry_size. specify the entry sizes the device
 489          *    supports
 490          */
 491         uint16_t entry_size_ctrl_supported;
 492
 493         /* the entry size the driver selected to use. */
 494         uint16_t entry_size_ctrl_enabled;
 495
 496         /* valid only if inline header is specified. First entry associated
 497          *    with the packet includes descriptors and header. Rest of the
 498          *    entries occupied by descriptors. This parameter defines the max
 499          *    number of descriptors precedding the header in the first entry.
 500          *    The field is bitfield of enum
 501          *    ena_admin_llq_num_descs_before_header and specify the values the
 502          *    device supports
 503          */
 504         uint16_t desc_num_before_header_supported;
 505
 506         /* the desire field the driver selected to use */
 507         uint16_t desc_num_before_header_enabled;
 508
 509         /* valid only if inline was chosen. bitfield of enum
 510          *    ena_admin_llq_stride_ctrl
 511          */
 512         uint16_t descriptors_stride_ctrl_supported;
 513
 514         /* the stride control the driver selected to use */
 515         uint16_t descriptors_stride_ctrl_enabled;
 516
 517         /* Maximum size in bytes taken by llq entries in a single tx burst.
 518          * Set to 0 when there is no such limit.
 519          */
 520         uint32_t max_tx_burst_size;
 521 };
 522
 523 struct ena_admin_queue_ext_feature_fields {
 524         uint32_t max_tx_sq_num;
 525
 526         uint32_t max_tx_cq_num;
 527
 528         uint32_t max_rx_sq_num;
 529
 530         uint32_t max_rx_cq_num;
 531
 532         uint32_t max_tx_sq_depth;
 533
 534         uint32_t max_tx_cq_depth;
 535
 536         uint32_t max_rx_sq_depth;
 537
 538         uint32_t max_rx_cq_depth;
 539
 540         uint32_t max_tx_header_size;
 541
 542         /* Maximum Descriptors number, including meta descriptor, allowed for
 543          *    a single Tx packet
 544          */
 545         uint16_t max_per_packet_tx_descs;
 546
 547         /* Maximum Descriptors number allowed for a single Rx packet */
 548         uint16_t max_per_packet_rx_descs;
 549 };
 550
 551 struct ena_admin_queue_feature_desc {
 552         uint32_t max_sq_num;
 553
 554         uint32_t max_sq_depth;
 555
 556         uint32_t max_cq_num;
 557
 558         uint32_t max_cq_depth;
 559
 560         uint32_t max_legacy_llq_num;
 561
 562         uint32_t max_legacy_llq_depth;
 563
 564         uint32_t max_header_size;
 565
 566         /* Maximum Descriptors number, including meta descriptor, allowed for
 567          *    a single Tx packet
 568          */
 569         uint16_t max_packet_tx_descs;
 570
 571         /* Maximum Descriptors number allowed for a single Rx packet */
 572         uint16_t max_packet_rx_descs;
 573 };
 574
 575 struct ena_admin_set_feature_mtu_desc {
 576         /* exclude L2 */
 577         uint32_t mtu;
 578 };
 579
 580 struct ena_admin_get_extra_properties_strings_desc {
 581         uint32_t count;
 582 };
 583
 584 struct ena_admin_get_extra_properties_flags_desc {
 585         uint32_t flags;
 586 };
 587
 588 struct ena_admin_set_feature_host_attr_desc {
 589         /* host OS info base address in OS memory. host info is 4KB of
 590          * physically contiguous
 591          */
 592         struct ena_common_mem_addr os_info_ba;
 593
 594         /* host debug area base address in OS memory. debug area must be
 595          * physically contiguous
 596          */
 597         struct ena_common_mem_addr debug_ba;
 598
 599         /* debug area size */
 600         uint32_t debug_area_size;
 601 };
 602
 603 struct ena_admin_feature_intr_moder_desc {
 604         /* interrupt delay granularity in usec */
 605         uint16_t intr_delay_resolution;
 606
 607         uint16_t reserved;
 608 };
 609
 610 struct ena_admin_get_feature_link_desc {
 611         /* Link speed in Mb */
 612         uint32_t speed;
 613
 614         /* bit field of enum ena_admin_link types */
 615         uint32_t supported;
 616
 617         /* 0 : autoneg
 618          * 1 : duplex - Full Duplex
 619          * 31:2 : reserved2
 620          */
 621         uint32_t flags;
 622 };
 623
 624 struct ena_admin_feature_aenq_desc {
 625         /* bitmask for AENQ groups the device can report */
 626         uint32_t supported_groups;
 627
 628         /* bitmask for AENQ groups to report */
 629         uint32_t enabled_groups;
 630 };
 631
 632 struct ena_admin_feature_offload_desc {
 633         /* 0 : TX_L3_csum_ipv4
 634          * 1 : TX_L4_ipv4_csum_part - The checksum field
 635          *    should be initialized with pseudo header checksum
 636          * 2 : TX_L4_ipv4_csum_full
 637          * 3 : TX_L4_ipv6_csum_part - The checksum field
 638          *    should be initialized with pseudo header checksum
 639          * 4 : TX_L4_ipv6_csum_full
 640          * 5 : tso_ipv4
 641          * 6 : tso_ipv6
 642          * 7 : tso_ecn
 643          */
 644         uint32_t tx;
 645
 646         /* Receive side supported stateless offload
 647          * 0 : RX_L3_csum_ipv4 - IPv4 checksum
 648          * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
 649          * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
 650          * 3 : RX_hash - Hash calculation
 651          */
 652         uint32_t rx_supported;
 653
 654         uint32_t rx_enabled;
 655 };
 656
 657 enum ena_admin_hash_functions {
 658         ENA_ADMIN_TOEPLITZ                          = 1,
 659         ENA_ADMIN_CRC32                             = 2,
 660 };
 661
 662 struct ena_admin_feature_rss_flow_hash_control {
 663         uint32_t keys_num;
 664
 665         uint32_t reserved;
 666
 667         uint32_t key[10];
 668 };
 669
 670 struct ena_admin_feature_rss_flow_hash_function {
 671         /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
 672         uint32_t supported_func;
 673
 674         /* 7:0 : selected_func - bitmask of
 675          *    ena_admin_hash_functions
 676          */
 677         uint32_t selected_func;
 678
 679         /* initial value */
 680         uint32_t init_val;
 681 };
 682
 683 /* RSS flow hash protocols */
 684 enum ena_admin_flow_hash_proto {
 685         ENA_ADMIN_RSS_TCP4                          = 0,
 686         ENA_ADMIN_RSS_UDP4                          = 1,
 687         ENA_ADMIN_RSS_TCP6                          = 2,
 688         ENA_ADMIN_RSS_UDP6                          = 3,
 689         ENA_ADMIN_RSS_IP4                           = 4,
 690         ENA_ADMIN_RSS_IP6                           = 5,
 691         ENA_ADMIN_RSS_IP4_FRAG                      = 6,
 692         ENA_ADMIN_RSS_NOT_IP                        = 7,
 693         /* TCPv6 with extension header */
 694         ENA_ADMIN_RSS_TCP6_EX                       = 8,
 695         /* IPv6 with extension header */
 696         ENA_ADMIN_RSS_IP6_EX                        = 9,
 697         ENA_ADMIN_RSS_PROTO_NUM                     = 16,
 698 };
 699
 700 /* RSS flow hash fields */
 701 enum ena_admin_flow_hash_fields {
 702         /* Ethernet Dest Addr */
 703         ENA_ADMIN_RSS_L2_DA                         = BIT(0),
 704         /* Ethernet Src Addr */
 705         ENA_ADMIN_RSS_L2_SA                         = BIT(1),
 706         /* ipv4/6 Dest Addr */
 707         ENA_ADMIN_RSS_L3_DA                         = BIT(2),
 708         /* ipv4/6 Src Addr */
 709         ENA_ADMIN_RSS_L3_SA                         = BIT(3),
 710         /* tcp/udp Dest Port */
 711         ENA_ADMIN_RSS_L4_DP                         = BIT(4),
 712         /* tcp/udp Src Port */
 713         ENA_ADMIN_RSS_L4_SP                         = BIT(5),
 714 };
 715
 716 struct ena_admin_proto_input {
 717         /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
 718         uint16_t fields;
 719
 720         uint16_t reserved2;
 721 };
 722
 723 struct ena_admin_feature_rss_hash_control {
 724         struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
 725
 726         struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
 727
 728         struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
 729
 730         struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
 731 };
 732
 733 struct ena_admin_feature_rss_flow_hash_input {
 734         /* supported hash input sorting
 735          * 1 : L3_sort - support swap L3 addresses if DA is
 736          *    smaller than SA
 737          * 2 : L4_sort - support swap L4 ports if DP smaller
 738          *    SP
 739          */
 740         uint16_t supported_input_sort;
 741
 742         /* enabled hash input sorting
 743          * 1 : enable_L3_sort - enable swap L3 addresses if
 744          *    DA smaller than SA
 745          * 2 : enable_L4_sort - enable swap L4 ports if DP
 746          *    smaller than SP
 747          */
 748         uint16_t enabled_input_sort;
 749 };
 750
 751 enum ena_admin_os_type {
 752         ENA_ADMIN_OS_LINUX                          = 1,
 753         ENA_ADMIN_OS_WIN                            = 2,
 754         ENA_ADMIN_OS_DPDK                           = 3,
 755         ENA_ADMIN_OS_FREEBSD                        = 4,
 756         ENA_ADMIN_OS_IPXE                           = 5,
 757         ENA_ADMIN_OS_ESXI                           = 6,
 758         ENA_ADMIN_OS_GROUPS_NUM                     = 6,
 759 };
 760
 761 struct ena_admin_host_info {
 762         /* defined in enum ena_admin_os_type */
 763         uint32_t os_type;
 764
 765         /* os distribution string format */
 766         uint8_t os_dist_str[128];
 767
 768         /* OS distribution numeric format */
 769         uint32_t os_dist;
 770
 771         /* kernel version string format */
 772         uint8_t kernel_ver_str[32];
 773
 774         /* Kernel version numeric format */
 775         uint32_t kernel_ver;
 776
 777         /* 7:0 : major
 778          * 15:8 : minor
 779          * 23:16 : sub_minor
 780          * 31:24 : module_type
 781          */
 782         uint32_t driver_version;
 783
 784         /* features bitmap */
 785         uint32_t supported_network_features[2];
 786
 787         /* ENA spec version of driver */
 788         uint16_t ena_spec_version;
 789
 790         /* ENA device's Bus, Device and Function
 791          * 2:0 : function
 792          * 7:3 : device
 793          * 15:8 : bus
 794          */
 795         uint16_t bdf;
 796
 797         /* Number of CPUs */
 798         uint16_t num_cpus;
 799
 800         uint16_t reserved;
 801
 802         /* 0 : mutable_rss_table_size
 803          * 1 : rx_offset
 804          * 2 : interrupt_moderation
 805          * 3 : map_rx_buf_bidirectional
 806          * 31:4 : reserved
 807          */
 808         uint32_t driver_supported_features;
 809 };
 810
 811 struct ena_admin_rss_ind_table_entry {
 812         uint16_t cq_idx;
 813
 814         uint16_t reserved;
 815 };
 816
 817 struct ena_admin_feature_rss_ind_table {
 818         /* min supported table size (2^min_size) */
 819         uint16_t min_size;
 820
 821         /* max supported table size (2^max_size) */
 822         uint16_t max_size;
 823
 824         /* table size (2^size) */
 825         uint16_t size;
 826
 827         /* 0 : one_entry_update - The ENA device supports
 828          *    setting a single RSS table entry
 829          */
 830         uint8_t flags;
 831
 832         uint8_t reserved;
 833
 834         /* index of the inline entry. 0xFFFFFFFF means invalid */
 835         uint32_t inline_index;
 836
 837         /* used for updating single entry, ignored when setting the entire
 838          * table through the control buffer.
 839          */
 840         struct ena_admin_rss_ind_table_entry inline_entry;
 841 };
 842
 843 /* When hint value is 0, driver should use it's own predefined value */
 844 struct ena_admin_ena_hw_hints {
 845         /* value in ms */
 846         uint16_t mmio_read_timeout;
 847
 848         /* value in ms */
 849         uint16_t driver_watchdog_timeout;
 850
 851         /* Per packet tx completion timeout. value in ms */
 852         uint16_t missing_tx_completion_timeout;
 853
 854         uint16_t missed_tx_completion_count_threshold_to_reset;
 855
 856         /* value in ms */
 857         uint16_t admin_completion_tx_timeout;
 858
 859         uint16_t netdev_wd_timeout;
 860
 861         uint16_t max_tx_sgl_size;
 862
 863         uint16_t max_rx_sgl_size;
 864
 865         uint16_t reserved[8];
 866 };
 867
 868 struct ena_admin_get_feat_cmd {
 869         struct ena_admin_aq_common_desc aq_common_descriptor;
 870
 871         struct ena_admin_ctrl_buff_info control_buffer;
 872
 873         struct ena_admin_get_set_feature_common_desc feat_common;
 874
 875         uint32_t raw[11];
 876 };
 877
 878 struct ena_admin_queue_ext_feature_desc {
 879         /* version */
 880         uint8_t version;
 881
 882         uint8_t reserved1[3];
 883
 884         union {
 885                 struct ena_admin_queue_ext_feature_fields max_queue_ext;
 886
 887                 uint32_t raw[10];
 888         } ;
 889 };
 890
 891 struct ena_admin_get_feat_resp {
 892         struct ena_admin_acq_common_desc acq_common_desc;
 893
 894         union {
 895                 uint32_t raw[14];
 896
 897                 struct ena_admin_device_attr_feature_desc dev_attr;
 898
 899                 struct ena_admin_feature_llq_desc llq;
 900
 901                 struct ena_admin_queue_feature_desc max_queue;
 902
 903                 struct ena_admin_queue_ext_feature_desc max_queue_ext;
 904
 905                 struct ena_admin_feature_aenq_desc aenq;
 906
 907                 struct ena_admin_get_feature_link_desc link;
 908
 909                 struct ena_admin_feature_offload_desc offload;
 910
 911                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 912
 913                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 914
 915                 struct ena_admin_feature_rss_ind_table ind_table;
 916
 917                 struct ena_admin_feature_intr_moder_desc intr_moderation;
 918
 919                 struct ena_admin_ena_hw_hints hw_hints;
 920
 921                 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
 922
 923                 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
 924         } u;
 925 };
 926
 927 struct ena_admin_set_feat_cmd {
 928         struct ena_admin_aq_common_desc aq_common_descriptor;
 929
 930         struct ena_admin_ctrl_buff_info control_buffer;
 931
 932         struct ena_admin_get_set_feature_common_desc feat_common;
 933
 934         union {
 935                 uint32_t raw[11];
 936
 937                 /* mtu size */
 938                 struct ena_admin_set_feature_mtu_desc mtu;
 939
 940                 /* host attributes */
 941                 struct ena_admin_set_feature_host_attr_desc host_attr;
 942
 943                 /* AENQ configuration */
 944                 struct ena_admin_feature_aenq_desc aenq;
 945
 946                 /* rss flow hash function */
 947                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 948
 949                 /* rss flow hash input */
 950                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 951
 952                 /* rss indirection table */
 953                 struct ena_admin_feature_rss_ind_table ind_table;
 954
 955                 /* LLQ configuration */
 956                 struct ena_admin_feature_llq_desc llq;
 957         } u;
 958 };
 959
 960 struct ena_admin_set_feat_resp {
 961         struct ena_admin_acq_common_desc acq_common_desc;
 962
 963         union {
 964                 uint32_t raw[14];
 965         } u;
 966 };
 967
 968 struct ena_admin_aenq_common_desc {
 969         uint16_t group;
 970
 971         uint16_t syndrom;
 972
 973         /* 0 : phase
 974          * 7:1 : reserved - MBZ
 975          */
 976         uint8_t flags;
 977
 978         uint8_t reserved1[3];
 979
 980         uint32_t timestamp_low;
 981
 982         uint32_t timestamp_high;
 983 };
 984
 985 /* asynchronous event notification groups */
 986 enum ena_admin_aenq_group {
 987         ENA_ADMIN_LINK_CHANGE                       = 0,
 988         ENA_ADMIN_FATAL_ERROR                       = 1,
 989         ENA_ADMIN_WARNING                           = 2,
 990         ENA_ADMIN_NOTIFICATION                      = 3,
 991         ENA_ADMIN_KEEP_ALIVE                        = 4,
 992         ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
 993 };
 994
 995 enum ena_admin_aenq_notification_syndrom {
 996         ENA_ADMIN_SUSPEND                           = 0,
 997         ENA_ADMIN_RESUME                            = 1,
 998         ENA_ADMIN_UPDATE_HINTS                      = 2,
 999 };
1000
1001 struct ena_admin_aenq_entry {
1002         struct ena_admin_aenq_common_desc aenq_common_desc;
1003
1004         /* command specific inline data */
1005         uint32_t inline_data_w4[12];
1006 };
1007
1008 struct ena_admin_aenq_link_change_desc {
1009         struct ena_admin_aenq_common_desc aenq_common_desc;
1010
1011         /* 0 : link_status */
1012         uint32_t flags;
1013 };
1014
1015 struct ena_admin_aenq_keep_alive_desc {
1016         struct ena_admin_aenq_common_desc aenq_common_desc;
1017
1018         uint32_t rx_drops_low;
1019
1020         uint32_t rx_drops_high;
1021
1022         uint32_t tx_drops_low;
1023
1024         uint32_t tx_drops_high;
1025 };
1026
1027 struct ena_admin_ena_mmio_req_read_less_resp {
1028         uint16_t req_id;
1029
1030         uint16_t reg_off;
1031
1032         /* value is valid when poll is cleared */
1033         uint32_t reg_val;
1034 };
1035
1036 /* aq_common_desc */
1037 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
1038 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
1039 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
1040 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
1041 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
1042 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
1043
1044 /* sq */
1045 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
1046 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
1047
1048 /* acq_common_desc */
1049 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
1050 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
1051
1052 /* aq_create_sq_cmd */
1053 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
1054 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
1055 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
1056 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
1057 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
1058 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1059
1060 /* aq_create_cq_cmd */
1061 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1062 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1063 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1064
1065 /* get_set_feature_common_desc */
1066 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
1067
1068 /* get_feature_link_desc */
1069 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
1070 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
1071 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
1072
1073 /* feature_offload_desc */
1074 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1075 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1076 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1077 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1078 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1079 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1080 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1081 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1082 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1083 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
1084 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
1085 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
1086 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
1087 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
1088 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
1089 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1090 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1091 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1092 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1093 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1094 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
1095 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
1096
1097 /* feature_rss_flow_hash_function */
1098 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1099 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1100
1101 /* feature_rss_flow_hash_input */
1102 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1103 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
1104 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1105 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
1106 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1107 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1108 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1109 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1110
1111 /* host_info */
1112 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
1113 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
1114 #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
1115 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
1116 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
1117 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
1118 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
1119 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
1120 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
1121 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
1122 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
1123 #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
1124 #define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK     BIT(0)
1125 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT                 1
1126 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK                  BIT(1)
1127 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT      2
1128 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK       BIT(2)
1129 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT  3
1130 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK   BIT(3)
1131
1132 /* feature_rss_ind_table */
1133 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1134
1135 /* aenq_common_desc */
1136 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
1137
1138 /* aenq_link_change_desc */
1139 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
1140
1141 #if !defined(DEFS_LINUX_MAINLINE)
1142 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1143 {
1144         return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1145 }
1146
1147 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1148 {
1149         p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1150 }
1151
1152 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1153 {
1154         return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1155 }
1156
1157 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1158 {
1159         p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1160 }
1161
1162 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1163 {
1164         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1165 }
1166
1167 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1168 {
1169         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1170 }
1171
1172 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1173 {
1174         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1175 }
1176
1177 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1178 {
1179         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1180 }
1181
1182 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1183 {
1184         return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1185 }
1186
1187 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1188 {
1189         p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1190 }
1191
1192 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1193 {
1194         return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1195 }
1196
1197 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1198 {
1199         p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1200 }
1201
1202 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1203 {
1204         return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1205 }
1206
1207 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1208 {
1209         p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1210 }
1211
1212 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1213 {
1214         return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1215 }
1216
1217 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1218 {
1219         p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1220 }
1221
1222 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1223 {
1224         return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1225 }
1226
1227 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1228 {
1229         p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1230 }
1231
1232 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1233 {
1234         return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1235 }
1236
1237 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1238 {
1239         p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1240 }
1241
1242 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1243 {
1244         return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1245 }
1246
1247 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1248 {
1249         p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1250 }
1251
1252 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1253 {
1254         return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1255 }
1256
1257 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1258 {
1259         p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1260 }
1261
1262 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1263 {
1264         return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1265 }
1266
1267 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1268 {
1269         p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1270 }
1271
1272 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1273 {
1274         return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1275 }
1276
1277 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1278 {
1279         p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1280 }
1281
1282 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1283 {
1284         return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1285 }
1286
1287 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1288 {
1289         p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1290 }
1291
1292 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1293 {
1294         return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1295 }
1296
1297 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1298 {
1299         p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1300 }
1301
1302 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1303 {
1304         return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1305 }
1306
1307 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1308 {
1309         p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1310 }
1311
1312 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1313 {
1314         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1315 }
1316
1317 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1318 {
1319         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1320 }
1321
1322 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1323 {
1324         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1325 }
1326
1327 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1328 {
1329         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1330 }
1331
1332 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1333 {
1334         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1335 }
1336
1337 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1338 {
1339         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1340 }
1341
1342 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1343 {
1344         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1345 }
1346
1347 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1348 {
1349         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1350 }
1351
1352 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1353 {
1354         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1355 }
1356
1357 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1358 {
1359         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1360 }
1361
1362 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1363 {
1364         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1365 }
1366
1367 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1368 {
1369         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1370 }
1371
1372 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1373 {
1374         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1375 }
1376
1377 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1378 {
1379         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1380 }
1381
1382 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1383 {
1384         return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1385 }
1386
1387 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1388 {
1389         p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1390 }
1391
1392 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1393 {
1394         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1395 }
1396
1397 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1398 {
1399         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1400 }
1401
1402 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1403 {
1404         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1405 }
1406
1407 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1408 {
1409         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1410 }
1411
1412 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1413 {
1414         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1415 }
1416
1417 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1418 {
1419         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1420 }
1421
1422 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1423 {
1424         return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1425 }
1426
1427 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1428 {
1429         p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1430 }
1431
1432 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1433 {
1434         return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1435 }
1436
1437 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1438 {
1439         p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1440 }
1441
1442 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1443 {
1444         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1445 }
1446
1447 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1448 {
1449         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1450 }
1451
1452 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1453 {
1454         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1455 }
1456
1457 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1458 {
1459         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1460 }
1461
1462 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1463 {
1464         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1465 }
1466
1467 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1468 {
1469         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1470 }
1471
1472 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1473 {
1474         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1475 }
1476
1477 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1478 {
1479         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1480 }
1481
1482 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1483 {
1484         return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1485 }
1486
1487 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1488 {
1489         p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1490 }
1491
1492 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1493 {
1494         return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1495 }
1496
1497 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1498 {
1499         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1500 }
1501
1502 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1503 {
1504         return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1505 }
1506
1507 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1508 {
1509         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1510 }
1511
1512 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1513 {
1514         return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1515 }
1516
1517 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1518 {
1519         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1520 }
1521
1522 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1523 {
1524         return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1525 }
1526
1527 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1528 {
1529         p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1530 }
1531
1532 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1533 {
1534         return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1535 }
1536
1537 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1538 {
1539         p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1540 }
1541
1542 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1543 {
1544         return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1545 }
1546
1547 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1548 {
1549         p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1550 }
1551
1552 static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p)
1553 {
1554         return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1555 }
1556
1557 static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val)
1558 {
1559         p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1560 }
1561
1562 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1563 {
1564         return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1565 }
1566
1567 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1568 {
1569         p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1570 }
1571
1572 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1573 {
1574         return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1575 }
1576
1577 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1578 {
1579         p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1580 }
1581
1582 static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p)
1583 {
1584         return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT;
1585 }
1586
1587 static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val)
1588 {
1589         p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK;
1590 }
1591
1592 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1593 {
1594         return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1595 }
1596
1597 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1598 {
1599         p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1600 }
1601
1602 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1603 {
1604         return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1605 }
1606
1607 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1608 {
1609         p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1610 }
1611
1612 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1613 {
1614         return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1615 }
1616
1617 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1618 {
1619         p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1620 }
1621
1622 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1623 #endif /* _ENA_ADMIN_H_ */