drivers/net/ena/base/ena_defs/ena_admin_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _ENA_ADMIN_H_
   7 #define _ENA_ADMIN_H_
   8
   9 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
  10 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT     32
  11
  12 enum ena_admin_aq_opcode {
  13         ENA_ADMIN_CREATE_SQ                         = 1,
  14         ENA_ADMIN_DESTROY_SQ                        = 2,
  15         ENA_ADMIN_CREATE_CQ                         = 3,
  16         ENA_ADMIN_DESTROY_CQ                        = 4,
  17         ENA_ADMIN_GET_FEATURE                       = 8,
  18         ENA_ADMIN_SET_FEATURE                       = 9,
  19         ENA_ADMIN_GET_STATS                         = 11,
  20 };
  21
  22 enum ena_admin_aq_completion_status {
  23         ENA_ADMIN_SUCCESS                           = 0,
  24         ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
  25         ENA_ADMIN_BAD_OPCODE                        = 2,
  26         ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
  27         ENA_ADMIN_MALFORMED_REQUEST                 = 4,
  28         /* Additional status is provided in ACQ entry extended_status */
  29         ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
  30         ENA_ADMIN_UNKNOWN_ERROR                     = 6,
  31         ENA_ADMIN_RESOURCE_BUSY                     = 7,
  32 };
  33
  34 enum ena_admin_aq_feature_id {
  35         ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
  36         ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
  37         ENA_ADMIN_HW_HINTS                          = 3,
  38         ENA_ADMIN_LLQ                               = 4,
  39         ENA_ADMIN_EXTRA_PROPERTIES_STRINGS          = 5,
  40         ENA_ADMIN_EXTRA_PROPERTIES_FLAGS            = 6,
  41         ENA_ADMIN_MAX_QUEUES_EXT                    = 7,
  42         ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
  43         ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
  44         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,
  45         ENA_ADMIN_MTU                               = 14,
  46         ENA_ADMIN_RSS_HASH_INPUT                    = 18,
  47         ENA_ADMIN_INTERRUPT_MODERATION              = 20,
  48         ENA_ADMIN_AENQ_CONFIG                       = 26,
  49         ENA_ADMIN_LINK_CONFIG                       = 27,
  50         ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
  51         ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
  52 };
  53
  54 enum ena_admin_placement_policy_type {
  55         /* descriptors and headers are in host memory */
  56         ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
  57         /* descriptors and headers are in device memory (a.k.a Low Latency
  58          * Queue)
  59          */
  60         ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
  61 };
  62
  63 enum ena_admin_link_types {
  64         ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
  65         ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
  66         ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
  67         ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
  68         ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
  69         ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
  70         ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
  71         ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
  72         ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
  73         ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
  74 };
  75
  76 enum ena_admin_completion_policy_type {
  77         /* completion queue entry for each sq descriptor */
  78         ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
  79         /* completion queue entry upon request in sq descriptor */
  80         ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
  81         /* current queue head pointer is updated in OS memory upon sq
  82          * descriptor request
  83          */
  84         ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
  85         /* current queue head pointer is updated in OS memory for each sq
  86          * descriptor
  87          */
  88         ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
  89 };
  90
  91 /* basic stats return ena_admin_basic_stats while extanded stats return a
  92  * buffer (string format) with additional statistics per queue and per
  93  * device id
  94  */
  95 enum ena_admin_get_stats_type {
  96         ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
  97         ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
  98         /* extra HW stats for specific network interface */
  99         ENA_ADMIN_GET_STATS_TYPE_ENI                = 2,
 100 };
 101
 102 enum ena_admin_get_stats_scope {
 103         ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
 104         ENA_ADMIN_ETH_TRAFFIC                       = 1,
 105 };
 106
 107 struct ena_admin_aq_common_desc {
 108         /* 11:0 : command_id
 109          * 15:12 : reserved12
 110          */
 111         uint16_t command_id;
 112
 113         /* as appears in ena_admin_aq_opcode */
 114         uint8_t opcode;
 115
 116         /* 0 : phase
 117          * 1 : ctrl_data - control buffer address valid
 118          * 2 : ctrl_data_indirect - control buffer address
 119          *    points to list of pages with addresses of control
 120          *    buffers
 121          * 7:3 : reserved3
 122          */
 123         uint8_t flags;
 124 };
 125
 126 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
 127  * page list chunk. Used also at the end of indirect mode page list chunks,
 128  * for chaining.
 129  */
 130 struct ena_admin_ctrl_buff_info {
 131         uint32_t length;
 132
 133         struct ena_common_mem_addr address;
 134 };
 135
 136 struct ena_admin_sq {
 137         uint16_t sq_idx;
 138
 139         /* 4:0 : reserved
 140          * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
 141          */
 142         uint8_t sq_identity;
 143
 144         uint8_t reserved1;
 145 };
 146
 147 struct ena_admin_aq_entry {
 148         struct ena_admin_aq_common_desc aq_common_descriptor;
 149
 150         union {
 151                 uint32_t inline_data_w1[3];
 152
 153                 struct ena_admin_ctrl_buff_info control_buffer;
 154         } u;
 155
 156         uint32_t inline_data_w4[12];
 157 };
 158
 159 struct ena_admin_acq_common_desc {
 160         /* command identifier to associate it with the aq descriptor
 161          * 11:0 : command_id
 162          * 15:12 : reserved12
 163          */
 164         uint16_t command;
 165
 166         uint8_t status;
 167
 168         /* 0 : phase
 169          * 7:1 : reserved1
 170          */
 171         uint8_t flags;
 172
 173         uint16_t extended_status;
 174
 175         /* indicates to the driver which AQ entry has been consumed by the
 176          *    device and could be reused
 177          */
 178         uint16_t sq_head_indx;
 179 };
 180
 181 struct ena_admin_acq_entry {
 182         struct ena_admin_acq_common_desc acq_common_descriptor;
 183
 184         uint32_t response_specific_data[14];
 185 };
 186
 187 struct ena_admin_aq_create_sq_cmd {
 188         struct ena_admin_aq_common_desc aq_common_descriptor;
 189
 190         /* 4:0 : reserved0_w1
 191          * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
 192          */
 193         uint8_t sq_identity;
 194
 195         uint8_t reserved8_w1;
 196
 197         /* 3:0 : placement_policy - Describing where the SQ
 198          *    descriptor ring and the SQ packet headers reside:
 199          *    0x1 - descriptors and headers are in OS memory,
 200          *    0x3 - descriptors and headers in device memory
 201          *    (a.k.a Low Latency Queue)
 202          * 6:4 : completion_policy - Describing what policy
 203          *    to use for generation completion entry (cqe) in
 204          *    the CQ associated with this SQ: 0x0 - cqe for each
 205          *    sq descriptor, 0x1 - cqe upon request in sq
 206          *    descriptor, 0x2 - current queue head pointer is
 207          *    updated in OS memory upon sq descriptor request
 208          *    0x3 - current queue head pointer is updated in OS
 209          *    memory for each sq descriptor
 210          * 7 : reserved15_w1
 211          */
 212         uint8_t sq_caps_2;
 213
 214         /* 0 : is_physically_contiguous - Described if the
 215          *    queue ring memory is allocated in physical
 216          *    contiguous pages or split.
 217          * 7:1 : reserved17_w1
 218          */
 219         uint8_t sq_caps_3;
 220
 221         /* associated completion queue id. This CQ must be created prior to
 222          *    SQ creation
 223          */
 224         uint16_t cq_idx;
 225
 226         /* submission queue depth in entries */
 227         uint16_t sq_depth;
 228
 229         /* SQ physical base address in OS memory. This field should not be
 230          * used for Low Latency queues. Has to be page aligned.
 231          */
 232         struct ena_common_mem_addr sq_ba;
 233
 234         /* specifies queue head writeback location in OS memory. Valid if
 235          * completion_policy is set to completion_policy_head_on_demand or
 236          * completion_policy_head. Has to be cache aligned
 237          */
 238         struct ena_common_mem_addr sq_head_writeback;
 239
 240         uint32_t reserved0_w7;
 241
 242         uint32_t reserved0_w8;
 243 };
 244
 245 enum ena_admin_sq_direction {
 246         ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
 247         ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
 248 };
 249
 250 struct ena_admin_acq_create_sq_resp_desc {
 251         struct ena_admin_acq_common_desc acq_common_desc;
 252
 253         uint16_t sq_idx;
 254
 255         uint16_t reserved;
 256
 257         /* queue doorbell address as an offset to PCIe MMIO REG BAR */
 258         uint32_t sq_doorbell_offset;
 259
 260         /* low latency queue ring base address as an offset to PCIe MMIO
 261          * LLQ_MEM BAR
 262          */
 263         uint32_t llq_descriptors_offset;
 264
 265         /* low latency queue headers' memory as an offset to PCIe MMIO
 266          * LLQ_MEM BAR
 267          */
 268         uint32_t llq_headers_offset;
 269 };
 270
 271 struct ena_admin_aq_destroy_sq_cmd {
 272         struct ena_admin_aq_common_desc aq_common_descriptor;
 273
 274         struct ena_admin_sq sq;
 275 };
 276
 277 struct ena_admin_acq_destroy_sq_resp_desc {
 278         struct ena_admin_acq_common_desc acq_common_desc;
 279 };
 280
 281 struct ena_admin_aq_create_cq_cmd {
 282         struct ena_admin_aq_common_desc aq_common_descriptor;
 283
 284         /* 4:0 : reserved5
 285          * 5 : interrupt_mode_enabled - if set, cq operates
 286          *    in interrupt mode, otherwise - polling
 287          * 7:6 : reserved6
 288          */
 289         uint8_t cq_caps_1;
 290
 291         /* 4:0 : cq_entry_size_words - size of CQ entry in
 292          *    32-bit words, valid values: 4, 8.
 293          * 7:5 : reserved7
 294          */
 295         uint8_t cq_caps_2;
 296
 297         /* completion queue depth in # of entries. must be power of 2 */
 298         uint16_t cq_depth;
 299
 300         /* msix vector assigned to this cq */
 301         uint32_t msix_vector;
 302
 303         /* cq physical base address in OS memory. CQ must be physically
 304          * contiguous
 305          */
 306         struct ena_common_mem_addr cq_ba;
 307 };
 308
 309 struct ena_admin_acq_create_cq_resp_desc {
 310         struct ena_admin_acq_common_desc acq_common_desc;
 311
 312         uint16_t cq_idx;
 313
 314         /* actual cq depth in number of entries */
 315         uint16_t cq_actual_depth;
 316
 317         uint32_t numa_node_register_offset;
 318
 319         uint32_t cq_head_db_register_offset;
 320
 321         uint32_t cq_interrupt_unmask_register_offset;
 322 };
 323
 324 struct ena_admin_aq_destroy_cq_cmd {
 325         struct ena_admin_aq_common_desc aq_common_descriptor;
 326
 327         uint16_t cq_idx;
 328
 329         uint16_t reserved1;
 330 };
 331
 332 struct ena_admin_acq_destroy_cq_resp_desc {
 333         struct ena_admin_acq_common_desc acq_common_desc;
 334 };
 335
 336 /* ENA AQ Get Statistics command. Extended statistics are placed in control
 337  * buffer pointed by AQ entry
 338  */
 339 struct ena_admin_aq_get_stats_cmd {
 340         struct ena_admin_aq_common_desc aq_common_descriptor;
 341
 342         union {
 343                 /* command specific inline data */
 344                 uint32_t inline_data_w1[3];
 345
 346                 struct ena_admin_ctrl_buff_info control_buffer;
 347         } u;
 348
 349         /* stats type as defined in enum ena_admin_get_stats_type */
 350         uint8_t type;
 351
 352         /* stats scope defined in enum ena_admin_get_stats_scope */
 353         uint8_t scope;
 354
 355         uint16_t reserved3;
 356
 357         /* queue id. used when scope is specific_queue */
 358         uint16_t queue_idx;
 359
 360         /* device id, value 0xFFFF means mine. only privileged device can get
 361          *    stats of other device
 362          */
 363         uint16_t device_id;
 364 };
 365
 366 /* Basic Statistics Command. */
 367 struct ena_admin_basic_stats {
 368         uint32_t tx_bytes_low;
 369
 370         uint32_t tx_bytes_high;
 371
 372         uint32_t tx_pkts_low;
 373
 374         uint32_t tx_pkts_high;
 375
 376         uint32_t rx_bytes_low;
 377
 378         uint32_t rx_bytes_high;
 379
 380         uint32_t rx_pkts_low;
 381
 382         uint32_t rx_pkts_high;
 383
 384         uint32_t rx_drops_low;
 385
 386         uint32_t rx_drops_high;
 387
 388         uint32_t tx_drops_low;
 389
 390         uint32_t tx_drops_high;
 391 };
 392
 393 /* ENI Statistics Command. */
 394 struct ena_admin_eni_stats {
 395         /* The number of packets shaped due to inbound aggregate BW
 396          * allowance being exceeded
 397          */
 398         uint64_t bw_in_allowance_exceeded;
 399
 400         /* The number of packets shaped due to outbound aggregate BW
 401          * allowance being exceeded
 402          */
 403         uint64_t bw_out_allowance_exceeded;
 404
 405         /* The number of packets shaped due to PPS allowance being exceeded */
 406         uint64_t pps_allowance_exceeded;
 407
 408         /* The number of packets shaped due to connection tracking
 409          * allowance being exceeded and leading to failure in establishment
 410          * of new connections
 411          */
 412         uint64_t conntrack_allowance_exceeded;
 413
 414         /* The number of packets shaped due to linklocal packet rate
 415          * allowance being exceeded
 416          */
 417         uint64_t linklocal_allowance_exceeded;
 418 };
 419
 420 struct ena_admin_acq_get_stats_resp {
 421         struct ena_admin_acq_common_desc acq_common_desc;
 422
 423         union {
 424                 uint64_t raw[7];
 425
 426                 struct ena_admin_basic_stats basic_stats;
 427
 428                 struct ena_admin_eni_stats eni_stats;
 429         } u;
 430 };
 431
 432 struct ena_admin_get_set_feature_common_desc {
 433         /* 1:0 : select - 0x1 - current value; 0x3 - default
 434          *    value
 435          * 7:3 : reserved3
 436          */
 437         uint8_t flags;
 438
 439         /* as appears in ena_admin_aq_feature_id */
 440         uint8_t feature_id;
 441
 442         /* The driver specifies the max feature version it supports and the
 443          *    device responds with the currently supported feature version. The
 444          *    field is zero based
 445          */
 446         uint8_t feature_version;
 447
 448         uint8_t reserved8;
 449 };
 450
 451 struct ena_admin_device_attr_feature_desc {
 452         uint32_t impl_id;
 453
 454         uint32_t device_version;
 455
 456         /* bitmap of ena_admin_aq_feature_id */
 457         uint32_t supported_features;
 458
 459         uint32_t reserved3;
 460
 461         /* Indicates how many bits are used physical address access. */
 462         uint32_t phys_addr_width;
 463
 464         /* Indicates how many bits are used virtual address access. */
 465         uint32_t virt_addr_width;
 466
 467         /* unicast MAC address (in Network byte order) */
 468         uint8_t mac_addr[6];
 469
 470         uint8_t reserved7[2];
 471
 472         uint32_t max_mtu;
 473 };
 474
 475 enum ena_admin_llq_header_location {
 476         /* header is in descriptor list */
 477         ENA_ADMIN_INLINE_HEADER                     = 1,
 478         /* header in a separate ring, implies 16B descriptor list entry */
 479         ENA_ADMIN_HEADER_RING                       = 2,
 480 };
 481
 482 enum ena_admin_llq_ring_entry_size {
 483         ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
 484         ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
 485         ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
 486 };
 487
 488 enum ena_admin_llq_num_descs_before_header {
 489         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
 490         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
 491         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
 492         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
 493         ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
 494 };
 495
 496 /* packet descriptor list entry always starts with one or more descriptors,
 497  * followed by a header. The rest of the descriptors are located in the
 498  * beginning of the subsequent entry. Stride refers to how the rest of the
 499  * descriptors are placed. This field is relevant only for inline header
 500  * mode
 501  */
 502 enum ena_admin_llq_stride_ctrl {
 503         ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
 504         ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
 505 };
 506
 507 enum ena_admin_accel_mode_feat {
 508         ENA_ADMIN_DISABLE_META_CACHING              = 0,
 509         ENA_ADMIN_LIMIT_TX_BURST                    = 1,
 510 };
 511
 512 struct ena_admin_accel_mode_get {
 513         /* bit field of enum ena_admin_accel_mode_feat */
 514         uint16_t supported_flags;
 515
 516         /* maximum burst size between two doorbells. The size is in bytes */
 517         uint16_t max_tx_burst_size;
 518 };
 519
 520 struct ena_admin_accel_mode_set {
 521         /* bit field of enum ena_admin_accel_mode_feat */
 522         uint16_t enabled_flags;
 523
 524         uint16_t reserved;
 525 };
 526
 527 struct ena_admin_accel_mode_req {
 528         union {
 529                 uint32_t raw[2];
 530
 531                 struct ena_admin_accel_mode_get get;
 532
 533                 struct ena_admin_accel_mode_set set;
 534         } u;
 535 };
 536
 537 struct ena_admin_feature_llq_desc {
 538         uint32_t max_llq_num;
 539
 540         uint32_t max_llq_depth;
 541
 542         /*  specify the header locations the device supports. bitfield of
 543          *    enum ena_admin_llq_header_location.
 544          */
 545         uint16_t header_location_ctrl_supported;
 546
 547         /* the header location the driver selected to use. */
 548         uint16_t header_location_ctrl_enabled;
 549
 550         /* if inline header is specified - this is the size of descriptor
 551          *    list entry. If header in a separate ring is specified - this is
 552          *    the size of header ring entry. bitfield of enum
 553          *    ena_admin_llq_ring_entry_size. specify the entry sizes the device
 554          *    supports
 555          */
 556         uint16_t entry_size_ctrl_supported;
 557
 558         /* the entry size the driver selected to use. */
 559         uint16_t entry_size_ctrl_enabled;
 560
 561         /* valid only if inline header is specified. First entry associated
 562          *    with the packet includes descriptors and header. Rest of the
 563          *    entries occupied by descriptors. This parameter defines the max
 564          *    number of descriptors precedding the header in the first entry.
 565          *    The field is bitfield of enum
 566          *    ena_admin_llq_num_descs_before_header and specify the values the
 567          *    device supports
 568          */
 569         uint16_t desc_num_before_header_supported;
 570
 571         /* the desire field the driver selected to use */
 572         uint16_t desc_num_before_header_enabled;
 573
 574         /* valid only if inline was chosen. bitfield of enum
 575          *    ena_admin_llq_stride_ctrl
 576          */
 577         uint16_t descriptors_stride_ctrl_supported;
 578
 579         /* the stride control the driver selected to use */
 580         uint16_t descriptors_stride_ctrl_enabled;
 581
 582         /* reserved */
 583         uint32_t reserved1;
 584
 585         /* accelerated low latency queues requirement. Driver needs to
 586          * support those requirements in order to use accelerated LLQ
 587          */
 588         struct ena_admin_accel_mode_req accel_mode;
 589 };
 590
 591 struct ena_admin_queue_ext_feature_fields {
 592         uint32_t max_tx_sq_num;
 593
 594         uint32_t max_tx_cq_num;
 595
 596         uint32_t max_rx_sq_num;
 597
 598         uint32_t max_rx_cq_num;
 599
 600         uint32_t max_tx_sq_depth;
 601
 602         uint32_t max_tx_cq_depth;
 603
 604         uint32_t max_rx_sq_depth;
 605
 606         uint32_t max_rx_cq_depth;
 607
 608         uint32_t max_tx_header_size;
 609
 610         /* Maximum Descriptors number, including meta descriptor, allowed for
 611          *    a single Tx packet
 612          */
 613         uint16_t max_per_packet_tx_descs;
 614
 615         /* Maximum Descriptors number allowed for a single Rx packet */
 616         uint16_t max_per_packet_rx_descs;
 617 };
 618
 619 struct ena_admin_queue_feature_desc {
 620         uint32_t max_sq_num;
 621
 622         uint32_t max_sq_depth;
 623
 624         uint32_t max_cq_num;
 625
 626         uint32_t max_cq_depth;
 627
 628         uint32_t max_legacy_llq_num;
 629
 630         uint32_t max_legacy_llq_depth;
 631
 632         uint32_t max_header_size;
 633
 634         /* Maximum Descriptors number, including meta descriptor, allowed for
 635          *    a single Tx packet
 636          */
 637         uint16_t max_packet_tx_descs;
 638
 639         /* Maximum Descriptors number allowed for a single Rx packet */
 640         uint16_t max_packet_rx_descs;
 641 };
 642
 643 struct ena_admin_set_feature_mtu_desc {
 644         /* exclude L2 */
 645         uint32_t mtu;
 646 };
 647
 648 struct ena_admin_get_extra_properties_strings_desc {
 649         uint32_t count;
 650 };
 651
 652 struct ena_admin_get_extra_properties_flags_desc {
 653         uint32_t flags;
 654 };
 655
 656 struct ena_admin_set_feature_host_attr_desc {
 657         /* host OS info base address in OS memory. host info is 4KB of
 658          * physically contiguous
 659          */
 660         struct ena_common_mem_addr os_info_ba;
 661
 662         /* host debug area base address in OS memory. debug area must be
 663          * physically contiguous
 664          */
 665         struct ena_common_mem_addr debug_ba;
 666
 667         /* debug area size */
 668         uint32_t debug_area_size;
 669 };
 670
 671 struct ena_admin_feature_intr_moder_desc {
 672         /* interrupt delay granularity in usec */
 673         uint16_t intr_delay_resolution;
 674
 675         uint16_t reserved;
 676 };
 677
 678 struct ena_admin_get_feature_link_desc {
 679         /* Link speed in Mb */
 680         uint32_t speed;
 681
 682         /* bit field of enum ena_admin_link types */
 683         uint32_t supported;
 684
 685         /* 0 : autoneg
 686          * 1 : duplex - Full Duplex
 687          * 31:2 : reserved2
 688          */
 689         uint32_t flags;
 690 };
 691
 692 struct ena_admin_feature_aenq_desc {
 693         /* bitmask for AENQ groups the device can report */
 694         uint32_t supported_groups;
 695
 696         /* bitmask for AENQ groups to report */
 697         uint32_t enabled_groups;
 698 };
 699
 700 struct ena_admin_feature_offload_desc {
 701         /* 0 : TX_L3_csum_ipv4
 702          * 1 : TX_L4_ipv4_csum_part - The checksum field
 703          *    should be initialized with pseudo header checksum
 704          * 2 : TX_L4_ipv4_csum_full
 705          * 3 : TX_L4_ipv6_csum_part - The checksum field
 706          *    should be initialized with pseudo header checksum
 707          * 4 : TX_L4_ipv6_csum_full
 708          * 5 : tso_ipv4
 709          * 6 : tso_ipv6
 710          * 7 : tso_ecn
 711          */
 712         uint32_t tx;
 713
 714         /* Receive side supported stateless offload
 715          * 0 : RX_L3_csum_ipv4 - IPv4 checksum
 716          * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
 717          * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
 718          * 3 : RX_hash - Hash calculation
 719          */
 720         uint32_t rx_supported;
 721
 722         uint32_t rx_enabled;
 723 };
 724
 725 enum ena_admin_hash_functions {
 726         ENA_ADMIN_TOEPLITZ                          = 1,
 727         ENA_ADMIN_CRC32                             = 2,
 728 };
 729
 730 struct ena_admin_feature_rss_flow_hash_control {
 731         uint32_t keys_num;
 732
 733         uint32_t reserved;
 734
 735         uint32_t key[10];
 736 };
 737
 738 struct ena_admin_feature_rss_flow_hash_function {
 739         /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
 740         uint32_t supported_func;
 741
 742         /* 7:0 : selected_func - bitmask of
 743          *    ena_admin_hash_functions
 744          */
 745         uint32_t selected_func;
 746
 747         /* initial value */
 748         uint32_t init_val;
 749 };
 750
 751 /* RSS flow hash protocols */
 752 enum ena_admin_flow_hash_proto {
 753         ENA_ADMIN_RSS_TCP4                          = 0,
 754         ENA_ADMIN_RSS_UDP4                          = 1,
 755         ENA_ADMIN_RSS_TCP6                          = 2,
 756         ENA_ADMIN_RSS_UDP6                          = 3,
 757         ENA_ADMIN_RSS_IP4                           = 4,
 758         ENA_ADMIN_RSS_IP6                           = 5,
 759         ENA_ADMIN_RSS_IP4_FRAG                      = 6,
 760         ENA_ADMIN_RSS_NOT_IP                        = 7,
 761         /* TCPv6 with extension header */
 762         ENA_ADMIN_RSS_TCP6_EX                       = 8,
 763         /* IPv6 with extension header */
 764         ENA_ADMIN_RSS_IP6_EX                        = 9,
 765         ENA_ADMIN_RSS_PROTO_NUM                     = 16,
 766 };
 767
 768 /* RSS flow hash fields */
 769 enum ena_admin_flow_hash_fields {
 770         /* Ethernet Dest Addr */
 771         ENA_ADMIN_RSS_L2_DA                         = BIT(0),
 772         /* Ethernet Src Addr */
 773         ENA_ADMIN_RSS_L2_SA                         = BIT(1),
 774         /* ipv4/6 Dest Addr */
 775         ENA_ADMIN_RSS_L3_DA                         = BIT(2),
 776         /* ipv4/6 Src Addr */
 777         ENA_ADMIN_RSS_L3_SA                         = BIT(3),
 778         /* tcp/udp Dest Port */
 779         ENA_ADMIN_RSS_L4_DP                         = BIT(4),
 780         /* tcp/udp Src Port */
 781         ENA_ADMIN_RSS_L4_SP                         = BIT(5),
 782 };
 783
 784 struct ena_admin_proto_input {
 785         /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
 786         uint16_t fields;
 787
 788         uint16_t reserved2;
 789 };
 790
 791 struct ena_admin_feature_rss_hash_control {
 792         struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
 793
 794         struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
 795
 796         struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
 797
 798         struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
 799 };
 800
 801 struct ena_admin_feature_rss_flow_hash_input {
 802         /* supported hash input sorting
 803          * 1 : L3_sort - support swap L3 addresses if DA is
 804          *    smaller than SA
 805          * 2 : L4_sort - support swap L4 ports if DP smaller
 806          *    SP
 807          */
 808         uint16_t supported_input_sort;
 809
 810         /* enabled hash input sorting
 811          * 1 : enable_L3_sort - enable swap L3 addresses if
 812          *    DA smaller than SA
 813          * 2 : enable_L4_sort - enable swap L4 ports if DP
 814          *    smaller than SP
 815          */
 816         uint16_t enabled_input_sort;
 817 };
 818
 819 enum ena_admin_os_type {
 820         ENA_ADMIN_OS_LINUX                          = 1,
 821         ENA_ADMIN_OS_WIN                            = 2,
 822         ENA_ADMIN_OS_DPDK                           = 3,
 823         ENA_ADMIN_OS_FREEBSD                        = 4,
 824         ENA_ADMIN_OS_IPXE                           = 5,
 825         ENA_ADMIN_OS_ESXI                           = 6,
 826         ENA_ADMIN_OS_GROUPS_NUM                     = 6,
 827 };
 828
 829 struct ena_admin_host_info {
 830         /* defined in enum ena_admin_os_type */
 831         uint32_t os_type;
 832
 833         /* os distribution string format */
 834         uint8_t os_dist_str[128];
 835
 836         /* OS distribution numeric format */
 837         uint32_t os_dist;
 838
 839         /* kernel version string format */
 840         uint8_t kernel_ver_str[32];
 841
 842         /* Kernel version numeric format */
 843         uint32_t kernel_ver;
 844
 845         /* 7:0 : major
 846          * 15:8 : minor
 847          * 23:16 : sub_minor
 848          * 31:24 : module_type
 849          */
 850         uint32_t driver_version;
 851
 852         /* features bitmap */
 853         uint32_t supported_network_features[2];
 854
 855         /* ENA spec version of driver */
 856         uint16_t ena_spec_version;
 857
 858         /* ENA device's Bus, Device and Function
 859          * 2:0 : function
 860          * 7:3 : device
 861          * 15:8 : bus
 862          */
 863         uint16_t bdf;
 864
 865         /* Number of CPUs */
 866         uint16_t num_cpus;
 867
 868         uint16_t reserved;
 869
 870         /* 0 : mutable_rss_table_size
 871          * 1 : rx_offset
 872          * 2 : interrupt_moderation
 873          * 3 : map_rx_buf_bidirectional
 874          * 31:4 : reserved
 875          */
 876         uint32_t driver_supported_features;
 877 };
 878
 879 struct ena_admin_rss_ind_table_entry {
 880         uint16_t cq_idx;
 881
 882         uint16_t reserved;
 883 };
 884
 885 struct ena_admin_feature_rss_ind_table {
 886         /* min supported table size (2^min_size) */
 887         uint16_t min_size;
 888
 889         /* max supported table size (2^max_size) */
 890         uint16_t max_size;
 891
 892         /* table size (2^size) */
 893         uint16_t size;
 894
 895         /* 0 : one_entry_update - The ENA device supports
 896          *    setting a single RSS table entry
 897          */
 898         uint8_t flags;
 899
 900         uint8_t reserved;
 901
 902         /* index of the inline entry. 0xFFFFFFFF means invalid */
 903         uint32_t inline_index;
 904
 905         /* used for updating single entry, ignored when setting the entire
 906          * table through the control buffer.
 907          */
 908         struct ena_admin_rss_ind_table_entry inline_entry;
 909 };
 910
 911 /* When hint value is 0, driver should use it's own predefined value */
 912 struct ena_admin_ena_hw_hints {
 913         /* value in ms */
 914         uint16_t mmio_read_timeout;
 915
 916         /* value in ms */
 917         uint16_t driver_watchdog_timeout;
 918
 919         /* Per packet tx completion timeout. value in ms */
 920         uint16_t missing_tx_completion_timeout;
 921
 922         uint16_t missed_tx_completion_count_threshold_to_reset;
 923
 924         /* value in ms */
 925         uint16_t admin_completion_tx_timeout;
 926
 927         uint16_t netdev_wd_timeout;
 928
 929         uint16_t max_tx_sgl_size;
 930
 931         uint16_t max_rx_sgl_size;
 932
 933         uint16_t reserved[8];
 934 };
 935
 936 struct ena_admin_get_feat_cmd {
 937         struct ena_admin_aq_common_desc aq_common_descriptor;
 938
 939         struct ena_admin_ctrl_buff_info control_buffer;
 940
 941         struct ena_admin_get_set_feature_common_desc feat_common;
 942
 943         uint32_t raw[11];
 944 };
 945
 946 struct ena_admin_queue_ext_feature_desc {
 947         /* version */
 948         uint8_t version;
 949
 950         uint8_t reserved1[3];
 951
 952         union {
 953                 struct ena_admin_queue_ext_feature_fields max_queue_ext;
 954
 955                 uint32_t raw[10];
 956         } ;
 957 };
 958
 959 struct ena_admin_get_feat_resp {
 960         struct ena_admin_acq_common_desc acq_common_desc;
 961
 962         union {
 963                 uint32_t raw[14];
 964
 965                 struct ena_admin_device_attr_feature_desc dev_attr;
 966
 967                 struct ena_admin_feature_llq_desc llq;
 968
 969                 struct ena_admin_queue_feature_desc max_queue;
 970
 971                 struct ena_admin_queue_ext_feature_desc max_queue_ext;
 972
 973                 struct ena_admin_feature_aenq_desc aenq;
 974
 975                 struct ena_admin_get_feature_link_desc link;
 976
 977                 struct ena_admin_feature_offload_desc offload;
 978
 979                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
 980
 981                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
 982
 983                 struct ena_admin_feature_rss_ind_table ind_table;
 984
 985                 struct ena_admin_feature_intr_moder_desc intr_moderation;
 986
 987                 struct ena_admin_ena_hw_hints hw_hints;
 988
 989                 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
 990
 991                 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
 992         } u;
 993 };
 994
 995 struct ena_admin_set_feat_cmd {
 996         struct ena_admin_aq_common_desc aq_common_descriptor;
 997
 998         struct ena_admin_ctrl_buff_info control_buffer;
 999
1000         struct ena_admin_get_set_feature_common_desc feat_common;
1001
1002         union {
1003                 uint32_t raw[11];
1004
1005                 /* mtu size */
1006                 struct ena_admin_set_feature_mtu_desc mtu;
1007
1008                 /* host attributes */
1009                 struct ena_admin_set_feature_host_attr_desc host_attr;
1010
1011                 /* AENQ configuration */
1012                 struct ena_admin_feature_aenq_desc aenq;
1013
1014                 /* rss flow hash function */
1015                 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1016
1017                 /* rss flow hash input */
1018                 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1019
1020                 /* rss indirection table */
1021                 struct ena_admin_feature_rss_ind_table ind_table;
1022
1023                 /* LLQ configuration */
1024                 struct ena_admin_feature_llq_desc llq;
1025         } u;
1026 };
1027
1028 struct ena_admin_set_feat_resp {
1029         struct ena_admin_acq_common_desc acq_common_desc;
1030
1031         union {
1032                 uint32_t raw[14];
1033         } u;
1034 };
1035
1036 struct ena_admin_aenq_common_desc {
1037         uint16_t group;
1038
1039         uint16_t syndrom;
1040
1041         /* 0 : phase
1042          * 7:1 : reserved - MBZ
1043          */
1044         uint8_t flags;
1045
1046         uint8_t reserved1[3];
1047
1048         uint32_t timestamp_low;
1049
1050         uint32_t timestamp_high;
1051 };
1052
1053 /* asynchronous event notification groups */
1054 enum ena_admin_aenq_group {
1055         ENA_ADMIN_LINK_CHANGE                       = 0,
1056         ENA_ADMIN_FATAL_ERROR                       = 1,
1057         ENA_ADMIN_WARNING                           = 2,
1058         ENA_ADMIN_NOTIFICATION                      = 3,
1059         ENA_ADMIN_KEEP_ALIVE                        = 4,
1060         ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
1061 };
1062
1063 enum ena_admin_aenq_notification_syndrom {
1064         ENA_ADMIN_SUSPEND                           = 0,
1065         ENA_ADMIN_RESUME                            = 1,
1066         ENA_ADMIN_UPDATE_HINTS                      = 2,
1067 };
1068
1069 struct ena_admin_aenq_entry {
1070         struct ena_admin_aenq_common_desc aenq_common_desc;
1071
1072         /* command specific inline data */
1073         uint32_t inline_data_w4[12];
1074 };
1075
1076 struct ena_admin_aenq_link_change_desc {
1077         struct ena_admin_aenq_common_desc aenq_common_desc;
1078
1079         /* 0 : link_status */
1080         uint32_t flags;
1081 };
1082
1083 struct ena_admin_aenq_keep_alive_desc {
1084         struct ena_admin_aenq_common_desc aenq_common_desc;
1085
1086         uint32_t rx_drops_low;
1087
1088         uint32_t rx_drops_high;
1089
1090         uint32_t tx_drops_low;
1091
1092         uint32_t tx_drops_high;
1093 };
1094
1095 struct ena_admin_ena_mmio_req_read_less_resp {
1096         uint16_t req_id;
1097
1098         uint16_t reg_off;
1099
1100         /* value is valid when poll is cleared */
1101         uint32_t reg_val;
1102 };
1103
1104 /* aq_common_desc */
1105 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
1106 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
1107 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
1108 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
1109 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
1110 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
1111
1112 /* sq */
1113 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
1114 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
1115
1116 /* acq_common_desc */
1117 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
1118 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
1119
1120 /* aq_create_sq_cmd */
1121 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
1122 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
1123 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
1124 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
1125 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
1126 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1127
1128 /* aq_create_cq_cmd */
1129 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1130 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1131 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1132
1133 /* get_set_feature_common_desc */
1134 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
1135
1136 /* get_feature_link_desc */
1137 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
1138 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
1139 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
1140
1141 /* feature_offload_desc */
1142 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1143 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1144 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1145 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1146 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1147 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1148 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1149 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1150 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1151 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
1152 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
1153 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
1154 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
1155 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
1156 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
1157 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1158 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1159 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1160 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1161 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1162 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
1163 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
1164
1165 /* feature_rss_flow_hash_function */
1166 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1167 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1168
1169 /* feature_rss_flow_hash_input */
1170 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1171 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
1172 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1173 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
1174 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1175 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1176 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1177 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1178
1179 /* host_info */
1180 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
1181 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
1182 #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
1183 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
1184 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
1185 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
1186 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
1187 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
1188 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
1189 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
1190 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
1191 #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
1192 #define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK     BIT(0)
1193 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT                 1
1194 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK                  BIT(1)
1195 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT      2
1196 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK       BIT(2)
1197 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT  3
1198 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK   BIT(3)
1199
1200 /* feature_rss_ind_table */
1201 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1202
1203 /* aenq_common_desc */
1204 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
1205
1206 /* aenq_link_change_desc */
1207 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
1208
1209 #if !defined(DEFS_LINUX_MAINLINE)
1210 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1211 {
1212         return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1213 }
1214
1215 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1216 {
1217         p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1218 }
1219
1220 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1221 {
1222         return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1223 }
1224
1225 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1226 {
1227         p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1228 }
1229
1230 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1231 {
1232         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1233 }
1234
1235 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1236 {
1237         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1238 }
1239
1240 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1241 {
1242         return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1243 }
1244
1245 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1246 {
1247         p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1248 }
1249
1250 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1251 {
1252         return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1253 }
1254
1255 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1256 {
1257         p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1258 }
1259
1260 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1261 {
1262         return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1263 }
1264
1265 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1266 {
1267         p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1268 }
1269
1270 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1271 {
1272         return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1273 }
1274
1275 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1276 {
1277         p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1278 }
1279
1280 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1281 {
1282         return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1283 }
1284
1285 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1286 {
1287         p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1288 }
1289
1290 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1291 {
1292         return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1293 }
1294
1295 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1296 {
1297         p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1298 }
1299
1300 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1301 {
1302         return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1303 }
1304
1305 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1306 {
1307         p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1308 }
1309
1310 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1311 {
1312         return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1313 }
1314
1315 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1316 {
1317         p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1318 }
1319
1320 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1321 {
1322         return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1323 }
1324
1325 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1326 {
1327         p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1328 }
1329
1330 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1331 {
1332         return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1333 }
1334
1335 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1336 {
1337         p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1338 }
1339
1340 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1341 {
1342         return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1343 }
1344
1345 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1346 {
1347         p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1348 }
1349
1350 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1351 {
1352         return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1353 }
1354
1355 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1356 {
1357         p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1358 }
1359
1360 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1361 {
1362         return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1363 }
1364
1365 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1366 {
1367         p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1368 }
1369
1370 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1371 {
1372         return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1373 }
1374
1375 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1376 {
1377         p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1378 }
1379
1380 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1381 {
1382         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1383 }
1384
1385 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1386 {
1387         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1388 }
1389
1390 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1391 {
1392         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1393 }
1394
1395 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1396 {
1397         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1398 }
1399
1400 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1401 {
1402         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1403 }
1404
1405 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1406 {
1407         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1408 }
1409
1410 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1411 {
1412         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1413 }
1414
1415 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1416 {
1417         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1418 }
1419
1420 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1421 {
1422         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1423 }
1424
1425 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1426 {
1427         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1428 }
1429
1430 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1431 {
1432         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1433 }
1434
1435 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1436 {
1437         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1438 }
1439
1440 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1441 {
1442         return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1443 }
1444
1445 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1446 {
1447         p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1448 }
1449
1450 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1451 {
1452         return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1453 }
1454
1455 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1456 {
1457         p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1458 }
1459
1460 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1461 {
1462         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1463 }
1464
1465 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1466 {
1467         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1468 }
1469
1470 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1471 {
1472         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1473 }
1474
1475 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1476 {
1477         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1478 }
1479
1480 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1481 {
1482         return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1483 }
1484
1485 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1486 {
1487         p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1488 }
1489
1490 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1491 {
1492         return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1493 }
1494
1495 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1496 {
1497         p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1498 }
1499
1500 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1501 {
1502         return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1503 }
1504
1505 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1506 {
1507         p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1508 }
1509
1510 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1511 {
1512         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1513 }
1514
1515 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1516 {
1517         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1518 }
1519
1520 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1521 {
1522         return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1523 }
1524
1525 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1526 {
1527         p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1528 }
1529
1530 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1531 {
1532         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1533 }
1534
1535 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1536 {
1537         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1538 }
1539
1540 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1541 {
1542         return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1543 }
1544
1545 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1546 {
1547         p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1548 }
1549
1550 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1551 {
1552         return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1553 }
1554
1555 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1556 {
1557         p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1558 }
1559
1560 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1561 {
1562         return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1563 }
1564
1565 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1566 {
1567         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1568 }
1569
1570 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1571 {
1572         return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1573 }
1574
1575 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1576 {
1577         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1578 }
1579
1580 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1581 {
1582         return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1583 }
1584
1585 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1586 {
1587         p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1588 }
1589
1590 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1591 {
1592         return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1593 }
1594
1595 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1596 {
1597         p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1598 }
1599
1600 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1601 {
1602         return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1603 }
1604
1605 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1606 {
1607         p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1608 }
1609
1610 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1611 {
1612         return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1613 }
1614
1615 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1616 {
1617         p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1618 }
1619
1620 static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p)
1621 {
1622         return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1623 }
1624
1625 static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val)
1626 {
1627         p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1628 }
1629
1630 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1631 {
1632         return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1633 }
1634
1635 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1636 {
1637         p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1638 }
1639
1640 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1641 {
1642         return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1643 }
1644
1645 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1646 {
1647         p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1648 }
1649
1650 static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p)
1651 {
1652         return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT;
1653 }
1654
1655 static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val)
1656 {
1657         p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK;
1658 }
1659
1660 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1661 {
1662         return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1663 }
1664
1665 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1666 {
1667         p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1668 }
1669
1670 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1671 {
1672         return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1673 }
1674
1675 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1676 {
1677         p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1678 }
1679
1680 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1681 {
1682         return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1683 }
1684
1685 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1686 {
1687         p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1688 }
1689
1690 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1691 #endif /* _ENA_ADMIN_H_ */