1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
8 #define ENA_ADMIN_RSS_KEY_PARTS 10
10 enum ena_admin_aq_opcode {
11 ENA_ADMIN_CREATE_SQ = 1,
12 ENA_ADMIN_DESTROY_SQ = 2,
13 ENA_ADMIN_CREATE_CQ = 3,
14 ENA_ADMIN_DESTROY_CQ = 4,
15 ENA_ADMIN_GET_FEATURE = 8,
16 ENA_ADMIN_SET_FEATURE = 9,
17 ENA_ADMIN_GET_STATS = 11,
20 enum ena_admin_aq_completion_status {
21 ENA_ADMIN_SUCCESS = 0,
22 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
23 ENA_ADMIN_BAD_OPCODE = 2,
24 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
25 ENA_ADMIN_MALFORMED_REQUEST = 4,
26 /* Additional status is provided in ACQ entry extended_status */
27 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
28 ENA_ADMIN_UNKNOWN_ERROR = 6,
29 ENA_ADMIN_RESOURCE_BUSY = 7,
32 /* subcommands for the set/get feature admin commands */
33 enum ena_admin_aq_feature_id {
34 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
35 ENA_ADMIN_MAX_QUEUES_NUM = 2,
36 ENA_ADMIN_HW_HINTS = 3,
38 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
39 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
40 ENA_ADMIN_MAX_QUEUES_EXT = 7,
41 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
42 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
43 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
45 ENA_ADMIN_RSS_HASH_INPUT = 18,
46 ENA_ADMIN_INTERRUPT_MODERATION = 20,
47 ENA_ADMIN_AENQ_CONFIG = 26,
48 ENA_ADMIN_LINK_CONFIG = 27,
49 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
50 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
53 enum ena_admin_placement_policy_type {
54 /* descriptors and headers are in host memory */
55 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
56 /* descriptors and headers are in device memory (a.k.a Low Latency
59 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
62 enum ena_admin_link_types {
63 ENA_ADMIN_LINK_SPEED_1G = 0x1,
64 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
65 ENA_ADMIN_LINK_SPEED_5G = 0x4,
66 ENA_ADMIN_LINK_SPEED_10G = 0x8,
67 ENA_ADMIN_LINK_SPEED_25G = 0x10,
68 ENA_ADMIN_LINK_SPEED_40G = 0x20,
69 ENA_ADMIN_LINK_SPEED_50G = 0x40,
70 ENA_ADMIN_LINK_SPEED_100G = 0x80,
71 ENA_ADMIN_LINK_SPEED_200G = 0x100,
72 ENA_ADMIN_LINK_SPEED_400G = 0x200,
75 enum ena_admin_completion_policy_type {
76 /* completion queue entry for each sq descriptor */
77 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
78 /* completion queue entry upon request in sq descriptor */
79 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
80 /* current queue head pointer is updated in OS memory upon sq
83 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
84 /* current queue head pointer is updated in OS memory for each sq
87 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
90 /* basic stats return ena_admin_basic_stats while extanded stats return a
91 * buffer (string format) with additional statistics per queue and per
94 enum ena_admin_get_stats_type {
95 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
96 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
97 /* extra HW stats for specific network interface */
98 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
101 enum ena_admin_get_stats_scope {
102 ENA_ADMIN_SPECIFIC_QUEUE = 0,
103 ENA_ADMIN_ETH_TRAFFIC = 1,
106 struct ena_admin_aq_common_desc {
112 /* as appears in ena_admin_aq_opcode */
116 * 1 : ctrl_data - control buffer address valid
117 * 2 : ctrl_data_indirect - control buffer address
118 * points to list of pages with addresses of control
125 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
126 * page list chunk. Used also at the end of indirect mode page list chunks,
129 struct ena_admin_ctrl_buff_info {
132 struct ena_common_mem_addr address;
135 struct ena_admin_sq {
139 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
146 struct ena_admin_aq_entry {
147 struct ena_admin_aq_common_desc aq_common_descriptor;
150 uint32_t inline_data_w1[3];
152 struct ena_admin_ctrl_buff_info control_buffer;
155 uint32_t inline_data_w4[12];
158 struct ena_admin_acq_common_desc {
159 /* command identifier to associate it with the aq descriptor
172 uint16_t extended_status;
174 /* indicates to the driver which AQ entry has been consumed by the
175 * device and could be reused
177 uint16_t sq_head_indx;
180 struct ena_admin_acq_entry {
181 struct ena_admin_acq_common_desc acq_common_descriptor;
183 uint32_t response_specific_data[14];
186 struct ena_admin_aq_create_sq_cmd {
187 struct ena_admin_aq_common_desc aq_common_descriptor;
189 /* 4:0 : reserved0_w1
190 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
194 uint8_t reserved8_w1;
196 /* 3:0 : placement_policy - Describing where the SQ
197 * descriptor ring and the SQ packet headers reside:
198 * 0x1 - descriptors and headers are in OS memory,
199 * 0x3 - descriptors and headers in device memory
200 * (a.k.a Low Latency Queue)
201 * 6:4 : completion_policy - Describing what policy
202 * to use for generation completion entry (cqe) in
203 * the CQ associated with this SQ: 0x0 - cqe for each
204 * sq descriptor, 0x1 - cqe upon request in sq
205 * descriptor, 0x2 - current queue head pointer is
206 * updated in OS memory upon sq descriptor request
207 * 0x3 - current queue head pointer is updated in OS
208 * memory for each sq descriptor
213 /* 0 : is_physically_contiguous - Described if the
214 * queue ring memory is allocated in physical
215 * contiguous pages or split.
216 * 7:1 : reserved17_w1
220 /* associated completion queue id. This CQ must be created prior to SQ
225 /* submission queue depth in entries */
228 /* SQ physical base address in OS memory. This field should not be
229 * used for Low Latency queues. Has to be page aligned.
231 struct ena_common_mem_addr sq_ba;
233 /* specifies queue head writeback location in OS memory. Valid if
234 * completion_policy is set to completion_policy_head_on_demand or
235 * completion_policy_head. Has to be cache aligned
237 struct ena_common_mem_addr sq_head_writeback;
239 uint32_t reserved0_w7;
241 uint32_t reserved0_w8;
244 enum ena_admin_sq_direction {
245 ENA_ADMIN_SQ_DIRECTION_TX = 1,
246 ENA_ADMIN_SQ_DIRECTION_RX = 2,
249 struct ena_admin_acq_create_sq_resp_desc {
250 struct ena_admin_acq_common_desc acq_common_desc;
256 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
257 uint32_t sq_doorbell_offset;
259 /* low latency queue ring base address as an offset to PCIe MMIO
262 uint32_t llq_descriptors_offset;
264 /* low latency queue headers' memory as an offset to PCIe MMIO
267 uint32_t llq_headers_offset;
270 struct ena_admin_aq_destroy_sq_cmd {
271 struct ena_admin_aq_common_desc aq_common_descriptor;
273 struct ena_admin_sq sq;
276 struct ena_admin_acq_destroy_sq_resp_desc {
277 struct ena_admin_acq_common_desc acq_common_desc;
280 struct ena_admin_aq_create_cq_cmd {
281 struct ena_admin_aq_common_desc aq_common_descriptor;
284 * 5 : interrupt_mode_enabled - if set, cq operates
285 * in interrupt mode, otherwise - polling
290 /* 4:0 : cq_entry_size_words - size of CQ entry in
291 * 32-bit words, valid values: 4, 8.
296 /* completion queue depth in # of entries. must be power of 2 */
299 /* msix vector assigned to this cq */
300 uint32_t msix_vector;
302 /* cq physical base address in OS memory. CQ must be physically
305 struct ena_common_mem_addr cq_ba;
308 struct ena_admin_acq_create_cq_resp_desc {
309 struct ena_admin_acq_common_desc acq_common_desc;
313 /* actual cq depth in number of entries */
314 uint16_t cq_actual_depth;
316 uint32_t numa_node_register_offset;
318 uint32_t cq_head_db_register_offset;
320 uint32_t cq_interrupt_unmask_register_offset;
323 struct ena_admin_aq_destroy_cq_cmd {
324 struct ena_admin_aq_common_desc aq_common_descriptor;
331 struct ena_admin_acq_destroy_cq_resp_desc {
332 struct ena_admin_acq_common_desc acq_common_desc;
335 /* ENA AQ Get Statistics command. Extended statistics are placed in control
336 * buffer pointed by AQ entry
338 struct ena_admin_aq_get_stats_cmd {
339 struct ena_admin_aq_common_desc aq_common_descriptor;
342 /* command specific inline data */
343 uint32_t inline_data_w1[3];
345 struct ena_admin_ctrl_buff_info control_buffer;
348 /* stats type as defined in enum ena_admin_get_stats_type */
351 /* stats scope defined in enum ena_admin_get_stats_scope */
356 /* queue id. used when scope is specific_queue */
359 /* device id, value 0xFFFF means mine. only privileged device can get
360 * stats of other device
365 /* Basic Statistics Command. */
366 struct ena_admin_basic_stats {
367 uint32_t tx_bytes_low;
369 uint32_t tx_bytes_high;
371 uint32_t tx_pkts_low;
373 uint32_t tx_pkts_high;
375 uint32_t rx_bytes_low;
377 uint32_t rx_bytes_high;
379 uint32_t rx_pkts_low;
381 uint32_t rx_pkts_high;
383 uint32_t rx_drops_low;
385 uint32_t rx_drops_high;
387 uint32_t tx_drops_low;
389 uint32_t tx_drops_high;
392 /* ENI Statistics Command. */
393 struct ena_admin_eni_stats {
394 /* The number of packets shaped due to inbound aggregate BW
395 * allowance being exceeded
397 uint64_t bw_in_allowance_exceeded;
399 /* The number of packets shaped due to outbound aggregate BW
400 * allowance being exceeded
402 uint64_t bw_out_allowance_exceeded;
404 /* The number of packets shaped due to PPS allowance being exceeded */
405 uint64_t pps_allowance_exceeded;
407 /* The number of packets shaped due to connection tracking
408 * allowance being exceeded and leading to failure in establishment
411 uint64_t conntrack_allowance_exceeded;
413 /* The number of packets shaped due to linklocal packet rate
414 * allowance being exceeded
416 uint64_t linklocal_allowance_exceeded;
419 struct ena_admin_acq_get_stats_resp {
420 struct ena_admin_acq_common_desc acq_common_desc;
425 struct ena_admin_basic_stats basic_stats;
427 struct ena_admin_eni_stats eni_stats;
431 struct ena_admin_get_set_feature_common_desc {
432 /* 1:0 : select - 0x1 - current value; 0x3 - default
438 /* as appears in ena_admin_aq_feature_id */
441 /* The driver specifies the max feature version it supports and the
442 * device responds with the currently supported feature version. The
443 * field is zero based
445 uint8_t feature_version;
450 struct ena_admin_device_attr_feature_desc {
453 uint32_t device_version;
455 /* bitmap of ena_admin_aq_feature_id, which represents supported
456 * subcommands for the set/get feature admin commands.
458 uint32_t supported_features;
462 /* Indicates how many bits are used physical address access. */
463 uint32_t phys_addr_width;
465 /* Indicates how many bits are used virtual address access. */
466 uint32_t virt_addr_width;
468 /* unicast MAC address (in Network byte order) */
471 uint8_t reserved7[2];
476 enum ena_admin_llq_header_location {
477 /* header is in descriptor list */
478 ENA_ADMIN_INLINE_HEADER = 1,
479 /* header in a separate ring, implies 16B descriptor list entry */
480 ENA_ADMIN_HEADER_RING = 2,
483 enum ena_admin_llq_ring_entry_size {
484 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
485 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
486 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
489 enum ena_admin_llq_num_descs_before_header {
490 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
491 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
492 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
493 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
494 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
497 /* packet descriptor list entry always starts with one or more descriptors,
498 * followed by a header. The rest of the descriptors are located in the
499 * beginning of the subsequent entry. Stride refers to how the rest of the
500 * descriptors are placed. This field is relevant only for inline header
503 enum ena_admin_llq_stride_ctrl {
504 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
505 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
508 enum ena_admin_accel_mode_feat {
509 ENA_ADMIN_DISABLE_META_CACHING = 0,
510 ENA_ADMIN_LIMIT_TX_BURST = 1,
513 struct ena_admin_accel_mode_get {
514 /* bit field of enum ena_admin_accel_mode_feat */
515 uint16_t supported_flags;
517 /* maximum burst size between two doorbells. The size is in bytes */
518 uint16_t max_tx_burst_size;
521 struct ena_admin_accel_mode_set {
522 /* bit field of enum ena_admin_accel_mode_feat */
523 uint16_t enabled_flags;
528 struct ena_admin_accel_mode_req {
532 struct ena_admin_accel_mode_get get;
534 struct ena_admin_accel_mode_set set;
538 struct ena_admin_feature_llq_desc {
539 uint32_t max_llq_num;
541 uint32_t max_llq_depth;
543 /* specify the header locations the device supports. bitfield of enum
544 * ena_admin_llq_header_location.
546 uint16_t header_location_ctrl_supported;
548 /* the header location the driver selected to use. */
549 uint16_t header_location_ctrl_enabled;
551 /* if inline header is specified - this is the size of descriptor list
552 * entry. If header in a separate ring is specified - this is the size
553 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
554 * specify the entry sizes the device supports
556 uint16_t entry_size_ctrl_supported;
558 /* the entry size the driver selected to use. */
559 uint16_t entry_size_ctrl_enabled;
561 /* valid only if inline header is specified. First entry associated with
562 * the packet includes descriptors and header. Rest of the entries
563 * occupied by descriptors. This parameter defines the max number of
564 * descriptors precedding the header in the first entry. The field is
565 * bitfield of enum ena_admin_llq_num_descs_before_header and specify
566 * the values the device supports
568 uint16_t desc_num_before_header_supported;
570 /* the desire field the driver selected to use */
571 uint16_t desc_num_before_header_enabled;
573 /* valid only if inline was chosen. bitfield of enum
574 * ena_admin_llq_stride_ctrl
576 uint16_t descriptors_stride_ctrl_supported;
578 /* the stride control the driver selected to use */
579 uint16_t descriptors_stride_ctrl_enabled;
584 /* accelerated low latency queues requirement. driver needs to
585 * support those requirements in order to use accelerated llq
587 struct ena_admin_accel_mode_req accel_mode;
590 struct ena_admin_queue_ext_feature_fields {
591 uint32_t max_tx_sq_num;
593 uint32_t max_tx_cq_num;
595 uint32_t max_rx_sq_num;
597 uint32_t max_rx_cq_num;
599 uint32_t max_tx_sq_depth;
601 uint32_t max_tx_cq_depth;
603 uint32_t max_rx_sq_depth;
605 uint32_t max_rx_cq_depth;
607 uint32_t max_tx_header_size;
609 /* Maximum Descriptors number, including meta descriptor, allowed for a
612 uint16_t max_per_packet_tx_descs;
614 /* Maximum Descriptors number allowed for a single Rx packet */
615 uint16_t max_per_packet_rx_descs;
618 struct ena_admin_queue_feature_desc {
621 uint32_t max_sq_depth;
625 uint32_t max_cq_depth;
627 uint32_t max_legacy_llq_num;
629 uint32_t max_legacy_llq_depth;
631 uint32_t max_header_size;
633 /* Maximum Descriptors number, including meta descriptor, allowed for a
636 uint16_t max_packet_tx_descs;
638 /* Maximum Descriptors number allowed for a single Rx packet */
639 uint16_t max_packet_rx_descs;
642 struct ena_admin_set_feature_mtu_desc {
647 struct ena_admin_get_extra_properties_strings_desc {
651 struct ena_admin_get_extra_properties_flags_desc {
655 struct ena_admin_set_feature_host_attr_desc {
656 /* host OS info base address in OS memory. host info is 4KB of
657 * physically contiguous
659 struct ena_common_mem_addr os_info_ba;
661 /* host debug area base address in OS memory. debug area must be
662 * physically contiguous
664 struct ena_common_mem_addr debug_ba;
666 /* debug area size */
667 uint32_t debug_area_size;
670 struct ena_admin_feature_intr_moder_desc {
671 /* interrupt delay granularity in usec */
672 uint16_t intr_delay_resolution;
677 struct ena_admin_get_feature_link_desc {
678 /* Link speed in Mb */
681 /* bit field of enum ena_admin_link types */
685 * 1 : duplex - Full Duplex
691 struct ena_admin_feature_aenq_desc {
692 /* bitmask for AENQ groups the device can report */
693 uint32_t supported_groups;
695 /* bitmask for AENQ groups to report */
696 uint32_t enabled_groups;
699 struct ena_admin_feature_offload_desc {
700 /* 0 : TX_L3_csum_ipv4
701 * 1 : TX_L4_ipv4_csum_part - The checksum field
702 * should be initialized with pseudo header checksum
703 * 2 : TX_L4_ipv4_csum_full
704 * 3 : TX_L4_ipv6_csum_part - The checksum field
705 * should be initialized with pseudo header checksum
706 * 4 : TX_L4_ipv6_csum_full
713 /* Receive side supported stateless offload
714 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
715 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
716 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
717 * 3 : RX_hash - Hash calculation
719 uint32_t rx_supported;
724 enum ena_admin_hash_functions {
725 ENA_ADMIN_TOEPLITZ = 1,
729 struct ena_admin_feature_rss_flow_hash_control {
734 uint32_t key[ENA_ADMIN_RSS_KEY_PARTS];
737 struct ena_admin_feature_rss_flow_hash_function {
738 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
739 uint32_t supported_func;
741 /* 7:0 : selected_func - bitmask of
742 * ena_admin_hash_functions
744 uint32_t selected_func;
750 /* RSS flow hash protocols */
751 enum ena_admin_flow_hash_proto {
752 ENA_ADMIN_RSS_TCP4 = 0,
753 ENA_ADMIN_RSS_UDP4 = 1,
754 ENA_ADMIN_RSS_TCP6 = 2,
755 ENA_ADMIN_RSS_UDP6 = 3,
756 ENA_ADMIN_RSS_IP4 = 4,
757 ENA_ADMIN_RSS_IP6 = 5,
758 ENA_ADMIN_RSS_IP4_FRAG = 6,
759 ENA_ADMIN_RSS_NOT_IP = 7,
760 /* TCPv6 with extension header */
761 ENA_ADMIN_RSS_TCP6_EX = 8,
762 /* IPv6 with extension header */
763 ENA_ADMIN_RSS_IP6_EX = 9,
764 ENA_ADMIN_RSS_PROTO_NUM = 16,
767 /* RSS flow hash fields */
768 enum ena_admin_flow_hash_fields {
769 /* Ethernet Dest Addr */
770 ENA_ADMIN_RSS_L2_DA = BIT(0),
771 /* Ethernet Src Addr */
772 ENA_ADMIN_RSS_L2_SA = BIT(1),
773 /* ipv4/6 Dest Addr */
774 ENA_ADMIN_RSS_L3_DA = BIT(2),
775 /* ipv4/6 Src Addr */
776 ENA_ADMIN_RSS_L3_SA = BIT(3),
777 /* tcp/udp Dest Port */
778 ENA_ADMIN_RSS_L4_DP = BIT(4),
779 /* tcp/udp Src Port */
780 ENA_ADMIN_RSS_L4_SP = BIT(5),
783 struct ena_admin_proto_input {
784 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
790 struct ena_admin_feature_rss_hash_control {
791 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
793 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
795 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
797 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
800 struct ena_admin_feature_rss_flow_hash_input {
801 /* supported hash input sorting
802 * 1 : L3_sort - support swap L3 addresses if DA is
804 * 2 : L4_sort - support swap L4 ports if DP smaller
807 uint16_t supported_input_sort;
809 /* enabled hash input sorting
810 * 1 : enable_L3_sort - enable swap L3 addresses if
812 * 2 : enable_L4_sort - enable swap L4 ports if DP
815 uint16_t enabled_input_sort;
818 enum ena_admin_os_type {
819 ENA_ADMIN_OS_LINUX = 1,
820 ENA_ADMIN_OS_WIN = 2,
821 ENA_ADMIN_OS_DPDK = 3,
822 ENA_ADMIN_OS_FREEBSD = 4,
823 ENA_ADMIN_OS_IPXE = 5,
824 ENA_ADMIN_OS_ESXI = 6,
825 ENA_ADMIN_OS_GROUPS_NUM = 6,
828 struct ena_admin_host_info {
829 /* defined in enum ena_admin_os_type */
832 /* os distribution string format */
833 uint8_t os_dist_str[128];
835 /* OS distribution numeric format */
838 /* kernel version string format */
839 uint8_t kernel_ver_str[32];
841 /* Kernel version numeric format */
847 * 31:24 : module_type
849 uint32_t driver_version;
851 /* features bitmap */
852 uint32_t supported_network_features[2];
854 /* ENA spec version of driver */
855 uint16_t ena_spec_version;
857 /* ENA device's Bus, Device and Function
869 /* 0 : mutable_rss_table_size
871 * 2 : interrupt_moderation
872 * 3 : rx_buf_mirroring
873 * 4 : rss_configurable_function_key
876 uint32_t driver_supported_features;
879 struct ena_admin_rss_ind_table_entry {
885 struct ena_admin_feature_rss_ind_table {
886 /* min supported table size (2^min_size) */
889 /* max supported table size (2^max_size) */
892 /* table size (2^size) */
895 /* 0 : one_entry_update - The ENA device supports
896 * setting a single RSS table entry
902 /* index of the inline entry. 0xFFFFFFFF means invalid */
903 uint32_t inline_index;
905 /* used for updating single entry, ignored when setting the entire
906 * table through the control buffer.
908 struct ena_admin_rss_ind_table_entry inline_entry;
911 /* When hint value is 0, driver should use it's own predefined value */
912 struct ena_admin_ena_hw_hints {
914 uint16_t mmio_read_timeout;
917 uint16_t driver_watchdog_timeout;
919 /* Per packet tx completion timeout. value in ms */
920 uint16_t missing_tx_completion_timeout;
922 uint16_t missed_tx_completion_count_threshold_to_reset;
925 uint16_t admin_completion_tx_timeout;
927 uint16_t netdev_wd_timeout;
929 uint16_t max_tx_sgl_size;
931 uint16_t max_rx_sgl_size;
933 uint16_t reserved[8];
936 struct ena_admin_get_feat_cmd {
937 struct ena_admin_aq_common_desc aq_common_descriptor;
939 struct ena_admin_ctrl_buff_info control_buffer;
941 struct ena_admin_get_set_feature_common_desc feat_common;
946 struct ena_admin_queue_ext_feature_desc {
950 uint8_t reserved1[3];
953 struct ena_admin_queue_ext_feature_fields max_queue_ext;
959 struct ena_admin_get_feat_resp {
960 struct ena_admin_acq_common_desc acq_common_desc;
965 struct ena_admin_device_attr_feature_desc dev_attr;
967 struct ena_admin_feature_llq_desc llq;
969 struct ena_admin_queue_feature_desc max_queue;
971 struct ena_admin_queue_ext_feature_desc max_queue_ext;
973 struct ena_admin_feature_aenq_desc aenq;
975 struct ena_admin_get_feature_link_desc link;
977 struct ena_admin_feature_offload_desc offload;
979 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
981 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
983 struct ena_admin_feature_rss_ind_table ind_table;
985 struct ena_admin_feature_intr_moder_desc intr_moderation;
987 struct ena_admin_ena_hw_hints hw_hints;
989 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
991 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
995 struct ena_admin_set_feat_cmd {
996 struct ena_admin_aq_common_desc aq_common_descriptor;
998 struct ena_admin_ctrl_buff_info control_buffer;
1000 struct ena_admin_get_set_feature_common_desc feat_common;
1006 struct ena_admin_set_feature_mtu_desc mtu;
1008 /* host attributes */
1009 struct ena_admin_set_feature_host_attr_desc host_attr;
1011 /* AENQ configuration */
1012 struct ena_admin_feature_aenq_desc aenq;
1014 /* rss flow hash function */
1015 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1017 /* rss flow hash input */
1018 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1020 /* rss indirection table */
1021 struct ena_admin_feature_rss_ind_table ind_table;
1023 /* LLQ configuration */
1024 struct ena_admin_feature_llq_desc llq;
1028 struct ena_admin_set_feat_resp {
1029 struct ena_admin_acq_common_desc acq_common_desc;
1036 struct ena_admin_aenq_common_desc {
1042 * 7:1 : reserved - MBZ
1046 uint8_t reserved1[3];
1048 uint32_t timestamp_low;
1050 uint32_t timestamp_high;
1053 /* asynchronous event notification groups */
1054 enum ena_admin_aenq_group {
1055 ENA_ADMIN_LINK_CHANGE = 0,
1056 ENA_ADMIN_FATAL_ERROR = 1,
1057 ENA_ADMIN_WARNING = 2,
1058 ENA_ADMIN_NOTIFICATION = 3,
1059 ENA_ADMIN_KEEP_ALIVE = 4,
1060 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
1063 enum ena_admin_aenq_notification_syndrome {
1064 ENA_ADMIN_SUSPEND = 0,
1065 ENA_ADMIN_RESUME = 1,
1066 ENA_ADMIN_UPDATE_HINTS = 2,
1069 struct ena_admin_aenq_entry {
1070 struct ena_admin_aenq_common_desc aenq_common_desc;
1072 /* command specific inline data */
1073 uint32_t inline_data_w4[12];
1076 struct ena_admin_aenq_link_change_desc {
1077 struct ena_admin_aenq_common_desc aenq_common_desc;
1079 /* 0 : link_status */
1083 struct ena_admin_aenq_keep_alive_desc {
1084 struct ena_admin_aenq_common_desc aenq_common_desc;
1086 uint32_t rx_drops_low;
1088 uint32_t rx_drops_high;
1090 uint32_t tx_drops_low;
1092 uint32_t tx_drops_high;
1095 struct ena_admin_ena_mmio_req_read_less_resp {
1100 /* value is valid when poll is cleared */
1104 /* aq_common_desc */
1105 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1106 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1107 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1108 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1109 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1110 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1113 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1114 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1116 /* acq_common_desc */
1117 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1118 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1120 /* aq_create_sq_cmd */
1121 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1122 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1123 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1124 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1125 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1126 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1128 /* aq_create_cq_cmd */
1129 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1130 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1131 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1133 /* get_set_feature_common_desc */
1134 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1136 /* get_feature_link_desc */
1137 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1138 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1139 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1141 /* feature_offload_desc */
1142 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1143 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1144 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1145 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1146 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1147 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1148 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1149 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1150 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1151 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1152 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1153 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1154 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1155 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1156 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1157 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1158 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1159 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1160 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1161 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1162 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1163 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1165 /* feature_rss_flow_hash_function */
1166 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1167 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1169 /* feature_rss_flow_hash_input */
1170 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1171 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1172 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1173 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1174 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1175 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1176 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1177 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1180 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1181 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1182 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1183 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1184 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1185 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1186 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1187 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1188 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1189 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1190 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1191 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1192 #define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0)
1193 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1194 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1195 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1196 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1197 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
1198 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
1199 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1200 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1202 /* feature_rss_ind_table */
1203 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1205 /* aenq_common_desc */
1206 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1208 /* aenq_link_change_desc */
1209 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1211 #if !defined(DEFS_LINUX_MAINLINE)
1212 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1214 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1217 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1219 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1222 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1224 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1227 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1229 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1232 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1234 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1237 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1239 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1242 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1244 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1247 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1249 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1252 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1254 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1257 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1259 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1262 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1264 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1267 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1269 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1272 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1274 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1277 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1279 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1282 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1284 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1287 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1289 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1292 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1294 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1297 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1299 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1302 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1304 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1307 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1309 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1312 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1314 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1317 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1319 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1322 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1324 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1327 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1329 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1332 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1334 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1337 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1339 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1342 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1344 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1347 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1349 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1352 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1354 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1357 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1359 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1362 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1364 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1367 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1369 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1372 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1374 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1377 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1379 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1382 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1384 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1387 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1389 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1392 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1394 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1397 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1399 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1402 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1404 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1407 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1409 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1412 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1414 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1417 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1419 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1422 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1424 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1427 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1429 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1432 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1434 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1437 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1439 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1442 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1444 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1447 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1449 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1452 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1454 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1457 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1459 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1462 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1464 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1467 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1469 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1472 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1474 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1477 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1479 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1482 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1484 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1487 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1489 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1492 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1494 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1497 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1499 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1502 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1504 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1507 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1509 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1512 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1514 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1517 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1519 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1522 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1524 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1527 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1529 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1532 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1534 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1537 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1539 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1542 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1544 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1547 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1549 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1552 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1554 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1557 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1559 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1562 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1564 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1567 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1569 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1572 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1574 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1577 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1579 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1582 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1584 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1587 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1589 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1592 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1594 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1597 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1599 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1602 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1604 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1607 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1609 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1612 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1614 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1617 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1619 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1622 static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p)
1624 return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1627 static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val)
1629 p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
1632 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1634 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1637 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1639 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1642 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1644 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1647 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1649 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1652 static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p)
1654 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT;
1657 static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val)
1659 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK;
1662 static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p)
1664 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT;
1667 static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val)
1669 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
1672 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1674 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1677 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1679 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1682 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1684 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1687 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1689 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1692 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1694 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1697 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1699 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1702 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1703 #endif /* _ENA_ADMIN_H_ */