4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _ENA_ETH_IO_H_
35 #define _ENA_ETH_IO_H_
37 /* Layer 3 protocol index */
38 enum ena_eth_io_l3_proto_index {
39 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
41 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
43 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
45 ENA_ETH_IO_L3_PROTO_FCOE = 21,
47 ENA_ETH_IO_L3_PROTO_ROCE = 22,
50 /* Layer 4 protocol index */
51 enum ena_eth_io_l4_proto_index {
52 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
54 ENA_ETH_IO_L4_PROTO_TCP = 12,
56 ENA_ETH_IO_L4_PROTO_UDP = 13,
58 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
61 /* ENA IO Queue Tx descriptor */
62 struct ena_eth_io_tx_desc {
64 /* length, request id and control flags
65 * 15:0 : length - Buffer length in bytes, must
66 * include any packet trailers that the ENA supposed
67 * to update like End-to-End CRC, Authentication GMAC
68 * etc. This length must not include the
69 * 'Push_Buffer' length. This length must not include
70 * the 4-byte added in the end for 802.3 Ethernet FCS
71 * 21:16 : req_id_hi - Request ID[15:10]
72 * 22 : reserved22 - MBZ
73 * 23 : meta_desc - MBZ
75 * 25 : reserved1 - MBZ
76 * 26 : first - Indicates first descriptor in
78 * 27 : last - Indicates last descriptor in
80 * 28 : comp_req - Indicates whether completion
81 * should be posted, after packet is transmitted.
82 * Valid only for first descriptor
83 * 30:29 : reserved29 - MBZ
84 * 31 : reserved31 - MBZ
90 * 3:0 : l3_proto_idx - L3 protocol. This field
91 * required when l3_csum_en,l3_csum or tso_en are set.
92 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
93 * DF flags of the IPv4 header is 0. Otherwise must
96 * 7 : tso_en - Enable TSO, For TCP only.
97 * 12:8 : l4_proto_idx - L4 protocol. This field need
98 * to be set when l4_csum_en or tso_en are set.
99 * 13 : l3_csum_en - enable IPv4 header checksum.
100 * 14 : l4_csum_en - enable TCP/UDP checksum.
101 * 15 : ethernet_fcs_dis - when set, the controller
102 * will not append the 802.3 Ethernet Frame Check
103 * Sequence to the packet
105 * 17 : l4_csum_partial - L4 partial checksum. when
106 * set to 0, the ENA calculates the L4 checksum,
107 * where the Destination Address required for the
108 * TCP/UDP pseudo-header is taken from the actual
109 * packet L3 header. when set to 1, the ENA doesn't
110 * calculate the sum of the pseudo-header, instead,
111 * the checksum field of the L4 is used instead. When
112 * TSO enabled, the checksum of the pseudo-header
113 * must not include the tcp length field. L4 partial
114 * checksum should be used for IPv6 packet that
115 * contains Routing Headers.
116 * 20:18 : reserved18 - MBZ
117 * 21 : reserved21 - MBZ
118 * 31:22 : req_id_lo - Request ID[9:0]
122 /* word 2 : Buffer address bits[31:0] */
123 uint32_t buff_addr_lo;
126 /* address high and header size
127 * 15:0 : addr_hi - Buffer Pointer[47:32]
128 * 23:16 : reserved16_w2
129 * 31:24 : header_length - Header length. For Low
130 * Latency Queues, this fields indicates the number
131 * of bytes written to the headers' memory. For
132 * normal queues, if packet is TCP or UDP, and longer
133 * than max_header_size, then this field should be
134 * set to the sum of L4 header offset and L4 header
135 * size(without options), otherwise, this field
136 * should be set to 0. For both modes, this field
137 * must not exceed the max_header_size.
138 * max_header_size value is reported by the Max
139 * Queues Feature descriptor
141 uint32_t buff_addr_hi_hdr_sz;
144 /* ENA IO Queue Tx Meta descriptor */
145 struct ena_eth_io_tx_meta_desc {
147 /* length, request id and control flags
148 * 9:0 : req_id_lo - Request ID[9:0]
149 * 11:10 : reserved10 - MBZ
150 * 12 : reserved12 - MBZ
151 * 13 : reserved13 - MBZ
152 * 14 : ext_valid - if set, offset fields in Word2
153 * are valid Also MSS High in Word 0 and Outer L3
154 * Offset High in WORD 0 and bits [31:24] in Word 3
155 * 15 : word3_valid - If set Crypto Info[23:0] of
158 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
159 * Extended Metadata Descriptor
160 * 21 : meta_store - Store extended metadata in queue
162 * 22 : reserved22 - MBZ
163 * 23 : meta_desc - MBO
165 * 25 : reserved25 - MBZ
166 * 26 : first - Indicates first descriptor in
168 * 27 : last - Indicates last descriptor in
170 * 28 : comp_req - Indicates whether completion
171 * should be posted, after packet is transmitted.
172 * Valid only for first descriptor
173 * 30:29 : reserved29 - MBZ
174 * 31 : reserved31 - MBZ
181 * 31:6 : reserved6 - MBZ
187 * 7:0 : l3_hdr_len - the header length L3 IP header.
188 * 15:8 : l3_hdr_off - the offset of the first byte
189 * in the L3 header from the beginning of the to-be
190 * transmitted packet.
191 * 21:16 : l4_hdr_len_in_words - counts the L4 header
192 * length in words. there is an explicit assumption
193 * that L4 header appears right after L3 header and
194 * L4 offset is based on l3_hdr_off+l3_hdr_len
203 /* ENA IO Queue Tx completions descriptor */
204 struct ena_eth_io_tx_cdesc {
206 /* Request ID[15:0] */
220 /* indicates location of submission queue head */
221 uint16_t sq_head_idx;
224 /* ENA IO Queue Rx descriptor */
225 struct ena_eth_io_rx_desc {
227 /* In bytes. 0 means 64KB */
235 * 1 : reserved1 - MBZ
236 * 2 : first - Indicates first descriptor in
238 * 3 : last - Indicates last descriptor in transaction
240 * 5 : reserved5 - MBO
241 * 7:6 : reserved6 - MBZ
251 /* word 2 : Buffer address bits[31:0] */
252 uint32_t buff_addr_lo;
255 /* Buffer Address bits[47:16] */
256 uint16_t buff_addr_hi;
259 uint16_t reserved16_w3;
262 /* ENA IO Queue Rx Completion Base Descriptor (4-word format). Note: all
263 * ethernet parsing information are valid only when last=1
265 struct ena_eth_io_rx_cdesc_base {
267 /* 4:0 : l3_proto_idx - L3 protocol index
268 * 6:5 : src_vlan_cnt - Source VLAN count
269 * 7 : reserved7 - MBZ
270 * 12:8 : l4_proto_idx - L4 protocol index
271 * 13 : l3_csum_err - when set, either the L3
272 * checksum error detected, or, the controller didn't
273 * validate the checksum. This bit is valid only when
274 * l3_proto_idx indicates IPv4 packet
275 * 14 : l4_csum_err - when set, either the L4
276 * checksum error detected, or, the controller didn't
277 * validate the checksum. This bit is valid only when
278 * l4_proto_idx indicates TCP/UDP packet, and,
279 * ipv4_frag is not set
280 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
283 * 25 : l3_csum2 - second checksum engine result
284 * 26 : first - Indicates first descriptor in
286 * 27 : last - Indicates last descriptor in
289 * 30 : buffer - 0: Metadata descriptor. 1: Buffer
290 * Descriptor was used
300 /* word 2 : 32-bit hash result */
304 /* submission queue number */
310 /* ENA IO Queue Rx Completion Descriptor (8-word format) */
311 struct ena_eth_io_rx_cdesc_ext {
312 /* words 0:3 : Rx Completion Extended */
313 struct ena_eth_io_rx_cdesc_base base;
315 /* word 4 : Completed Buffer address bits[31:0] */
316 uint32_t buff_addr_lo;
319 /* the buffer address used bits[47:32] */
320 uint16_t buff_addr_hi;
324 /* word 6 : Reserved */
325 uint32_t reserved_w6;
327 /* word 7 : Reserved */
328 uint32_t reserved_w7;
331 /* ENA Interrupt Unmask Register */
332 struct ena_eth_io_intr_reg {
334 /* 14:0 : rx_intr_delay - rx interrupt delay value
335 * 29:15 : tx_intr_delay - tx interrupt delay value
336 * 30 : intr_unmask - if set, unmasks interrupt
339 uint32_t intr_control;
342 /* ENA NUMA Node configuration register */
343 struct ena_eth_io_numa_node_cfg_reg {
353 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
354 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
355 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
356 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
357 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
358 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
359 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
360 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
361 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
362 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
363 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
364 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
365 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
366 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
367 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
368 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
369 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
370 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
371 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
372 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
373 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
374 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
375 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
376 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
377 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
378 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
379 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
380 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
381 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
382 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
383 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
384 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
385 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
388 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
389 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
390 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
391 #define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT 15
392 #define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK BIT(15)
393 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT 16
394 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK GENMASK(19, 16)
395 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
396 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
397 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
398 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
399 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
400 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
401 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
402 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
403 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
404 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
405 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
406 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
407 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
408 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
409 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
410 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
411 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
412 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
413 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
414 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
415 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
416 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
419 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
422 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
423 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
424 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
425 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
426 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
427 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
428 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
431 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
432 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
433 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
434 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
435 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
436 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
437 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
438 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
439 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
440 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
441 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
442 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
443 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
444 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
445 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
446 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
447 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
448 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
449 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
450 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
451 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
454 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
455 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
456 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
457 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
458 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
460 /* numa_node_cfg_reg */
461 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
462 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
463 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
465 #if !defined(ENA_DEFS_LINUX_MAINLINE)
466 static inline uint32_t get_ena_eth_io_tx_desc_length(
467 const struct ena_eth_io_tx_desc *p)
469 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
472 static inline void set_ena_eth_io_tx_desc_length(
473 struct ena_eth_io_tx_desc *p,
476 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
479 static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(
480 const struct ena_eth_io_tx_desc *p)
482 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK)
483 >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;
486 static inline void set_ena_eth_io_tx_desc_req_id_hi(
487 struct ena_eth_io_tx_desc *p,
491 (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT)
492 & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
495 static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(
496 const struct ena_eth_io_tx_desc *p)
498 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK)
499 >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;
502 static inline void set_ena_eth_io_tx_desc_meta_desc(
503 struct ena_eth_io_tx_desc *p,
507 (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT)
508 & ENA_ETH_IO_TX_DESC_META_DESC_MASK;
511 static inline uint32_t get_ena_eth_io_tx_desc_phase(
512 const struct ena_eth_io_tx_desc *p)
514 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK)
515 >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;
518 static inline void set_ena_eth_io_tx_desc_phase(
519 struct ena_eth_io_tx_desc *p,
523 (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT)
524 & ENA_ETH_IO_TX_DESC_PHASE_MASK;
527 static inline uint32_t get_ena_eth_io_tx_desc_first(
528 const struct ena_eth_io_tx_desc *p)
530 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK)
531 >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;
534 static inline void set_ena_eth_io_tx_desc_first(
535 struct ena_eth_io_tx_desc *p,
539 (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT)
540 & ENA_ETH_IO_TX_DESC_FIRST_MASK;
543 static inline uint32_t get_ena_eth_io_tx_desc_last(
544 const struct ena_eth_io_tx_desc *p)
546 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK)
547 >> ENA_ETH_IO_TX_DESC_LAST_SHIFT;
550 static inline void set_ena_eth_io_tx_desc_last(
551 struct ena_eth_io_tx_desc *p,
555 (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT)
556 & ENA_ETH_IO_TX_DESC_LAST_MASK;
559 static inline uint32_t get_ena_eth_io_tx_desc_comp_req(
560 const struct ena_eth_io_tx_desc *p)
562 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK)
563 >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;
566 static inline void set_ena_eth_io_tx_desc_comp_req(
567 struct ena_eth_io_tx_desc *p,
571 (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT)
572 & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
575 static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(
576 const struct ena_eth_io_tx_desc *p)
578 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
581 static inline void set_ena_eth_io_tx_desc_l3_proto_idx(
582 struct ena_eth_io_tx_desc *p,
585 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
588 static inline uint32_t get_ena_eth_io_tx_desc_DF(
589 const struct ena_eth_io_tx_desc *p)
591 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK)
592 >> ENA_ETH_IO_TX_DESC_DF_SHIFT;
595 static inline void set_ena_eth_io_tx_desc_DF(
596 struct ena_eth_io_tx_desc *p,
600 (val << ENA_ETH_IO_TX_DESC_DF_SHIFT)
601 & ENA_ETH_IO_TX_DESC_DF_MASK;
604 static inline uint32_t get_ena_eth_io_tx_desc_tso_en(
605 const struct ena_eth_io_tx_desc *p)
607 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK)
608 >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;
611 static inline void set_ena_eth_io_tx_desc_tso_en(
612 struct ena_eth_io_tx_desc *p,
616 (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT)
617 & ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
620 static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(
621 const struct ena_eth_io_tx_desc *p)
623 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK)
624 >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;
627 static inline void set_ena_eth_io_tx_desc_l4_proto_idx(
628 struct ena_eth_io_tx_desc *p,
632 (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT)
633 & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
636 static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(
637 const struct ena_eth_io_tx_desc *p)
639 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK)
640 >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;
643 static inline void set_ena_eth_io_tx_desc_l3_csum_en(
644 struct ena_eth_io_tx_desc *p,
648 (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT)
649 & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
652 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(
653 const struct ena_eth_io_tx_desc *p)
655 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK)
656 >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;
659 static inline void set_ena_eth_io_tx_desc_l4_csum_en(
660 struct ena_eth_io_tx_desc *p,
664 (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT)
665 & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
668 static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(
669 const struct ena_eth_io_tx_desc *p)
671 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK)
672 >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;
675 static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(
676 struct ena_eth_io_tx_desc *p,
680 (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT)
681 & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;
684 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(
685 const struct ena_eth_io_tx_desc *p)
687 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK)
688 >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;
691 static inline void set_ena_eth_io_tx_desc_l4_csum_partial(
692 struct ena_eth_io_tx_desc *p,
696 (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT)
697 & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
700 static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(
701 const struct ena_eth_io_tx_desc *p)
703 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK)
704 >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;
707 static inline void set_ena_eth_io_tx_desc_req_id_lo(
708 struct ena_eth_io_tx_desc *p, uint32_t val)
710 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)
711 & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
714 static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(
715 const struct ena_eth_io_tx_desc *p)
717 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
720 static inline void set_ena_eth_io_tx_desc_addr_hi(
721 struct ena_eth_io_tx_desc *p,
724 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
727 static inline uint32_t get_ena_eth_io_tx_desc_header_length(
728 const struct ena_eth_io_tx_desc *p)
730 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK)
731 >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;
734 static inline void set_ena_eth_io_tx_desc_header_length(
735 struct ena_eth_io_tx_desc *p,
738 p->buff_addr_hi_hdr_sz |=
739 (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT)
740 & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
743 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(
744 const struct ena_eth_io_tx_meta_desc *p)
746 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
749 static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(
750 struct ena_eth_io_tx_meta_desc *p,
753 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
756 static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(
757 const struct ena_eth_io_tx_meta_desc *p)
759 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK)
760 >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;
763 static inline void set_ena_eth_io_tx_meta_desc_ext_valid(
764 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
766 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)
767 & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
770 static inline uint32_t get_ena_eth_io_tx_meta_desc_word3_valid(
771 const struct ena_eth_io_tx_meta_desc *p)
773 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK)
774 >> ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT;
777 static inline void set_ena_eth_io_tx_meta_desc_word3_valid(
778 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
780 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)
781 & ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK;
784 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi_ptp(
785 const struct ena_eth_io_tx_meta_desc *p)
787 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK)
788 >> ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT;
791 static inline void set_ena_eth_io_tx_meta_desc_mss_hi_ptp(
792 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
794 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)
795 & ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;
798 static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(
799 const struct ena_eth_io_tx_meta_desc *p)
801 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK)
802 >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;
805 static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(
806 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
808 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)
809 & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
812 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(
813 const struct ena_eth_io_tx_meta_desc *p)
815 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK)
816 >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;
819 static inline void set_ena_eth_io_tx_meta_desc_meta_store(
820 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
822 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)
823 & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
826 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(
827 const struct ena_eth_io_tx_meta_desc *p)
829 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK)
830 >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;
833 static inline void set_ena_eth_io_tx_meta_desc_meta_desc(
834 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
836 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)
837 & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
840 static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(
841 const struct ena_eth_io_tx_meta_desc *p)
843 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK)
844 >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;
847 static inline void set_ena_eth_io_tx_meta_desc_phase(
848 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
850 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)
851 & ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
854 static inline uint32_t get_ena_eth_io_tx_meta_desc_first(
855 const struct ena_eth_io_tx_meta_desc *p)
857 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK)
858 >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;
861 static inline void set_ena_eth_io_tx_meta_desc_first(
862 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
864 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)
865 & ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
868 static inline uint32_t get_ena_eth_io_tx_meta_desc_last(
869 const struct ena_eth_io_tx_meta_desc *p)
871 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK)
872 >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;
875 static inline void set_ena_eth_io_tx_meta_desc_last(
876 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
878 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)
879 & ENA_ETH_IO_TX_META_DESC_LAST_MASK;
882 static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(
883 const struct ena_eth_io_tx_meta_desc *p)
885 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK)
886 >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;
889 static inline void set_ena_eth_io_tx_meta_desc_comp_req(
890 struct ena_eth_io_tx_meta_desc *p, uint32_t val)
892 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)
893 & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
896 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(
897 const struct ena_eth_io_tx_meta_desc *p)
899 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
902 static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(
903 struct ena_eth_io_tx_meta_desc *p,
906 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
909 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(
910 const struct ena_eth_io_tx_meta_desc *p)
912 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
915 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(
916 struct ena_eth_io_tx_meta_desc *p,
919 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
922 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(
923 const struct ena_eth_io_tx_meta_desc *p)
925 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK)
926 >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;
929 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(
930 struct ena_eth_io_tx_meta_desc *p,
934 (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT)
935 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
938 static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(
939 const struct ena_eth_io_tx_meta_desc *p)
941 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK)
942 >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;
945 static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(
946 struct ena_eth_io_tx_meta_desc *p,
950 (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT)
951 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
954 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(
955 const struct ena_eth_io_tx_meta_desc *p)
957 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK)
958 >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;
961 static inline void set_ena_eth_io_tx_meta_desc_mss_lo(
962 struct ena_eth_io_tx_meta_desc *p,
966 (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT)
967 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
970 static inline uint8_t get_ena_eth_io_tx_cdesc_phase(
971 const struct ena_eth_io_tx_cdesc *p)
973 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
976 static inline void set_ena_eth_io_tx_cdesc_phase(
977 struct ena_eth_io_tx_cdesc *p,
980 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
983 static inline uint8_t get_ena_eth_io_rx_desc_phase(
984 const struct ena_eth_io_rx_desc *p)
986 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;
989 static inline void set_ena_eth_io_rx_desc_phase(
990 struct ena_eth_io_rx_desc *p,
993 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK;
996 static inline uint8_t get_ena_eth_io_rx_desc_first(
997 const struct ena_eth_io_rx_desc *p)
999 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK)
1000 >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;
1003 static inline void set_ena_eth_io_rx_desc_first(
1004 struct ena_eth_io_rx_desc *p,
1008 (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT)
1009 & ENA_ETH_IO_RX_DESC_FIRST_MASK;
1012 static inline uint8_t get_ena_eth_io_rx_desc_last(
1013 const struct ena_eth_io_rx_desc *p)
1015 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK)
1016 >> ENA_ETH_IO_RX_DESC_LAST_SHIFT;
1019 static inline void set_ena_eth_io_rx_desc_last(
1020 struct ena_eth_io_rx_desc *p,
1024 (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT)
1025 & ENA_ETH_IO_RX_DESC_LAST_MASK;
1028 static inline uint8_t get_ena_eth_io_rx_desc_comp_req(
1029 const struct ena_eth_io_rx_desc *p)
1031 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK)
1032 >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;
1035 static inline void set_ena_eth_io_rx_desc_comp_req(
1036 struct ena_eth_io_rx_desc *p,
1040 (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT)
1041 & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
1044 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(
1045 const struct ena_eth_io_rx_cdesc_base *p)
1047 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
1050 static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(
1051 struct ena_eth_io_rx_cdesc_base *p,
1054 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
1057 static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(
1058 const struct ena_eth_io_rx_cdesc_base *p)
1060 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK)
1061 >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;
1064 static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(
1065 struct ena_eth_io_rx_cdesc_base *p,
1069 (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT)
1070 & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
1073 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(
1074 const struct ena_eth_io_rx_cdesc_base *p)
1076 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK)
1077 >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
1080 static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(
1081 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1083 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)
1084 & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
1087 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(
1088 const struct ena_eth_io_rx_cdesc_base *p)
1090 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK)
1091 >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
1094 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(
1095 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1097 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)
1098 & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
1101 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(
1102 const struct ena_eth_io_rx_cdesc_base *p)
1104 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK)
1105 >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;
1108 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(
1109 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1111 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)
1112 & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
1115 static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(
1116 const struct ena_eth_io_rx_cdesc_base *p)
1118 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK)
1119 >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
1122 static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(
1123 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1125 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)
1126 & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
1129 static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(
1130 const struct ena_eth_io_rx_cdesc_base *p)
1132 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK)
1133 >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
1136 static inline void set_ena_eth_io_rx_cdesc_base_phase(
1137 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1139 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)
1140 & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
1143 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(
1144 const struct ena_eth_io_rx_cdesc_base *p)
1146 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK)
1147 >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;
1150 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(
1151 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1153 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)
1154 & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
1157 static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(
1158 const struct ena_eth_io_rx_cdesc_base *p)
1160 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK)
1161 >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;
1164 static inline void set_ena_eth_io_rx_cdesc_base_first(
1165 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1167 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)
1168 & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
1171 static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(
1172 const struct ena_eth_io_rx_cdesc_base *p)
1174 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK)
1175 >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
1178 static inline void set_ena_eth_io_rx_cdesc_base_last(
1179 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1181 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)
1182 & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
1185 static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(
1186 const struct ena_eth_io_rx_cdesc_base *p)
1188 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK)
1189 >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;
1192 static inline void set_ena_eth_io_rx_cdesc_base_buffer(
1193 struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
1195 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)
1196 & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
1199 static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(
1200 const struct ena_eth_io_intr_reg *p)
1202 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1205 static inline void set_ena_eth_io_intr_reg_rx_intr_delay(
1206 struct ena_eth_io_intr_reg *p, uint32_t val)
1208 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1211 static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(
1212 const struct ena_eth_io_intr_reg *p)
1214 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK)
1215 >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;
1218 static inline void set_ena_eth_io_intr_reg_tx_intr_delay(
1219 struct ena_eth_io_intr_reg *p, uint32_t val)
1221 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
1222 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
1225 static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(
1226 const struct ena_eth_io_intr_reg *p)
1228 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK)
1229 >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;
1232 static inline void set_ena_eth_io_intr_reg_intr_unmask(
1233 struct ena_eth_io_intr_reg *p, uint32_t val)
1235 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)
1236 & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
1239 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(
1240 const struct ena_eth_io_numa_node_cfg_reg *p)
1242 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
1245 static inline void set_ena_eth_io_numa_node_cfg_reg_numa(
1246 struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
1248 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
1251 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(
1252 const struct ena_eth_io_numa_node_cfg_reg *p)
1254 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK)
1255 >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
1258 static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(
1259 struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
1261 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT)
1262 & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
1265 #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
1266 #endif /*_ENA_ETH_IO_H_ */