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36 enum ena_regs_reset_reason_types {
37 ENA_REGS_RESET_NORMAL = 0,
38 ENA_REGS_RESET_KEEP_ALIVE_TO = 1,
39 ENA_REGS_RESET_ADMIN_TO = 2,
40 ENA_REGS_RESET_MISS_TX_CMPL = 3,
41 ENA_REGS_RESET_INV_RX_REQ_ID = 4,
42 ENA_REGS_RESET_INV_TX_REQ_ID = 5,
43 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6,
44 ENA_REGS_RESET_INIT_ERR = 7,
45 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8,
46 ENA_REGS_RESET_OS_TRIGGER = 9,
47 ENA_REGS_RESET_OS_NETDEV_WD = 10,
48 ENA_REGS_RESET_SHUTDOWN = 11,
49 ENA_REGS_RESET_USER_TRIGGER = 12,
50 ENA_REGS_RESET_GENERIC = 13,
51 ENA_REGS_RESET_MISS_INTERRUPT = 14,
54 /* ena_registers offsets */
57 #define ENA_REGS_VERSION_OFF 0x0
58 #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
59 #define ENA_REGS_CAPS_OFF 0x8
60 #define ENA_REGS_CAPS_EXT_OFF 0xc
61 #define ENA_REGS_AQ_BASE_LO_OFF 0x10
62 #define ENA_REGS_AQ_BASE_HI_OFF 0x14
63 #define ENA_REGS_AQ_CAPS_OFF 0x18
64 #define ENA_REGS_ACQ_BASE_LO_OFF 0x20
65 #define ENA_REGS_ACQ_BASE_HI_OFF 0x24
66 #define ENA_REGS_ACQ_CAPS_OFF 0x28
67 #define ENA_REGS_AQ_DB_OFF 0x2c
68 #define ENA_REGS_ACQ_TAIL_OFF 0x30
69 #define ENA_REGS_AENQ_CAPS_OFF 0x34
70 #define ENA_REGS_AENQ_BASE_LO_OFF 0x38
71 #define ENA_REGS_AENQ_BASE_HI_OFF 0x3c
72 #define ENA_REGS_AENQ_HEAD_DB_OFF 0x40
73 #define ENA_REGS_AENQ_TAIL_OFF 0x44
74 #define ENA_REGS_INTR_MASK_OFF 0x4c
75 #define ENA_REGS_DEV_CTL_OFF 0x54
76 #define ENA_REGS_DEV_STS_OFF 0x58
77 #define ENA_REGS_MMIO_REG_READ_OFF 0x5c
78 #define ENA_REGS_MMIO_RESP_LO_OFF 0x60
79 #define ENA_REGS_MMIO_RESP_HI_OFF 0x64
80 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68
82 /* version register */
83 #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff
84 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8
85 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
87 /* controller_version register */
88 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
89 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8
90 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
91 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16
92 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
93 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24
94 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
97 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
98 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1
99 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
100 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
101 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
102 #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
103 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
105 /* aq_caps register */
106 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
107 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16
108 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
110 /* acq_caps register */
111 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
112 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16
113 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000
115 /* aenq_caps register */
116 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
117 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16
118 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000
120 /* dev_ctl register */
121 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
122 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1
123 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
124 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2
125 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
126 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3
127 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
128 #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28
129 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
131 /* dev_sts register */
132 #define ENA_REGS_DEV_STS_READY_MASK 0x1
133 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1
134 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
135 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2
136 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
137 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3
138 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
139 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4
140 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
141 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5
142 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
143 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6
144 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40
145 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7
146 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80
148 /* mmio_reg_read register */
149 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
150 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16
151 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
153 /* rss_ind_entry_update register */
154 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff
155 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16
156 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000
158 #endif /*_ENA_REGS_H_ */