drivers/net/ena/base/ena_defs/ena_regs_defs.h

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #ifndef _ENA_REGS_H_
  35 #define _ENA_REGS_H_
  36
  37 /* ena_registers offsets */
  38 #define ENA_REGS_VERSION_OFF            0x0
  39 #define ENA_REGS_CONTROLLER_VERSION_OFF         0x4
  40 #define ENA_REGS_CAPS_OFF               0x8
  41 #define ENA_REGS_CAPS_EXT_OFF           0xc
  42 #define ENA_REGS_AQ_BASE_LO_OFF         0x10
  43 #define ENA_REGS_AQ_BASE_HI_OFF         0x14
  44 #define ENA_REGS_AQ_CAPS_OFF            0x18
  45 #define ENA_REGS_ACQ_BASE_LO_OFF                0x20
  46 #define ENA_REGS_ACQ_BASE_HI_OFF                0x24
  47 #define ENA_REGS_ACQ_CAPS_OFF           0x28
  48 #define ENA_REGS_AQ_DB_OFF              0x2c
  49 #define ENA_REGS_ACQ_TAIL_OFF           0x30
  50 #define ENA_REGS_AENQ_CAPS_OFF          0x34
  51 #define ENA_REGS_AENQ_BASE_LO_OFF               0x38
  52 #define ENA_REGS_AENQ_BASE_HI_OFF               0x3c
  53 #define ENA_REGS_AENQ_HEAD_DB_OFF               0x40
  54 #define ENA_REGS_AENQ_TAIL_OFF          0x44
  55 #define ENA_REGS_INTR_MASK_OFF          0x4c
  56 #define ENA_REGS_DEV_CTL_OFF            0x54
  57 #define ENA_REGS_DEV_STS_OFF            0x58
  58 #define ENA_REGS_MMIO_REG_READ_OFF              0x5c
  59 #define ENA_REGS_MMIO_RESP_LO_OFF               0x60
  60 #define ENA_REGS_MMIO_RESP_HI_OFF               0x64
  61 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF               0x68
  62
  63 /* version register */
  64 #define ENA_REGS_VERSION_MINOR_VERSION_MASK             0xff
  65 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT            8
  66 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK             0xff00
  67
  68 /* controller_version register */
  69 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK               0xff
  70 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT         8
  71 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK          0xff00
  72 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT         16
  73 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK          0xff0000
  74 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT               24
  75 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK                0xff000000
  76
  77 /* caps register */
  78 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK            0x1
  79 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT               1
  80 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                0x3e
  81 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT              8
  82 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK               0xff00
  83
  84 /* aq_caps register */
  85 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK          0xffff
  86 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT            16
  87 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK             0xffff0000
  88
  89 /* acq_caps register */
  90 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                0xffff
  91 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT          16
  92 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK           0xffff0000
  93
  94 /* aenq_caps register */
  95 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK              0xffff
  96 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT                16
  97 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK         0xffff0000
  98
  99 /* dev_ctl register */
 100 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK         0x1
 101 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT               1
 102 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                0x2
 103 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                2
 104 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK         0x4
 105 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                3
 106 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK         0x8
 107
 108 /* dev_sts register */
 109 #define ENA_REGS_DEV_STS_READY_MASK             0x1
 110 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT           1
 111 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK            0x2
 112 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT              2
 113 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK               0x4
 114 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT                3
 115 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK         0x8
 116 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT           4
 117 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK            0x10
 118 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT              5
 119 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK               0x20
 120 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT              6
 121 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK               0x40
 122 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT         7
 123 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK          0x80
 124
 125 /* mmio_reg_read register */
 126 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK              0xffff
 127 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT            16
 128 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK             0xffff0000
 129
 130 /* rss_ind_entry_update register */
 131 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK                0xffff
 132 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT              16
 133 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK               0xffff0000
 134
 135 #endif /*_ENA_REGS_H_ */