1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include "ena_eth_com.h"
8 static struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(
9 struct ena_com_io_cq *io_cq)
11 struct ena_eth_io_rx_cdesc_base *cdesc;
12 u16 expected_phase, head_masked;
15 head_masked = io_cq->head & (io_cq->q_depth - 1);
16 expected_phase = io_cq->phase;
18 cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr
19 + (head_masked * io_cq->cdesc_entry_size_in_bytes));
21 desc_phase = (READ_ONCE32(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>
22 ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
24 if (desc_phase != expected_phase)
27 /* Make sure we read the rest of the descriptor after the phase bit
35 static void *get_sq_desc_regular_queue(struct ena_com_io_sq *io_sq)
40 tail_masked = io_sq->tail & (io_sq->q_depth - 1);
42 offset = tail_masked * io_sq->desc_entry_size;
44 return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset);
47 static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,
50 struct ena_com_llq_info *llq_info = &io_sq->llq_info;
55 dst_tail_mask = io_sq->tail & (io_sq->q_depth - 1);
56 dst_offset = dst_tail_mask * llq_info->desc_list_entry_size;
58 if (is_llq_max_tx_burst_exists(io_sq)) {
59 if (unlikely(!io_sq->entries_in_tx_burst_left)) {
60 ena_trc_err("Error: trying to send more packets than tx burst allows\n");
61 return ENA_COM_NO_SPACE;
64 io_sq->entries_in_tx_burst_left--;
65 ena_trc_dbg("decreasing entries_in_tx_burst_left of queue %d to %d\n",
66 io_sq->qid, io_sq->entries_in_tx_burst_left);
69 /* Make sure everything was written into the bounce buffer before
70 * writing the bounce buffer to the device
74 /* The line is completed. Copy it to dev */
75 ENA_MEMCPY_TO_DEVICE_64(io_sq->desc_addr.pbuf_dev_addr + dst_offset,
77 llq_info->desc_list_entry_size);
81 /* Switch phase bit in case of wrap around */
82 if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
88 static int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq,
92 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
93 struct ena_com_llq_info *llq_info = &io_sq->llq_info;
94 u8 *bounce_buffer = pkt_ctrl->curr_bounce_buf;
97 if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST))
101 llq_info->descs_num_before_header * io_sq->desc_entry_size;
103 if (unlikely((header_offset + header_len) > llq_info->desc_list_entry_size)) {
104 ena_trc_err("trying to write header larger than llq entry can accommodate\n");
105 return ENA_COM_FAULT;
108 if (unlikely(!bounce_buffer)) {
109 ena_trc_err("bounce buffer is NULL\n");
110 return ENA_COM_FAULT;
113 memcpy(bounce_buffer + header_offset, header_src, header_len);
118 static void *get_sq_desc_llq(struct ena_com_io_sq *io_sq)
120 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
124 bounce_buffer = pkt_ctrl->curr_bounce_buf;
126 if (unlikely(!bounce_buffer)) {
127 ena_trc_err("bounce buffer is NULL\n");
131 sq_desc = bounce_buffer + pkt_ctrl->idx * io_sq->desc_entry_size;
133 pkt_ctrl->descs_left_in_line--;
138 static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)
140 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
141 struct ena_com_llq_info *llq_info = &io_sq->llq_info;
144 if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST))
147 /* bounce buffer was used, so write it and get a new one */
149 rc = ena_com_write_bounce_buffer_to_dev(io_sq,
150 pkt_ctrl->curr_bounce_buf);
152 ena_trc_err("failed to write bounce buffer to device\n");
156 pkt_ctrl->curr_bounce_buf =
157 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
158 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
159 0x0, llq_info->desc_list_entry_size);
163 pkt_ctrl->descs_left_in_line = llq_info->descs_num_before_header;
167 static void *get_sq_desc(struct ena_com_io_sq *io_sq)
169 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
170 return get_sq_desc_llq(io_sq);
172 return get_sq_desc_regular_queue(io_sq);
175 static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)
177 struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
178 struct ena_com_llq_info *llq_info = &io_sq->llq_info;
181 if (!pkt_ctrl->descs_left_in_line) {
182 rc = ena_com_write_bounce_buffer_to_dev(io_sq,
183 pkt_ctrl->curr_bounce_buf);
185 ena_trc_err("failed to write bounce buffer to device\n");
189 pkt_ctrl->curr_bounce_buf =
190 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
191 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
192 0x0, llq_info->desc_list_entry_size);
195 if (unlikely(llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY))
196 pkt_ctrl->descs_left_in_line = 1;
198 pkt_ctrl->descs_left_in_line =
199 llq_info->desc_list_entry_size / io_sq->desc_entry_size;
205 static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)
207 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
208 return ena_com_sq_update_llq_tail(io_sq);
212 /* Switch phase bit in case of wrap around */
213 if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
219 static struct ena_eth_io_rx_cdesc_base *
220 ena_com_rx_cdesc_idx_to_ptr(struct ena_com_io_cq *io_cq, u16 idx)
222 idx &= (io_cq->q_depth - 1);
223 return (struct ena_eth_io_rx_cdesc_base *)
224 ((uintptr_t)io_cq->cdesc_addr.virt_addr +
225 idx * io_cq->cdesc_entry_size_in_bytes);
228 static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
229 u16 *first_cdesc_idx)
231 struct ena_eth_io_rx_cdesc_base *cdesc;
232 u16 count = 0, head_masked;
236 cdesc = ena_com_get_next_rx_cdesc(io_cq);
240 ena_com_cq_inc_head(io_cq);
242 last = (READ_ONCE32(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>
243 ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
247 *first_cdesc_idx = io_cq->cur_rx_pkt_cdesc_start_idx;
248 count += io_cq->cur_rx_pkt_cdesc_count;
250 head_masked = io_cq->head & (io_cq->q_depth - 1);
252 io_cq->cur_rx_pkt_cdesc_count = 0;
253 io_cq->cur_rx_pkt_cdesc_start_idx = head_masked;
255 ena_trc_dbg("ena q_id: %d packets were completed. first desc idx %u descs# %d\n",
256 io_cq->qid, *first_cdesc_idx, count);
258 io_cq->cur_rx_pkt_cdesc_count += count;
265 static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
266 struct ena_com_tx_meta *ena_meta)
268 struct ena_eth_io_tx_meta_desc *meta_desc = NULL;
270 meta_desc = get_sq_desc(io_sq);
271 if (unlikely(!meta_desc))
272 return ENA_COM_FAULT;
274 memset(meta_desc, 0x0, sizeof(struct ena_eth_io_tx_meta_desc));
276 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
278 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
280 /* bits 0-9 of the mss */
281 meta_desc->word2 |= ((u32)ena_meta->mss <<
282 ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) &
283 ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
284 /* bits 10-13 of the mss */
285 meta_desc->len_ctrl |= ((ena_meta->mss >> 10) <<
286 ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) &
287 ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
289 /* Extended meta desc */
290 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
291 meta_desc->len_ctrl |= ((u32)io_sq->phase <<
292 ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) &
293 ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
295 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
296 meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
298 meta_desc->word2 |= ena_meta->l3_hdr_len &
299 ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
300 meta_desc->word2 |= (ena_meta->l3_hdr_offset <<
301 ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) &
302 ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
304 meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len <<
305 ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) &
306 ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
308 return ena_com_sq_update_tail(io_sq);
311 static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
312 struct ena_com_tx_ctx *ena_tx_ctx,
315 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
317 /* When disable meta caching is set, don't bother to save the meta and
318 * compare it to the stored version, just create the meta
320 if (io_sq->disable_meta_caching) {
321 if (unlikely(!ena_tx_ctx->meta_valid))
322 return ENA_COM_INVAL;
325 return ena_com_create_meta(io_sq, ena_meta);
326 } else if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) {
328 /* Cache the meta desc */
329 memcpy(&io_sq->cached_tx_meta, ena_meta,
330 sizeof(struct ena_com_tx_meta));
331 return ena_com_create_meta(io_sq, ena_meta);
338 static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
339 struct ena_eth_io_rx_cdesc_base *cdesc)
341 ena_rx_ctx->l3_proto = cdesc->status &
342 ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
343 ena_rx_ctx->l4_proto =
344 (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>
345 ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
346 ena_rx_ctx->l3_csum_err =
347 !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >>
348 ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT);
349 ena_rx_ctx->l4_csum_err =
350 !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >>
351 ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT);
352 ena_rx_ctx->l4_csum_checked =
353 !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >>
354 ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT);
355 ena_rx_ctx->hash = cdesc->hash;
357 (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >>
358 ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
360 ena_trc_dbg("ena_rx_ctx->l3_proto %d ena_rx_ctx->l4_proto %d\nena_rx_ctx->l3_csum_err %d ena_rx_ctx->l4_csum_err %d\nhash frag %d frag: %d cdesc_status: %x\n",
361 ena_rx_ctx->l3_proto,
362 ena_rx_ctx->l4_proto,
363 ena_rx_ctx->l3_csum_err,
364 ena_rx_ctx->l4_csum_err,
370 /*****************************************************************************/
371 /***************************** API **********************************/
372 /*****************************************************************************/
374 int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
375 struct ena_com_tx_ctx *ena_tx_ctx,
378 struct ena_eth_io_tx_desc *desc = NULL;
379 struct ena_com_buf *ena_bufs = ena_tx_ctx->ena_bufs;
380 void *buffer_to_push = ena_tx_ctx->push_header;
381 u16 header_len = ena_tx_ctx->header_len;
382 u16 num_bufs = ena_tx_ctx->num_bufs;
383 u16 start_tail = io_sq->tail;
388 ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX,
391 /* num_bufs +1 for potential meta desc */
392 if (unlikely(!ena_com_sq_have_enough_space(io_sq, num_bufs + 1))) {
393 ena_trc_dbg("Not enough space in the tx queue\n");
394 return ENA_COM_NO_MEM;
397 if (unlikely(header_len > io_sq->tx_max_header_size)) {
398 ena_trc_err("header size is too large %d max header: %d\n",
399 header_len, io_sq->tx_max_header_size);
400 return ENA_COM_INVAL;
403 if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV
404 && !buffer_to_push)) {
405 ena_trc_err("push header wasn't provided on LLQ mode\n");
406 return ENA_COM_INVAL;
409 rc = ena_com_write_header_to_bounce(io_sq, buffer_to_push, header_len);
413 rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx, &have_meta);
415 ena_trc_err("failed to create and store tx meta desc\n");
419 /* If the caller doesn't want to send packets */
420 if (unlikely(!num_bufs && !header_len)) {
421 rc = ena_com_close_bounce_buffer(io_sq);
423 ena_trc_err("failed to write buffers to LLQ\n");
424 *nb_hw_desc = io_sq->tail - start_tail;
428 desc = get_sq_desc(io_sq);
430 return ENA_COM_FAULT;
431 memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
433 /* Set first desc when we don't have meta descriptor */
435 desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK;
437 desc->buff_addr_hi_hdr_sz |= ((u32)header_len <<
438 ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) &
439 ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
440 desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
441 ENA_ETH_IO_TX_DESC_PHASE_MASK;
443 desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
446 desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id <<
447 ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) &
448 ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
450 desc->meta_ctrl |= (ena_tx_ctx->df <<
451 ENA_ETH_IO_TX_DESC_DF_SHIFT) &
452 ENA_ETH_IO_TX_DESC_DF_MASK;
455 desc->len_ctrl |= ((ena_tx_ctx->req_id >> 10) <<
456 ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) &
457 ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
459 if (ena_tx_ctx->meta_valid) {
460 desc->meta_ctrl |= (ena_tx_ctx->tso_enable <<
461 ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) &
462 ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
463 desc->meta_ctrl |= ena_tx_ctx->l3_proto &
464 ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
465 desc->meta_ctrl |= (ena_tx_ctx->l4_proto <<
466 ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) &
467 ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
468 desc->meta_ctrl |= (ena_tx_ctx->l3_csum_enable <<
469 ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) &
470 ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
471 desc->meta_ctrl |= (ena_tx_ctx->l4_csum_enable <<
472 ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) &
473 ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
474 desc->meta_ctrl |= (ena_tx_ctx->l4_csum_partial <<
475 ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) &
476 ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
479 for (i = 0; i < num_bufs; i++) {
480 /* The first desc share the same desc as the header */
481 if (likely(i != 0)) {
482 rc = ena_com_sq_update_tail(io_sq);
484 ena_trc_err("failed to update sq tail\n");
488 desc = get_sq_desc(io_sq);
490 return ENA_COM_FAULT;
492 memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
494 desc->len_ctrl |= ((u32)io_sq->phase <<
495 ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
496 ENA_ETH_IO_TX_DESC_PHASE_MASK;
499 desc->len_ctrl |= ena_bufs->len &
500 ENA_ETH_IO_TX_DESC_LENGTH_MASK;
502 addr_hi = ((ena_bufs->paddr &
503 GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
505 desc->buff_addr_lo = (u32)ena_bufs->paddr;
506 desc->buff_addr_hi_hdr_sz |= addr_hi &
507 ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
511 /* set the last desc indicator */
512 desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK;
514 rc = ena_com_sq_update_tail(io_sq);
516 ena_trc_err("failed to update sq tail of the last descriptor\n");
520 rc = ena_com_close_bounce_buffer(io_sq);
522 ena_trc_err("failed when closing bounce buffer\n");
524 *nb_hw_desc = io_sq->tail - start_tail;
528 int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
529 struct ena_com_io_sq *io_sq,
530 struct ena_com_rx_ctx *ena_rx_ctx)
532 struct ena_com_rx_buf_info *ena_buf = &ena_rx_ctx->ena_bufs[0];
533 struct ena_eth_io_rx_cdesc_base *cdesc = NULL;
538 ENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
541 nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);
542 if (nb_hw_desc == 0) {
543 ena_rx_ctx->descs = nb_hw_desc;
547 ena_trc_dbg("fetch rx packet: queue %d completed desc: %d\n",
548 io_cq->qid, nb_hw_desc);
550 if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) {
551 ena_trc_err("Too many RX cdescs (%d) > MAX(%d)\n",
552 nb_hw_desc, ena_rx_ctx->max_bufs);
553 return ENA_COM_NO_SPACE;
556 cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx);
557 ena_rx_ctx->pkt_offset = cdesc->offset;
560 ena_buf[i].len = cdesc->length;
561 ena_buf[i].req_id = cdesc->req_id;
563 if (++i >= nb_hw_desc)
566 cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);
570 /* Update SQ head ptr */
571 io_sq->next_to_comp += nb_hw_desc;
573 ena_trc_dbg("[%s][QID#%d] Updating SQ head to: %d\n", __func__,
574 io_sq->qid, io_sq->next_to_comp);
576 /* Get rx flags from the last pkt */
577 ena_com_rx_set_flags(ena_rx_ctx, cdesc);
579 ena_rx_ctx->descs = nb_hw_desc;
583 int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
584 struct ena_com_buf *ena_buf,
587 struct ena_eth_io_rx_desc *desc;
589 ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
592 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1)))
593 return ENA_COM_NO_SPACE;
595 desc = get_sq_desc(io_sq);
597 return ENA_COM_FAULT;
599 memset(desc, 0x0, sizeof(struct ena_eth_io_rx_desc));
601 desc->length = ena_buf->len;
603 desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |
604 ENA_ETH_IO_RX_DESC_LAST_MASK |
605 (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) |
606 ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
608 desc->req_id = req_id;
610 desc->buff_addr_lo = (u32)ena_buf->paddr;
612 ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
614 return ena_com_sq_update_tail(io_sq);
617 bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)
619 struct ena_eth_io_rx_cdesc_base *cdesc;
621 cdesc = ena_com_get_next_rx_cdesc(io_cq);