4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef ENA_ETH_COM_H_
35 #define ENA_ETH_COM_H_
37 #if defined(__cplusplus)
42 /* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */
43 #define ENA_COMP_HEAD_THRESH 4
45 struct ena_com_tx_ctx {
46 struct ena_com_tx_meta ena_meta;
47 struct ena_com_buf *ena_bufs;
48 /* For LLQ, header buffer - pushed to the device mem space */
51 enum ena_eth_io_l3_proto_index l3_proto;
52 enum ena_eth_io_l4_proto_index l4_proto;
55 /* For regular queue, indicate the size of the header
56 * For LLQ, indicate the size of the pushed buffer
65 u8 df; /* Don't fragment */
68 struct ena_com_rx_ctx {
69 struct ena_com_rx_buf_info *ena_bufs;
70 enum ena_eth_io_l3_proto_index l3_proto;
71 enum ena_eth_io_l4_proto_index l4_proto;
74 /* fragmented packet */
81 int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
82 struct ena_com_tx_ctx *ena_tx_ctx,
85 int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
86 struct ena_com_io_sq *io_sq,
87 struct ena_com_rx_ctx *ena_rx_ctx);
89 int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
90 struct ena_com_buf *ena_buf,
93 int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
95 bool ena_com_cq_empty(struct ena_com_io_cq *io_cq);
97 static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
98 struct ena_eth_io_intr_reg *intr_reg)
100 ENA_REG_WRITE32(io_cq->bus, intr_reg->intr_control, io_cq->unmask_reg);
103 static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)
105 u16 tail, next_to_comp, cnt;
107 next_to_comp = io_sq->next_to_comp;
109 cnt = tail - next_to_comp;
111 return io_sq->q_depth - 1 - cnt;
114 static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
120 ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n",
123 ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
128 static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
130 u16 unreported_comp, head;
134 unreported_comp = head - io_cq->last_head_update;
135 need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
137 if (io_cq->cq_head_db_reg && need_update) {
138 ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n",
140 ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);
141 io_cq->last_head_update = head;
147 static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
150 struct ena_eth_io_numa_node_cfg_reg numa_cfg;
152 if (!io_cq->numa_node_cfg_reg)
155 numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
156 | ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
158 ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
161 static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)
163 io_sq->next_to_comp += elem;
166 #if defined(__cplusplus)
169 #endif /* ENA_ETH_COM_H_ */