drivers/net/ena/base/ena_plat_dpdk.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_
   7 #define DPDK_ENA_COM_ENA_PLAT_DPDK_H_
   8
   9 #include <stdbool.h>
  10 #include <stdlib.h>
  11 #include <pthread.h>
  12 #include <stdint.h>
  13 #include <inttypes.h>
  14 #include <string.h>
  15 #include <errno.h>
  16
  17 #include <rte_atomic.h>
  18 #include <rte_branch_prediction.h>
  19 #include <rte_cycles.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memzone.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_spinlock.h>
  26
  27 #include <sys/time.h>
  28
  29 typedef uint64_t u64;
  30 typedef uint32_t u32;
  31 typedef uint16_t u16;
  32 typedef uint8_t u8;
  33
  34 typedef uint64_t dma_addr_t;
  35 #ifndef ETIME
  36 #define ETIME ETIMEDOUT
  37 #endif
  38
  39 #define ena_atomic32_t rte_atomic32_t
  40 #define ena_mem_handle_t const struct rte_memzone *
  41
  42 #define SZ_256 (256U)
  43 #define SZ_4K (4096U)
  44
  45 #define ENA_COM_OK      0
  46 #define ENA_COM_NO_MEM  -ENOMEM
  47 #define ENA_COM_INVAL   -EINVAL
  48 #define ENA_COM_NO_SPACE        -ENOSPC
  49 #define ENA_COM_NO_DEVICE       -ENODEV
  50 #define ENA_COM_TIMER_EXPIRED   -ETIME
  51 #define ENA_COM_FAULT   -EFAULT
  52 #define ENA_COM_TRY_AGAIN       -EAGAIN
  53 #define ENA_COM_UNSUPPORTED    -EOPNOTSUPP
  54
  55 #define ____cacheline_aligned __rte_cache_aligned
  56
  57 #define ENA_ABORT() abort()
  58
  59 #define ENA_MSLEEP(x) rte_delay_us_sleep(x * 1000)
  60 #define ENA_USLEEP(x) rte_delay_us_sleep(x)
  61 #define ENA_UDELAY(x) rte_delay_us_block(x)
  62
  63 #define ENA_TOUCH(x) ((void)(x))
  64 #define memcpy_toio memcpy
  65 #define wmb rte_wmb
  66 #define rmb rte_rmb
  67 #define mb rte_mb
  68 #define mmiowb rte_io_wmb
  69 #define __iomem
  70
  71 #define US_PER_S 1000000
  72 #define ENA_GET_SYSTEM_USECS()                                          \
  73         (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz())
  74
  75 extern int ena_logtype_com;
  76
  77 #define ENA_MAX_T(type, x, y) RTE_MAX((type)(x), (type)(y))
  78 #define ENA_MAX32(x, y) ENA_MAX_T(uint32_t, (x), (y))
  79 #define ENA_MAX16(x, y) ENA_MAX_T(uint16_t, (x), (y))
  80 #define ENA_MAX8(x, y) ENA_MAX_T(uint8_t, (x), (y))
  81 #define ENA_MIN_T(type, x, y) RTE_MIN((type)(x), (type)(y))
  82 #define ENA_MIN32(x, y) ENA_MIN_T(uint32_t, (x), (y))
  83 #define ENA_MIN16(x, y) ENA_MIN_T(uint16_t, (x), (y))
  84 #define ENA_MIN8(x, y) ENA_MIN_T(uint8_t, (x), (y))
  85
  86 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
  87 #define U64_C(x) x ## ULL
  88 #define BIT(nr)         (1UL << (nr))
  89 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  90 #define GENMASK(h, l)   (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
  91 #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \
  92                           (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
  93
  94 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
  95 #define ena_trc_log(level, fmt, arg...) \
  96         rte_log(RTE_LOG_ ## level, ena_logtype_com, \
  97                 "[ENA_COM: %s]" fmt, __func__, ##arg)
  98
  99 #define ena_trc_dbg(format, arg...)     ena_trc_log(DEBUG, format, ##arg)
 100 #define ena_trc_info(format, arg...)    ena_trc_log(INFO, format, ##arg)
 101 #define ena_trc_warn(format, arg...)    ena_trc_log(WARNING, format, ##arg)
 102 #define ena_trc_err(format, arg...)     ena_trc_log(ERR, format, ##arg)
 103 #else
 104 #define ena_trc_dbg(format, arg...) do { } while (0)
 105 #define ena_trc_info(format, arg...) do { } while (0)
 106 #define ena_trc_warn(format, arg...) do { } while (0)
 107 #define ena_trc_err(format, arg...) do { } while (0)
 108 #endif /* RTE_LIBRTE_ENA_COM_DEBUG */
 109
 110 #define ENA_WARN(cond, format, arg...)                                 \
 111 do {                                                                   \
 112        if (unlikely(cond)) {                                           \
 113                ena_trc_err(                                            \
 114                        "Warn failed on %s:%s:%d:" format,              \
 115                        __FILE__, __func__, __LINE__, ##arg);           \
 116        }                                                               \
 117 } while (0)
 118
 119 /* Spinlock related methods */
 120 #define ena_spinlock_t rte_spinlock_t
 121 #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)
 122 #define ENA_SPINLOCK_LOCK(spinlock, flags)                              \
 123         ({(void)flags; rte_spinlock_lock(&spinlock); })
 124 #define ENA_SPINLOCK_UNLOCK(spinlock, flags)                            \
 125         ({(void)flags; rte_spinlock_unlock(&(spinlock)); })
 126 #define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock)
 127
 128 #define q_waitqueue_t                   \
 129         struct {                        \
 130                 pthread_cond_t cond;    \
 131                 pthread_mutex_t mutex;  \
 132         }
 133
 134 #define ena_wait_queue_t q_waitqueue_t
 135
 136 #define ENA_WAIT_EVENT_INIT(waitqueue)                                  \
 137         do {                                                            \
 138                 pthread_mutex_init(&(waitqueue).mutex, NULL);           \
 139                 pthread_cond_init(&(waitqueue).cond, NULL);             \
 140         } while (0)
 141
 142 #define ENA_WAIT_EVENT_WAIT(waitevent, timeout)                         \
 143         do {                                                            \
 144                 struct timespec wait;                                   \
 145                 struct timeval now;                                     \
 146                 unsigned long timeout_us;                               \
 147                 gettimeofday(&now, NULL);                               \
 148                 wait.tv_sec = now.tv_sec + timeout / 1000000UL;         \
 149                 timeout_us = timeout % 1000000UL;                       \
 150                 wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL;     \
 151                 pthread_mutex_lock(&waitevent.mutex);                   \
 152                 pthread_cond_timedwait(&waitevent.cond,                 \
 153                                 &waitevent.mutex, &wait);               \
 154                 pthread_mutex_unlock(&waitevent.mutex);                 \
 155         } while (0)
 156 #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)
 157 /* pthread condition doesn't need to be rearmed after usage */
 158 #define ENA_WAIT_EVENT_CLEAR(...)
 159 #define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
 160
 161 #define ena_wait_event_t ena_wait_queue_t
 162 #define ENA_MIGHT_SLEEP()
 163
 164 #define ena_time_t uint64_t
 165 #define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())
 166 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                             \
 167        (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
 168
 169 /*
 170  * Each rte_memzone should have unique name.
 171  * To satisfy it, count number of allocations and add it to name.
 172  */
 173 extern rte_atomic32_t ena_alloc_cnt;
 174
 175 #define ENA_MEM_ALLOC_COHERENT_ALIGNED(                                 \
 176         dmadev, size, virt, phys, handle, alignment)                    \
 177         do {                                                            \
 178                 const struct rte_memzone *mz = NULL;                    \
 179                 ENA_TOUCH(dmadev); ENA_TOUCH(handle);                   \
 180                 if (size > 0) {                                         \
 181                         char z_name[RTE_MEMZONE_NAMESIZE];              \
 182                         snprintf(z_name, sizeof(z_name),                \
 183                          "ena_alloc_%d",                                \
 184                          rte_atomic32_add_return(&ena_alloc_cnt, 1));   \
 185                         mz = rte_memzone_reserve_aligned(z_name, size,  \
 186                                         SOCKET_ID_ANY,                  \
 187                                         RTE_MEMZONE_IOVA_CONTIG,        \
 188                                         alignment);                     \
 189                         handle = mz;                                    \
 190                 }                                                       \
 191                 if (mz == NULL) {                                       \
 192                         virt = NULL;                                    \
 193                         phys = 0;                                       \
 194                 } else {                                                \
 195                         memset(mz->addr, 0, size);                      \
 196                         virt = mz->addr;                                \
 197                         phys = mz->iova;                                \
 198                 }                                                       \
 199         } while (0)
 200 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)        \
 201                 ENA_MEM_ALLOC_COHERENT_ALIGNED(                         \
 202                         dmadev,                                         \
 203                         size,                                           \
 204                         virt,                                           \
 205                         phys,                                           \
 206                         handle,                                         \
 207                         RTE_CACHE_LINE_SIZE)
 208 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle)         \
 209                 ({ ENA_TOUCH(size); ENA_TOUCH(phys);                    \
 210                    ENA_TOUCH(dmadev);                                   \
 211                    rte_memzone_free(handle); })
 212
 213 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(                            \
 214         dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \
 215         do {                                                            \
 216                 const struct rte_memzone *mz = NULL;                    \
 217                 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);                 \
 218                 if (size > 0) {                                         \
 219                         char z_name[RTE_MEMZONE_NAMESIZE];              \
 220                         snprintf(z_name, sizeof(z_name),                \
 221                          "ena_alloc_%d",                                \
 222                          rte_atomic32_add_return(&ena_alloc_cnt, 1));   \
 223                         mz = rte_memzone_reserve_aligned(z_name, size, node, \
 224                                 RTE_MEMZONE_IOVA_CONTIG, alignment);    \
 225                         mem_handle = mz;                                \
 226                 }                                                       \
 227                 if (mz == NULL) {                                       \
 228                         virt = NULL;                                    \
 229                         phys = 0;                                       \
 230                 } else {                                                \
 231                         memset(mz->addr, 0, size);                      \
 232                         virt = mz->addr;                                \
 233                         phys = mz->iova;                                \
 234                 }                                                       \
 235         } while (0)
 236 #define ENA_MEM_ALLOC_COHERENT_NODE(                                    \
 237         dmadev, size, virt, phys, mem_handle, node, dev_node)           \
 238                 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(                    \
 239                         dmadev,                                         \
 240                         size,                                           \
 241                         virt,                                           \
 242                         phys,                                           \
 243                         mem_handle,                                     \
 244                         node,                                           \
 245                         dev_node,                                       \
 246                         RTE_CACHE_LINE_SIZE)
 247 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \
 248         do {                                                            \
 249                 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);                 \
 250                 virt = rte_zmalloc_socket(NULL, size, 0, node);         \
 251         } while (0)
 252
 253 #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
 254 #define ENA_MEM_FREE(dmadev, ptr, size)                                 \
 255         ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); })
 256
 257 #define ENA_DB_SYNC(mem_handle) ((void)mem_handle)
 258
 259 #define ENA_REG_WRITE32(bus, value, reg)                                \
 260         ({ (void)(bus); rte_write32((value), (reg)); })
 261 #define ENA_REG_WRITE32_RELAXED(bus, value, reg)                        \
 262         ({ (void)(bus); rte_write32_relaxed((value), (reg)); })
 263 #define ENA_REG_READ32(bus, reg)                                        \
 264         ({ (void)(bus); rte_read32_relaxed((reg)); })
 265
 266 #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
 267 #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
 268 #define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val)
 269 #define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr)
 270
 271 #define msleep(x) rte_delay_us(x * 1000)
 272 #define udelay(x) rte_delay_us(x)
 273
 274 #define dma_rmb() rmb()
 275
 276 #define MAX_ERRNO       4095
 277 #define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO)
 278 #define ERR_PTR(error) ((void *)(long)error)
 279 #define PTR_ERR(error) ((long)(void *)error)
 280 #define might_sleep()
 281
 282 #define prefetch(x) rte_prefetch0(x)
 283 #define prefetchw(x) prefetch(x)
 284
 285 #define lower_32_bits(x) ((uint32_t)(x))
 286 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
 287
 288 #define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())
 289 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                              \
 290     (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
 291 #define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
 292
 293 #ifndef READ_ONCE
 294 #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))
 295 #endif
 296
 297 #define READ_ONCE8(var) READ_ONCE(var)
 298 #define READ_ONCE16(var) READ_ONCE(var)
 299 #define READ_ONCE32(var) READ_ONCE(var)
 300
 301 /* The size must be 8 byte align */
 302 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)                         \
 303         do {                                                            \
 304                 int count, i;                                           \
 305                 uint64_t *to = (uint64_t *)(dst);                       \
 306                 const uint64_t *from = (const uint64_t *)(src);         \
 307                 count = (size) / 8;                                     \
 308                 for (i = 0; i < count; i++, from++, to++)               \
 309                         rte_write64_relaxed(*from, to);                 \
 310         } while(0)
 311
 312 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 313
 314 #define ENA_FFS(x) ffs(x)
 315
 316 void ena_rss_key_fill(void *key, size_t size);
 317
 318 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size)
 319
 320 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0
 321
 322 #define ENA_PRIu64 PRIu64
 323
 324 #include "ena_includes.h"
 325 #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */