4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_
35 #define DPDK_ENA_COM_ENA_PLAT_DPDK_H_
44 #include <rte_atomic.h>
45 #include <rte_branch_prediction.h>
46 #include <rte_cycles.h>
49 #include <rte_malloc.h>
50 #include <rte_memzone.h>
51 #include <rte_prefetch.h>
52 #include <rte_spinlock.h>
61 typedef uint64_t dma_addr_t;
63 #define ETIME ETIMEDOUT
66 #define ena_atomic32_t rte_atomic32_t
67 #define ena_mem_handle_t const struct rte_memzone *
73 #define ENA_COM_NO_MEM -ENOMEM
74 #define ENA_COM_INVAL -EINVAL
75 #define ENA_COM_NO_SPACE -ENOSPC
76 #define ENA_COM_NO_DEVICE -ENODEV
77 #define ENA_COM_TIMER_EXPIRED -ETIME
78 #define ENA_COM_FAULT -EFAULT
79 #define ENA_COM_TRY_AGAIN -EAGAIN
80 #define ENA_COM_UNSUPPORTED -EOPNOTSUPP
82 #define ____cacheline_aligned __rte_cache_aligned
84 #define ENA_ABORT() abort()
86 #define ENA_MSLEEP(x) rte_delay_ms(x)
87 #define ENA_UDELAY(x) rte_delay_us(x)
89 #define ENA_TOUCH(x) ((void)(x))
90 #define memcpy_toio memcpy
94 #define mmiowb rte_io_wmb
97 #define US_PER_S 1000000
98 #define ENA_GET_SYSTEM_USECS() \
99 (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz())
101 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
102 #define ENA_ASSERT(cond, format, arg...) \
104 if (unlikely(!(cond))) { \
105 RTE_LOG(ERR, PMD, format, ##arg); \
106 rte_panic("line %d\tassert \"" #cond "\"" \
107 "failed\n", __LINE__); \
111 #define ENA_ASSERT(cond, format, arg...) do {} while (0)
114 #define ENA_MAX32(x, y) RTE_MAX((x), (y))
115 #define ENA_MAX16(x, y) RTE_MAX((x), (y))
116 #define ENA_MAX8(x, y) RTE_MAX((x), (y))
117 #define ENA_MIN32(x, y) RTE_MIN((x), (y))
118 #define ENA_MIN16(x, y) RTE_MIN((x), (y))
119 #define ENA_MIN8(x, y) RTE_MIN((x), (y))
121 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
122 #define U64_C(x) x ## ULL
123 #define BIT(nr) (1UL << (nr))
124 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
125 #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
126 #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \
127 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
129 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
130 #define ena_trc_dbg(format, arg...) \
131 RTE_LOG(DEBUG, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
132 #define ena_trc_info(format, arg...) \
133 RTE_LOG(INFO, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
134 #define ena_trc_warn(format, arg...) \
135 RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
136 #define ena_trc_err(format, arg...) \
137 RTE_LOG(ERR, PMD, "[ENA_COM: %s] " format, __func__, ##arg)
139 #define ena_trc_dbg(format, arg...) do { } while (0)
140 #define ena_trc_info(format, arg...) do { } while (0)
141 #define ena_trc_warn(format, arg...) do { } while (0)
142 #define ena_trc_err(format, arg...) do { } while (0)
143 #endif /* RTE_LIBRTE_ENA_COM_DEBUG */
145 #define ENA_WARN(cond, format, arg...) \
147 if (unlikely(cond)) { \
149 "Warn failed on %s:%s:%d:" format, \
150 __FILE__, __func__, __LINE__, ##arg); \
154 /* Spinlock related methods */
155 #define ena_spinlock_t rte_spinlock_t
156 #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)
157 #define ENA_SPINLOCK_LOCK(spinlock, flags) \
158 ({(void)flags; rte_spinlock_lock(&spinlock); })
159 #define ENA_SPINLOCK_UNLOCK(spinlock, flags) \
160 ({(void)flags; rte_spinlock_unlock(&(spinlock)); })
161 #define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock)
163 #define q_waitqueue_t \
165 pthread_cond_t cond; \
166 pthread_mutex_t mutex; \
169 #define ena_wait_queue_t q_waitqueue_t
171 #define ENA_WAIT_EVENT_INIT(waitqueue) \
173 pthread_mutex_init(&(waitqueue).mutex, NULL); \
174 pthread_cond_init(&(waitqueue).cond, NULL); \
177 #define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \
179 struct timespec wait; \
180 struct timeval now; \
181 unsigned long timeout_us; \
182 gettimeofday(&now, NULL); \
183 wait.tv_sec = now.tv_sec + timeout / 1000000UL; \
184 timeout_us = timeout % 1000000UL; \
185 wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \
186 pthread_mutex_lock(&waitevent.mutex); \
187 pthread_cond_timedwait(&waitevent.cond, \
188 &waitevent.mutex, &wait); \
189 pthread_mutex_unlock(&waitevent.mutex); \
191 #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)
192 /* pthread condition doesn't need to be rearmed after usage */
193 #define ENA_WAIT_EVENT_CLEAR(...)
194 #define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
196 #define ena_wait_event_t ena_wait_queue_t
197 #define ENA_MIGHT_SLEEP()
199 #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())
200 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \
201 (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
204 * Each rte_memzone should have unique name.
205 * To satisfy it, count number of allocations and add it to name.
207 extern uint32_t ena_alloc_cnt;
209 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \
211 const struct rte_memzone *mz; \
212 char z_name[RTE_MEMZONE_NAMESIZE]; \
213 ENA_TOUCH(dmadev); ENA_TOUCH(handle); \
214 snprintf(z_name, sizeof(z_name), \
215 "ena_alloc_%d", ena_alloc_cnt++); \
216 mz = rte_memzone_reserve(z_name, size, SOCKET_ID_ANY, \
217 RTE_MEMZONE_IOVA_CONTIG); \
223 memset(mz->addr, 0, size); \
228 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \
229 ({ ENA_TOUCH(size); ENA_TOUCH(phys); \
231 rte_memzone_free(handle); })
233 #define ENA_MEM_ALLOC_COHERENT_NODE( \
234 dmadev, size, virt, phys, mem_handle, node, dev_node) \
236 const struct rte_memzone *mz; \
237 char z_name[RTE_MEMZONE_NAMESIZE]; \
238 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \
239 snprintf(z_name, sizeof(z_name), \
240 "ena_alloc_%d", ena_alloc_cnt++); \
241 mz = rte_memzone_reserve(z_name, size, node, \
242 RTE_MEMZONE_IOVA_CONTIG); \
248 memset(mz->addr, 0, size); \
254 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \
256 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \
257 virt = rte_zmalloc_socket(NULL, size, 0, node); \
260 #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
261 #define ENA_MEM_FREE(dmadev, ptr) ({ENA_TOUCH(dmadev); rte_free(ptr); })
263 #define ENA_DB_SYNC(mem_handle) ((void)mem_handle)
265 #define ENA_REG_WRITE32(bus, value, reg) \
266 ({ (void)(bus); rte_write32((value), (reg)); })
267 #define ENA_REG_WRITE32_RELAXED(bus, value, reg) \
268 ({ (void)(bus); rte_write32_relaxed((value), (reg)); })
269 #define ENA_REG_READ32(bus, reg) \
270 ({ (void)(bus); rte_read32_relaxed((reg)); })
272 #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
273 #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
274 #define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val)
275 #define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr)
277 #define msleep(x) rte_delay_us(x * 1000)
278 #define udelay(x) rte_delay_us(x)
280 #define dma_rmb() rmb()
282 #define MAX_ERRNO 4095
283 #define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO)
284 #define ERR_PTR(error) ((void *)(long)error)
285 #define PTR_ERR(error) ((long)(void *)error)
286 #define might_sleep()
288 #define prefetch(x) rte_prefetch0(x)
290 #define lower_32_bits(x) ((uint32_t)(x))
291 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
293 #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())
294 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \
295 (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
296 #define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
299 #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))
302 #define READ_ONCE8(var) READ_ONCE(var)
303 #define READ_ONCE16(var) READ_ONCE(var)
304 #define READ_ONCE32(var) READ_ONCE(var)
306 /* The size must be 8 byte align */
307 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \
310 uint64_t *to = (uint64_t *)(dst); \
311 const uint64_t *from = (const uint64_t *)(src); \
312 count = (size) / 8; \
313 for (i = 0; i < count; i++, from++, to++) \
314 rte_write64_relaxed(*from, to); \
317 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
319 #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */