drivers/net/ena/base/ena_plat_dpdk.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef DPDK_ENA_COM_ENA_PLAT_DPDK_H_
   7 #define DPDK_ENA_COM_ENA_PLAT_DPDK_H_
   8
   9 #include <stdbool.h>
  10 #include <stdlib.h>
  11 #include <pthread.h>
  12 #include <stdint.h>
  13 #include <inttypes.h>
  14 #include <string.h>
  15 #include <errno.h>
  16
  17 #include <rte_atomic.h>
  18 #include <rte_branch_prediction.h>
  19 #include <rte_cycles.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memzone.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_spinlock.h>
  26
  27 #include <sys/time.h>
  28 #include <rte_memcpy.h>
  29
  30 typedef uint64_t u64;
  31 typedef uint32_t u32;
  32 typedef uint16_t u16;
  33 typedef uint8_t u8;
  34
  35 typedef struct rte_eth_dev ena_netdev;
  36 typedef uint64_t dma_addr_t;
  37
  38 #ifndef ETIME
  39 #define ETIME ETIMEDOUT
  40 #endif
  41
  42 #define ENA_PRIu64 PRIu64
  43 #define ena_atomic32_t rte_atomic32_t
  44 #define ena_mem_handle_t const struct rte_memzone *
  45
  46 #define SZ_256 (256U)
  47 #define SZ_4K (4096U)
  48
  49 #define ENA_COM_OK      0
  50 #define ENA_COM_NO_MEM  -ENOMEM
  51 #define ENA_COM_INVAL   -EINVAL
  52 #define ENA_COM_NO_SPACE        -ENOSPC
  53 #define ENA_COM_NO_DEVICE       -ENODEV
  54 #define ENA_COM_TIMER_EXPIRED   -ETIME
  55 #define ENA_COM_FAULT   -EFAULT
  56 #define ENA_COM_TRY_AGAIN       -EAGAIN
  57 #define ENA_COM_UNSUPPORTED    -EOPNOTSUPP
  58 #define ENA_COM_EIO    -EIO
  59
  60 #define ____cacheline_aligned __rte_cache_aligned
  61
  62 #define ENA_ABORT() abort()
  63
  64 #define ENA_MSLEEP(x) rte_delay_us_sleep(x * 1000)
  65 #define ENA_USLEEP(x) rte_delay_us_sleep(x)
  66 #define ENA_UDELAY(x) rte_delay_us_block(x)
  67
  68 #define ENA_TOUCH(x) ((void)(x))
  69 /* Avoid nested declaration on arm64, as it may define rte_memcpy as memcpy. */
  70 #if defined(RTE_ARCH_X86)
  71 #undef memcpy
  72 #define memcpy rte_memcpy
  73 #endif
  74 #define wmb rte_wmb
  75 #define rmb rte_rmb
  76 #define mb rte_mb
  77 #define mmiowb rte_io_wmb
  78 #define __iomem
  79
  80 #define US_PER_S 1000000
  81 #define ENA_GET_SYSTEM_USECS()                                                 \
  82         (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz())
  83
  84 extern int ena_logtype_com;
  85
  86 #define ENA_MAX_T(type, x, y) RTE_MAX((type)(x), (type)(y))
  87 #define ENA_MAX32(x, y) ENA_MAX_T(uint32_t, (x), (y))
  88 #define ENA_MAX16(x, y) ENA_MAX_T(uint16_t, (x), (y))
  89 #define ENA_MAX8(x, y) ENA_MAX_T(uint8_t, (x), (y))
  90 #define ENA_MIN_T(type, x, y) RTE_MIN((type)(x), (type)(y))
  91 #define ENA_MIN32(x, y) ENA_MIN_T(uint32_t, (x), (y))
  92 #define ENA_MIN16(x, y) ENA_MIN_T(uint16_t, (x), (y))
  93 #define ENA_MIN8(x, y) ENA_MIN_T(uint8_t, (x), (y))
  94
  95 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
  96 #define U64_C(x) x ## ULL
  97 #define BIT(nr)         (1UL << (nr))
  98 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  99 #define GENMASK(h, l)   (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
 100 #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) &                     \
 101                           (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
 102
 103 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 104 #define ena_trc_log(dev, level, fmt, arg...)                                   \
 105         (                                                                      \
 106                 ENA_TOUCH(dev),                                                \
 107                 rte_log(RTE_LOG_ ## level, ena_logtype_com,                    \
 108                         "[ENA_COM: %s]" fmt, __func__, ##arg)                  \
 109         )
 110
 111 #define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg)
 112 #define ena_trc_info(dev, format, arg...) ena_trc_log(dev, INFO, format, ##arg)
 113 #define ena_trc_warn(dev, format, arg...)                                      \
 114         ena_trc_log(dev, WARNING, format, ##arg)
 115 #define ena_trc_err(dev, format, arg...) ena_trc_log(dev, ERR, format, ##arg)
 116 #else
 117 #define ena_trc_dbg(dev, format, arg...) ENA_TOUCH(dev)
 118 #define ena_trc_info(dev, format, arg...) ENA_TOUCH(dev)
 119 #define ena_trc_warn(dev, format, arg...) ENA_TOUCH(dev)
 120 #define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev)
 121 #endif /* RTE_LIBRTE_ENA_COM_DEBUG */
 122
 123 #define ENA_WARN(cond, dev, format, arg...)                                    \
 124         do {                                                                   \
 125                 if (unlikely(cond)) {                                          \
 126                         ena_trc_err(dev,                                       \
 127                                 "Warn failed on %s:%s:%d:" format,             \
 128                                 __FILE__, __func__, __LINE__, ##arg);          \
 129                 }                                                              \
 130         } while (0)
 131
 132 /* Spinlock related methods */
 133 #define ena_spinlock_t rte_spinlock_t
 134 #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&(spinlock))
 135 #define ENA_SPINLOCK_LOCK(spinlock, flags)                                     \
 136         ({(void)flags; rte_spinlock_lock(&(spinlock)); })
 137 #define ENA_SPINLOCK_UNLOCK(spinlock, flags)                                   \
 138         ({(void)flags; rte_spinlock_unlock(&(spinlock)); })
 139 #define ENA_SPINLOCK_DESTROY(spinlock) ((void)(spinlock))
 140
 141 #define q_waitqueue_t                                                          \
 142         struct {                                                               \
 143                 pthread_cond_t cond;                                           \
 144                 pthread_mutex_t mutex;                                         \
 145         }
 146
 147 #define ena_wait_queue_t q_waitqueue_t
 148
 149 #define ENA_WAIT_EVENT_INIT(waitqueue)                                         \
 150         do {                                                                   \
 151                 pthread_mutex_init(&(waitqueue).mutex, NULL);                  \
 152                 pthread_cond_init(&(waitqueue).cond, NULL);                    \
 153         } while (0)
 154
 155 #define ENA_WAIT_EVENT_WAIT(waitevent, timeout)                                \
 156         do {                                                                   \
 157                 struct timespec wait;                                          \
 158                 struct timeval now;                                            \
 159                 unsigned long timeout_us;                                      \
 160                 gettimeofday(&now, NULL);                                      \
 161                 wait.tv_sec = now.tv_sec + (timeout) / 1000000UL;              \
 162                 timeout_us = (timeout) % 1000000UL;                            \
 163                 wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL;            \
 164                 pthread_mutex_lock(&(waitevent).mutex);                        \
 165                 pthread_cond_timedwait(&(waitevent).cond,                      \
 166                                 &(waitevent).mutex, &wait);                    \
 167                 pthread_mutex_unlock(&(waitevent).mutex);                      \
 168         } while (0)
 169 #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)
 170 /* pthread condition doesn't need to be rearmed after usage */
 171 #define ENA_WAIT_EVENT_CLEAR(...)
 172 #define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
 173
 174 #define ena_wait_event_t ena_wait_queue_t
 175 #define ENA_MIGHT_SLEEP()
 176
 177 #define ena_time_t uint64_t
 178 #define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())
 179 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                                     \
 180         ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
 181
 182 /*
 183  * Each rte_memzone should have unique name.
 184  * To satisfy it, count number of allocations and add it to name.
 185  */
 186 extern rte_atomic64_t ena_alloc_cnt;
 187
 188 #define ENA_MEM_ALLOC_COHERENT_ALIGNED(                                        \
 189         dmadev, size, virt, phys, mem_handle, alignment)                       \
 190         do {                                                                   \
 191                 const struct rte_memzone *mz = NULL;                           \
 192                 ENA_TOUCH(dmadev);                                             \
 193                 if ((size) > 0) {                                              \
 194                         char z_name[RTE_MEMZONE_NAMESIZE];                     \
 195                         snprintf(z_name, sizeof(z_name),                       \
 196                                 "ena_alloc_%" PRIi64 "",                       \
 197                                 rte_atomic64_add_return(&ena_alloc_cnt, 1));   \
 198                         mz = rte_memzone_reserve_aligned(z_name, (size),       \
 199                                         SOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG,\
 200                                         alignment);                            \
 201                         mem_handle = mz;                                       \
 202                 }                                                              \
 203                 if (mz == NULL) {                                              \
 204                         virt = NULL;                                           \
 205                         phys = 0;                                              \
 206                 } else {                                                       \
 207                         memset(mz->addr, 0, (size));                           \
 208                         virt = mz->addr;                                       \
 209                         phys = mz->iova;                                       \
 210                 }                                                              \
 211         } while (0)
 212 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, mem_handle)           \
 213                 ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys,       \
 214                         mem_handle, RTE_CACHE_LINE_SIZE)
 215 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, mem_handle)            \
 216                 ({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev);        \
 217                    rte_memzone_free(mem_handle); })
 218
 219 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(                                   \
 220         dmadev, size, virt, phys, mem_handle, node, dev_node, alignment)       \
 221         do {                                                                   \
 222                 const struct rte_memzone *mz = NULL;                           \
 223                 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);                        \
 224                 if ((size) > 0) {                                              \
 225                         char z_name[RTE_MEMZONE_NAMESIZE];                     \
 226                         snprintf(z_name, sizeof(z_name),                       \
 227                                 "ena_alloc_%" PRIi64 "",                       \
 228                                 rte_atomic64_add_return(&ena_alloc_cnt, 1));   \
 229                         mz = rte_memzone_reserve_aligned(z_name, (size),       \
 230                                 node, RTE_MEMZONE_IOVA_CONTIG, alignment);     \
 231                         mem_handle = mz;                                       \
 232                 }                                                              \
 233                 if (mz == NULL) {                                              \
 234                         virt = NULL;                                           \
 235                         phys = 0;                                              \
 236                 } else {                                                       \
 237                         memset(mz->addr, 0, (size));                           \
 238                         virt = mz->addr;                                       \
 239                         phys = mz->iova;                                       \
 240                 }                                                              \
 241         } while (0)
 242 #define ENA_MEM_ALLOC_COHERENT_NODE(                                           \
 243         dmadev, size, virt, phys, mem_handle, node, dev_node)                  \
 244                 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys,  \
 245                         mem_handle, node, dev_node, RTE_CACHE_LINE_SIZE)
 246 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node)                 \
 247         do {                                                                   \
 248                 ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);                        \
 249                 virt = rte_zmalloc_socket(NULL, size, 0, node);                \
 250         } while (0)
 251
 252 #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
 253 #define ENA_MEM_FREE(dmadev, ptr, size)                                        \
 254         ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); })
 255
 256 #define ENA_DB_SYNC(mem_handle) ((void)mem_handle)
 257
 258 #define ENA_REG_WRITE32(bus, value, reg)                                       \
 259         ({ (void)(bus); rte_write32((value), (reg)); })
 260 #define ENA_REG_WRITE32_RELAXED(bus, value, reg)                               \
 261         ({ (void)(bus); rte_write32_relaxed((value), (reg)); })
 262 #define ENA_REG_READ32(bus, reg)                                               \
 263         ({ (void)(bus); rte_read32_relaxed((reg)); })
 264
 265 #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
 266 #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
 267 #define ATOMIC32_SET(i32_ptr, val) rte_atomic32_set(i32_ptr, val)
 268 #define ATOMIC32_READ(i32_ptr) rte_atomic32_read(i32_ptr)
 269
 270 #define msleep(x) rte_delay_us(x * 1000)
 271 #define udelay(x) rte_delay_us(x)
 272
 273 #define dma_rmb() rmb()
 274
 275 #define MAX_ERRNO       4095
 276 #define IS_ERR(x) (((unsigned long)x) >= (unsigned long)-MAX_ERRNO)
 277 #define ERR_PTR(error) ((void *)(long)error)
 278 #define PTR_ERR(error) ((long)(void *)error)
 279 #define might_sleep()
 280
 281 #define prefetch(x) rte_prefetch0(x)
 282 #define prefetchw(x) rte_prefetch0_write(x)
 283
 284 #define lower_32_bits(x) ((uint32_t)(x))
 285 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
 286
 287 #define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())
 288 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                                     \
 289         ((timeout_us) * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
 290 #define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue))
 291
 292 #ifndef READ_ONCE
 293 #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))
 294 #endif
 295
 296 #define READ_ONCE8(var) READ_ONCE(var)
 297 #define READ_ONCE16(var) READ_ONCE(var)
 298 #define READ_ONCE32(var) READ_ONCE(var)
 299
 300 /* The size must be 8 byte align */
 301 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)                                \
 302         do {                                                                   \
 303                 int count, i;                                                  \
 304                 uint64_t *to = (uint64_t *)(dst);                              \
 305                 const uint64_t *from = (const uint64_t *)(src);                \
 306                 count = (size) / 8;                                            \
 307                 for (i = 0; i < count; i++, from++, to++)                      \
 308                         rte_write64_relaxed(*from, to);                        \
 309         } while(0)
 310
 311 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 312
 313 #define ENA_FFS(x) ffs(x)
 314
 315 void ena_rss_key_fill(void *key, size_t size);
 316
 317 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size)
 318
 319 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0
 320
 321 #include "ena_includes.h"
 322 #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */