drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    1
  31 #define DRV_MODULE_VER_SUBMINOR 0
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 enum ethtool_stringset {
  55         ETH_SS_TEST             = 0,
  56         ETH_SS_STATS,
  57 };
  58
  59 struct ena_stats {
  60         char name[ETH_GSTRING_LEN];
  61         int stat_offset;
  62 };
  63
  64 #define ENA_STAT_ENTRY(stat, stat_type) { \
  65         .name = #stat, \
  66         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  67 }
  68
  69 #define ENA_STAT_RX_ENTRY(stat) \
  70         ENA_STAT_ENTRY(stat, rx)
  71
  72 #define ENA_STAT_TX_ENTRY(stat) \
  73         ENA_STAT_ENTRY(stat, tx)
  74
  75 #define ENA_STAT_ENI_ENTRY(stat) \
  76         ENA_STAT_ENTRY(stat, eni)
  77
  78 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  79         ENA_STAT_ENTRY(stat, dev)
  80
  81 /* Device arguments */
  82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  83
  84 /*
  85  * Each rte_memzone should have unique name.
  86  * To satisfy it, count number of allocation and add it to name.
  87  */
  88 rte_atomic32_t ena_alloc_cnt;
  89
  90 static const struct ena_stats ena_stats_global_strings[] = {
  91         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  92         ENA_STAT_GLOBAL_ENTRY(dev_start),
  93         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  94         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  95 };
  96
  97 static const struct ena_stats ena_stats_eni_strings[] = {
  98         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  99         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
 100         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
 101         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
 102         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
 103 };
 104
 105 static const struct ena_stats ena_stats_tx_strings[] = {
 106         ENA_STAT_TX_ENTRY(cnt),
 107         ENA_STAT_TX_ENTRY(bytes),
 108         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 109         ENA_STAT_TX_ENTRY(linearize),
 110         ENA_STAT_TX_ENTRY(linearize_failed),
 111         ENA_STAT_TX_ENTRY(tx_poll),
 112         ENA_STAT_TX_ENTRY(doorbells),
 113         ENA_STAT_TX_ENTRY(bad_req_id),
 114         ENA_STAT_TX_ENTRY(available_desc),
 115 };
 116
 117 static const struct ena_stats ena_stats_rx_strings[] = {
 118         ENA_STAT_RX_ENTRY(cnt),
 119         ENA_STAT_RX_ENTRY(bytes),
 120         ENA_STAT_RX_ENTRY(refill_partial),
 121         ENA_STAT_RX_ENTRY(bad_csum),
 122         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 123         ENA_STAT_RX_ENTRY(bad_desc_num),
 124         ENA_STAT_RX_ENTRY(bad_req_id),
 125 };
 126
 127 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 128 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 129 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 130 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 131
 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 133                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 134                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 135                         DEV_TX_OFFLOAD_TCP_TSO)
 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 137                        PKT_TX_IP_CKSUM |\
 138                        PKT_TX_TCP_SEG)
 139
 140 /** Vendor ID used by Amazon devices */
 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 142 /** Amazon devices */
 143 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 144 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 145
 146 #define ENA_TX_OFFLOAD_MASK     (\
 147         PKT_TX_L4_MASK |         \
 148         PKT_TX_IPV6 |            \
 149         PKT_TX_IPV4 |            \
 150         PKT_TX_IP_CKSUM |        \
 151         PKT_TX_TCP_SEG)
 152
 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 154         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 155
 156 static const struct rte_pci_id pci_id_ena_map[] = {
 157         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 158         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 159         { .device_id = 0 },
 160 };
 161
 162 static struct ena_aenq_handlers aenq_handlers;
 163
 164 static int ena_device_init(struct ena_com_dev *ena_dev,
 165                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 166                            bool *wd_state);
 167 static int ena_dev_configure(struct rte_eth_dev *dev);
 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 169         struct ena_tx_buffer *tx_info,
 170         struct rte_mbuf *mbuf,
 171         void **push_header,
 172         uint16_t *header_len);
 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 174 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 176                                   uint16_t nb_pkts);
 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 178                 uint16_t nb_pkts);
 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 180                               uint16_t nb_desc, unsigned int socket_id,
 181                               const struct rte_eth_txconf *tx_conf);
 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_rxconf *rx_conf,
 185                               struct rte_mempool *mp);
 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 188                                     struct ena_com_rx_buf_info *ena_bufs,
 189                                     uint32_t descs,
 190                                     uint16_t *next_to_clean,
 191                                     uint8_t offset);
 192 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 193                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 195                                   struct rte_mbuf *mbuf, uint16_t id);
 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 197 static void ena_init_rings(struct ena_adapter *adapter,
 198                            bool disable_meta_caching);
 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200 static int ena_start(struct rte_eth_dev *dev);
 201 static void ena_stop(struct rte_eth_dev *dev);
 202 static void ena_close(struct rte_eth_dev *dev);
 203 static int ena_dev_reset(struct rte_eth_dev *dev);
 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 207 static void ena_rx_queue_release(void *queue);
 208 static void ena_tx_queue_release(void *queue);
 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 211 static int ena_link_update(struct rte_eth_dev *dev,
 212                            int wait_to_complete);
 213 static int ena_create_io_queue(struct ena_ring *ring);
 214 static void ena_queue_stop(struct ena_ring *ring);
 215 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 216                               enum ena_ring_type ring_type);
 217 static int ena_queue_start(struct ena_ring *ring);
 218 static int ena_queue_start_all(struct rte_eth_dev *dev,
 219                                enum ena_ring_type ring_type);
 220 static void ena_stats_restart(struct rte_eth_dev *dev);
 221 static int ena_infos_get(struct rte_eth_dev *dev,
 222                          struct rte_eth_dev_info *dev_info);
 223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 224                                struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                uint16_t reta_size);
 226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 227                               struct rte_eth_rss_reta_entry64 *reta_conf,
 228                               uint16_t reta_size);
 229 static void ena_interrupt_handler_rte(void *cb_arg);
 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 233 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 234                                 struct rte_eth_xstat_name *xstats_names,
 235                                 unsigned int n);
 236 static int ena_xstats_get(struct rte_eth_dev *dev,
 237                           struct rte_eth_xstat *stats,
 238                           unsigned int n);
 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 240                                 const uint64_t *ids,
 241                                 uint64_t *values,
 242                                 unsigned int n);
 243 static int ena_process_bool_devarg(const char *key,
 244                                    const char *value,
 245                                    void *opaque);
 246 static int ena_parse_devargs(struct ena_adapter *adapter,
 247                              struct rte_devargs *devargs);
 248 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 249
 250 static const struct eth_dev_ops ena_dev_ops = {
 251         .dev_configure        = ena_dev_configure,
 252         .dev_infos_get        = ena_infos_get,
 253         .rx_queue_setup       = ena_rx_queue_setup,
 254         .tx_queue_setup       = ena_tx_queue_setup,
 255         .dev_start            = ena_start,
 256         .dev_stop             = ena_stop,
 257         .link_update          = ena_link_update,
 258         .stats_get            = ena_stats_get,
 259         .xstats_get_names     = ena_xstats_get_names,
 260         .xstats_get           = ena_xstats_get,
 261         .xstats_get_by_id     = ena_xstats_get_by_id,
 262         .mtu_set              = ena_mtu_set,
 263         .rx_queue_release     = ena_rx_queue_release,
 264         .tx_queue_release     = ena_tx_queue_release,
 265         .dev_close            = ena_close,
 266         .dev_reset            = ena_dev_reset,
 267         .reta_update          = ena_rss_reta_update,
 268         .reta_query           = ena_rss_reta_query,
 269 };
 270
 271 void ena_rss_key_fill(void *key, size_t size)
 272 {
 273         static bool key_generated;
 274         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 275         size_t i;
 276
 277         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 278
 279         if (!key_generated) {
 280                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 281                         default_key[i] = rte_rand() & 0xff;
 282                 key_generated = true;
 283         }
 284
 285         rte_memcpy(key, default_key, size);
 286 }
 287
 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 289                                        struct ena_com_rx_ctx *ena_rx_ctx)
 290 {
 291         uint64_t ol_flags = 0;
 292         uint32_t packet_type = 0;
 293
 294         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 295                 packet_type |= RTE_PTYPE_L4_TCP;
 296         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 297                 packet_type |= RTE_PTYPE_L4_UDP;
 298
 299         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 300                 packet_type |= RTE_PTYPE_L3_IPV4;
 301         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 302                 packet_type |= RTE_PTYPE_L3_IPV6;
 303
 304         if (!ena_rx_ctx->l4_csum_checked)
 305                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 306         else
 307                 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
 308                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 309                 else
 310                         ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 311
 312         if (unlikely(ena_rx_ctx->l3_csum_err))
 313                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 314
 315         mbuf->ol_flags = ol_flags;
 316         mbuf->packet_type = packet_type;
 317 }
 318
 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 320                                        struct ena_com_tx_ctx *ena_tx_ctx,
 321                                        uint64_t queue_offloads,
 322                                        bool disable_meta_caching)
 323 {
 324         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 325
 326         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 327             (queue_offloads & QUEUE_OFFLOADS)) {
 328                 /* check if TSO is required */
 329                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 330                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 331                         ena_tx_ctx->tso_enable = true;
 332
 333                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 334                 }
 335
 336                 /* check if L3 checksum is needed */
 337                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 338                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 339                         ena_tx_ctx->l3_csum_enable = true;
 340
 341                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 342                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 343                 } else {
 344                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 345
 346                         /* set don't fragment (DF) flag */
 347                         if (mbuf->packet_type &
 348                                 (RTE_PTYPE_L4_NONFRAG
 349                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 350                                 ena_tx_ctx->df = true;
 351                 }
 352
 353                 /* check if L4 checksum is needed */
 354                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 355                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 357                         ena_tx_ctx->l4_csum_enable = true;
 358                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 359                                 PKT_TX_UDP_CKSUM) &&
 360                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 361                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 362                         ena_tx_ctx->l4_csum_enable = true;
 363                 } else {
 364                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 365                         ena_tx_ctx->l4_csum_enable = false;
 366                 }
 367
 368                 ena_meta->mss = mbuf->tso_segsz;
 369                 ena_meta->l3_hdr_len = mbuf->l3_len;
 370                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 371
 372                 ena_tx_ctx->meta_valid = true;
 373         } else if (disable_meta_caching) {
 374                 memset(ena_meta, 0, sizeof(*ena_meta));
 375                 ena_tx_ctx->meta_valid = true;
 376         } else {
 377                 ena_tx_ctx->meta_valid = false;
 378         }
 379 }
 380
 381 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 382 {
 383         if (likely(req_id < rx_ring->ring_size))
 384                 return 0;
 385
 386         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 387
 388         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 389         rx_ring->adapter->trigger_reset = true;
 390         ++rx_ring->rx_stats.bad_req_id;
 391
 392         return -EFAULT;
 393 }
 394
 395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 396 {
 397         struct ena_tx_buffer *tx_info = NULL;
 398
 399         if (likely(req_id < tx_ring->ring_size)) {
 400                 tx_info = &tx_ring->tx_buffer_info[req_id];
 401                 if (likely(tx_info->mbuf))
 402                         return 0;
 403         }
 404
 405         if (tx_info)
 406                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 407         else
 408                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 409
 410         /* Trigger device reset */
 411         ++tx_ring->tx_stats.bad_req_id;
 412         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 413         tx_ring->adapter->trigger_reset = true;
 414         return -EFAULT;
 415 }
 416
 417 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 418 {
 419         struct ena_admin_host_info *host_info;
 420         int rc;
 421
 422         /* Allocate only the host info */
 423         rc = ena_com_allocate_host_info(ena_dev);
 424         if (rc) {
 425                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 426                 return;
 427         }
 428
 429         host_info = ena_dev->host_attr.host_info;
 430
 431         host_info->os_type = ENA_ADMIN_OS_DPDK;
 432         host_info->kernel_ver = RTE_VERSION;
 433         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 434                 sizeof(host_info->kernel_ver_str));
 435         host_info->os_dist = RTE_VERSION;
 436         strlcpy((char *)host_info->os_dist_str, rte_version(),
 437                 sizeof(host_info->os_dist_str));
 438         host_info->driver_version =
 439                 (DRV_MODULE_VER_MAJOR) |
 440                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 441                 (DRV_MODULE_VER_SUBMINOR <<
 442                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 443         host_info->num_cpus = rte_lcore_count();
 444
 445         host_info->driver_supported_features =
 446                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 447
 448         rc = ena_com_set_host_attributes(ena_dev);
 449         if (rc) {
 450                 if (rc == -ENA_COM_UNSUPPORTED)
 451                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 452                 else
 453                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 454
 455                 goto err;
 456         }
 457
 458         return;
 459
 460 err:
 461         ena_com_delete_host_info(ena_dev);
 462 }
 463
 464 /* This function calculates the number of xstats based on the current config */
 465 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 466 {
 467         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 468                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 469                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 470 }
 471
 472 static void ena_config_debug_area(struct ena_adapter *adapter)
 473 {
 474         u32 debug_area_size;
 475         int rc, ss_count;
 476
 477         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 478
 479         /* allocate 32 bytes for each string and 64bit for the value */
 480         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 481
 482         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 483         if (rc) {
 484                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 485                 return;
 486         }
 487
 488         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 489         if (rc) {
 490                 if (rc == -ENA_COM_UNSUPPORTED)
 491                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 492                 else
 493                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 494
 495                 goto err;
 496         }
 497
 498         return;
 499 err:
 500         ena_com_delete_debug_area(&adapter->ena_dev);
 501 }
 502
 503 static void ena_close(struct rte_eth_dev *dev)
 504 {
 505         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 506         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 507         struct ena_adapter *adapter = dev->data->dev_private;
 508
 509         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 510                 ena_stop(dev);
 511         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 512
 513         ena_rx_queue_release_all(dev);
 514         ena_tx_queue_release_all(dev);
 515
 516         rte_free(adapter->drv_stats);
 517         adapter->drv_stats = NULL;
 518
 519         rte_intr_disable(intr_handle);
 520         rte_intr_callback_unregister(intr_handle,
 521                                      ena_interrupt_handler_rte,
 522                                      adapter);
 523
 524         /*
 525          * MAC is not allocated dynamically. Setting NULL should prevent from
 526          * release of the resource in the rte_eth_dev_release_port().
 527          */
 528         dev->data->mac_addrs = NULL;
 529 }
 530
 531 static int
 532 ena_dev_reset(struct rte_eth_dev *dev)
 533 {
 534         int rc = 0;
 535
 536         ena_destroy_device(dev);
 537         rc = eth_ena_dev_init(dev);
 538         if (rc)
 539                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 540
 541         return rc;
 542 }
 543
 544 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 545                                struct rte_eth_rss_reta_entry64 *reta_conf,
 546                                uint16_t reta_size)
 547 {
 548         struct ena_adapter *adapter = dev->data->dev_private;
 549         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 550         int rc, i;
 551         u16 entry_value;
 552         int conf_idx;
 553         int idx;
 554
 555         if ((reta_size == 0) || (reta_conf == NULL))
 556                 return -EINVAL;
 557
 558         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 559                 PMD_DRV_LOG(WARNING,
 560                         "indirection table %d is bigger than supported (%d)\n",
 561                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 562                 return -EINVAL;
 563         }
 564
 565         for (i = 0 ; i < reta_size ; i++) {
 566                 /* each reta_conf is for 64 entries.
 567                  * to support 128 we use 2 conf of 64
 568                  */
 569                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 570                 idx = i % RTE_RETA_GROUP_SIZE;
 571                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 572                         entry_value =
 573                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 574
 575                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 576                                                                i,
 577                                                                entry_value);
 578                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 579                                 PMD_DRV_LOG(ERR,
 580                                         "Cannot fill indirect table\n");
 581                                 return rc;
 582                         }
 583                 }
 584         }
 585
 586         rte_spinlock_lock(&adapter->admin_lock);
 587         rc = ena_com_indirect_table_set(ena_dev);
 588         rte_spinlock_unlock(&adapter->admin_lock);
 589         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 590                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 591                 return rc;
 592         }
 593
 594         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 595                 __func__, reta_size, adapter->rte_dev->data->port_id);
 596
 597         return 0;
 598 }
 599
 600 /* Query redirection table. */
 601 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 602                               struct rte_eth_rss_reta_entry64 *reta_conf,
 603                               uint16_t reta_size)
 604 {
 605         struct ena_adapter *adapter = dev->data->dev_private;
 606         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 607         int rc;
 608         int i;
 609         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 610         int reta_conf_idx;
 611         int reta_idx;
 612
 613         if (reta_size == 0 || reta_conf == NULL ||
 614             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 615                 return -EINVAL;
 616
 617         rte_spinlock_lock(&adapter->admin_lock);
 618         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 619         rte_spinlock_unlock(&adapter->admin_lock);
 620         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 621                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 622                 return -ENOTSUP;
 623         }
 624
 625         for (i = 0 ; i < reta_size ; i++) {
 626                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 627                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 628                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 629                         reta_conf[reta_conf_idx].reta[reta_idx] =
 630                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 631         }
 632
 633         return 0;
 634 }
 635
 636 static int ena_rss_init_default(struct ena_adapter *adapter)
 637 {
 638         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 639         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 640         int rc, i;
 641         u32 val;
 642
 643         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 644         if (unlikely(rc)) {
 645                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 646                 goto err_rss_init;
 647         }
 648
 649         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 650                 val = i % nb_rx_queues;
 651                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 652                                                        ENA_IO_RXQ_IDX(val));
 653                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 654                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 655                         goto err_fill_indir;
 656                 }
 657         }
 658
 659         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 660                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 661         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 662                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 663                 goto err_fill_indir;
 664         }
 665
 666         rc = ena_com_set_default_hash_ctrl(ena_dev);
 667         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 668                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 669                 goto err_fill_indir;
 670         }
 671
 672         rc = ena_com_indirect_table_set(ena_dev);
 673         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 674                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 675                 goto err_fill_indir;
 676         }
 677         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 678                 adapter->rte_dev->data->port_id);
 679
 680         return 0;
 681
 682 err_fill_indir:
 683         ena_com_rss_destroy(ena_dev);
 684 err_rss_init:
 685
 686         return rc;
 687 }
 688
 689 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 690 {
 691         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 692         int nb_queues = dev->data->nb_rx_queues;
 693         int i;
 694
 695         for (i = 0; i < nb_queues; i++)
 696                 ena_rx_queue_release(queues[i]);
 697 }
 698
 699 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 700 {
 701         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 702         int nb_queues = dev->data->nb_tx_queues;
 703         int i;
 704
 705         for (i = 0; i < nb_queues; i++)
 706                 ena_tx_queue_release(queues[i]);
 707 }
 708
 709 static void ena_rx_queue_release(void *queue)
 710 {
 711         struct ena_ring *ring = (struct ena_ring *)queue;
 712
 713         /* Free ring resources */
 714         if (ring->rx_buffer_info)
 715                 rte_free(ring->rx_buffer_info);
 716         ring->rx_buffer_info = NULL;
 717
 718         if (ring->rx_refill_buffer)
 719                 rte_free(ring->rx_refill_buffer);
 720         ring->rx_refill_buffer = NULL;
 721
 722         if (ring->empty_rx_reqs)
 723                 rte_free(ring->empty_rx_reqs);
 724         ring->empty_rx_reqs = NULL;
 725
 726         ring->configured = 0;
 727
 728         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 729                 ring->port_id, ring->id);
 730 }
 731
 732 static void ena_tx_queue_release(void *queue)
 733 {
 734         struct ena_ring *ring = (struct ena_ring *)queue;
 735
 736         /* Free ring resources */
 737         if (ring->push_buf_intermediate_buf)
 738                 rte_free(ring->push_buf_intermediate_buf);
 739
 740         if (ring->tx_buffer_info)
 741                 rte_free(ring->tx_buffer_info);
 742
 743         if (ring->empty_tx_reqs)
 744                 rte_free(ring->empty_tx_reqs);
 745
 746         ring->empty_tx_reqs = NULL;
 747         ring->tx_buffer_info = NULL;
 748         ring->push_buf_intermediate_buf = NULL;
 749
 750         ring->configured = 0;
 751
 752         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 753                 ring->port_id, ring->id);
 754 }
 755
 756 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 757 {
 758         unsigned int i;
 759
 760         for (i = 0; i < ring->ring_size; ++i) {
 761                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 762                 if (rx_info->mbuf) {
 763                         rte_mbuf_raw_free(rx_info->mbuf);
 764                         rx_info->mbuf = NULL;
 765                 }
 766         }
 767 }
 768
 769 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 770 {
 771         unsigned int i;
 772
 773         for (i = 0; i < ring->ring_size; ++i) {
 774                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 775
 776                 if (tx_buf->mbuf)
 777                         rte_pktmbuf_free(tx_buf->mbuf);
 778         }
 779 }
 780
 781 static int ena_link_update(struct rte_eth_dev *dev,
 782                            __rte_unused int wait_to_complete)
 783 {
 784         struct rte_eth_link *link = &dev->data->dev_link;
 785         struct ena_adapter *adapter = dev->data->dev_private;
 786
 787         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 788         link->link_speed = ETH_SPEED_NUM_NONE;
 789         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 790
 791         return 0;
 792 }
 793
 794 static int ena_queue_start_all(struct rte_eth_dev *dev,
 795                                enum ena_ring_type ring_type)
 796 {
 797         struct ena_adapter *adapter = dev->data->dev_private;
 798         struct ena_ring *queues = NULL;
 799         int nb_queues;
 800         int i = 0;
 801         int rc = 0;
 802
 803         if (ring_type == ENA_RING_TYPE_RX) {
 804                 queues = adapter->rx_ring;
 805                 nb_queues = dev->data->nb_rx_queues;
 806         } else {
 807                 queues = adapter->tx_ring;
 808                 nb_queues = dev->data->nb_tx_queues;
 809         }
 810         for (i = 0; i < nb_queues; i++) {
 811                 if (queues[i].configured) {
 812                         if (ring_type == ENA_RING_TYPE_RX) {
 813                                 ena_assert_msg(
 814                                         dev->data->rx_queues[i] == &queues[i],
 815                                         "Inconsistent state of rx queues\n");
 816                         } else {
 817                                 ena_assert_msg(
 818                                         dev->data->tx_queues[i] == &queues[i],
 819                                         "Inconsistent state of tx queues\n");
 820                         }
 821
 822                         rc = ena_queue_start(&queues[i]);
 823
 824                         if (rc) {
 825                                 PMD_INIT_LOG(ERR,
 826                                              "failed to start queue %d type(%d)",
 827                                              i, ring_type);
 828                                 goto err;
 829                         }
 830                 }
 831         }
 832
 833         return 0;
 834
 835 err:
 836         while (i--)
 837                 if (queues[i].configured)
 838                         ena_queue_stop(&queues[i]);
 839
 840         return rc;
 841 }
 842
 843 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 844 {
 845         uint32_t max_frame_len = adapter->max_mtu;
 846
 847         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 848             DEV_RX_OFFLOAD_JUMBO_FRAME)
 849                 max_frame_len =
 850                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 851
 852         return max_frame_len;
 853 }
 854
 855 static int ena_check_valid_conf(struct ena_adapter *adapter)
 856 {
 857         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 858
 859         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 860                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 861                                   "max mtu: %d, min mtu: %d",
 862                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 863                 return ENA_COM_UNSUPPORTED;
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int
 870 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 871                        bool use_large_llq_hdr)
 872 {
 873         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 874         struct ena_com_dev *ena_dev = ctx->ena_dev;
 875         uint32_t max_tx_queue_size;
 876         uint32_t max_rx_queue_size;
 877
 878         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 879                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 880                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 881                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 882                         max_queue_ext->max_rx_sq_depth);
 883                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 884
 885                 if (ena_dev->tx_mem_queue_type ==
 886                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 887                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 888                                 llq->max_llq_depth);
 889                 } else {
 890                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 891                                 max_queue_ext->max_tx_sq_depth);
 892                 }
 893
 894                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 895                         max_queue_ext->max_per_packet_rx_descs);
 896                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 897                         max_queue_ext->max_per_packet_tx_descs);
 898         } else {
 899                 struct ena_admin_queue_feature_desc *max_queues =
 900                         &ctx->get_feat_ctx->max_queues;
 901                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 902                         max_queues->max_sq_depth);
 903                 max_tx_queue_size = max_queues->max_cq_depth;
 904
 905                 if (ena_dev->tx_mem_queue_type ==
 906                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 907                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 908                                 llq->max_llq_depth);
 909                 } else {
 910                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 911                                 max_queues->max_sq_depth);
 912                 }
 913
 914                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 915                         max_queues->max_packet_rx_descs);
 916                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 917                         max_queues->max_packet_tx_descs);
 918         }
 919
 920         /* Round down to the nearest power of 2 */
 921         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 922         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 923
 924         if (use_large_llq_hdr) {
 925                 if ((llq->entry_size_ctrl_supported &
 926                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 927                     (ena_dev->tx_mem_queue_type ==
 928                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 929                         max_tx_queue_size /= 2;
 930                         PMD_INIT_LOG(INFO,
 931                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 932                                 max_tx_queue_size);
 933                 } else {
 934                         PMD_INIT_LOG(ERR,
 935                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 936                 }
 937         }
 938
 939         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 940                 PMD_INIT_LOG(ERR, "Invalid queue size");
 941                 return -EFAULT;
 942         }
 943
 944         ctx->max_tx_queue_size = max_tx_queue_size;
 945         ctx->max_rx_queue_size = max_rx_queue_size;
 946
 947         return 0;
 948 }
 949
 950 static void ena_stats_restart(struct rte_eth_dev *dev)
 951 {
 952         struct ena_adapter *adapter = dev->data->dev_private;
 953
 954         rte_atomic64_init(&adapter->drv_stats->ierrors);
 955         rte_atomic64_init(&adapter->drv_stats->oerrors);
 956         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 957         adapter->drv_stats->rx_drops = 0;
 958 }
 959
 960 static int ena_stats_get(struct rte_eth_dev *dev,
 961                           struct rte_eth_stats *stats)
 962 {
 963         struct ena_admin_basic_stats ena_stats;
 964         struct ena_adapter *adapter = dev->data->dev_private;
 965         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 966         int rc;
 967         int i;
 968         int max_rings_stats;
 969
 970         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 971                 return -ENOTSUP;
 972
 973         memset(&ena_stats, 0, sizeof(ena_stats));
 974
 975         rte_spinlock_lock(&adapter->admin_lock);
 976         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 977         rte_spinlock_unlock(&adapter->admin_lock);
 978         if (unlikely(rc)) {
 979                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 980                 return rc;
 981         }
 982
 983         /* Set of basic statistics from ENA */
 984         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 985                                           ena_stats.rx_pkts_low);
 986         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 987                                           ena_stats.tx_pkts_low);
 988         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 989                                         ena_stats.rx_bytes_low);
 990         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 991                                         ena_stats.tx_bytes_low);
 992
 993         /* Driver related stats */
 994         stats->imissed = adapter->drv_stats->rx_drops;
 995         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 996         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 997         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 998
 999         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1000                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1001         for (i = 0; i < max_rings_stats; ++i) {
1002                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1003
1004                 stats->q_ibytes[i] = rx_stats->bytes;
1005                 stats->q_ipackets[i] = rx_stats->cnt;
1006                 stats->q_errors[i] = rx_stats->bad_desc_num +
1007                         rx_stats->bad_req_id;
1008         }
1009
1010         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1011                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1012         for (i = 0; i < max_rings_stats; ++i) {
1013                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1014
1015                 stats->q_obytes[i] = tx_stats->bytes;
1016                 stats->q_opackets[i] = tx_stats->cnt;
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1023 {
1024         struct ena_adapter *adapter;
1025         struct ena_com_dev *ena_dev;
1026         int rc = 0;
1027
1028         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1029         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1030         adapter = dev->data->dev_private;
1031
1032         ena_dev = &adapter->ena_dev;
1033         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1034
1035         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1036                 PMD_DRV_LOG(ERR,
1037                         "Invalid MTU setting. new_mtu: %d "
1038                         "max mtu: %d min mtu: %d\n",
1039                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1040                 return -EINVAL;
1041         }
1042
1043         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1044         if (rc)
1045                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1046         else
1047                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1048
1049         return rc;
1050 }
1051
1052 static int ena_start(struct rte_eth_dev *dev)
1053 {
1054         struct ena_adapter *adapter = dev->data->dev_private;
1055         uint64_t ticks;
1056         int rc = 0;
1057
1058         rc = ena_check_valid_conf(adapter);
1059         if (rc)
1060                 return rc;
1061
1062         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1063         if (rc)
1064                 return rc;
1065
1066         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1067         if (rc)
1068                 goto err_start_tx;
1069
1070         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1071             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1072                 rc = ena_rss_init_default(adapter);
1073                 if (rc)
1074                         goto err_rss_init;
1075         }
1076
1077         ena_stats_restart(dev);
1078
1079         adapter->timestamp_wd = rte_get_timer_cycles();
1080         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1081
1082         ticks = rte_get_timer_hz();
1083         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1084                         ena_timer_wd_callback, adapter);
1085
1086         ++adapter->dev_stats.dev_start;
1087         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1088
1089         return 0;
1090
1091 err_rss_init:
1092         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1093 err_start_tx:
1094         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1095         return rc;
1096 }
1097
1098 static void ena_stop(struct rte_eth_dev *dev)
1099 {
1100         struct ena_adapter *adapter = dev->data->dev_private;
1101         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1102         int rc;
1103
1104         rte_timer_stop_sync(&adapter->timer_wd);
1105         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1106         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1107
1108         if (adapter->trigger_reset) {
1109                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1110                 if (rc)
1111                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1112         }
1113
1114         ++adapter->dev_stats.dev_stop;
1115         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1116 }
1117
1118 static int ena_create_io_queue(struct ena_ring *ring)
1119 {
1120         struct ena_adapter *adapter;
1121         struct ena_com_dev *ena_dev;
1122         struct ena_com_create_io_ctx ctx =
1123                 /* policy set to _HOST just to satisfy icc compiler */
1124                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1125                   0, 0, 0, 0, 0 };
1126         uint16_t ena_qid;
1127         unsigned int i;
1128         int rc;
1129
1130         adapter = ring->adapter;
1131         ena_dev = &adapter->ena_dev;
1132
1133         if (ring->type == ENA_RING_TYPE_TX) {
1134                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1135                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1136                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1137                 for (i = 0; i < ring->ring_size; i++)
1138                         ring->empty_tx_reqs[i] = i;
1139         } else {
1140                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1141                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1142                 for (i = 0; i < ring->ring_size; i++)
1143                         ring->empty_rx_reqs[i] = i;
1144         }
1145         ctx.queue_size = ring->ring_size;
1146         ctx.qid = ena_qid;
1147         ctx.msix_vector = -1; /* interrupts not used */
1148         ctx.numa_node = ring->numa_socket_id;
1149
1150         rc = ena_com_create_io_queue(ena_dev, &ctx);
1151         if (rc) {
1152                 PMD_DRV_LOG(ERR,
1153                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1154                         ring->id, ena_qid, rc);
1155                 return rc;
1156         }
1157
1158         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1159                                      &ring->ena_com_io_sq,
1160                                      &ring->ena_com_io_cq);
1161         if (rc) {
1162                 PMD_DRV_LOG(ERR,
1163                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1164                         ring->id, rc);
1165                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1166                 return rc;
1167         }
1168
1169         if (ring->type == ENA_RING_TYPE_TX)
1170                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1171
1172         return 0;
1173 }
1174
1175 static void ena_queue_stop(struct ena_ring *ring)
1176 {
1177         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1178
1179         if (ring->type == ENA_RING_TYPE_RX) {
1180                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1181                 ena_rx_queue_release_bufs(ring);
1182         } else {
1183                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1184                 ena_tx_queue_release_bufs(ring);
1185         }
1186 }
1187
1188 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1189                               enum ena_ring_type ring_type)
1190 {
1191         struct ena_adapter *adapter = dev->data->dev_private;
1192         struct ena_ring *queues = NULL;
1193         uint16_t nb_queues, i;
1194
1195         if (ring_type == ENA_RING_TYPE_RX) {
1196                 queues = adapter->rx_ring;
1197                 nb_queues = dev->data->nb_rx_queues;
1198         } else {
1199                 queues = adapter->tx_ring;
1200                 nb_queues = dev->data->nb_tx_queues;
1201         }
1202
1203         for (i = 0; i < nb_queues; ++i)
1204                 if (queues[i].configured)
1205                         ena_queue_stop(&queues[i]);
1206 }
1207
1208 static int ena_queue_start(struct ena_ring *ring)
1209 {
1210         int rc, bufs_num;
1211
1212         ena_assert_msg(ring->configured == 1,
1213                        "Trying to start unconfigured queue\n");
1214
1215         rc = ena_create_io_queue(ring);
1216         if (rc) {
1217                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1218                 return rc;
1219         }
1220
1221         ring->next_to_clean = 0;
1222         ring->next_to_use = 0;
1223
1224         if (ring->type == ENA_RING_TYPE_TX) {
1225                 ring->tx_stats.available_desc =
1226                         ena_com_free_q_entries(ring->ena_com_io_sq);
1227                 return 0;
1228         }
1229
1230         bufs_num = ring->ring_size - 1;
1231         rc = ena_populate_rx_queue(ring, bufs_num);
1232         if (rc != bufs_num) {
1233                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1234                                          ENA_IO_RXQ_IDX(ring->id));
1235                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1236                 return ENA_COM_FAULT;
1237         }
1238
1239         return 0;
1240 }
1241
1242 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1243                               uint16_t queue_idx,
1244                               uint16_t nb_desc,
1245                               unsigned int socket_id,
1246                               const struct rte_eth_txconf *tx_conf)
1247 {
1248         struct ena_ring *txq = NULL;
1249         struct ena_adapter *adapter = dev->data->dev_private;
1250         unsigned int i;
1251
1252         txq = &adapter->tx_ring[queue_idx];
1253
1254         if (txq->configured) {
1255                 PMD_DRV_LOG(CRIT,
1256                         "API violation. Queue %d is already configured\n",
1257                         queue_idx);
1258                 return ENA_COM_FAULT;
1259         }
1260
1261         if (!rte_is_power_of_2(nb_desc)) {
1262                 PMD_DRV_LOG(ERR,
1263                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1264                         nb_desc);
1265                 return -EINVAL;
1266         }
1267
1268         if (nb_desc > adapter->max_tx_ring_size) {
1269                 PMD_DRV_LOG(ERR,
1270                         "Unsupported size of TX queue (max size: %d)\n",
1271                         adapter->max_tx_ring_size);
1272                 return -EINVAL;
1273         }
1274
1275         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1276                 nb_desc = adapter->max_tx_ring_size;
1277
1278         txq->port_id = dev->data->port_id;
1279         txq->next_to_clean = 0;
1280         txq->next_to_use = 0;
1281         txq->ring_size = nb_desc;
1282         txq->size_mask = nb_desc - 1;
1283         txq->numa_socket_id = socket_id;
1284
1285         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1286                                           sizeof(struct ena_tx_buffer) *
1287                                           txq->ring_size,
1288                                           RTE_CACHE_LINE_SIZE);
1289         if (!txq->tx_buffer_info) {
1290                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1291                 return -ENOMEM;
1292         }
1293
1294         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1295                                          sizeof(u16) * txq->ring_size,
1296                                          RTE_CACHE_LINE_SIZE);
1297         if (!txq->empty_tx_reqs) {
1298                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1299                 rte_free(txq->tx_buffer_info);
1300                 return -ENOMEM;
1301         }
1302
1303         txq->push_buf_intermediate_buf =
1304                 rte_zmalloc("txq->push_buf_intermediate_buf",
1305                             txq->tx_max_header_size,
1306                             RTE_CACHE_LINE_SIZE);
1307         if (!txq->push_buf_intermediate_buf) {
1308                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1309                 rte_free(txq->tx_buffer_info);
1310                 rte_free(txq->empty_tx_reqs);
1311                 return -ENOMEM;
1312         }
1313
1314         for (i = 0; i < txq->ring_size; i++)
1315                 txq->empty_tx_reqs[i] = i;
1316
1317         if (tx_conf != NULL) {
1318                 txq->offloads =
1319                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1320         }
1321         /* Store pointer to this queue in upper layer */
1322         txq->configured = 1;
1323         dev->data->tx_queues[queue_idx] = txq;
1324
1325         return 0;
1326 }
1327
1328 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1329                               uint16_t queue_idx,
1330                               uint16_t nb_desc,
1331                               unsigned int socket_id,
1332                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1333                               struct rte_mempool *mp)
1334 {
1335         struct ena_adapter *adapter = dev->data->dev_private;
1336         struct ena_ring *rxq = NULL;
1337         size_t buffer_size;
1338         int i;
1339
1340         rxq = &adapter->rx_ring[queue_idx];
1341         if (rxq->configured) {
1342                 PMD_DRV_LOG(CRIT,
1343                         "API violation. Queue %d is already configured\n",
1344                         queue_idx);
1345                 return ENA_COM_FAULT;
1346         }
1347
1348         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1349                 nb_desc = adapter->max_rx_ring_size;
1350
1351         if (!rte_is_power_of_2(nb_desc)) {
1352                 PMD_DRV_LOG(ERR,
1353                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1354                         nb_desc);
1355                 return -EINVAL;
1356         }
1357
1358         if (nb_desc > adapter->max_rx_ring_size) {
1359                 PMD_DRV_LOG(ERR,
1360                         "Unsupported size of RX queue (max size: %d)\n",
1361                         adapter->max_rx_ring_size);
1362                 return -EINVAL;
1363         }
1364
1365         /* ENA isn't supporting buffers smaller than 1400 bytes */
1366         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1367         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1368                 PMD_DRV_LOG(ERR,
1369                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1370                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1371                 return -EINVAL;
1372         }
1373
1374         rxq->port_id = dev->data->port_id;
1375         rxq->next_to_clean = 0;
1376         rxq->next_to_use = 0;
1377         rxq->ring_size = nb_desc;
1378         rxq->size_mask = nb_desc - 1;
1379         rxq->numa_socket_id = socket_id;
1380         rxq->mb_pool = mp;
1381
1382         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1383                 sizeof(struct ena_rx_buffer) * nb_desc,
1384                 RTE_CACHE_LINE_SIZE);
1385         if (!rxq->rx_buffer_info) {
1386                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1387                 return -ENOMEM;
1388         }
1389
1390         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1391                                             sizeof(struct rte_mbuf *) * nb_desc,
1392                                             RTE_CACHE_LINE_SIZE);
1393
1394         if (!rxq->rx_refill_buffer) {
1395                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1396                 rte_free(rxq->rx_buffer_info);
1397                 rxq->rx_buffer_info = NULL;
1398                 return -ENOMEM;
1399         }
1400
1401         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1402                                          sizeof(uint16_t) * nb_desc,
1403                                          RTE_CACHE_LINE_SIZE);
1404         if (!rxq->empty_rx_reqs) {
1405                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1406                 rte_free(rxq->rx_buffer_info);
1407                 rxq->rx_buffer_info = NULL;
1408                 rte_free(rxq->rx_refill_buffer);
1409                 rxq->rx_refill_buffer = NULL;
1410                 return -ENOMEM;
1411         }
1412
1413         for (i = 0; i < nb_desc; i++)
1414                 rxq->empty_rx_reqs[i] = i;
1415
1416         /* Store pointer to this queue in upper layer */
1417         rxq->configured = 1;
1418         dev->data->rx_queues[queue_idx] = rxq;
1419
1420         return 0;
1421 }
1422
1423 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1424                                   struct rte_mbuf *mbuf, uint16_t id)
1425 {
1426         struct ena_com_buf ebuf;
1427         int rc;
1428
1429         /* prepare physical address for DMA transaction */
1430         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1431         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1432
1433         /* pass resource to device */
1434         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1435         if (unlikely(rc != 0))
1436                 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1437
1438         return rc;
1439 }
1440
1441 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1442 {
1443         unsigned int i;
1444         int rc;
1445         uint16_t next_to_use = rxq->next_to_use;
1446         uint16_t in_use, req_id;
1447         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1448
1449         if (unlikely(!count))
1450                 return 0;
1451
1452         in_use = rxq->ring_size - 1 -
1453                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1454         ena_assert_msg(((in_use + count) < rxq->ring_size),
1455                 "bad ring state\n");
1456
1457         /* get resources for incoming packets */
1458         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1459         if (unlikely(rc < 0)) {
1460                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1461                 ++rxq->rx_stats.mbuf_alloc_fail;
1462                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1463                 return 0;
1464         }
1465
1466         for (i = 0; i < count; i++) {
1467                 struct rte_mbuf *mbuf = mbufs[i];
1468                 struct ena_rx_buffer *rx_info;
1469
1470                 if (likely((i + 4) < count))
1471                         rte_prefetch0(mbufs[i + 4]);
1472
1473                 req_id = rxq->empty_rx_reqs[next_to_use];
1474                 rc = validate_rx_req_id(rxq, req_id);
1475                 if (unlikely(rc))
1476                         break;
1477
1478                 rx_info = &rxq->rx_buffer_info[req_id];
1479
1480                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1481                 if (unlikely(rc != 0))
1482                         break;
1483
1484                 rx_info->mbuf = mbuf;
1485                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1486         }
1487
1488         if (unlikely(i < count)) {
1489                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1490                         "buffers (from %d)\n", rxq->id, i, count);
1491                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1492                                      count - i);
1493                 ++rxq->rx_stats.refill_partial;
1494         }
1495
1496         /* When we submitted free recources to device... */
1497         if (likely(i > 0)) {
1498                 /* ...let HW know that it can fill buffers with data. */
1499                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1500
1501                 rxq->next_to_use = next_to_use;
1502         }
1503
1504         return i;
1505 }
1506
1507 static int ena_device_init(struct ena_com_dev *ena_dev,
1508                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1509                            bool *wd_state)
1510 {
1511         uint32_t aenq_groups;
1512         int rc;
1513         bool readless_supported;
1514
1515         /* Initialize mmio registers */
1516         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1517         if (rc) {
1518                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1519                 return rc;
1520         }
1521
1522         /* The PCIe configuration space revision id indicate if mmio reg
1523          * read is disabled.
1524          */
1525         readless_supported =
1526                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1527                                & ENA_MMIO_DISABLE_REG_READ);
1528         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1529
1530         /* reset device */
1531         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1532         if (rc) {
1533                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1534                 goto err_mmio_read_less;
1535         }
1536
1537         /* check FW version */
1538         rc = ena_com_validate_version(ena_dev);
1539         if (rc) {
1540                 PMD_DRV_LOG(ERR, "device version is too low\n");
1541                 goto err_mmio_read_less;
1542         }
1543
1544         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1545
1546         /* ENA device administration layer init */
1547         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1548         if (rc) {
1549                 PMD_DRV_LOG(ERR,
1550                         "cannot initialize ena admin queue with device\n");
1551                 goto err_mmio_read_less;
1552         }
1553
1554         /* To enable the msix interrupts the driver needs to know the number
1555          * of queues. So the driver uses polling mode to retrieve this
1556          * information.
1557          */
1558         ena_com_set_admin_polling_mode(ena_dev, true);
1559
1560         ena_config_host_info(ena_dev);
1561
1562         /* Get Device Attributes and features */
1563         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1564         if (rc) {
1565                 PMD_DRV_LOG(ERR,
1566                         "cannot get attribute for ena device rc= %d\n", rc);
1567                 goto err_admin_init;
1568         }
1569
1570         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1571                       BIT(ENA_ADMIN_NOTIFICATION) |
1572                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1573                       BIT(ENA_ADMIN_FATAL_ERROR) |
1574                       BIT(ENA_ADMIN_WARNING);
1575
1576         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1577         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1578         if (rc) {
1579                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1580                 goto err_admin_init;
1581         }
1582
1583         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1584
1585         return 0;
1586
1587 err_admin_init:
1588         ena_com_admin_destroy(ena_dev);
1589
1590 err_mmio_read_less:
1591         ena_com_mmio_reg_read_request_destroy(ena_dev);
1592
1593         return rc;
1594 }
1595
1596 static void ena_interrupt_handler_rte(void *cb_arg)
1597 {
1598         struct ena_adapter *adapter = cb_arg;
1599         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1600
1601         ena_com_admin_q_comp_intr_handler(ena_dev);
1602         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1603                 ena_com_aenq_intr_handler(ena_dev, adapter);
1604 }
1605
1606 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1607 {
1608         if (!adapter->wd_state)
1609                 return;
1610
1611         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1612                 return;
1613
1614         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1615             adapter->keep_alive_timeout)) {
1616                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1617                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1618                 adapter->trigger_reset = true;
1619                 ++adapter->dev_stats.wd_expired;
1620         }
1621 }
1622
1623 /* Check if admin queue is enabled */
1624 static void check_for_admin_com_state(struct ena_adapter *adapter)
1625 {
1626         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1627                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1628                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1629                 adapter->trigger_reset = true;
1630         }
1631 }
1632
1633 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1634                                   void *arg)
1635 {
1636         struct ena_adapter *adapter = arg;
1637         struct rte_eth_dev *dev = adapter->rte_dev;
1638
1639         check_for_missing_keep_alive(adapter);
1640         check_for_admin_com_state(adapter);
1641
1642         if (unlikely(adapter->trigger_reset)) {
1643                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1644                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1645                         NULL);
1646         }
1647 }
1648
1649 static inline void
1650 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1651                                struct ena_admin_feature_llq_desc *llq,
1652                                bool use_large_llq_hdr)
1653 {
1654         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1655         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1656         llq_config->llq_num_decs_before_header =
1657                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1658
1659         if (use_large_llq_hdr &&
1660             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1661                 llq_config->llq_ring_entry_size =
1662                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1663                 llq_config->llq_ring_entry_size_value = 256;
1664         } else {
1665                 llq_config->llq_ring_entry_size =
1666                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1667                 llq_config->llq_ring_entry_size_value = 128;
1668         }
1669 }
1670
1671 static int
1672 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1673                                 struct ena_com_dev *ena_dev,
1674                                 struct ena_admin_feature_llq_desc *llq,
1675                                 struct ena_llq_configurations *llq_default_configurations)
1676 {
1677         int rc;
1678         u32 llq_feature_mask;
1679
1680         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1681         if (!(ena_dev->supported_features & llq_feature_mask)) {
1682                 PMD_DRV_LOG(INFO,
1683                         "LLQ is not supported. Fallback to host mode policy.\n");
1684                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1685                 return 0;
1686         }
1687
1688         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1689         if (unlikely(rc)) {
1690                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1691                         "Fallback to host mode policy.");
1692                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1693                 return 0;
1694         }
1695
1696         /* Nothing to config, exit */
1697         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1698                 return 0;
1699
1700         if (!adapter->dev_mem_base) {
1701                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1702                         "Fallback to host mode policy.\n.");
1703                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1704                 return 0;
1705         }
1706
1707         ena_dev->mem_bar = adapter->dev_mem_base;
1708
1709         return 0;
1710 }
1711
1712 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1713         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1714 {
1715         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1716
1717         /* Regular queues capabilities */
1718         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1719                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1720                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1721                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1722                                     max_queue_ext->max_rx_cq_num);
1723                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1724                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1725         } else {
1726                 struct ena_admin_queue_feature_desc *max_queues =
1727                         &get_feat_ctx->max_queues;
1728                 io_tx_sq_num = max_queues->max_sq_num;
1729                 io_tx_cq_num = max_queues->max_cq_num;
1730                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1731         }
1732
1733         /* In case of LLQ use the llq number in the get feature cmd */
1734         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1735                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1736
1737         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1738         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1739         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1740
1741         if (unlikely(max_num_io_queues == 0)) {
1742                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1743                 return -EFAULT;
1744         }
1745
1746         return max_num_io_queues;
1747 }
1748
1749 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1750 {
1751         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1752         struct rte_pci_device *pci_dev;
1753         struct rte_intr_handle *intr_handle;
1754         struct ena_adapter *adapter = eth_dev->data->dev_private;
1755         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1756         struct ena_com_dev_get_features_ctx get_feat_ctx;
1757         struct ena_llq_configurations llq_config;
1758         const char *queue_type_str;
1759         uint32_t max_num_io_queues;
1760         int rc;
1761         static int adapters_found;
1762         bool disable_meta_caching;
1763         bool wd_state = false;
1764
1765         eth_dev->dev_ops = &ena_dev_ops;
1766         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1767         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1768         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1769
1770         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1771                 return 0;
1772
1773         memset(adapter, 0, sizeof(struct ena_adapter));
1774         ena_dev = &adapter->ena_dev;
1775
1776         adapter->rte_eth_dev_data = eth_dev->data;
1777         adapter->rte_dev = eth_dev;
1778
1779         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1780         adapter->pdev = pci_dev;
1781
1782         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1783                      pci_dev->addr.domain,
1784                      pci_dev->addr.bus,
1785                      pci_dev->addr.devid,
1786                      pci_dev->addr.function);
1787
1788         intr_handle = &pci_dev->intr_handle;
1789
1790         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1791         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1792
1793         if (!adapter->regs) {
1794                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1795                              ENA_REGS_BAR);
1796                 return -ENXIO;
1797         }
1798
1799         ena_dev->reg_bar = adapter->regs;
1800         ena_dev->dmadev = adapter->pdev;
1801
1802         adapter->id_number = adapters_found;
1803
1804         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1805                  adapter->id_number);
1806
1807         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1808         if (rc != 0) {
1809                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1810                 goto err;
1811         }
1812
1813         /* device specific initialization routine */
1814         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1815         if (rc) {
1816                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1817                 goto err;
1818         }
1819         adapter->wd_state = wd_state;
1820
1821         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1822                 adapter->use_large_llq_hdr);
1823         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1824                                              &get_feat_ctx.llq, &llq_config);
1825         if (unlikely(rc)) {
1826                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1827                 return rc;
1828         }
1829
1830         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1831                 queue_type_str = "Regular";
1832         else
1833                 queue_type_str = "Low latency";
1834         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1835
1836         calc_queue_ctx.ena_dev = ena_dev;
1837         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1838
1839         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1840         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1841                 adapter->use_large_llq_hdr);
1842         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1843                 rc = -EFAULT;
1844                 goto err_device_destroy;
1845         }
1846
1847         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1848         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1849         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1850         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1851         adapter->max_num_io_queues = max_num_io_queues;
1852
1853         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1854                 disable_meta_caching =
1855                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1856                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1857         } else {
1858                 disable_meta_caching = false;
1859         }
1860
1861         /* prepare ring structures */
1862         ena_init_rings(adapter, disable_meta_caching);
1863
1864         ena_config_debug_area(adapter);
1865
1866         /* Set max MTU for this device */
1867         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1868
1869         /* set device support for offloads */
1870         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1871                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1872         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1873                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1874         adapter->offloads.rx_csum_supported =
1875                 (get_feat_ctx.offload.rx_supported &
1876                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1877
1878         /* Copy MAC address and point DPDK to it */
1879         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1880         rte_ether_addr_copy((struct rte_ether_addr *)
1881                         get_feat_ctx.dev_attr.mac_addr,
1882                         (struct rte_ether_addr *)adapter->mac_addr);
1883
1884         /*
1885          * Pass the information to the rte_eth_dev_close() that it should also
1886          * release the private port resources.
1887          */
1888         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1889
1890         adapter->drv_stats = rte_zmalloc("adapter stats",
1891                                          sizeof(*adapter->drv_stats),
1892                                          RTE_CACHE_LINE_SIZE);
1893         if (!adapter->drv_stats) {
1894                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1895                 rc = -ENOMEM;
1896                 goto err_delete_debug_area;
1897         }
1898
1899         rte_spinlock_init(&adapter->admin_lock);
1900
1901         rte_intr_callback_register(intr_handle,
1902                                    ena_interrupt_handler_rte,
1903                                    adapter);
1904         rte_intr_enable(intr_handle);
1905         ena_com_set_admin_polling_mode(ena_dev, false);
1906         ena_com_admin_aenq_enable(ena_dev);
1907
1908         if (adapters_found == 0)
1909                 rte_timer_subsystem_init();
1910         rte_timer_init(&adapter->timer_wd);
1911
1912         adapters_found++;
1913         adapter->state = ENA_ADAPTER_STATE_INIT;
1914
1915         return 0;
1916
1917 err_delete_debug_area:
1918         ena_com_delete_debug_area(ena_dev);
1919
1920 err_device_destroy:
1921         ena_com_delete_host_info(ena_dev);
1922         ena_com_admin_destroy(ena_dev);
1923
1924 err:
1925         return rc;
1926 }
1927
1928 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1929 {
1930         struct ena_adapter *adapter = eth_dev->data->dev_private;
1931         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1932
1933         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1934                 return;
1935
1936         ena_com_set_admin_running_state(ena_dev, false);
1937
1938         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1939                 ena_close(eth_dev);
1940
1941         ena_com_delete_debug_area(ena_dev);
1942         ena_com_delete_host_info(ena_dev);
1943
1944         ena_com_abort_admin_commands(ena_dev);
1945         ena_com_wait_for_abort_completion(ena_dev);
1946         ena_com_admin_destroy(ena_dev);
1947         ena_com_mmio_reg_read_request_destroy(ena_dev);
1948
1949         adapter->state = ENA_ADAPTER_STATE_FREE;
1950 }
1951
1952 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1953 {
1954         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1955                 return 0;
1956
1957         ena_destroy_device(eth_dev);
1958
1959         eth_dev->dev_ops = NULL;
1960         eth_dev->rx_pkt_burst = NULL;
1961         eth_dev->tx_pkt_burst = NULL;
1962         eth_dev->tx_pkt_prepare = NULL;
1963
1964         return 0;
1965 }
1966
1967 static int ena_dev_configure(struct rte_eth_dev *dev)
1968 {
1969         struct ena_adapter *adapter = dev->data->dev_private;
1970
1971         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1972
1973         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1974         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1975         return 0;
1976 }
1977
1978 static void ena_init_rings(struct ena_adapter *adapter,
1979                            bool disable_meta_caching)
1980 {
1981         size_t i;
1982
1983         for (i = 0; i < adapter->max_num_io_queues; i++) {
1984                 struct ena_ring *ring = &adapter->tx_ring[i];
1985
1986                 ring->configured = 0;
1987                 ring->type = ENA_RING_TYPE_TX;
1988                 ring->adapter = adapter;
1989                 ring->id = i;
1990                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1991                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1992                 ring->sgl_size = adapter->max_tx_sgl_size;
1993                 ring->disable_meta_caching = disable_meta_caching;
1994         }
1995
1996         for (i = 0; i < adapter->max_num_io_queues; i++) {
1997                 struct ena_ring *ring = &adapter->rx_ring[i];
1998
1999                 ring->configured = 0;
2000                 ring->type = ENA_RING_TYPE_RX;
2001                 ring->adapter = adapter;
2002                 ring->id = i;
2003                 ring->sgl_size = adapter->max_rx_sgl_size;
2004         }
2005 }
2006
2007 static int ena_infos_get(struct rte_eth_dev *dev,
2008                           struct rte_eth_dev_info *dev_info)
2009 {
2010         struct ena_adapter *adapter;
2011         struct ena_com_dev *ena_dev;
2012         uint64_t rx_feat = 0, tx_feat = 0;
2013
2014         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2015         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2016         adapter = dev->data->dev_private;
2017
2018         ena_dev = &adapter->ena_dev;
2019         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2020
2021         dev_info->speed_capa =
2022                         ETH_LINK_SPEED_1G   |
2023                         ETH_LINK_SPEED_2_5G |
2024                         ETH_LINK_SPEED_5G   |
2025                         ETH_LINK_SPEED_10G  |
2026                         ETH_LINK_SPEED_25G  |
2027                         ETH_LINK_SPEED_40G  |
2028                         ETH_LINK_SPEED_50G  |
2029                         ETH_LINK_SPEED_100G;
2030
2031         /* Set Tx & Rx features available for device */
2032         if (adapter->offloads.tso4_supported)
2033                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2034
2035         if (adapter->offloads.tx_csum_supported)
2036                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2037                         DEV_TX_OFFLOAD_UDP_CKSUM |
2038                         DEV_TX_OFFLOAD_TCP_CKSUM;
2039
2040         if (adapter->offloads.rx_csum_supported)
2041                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2042                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2043                         DEV_RX_OFFLOAD_TCP_CKSUM;
2044
2045         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2046
2047         /* Inform framework about available features */
2048         dev_info->rx_offload_capa = rx_feat;
2049         dev_info->rx_queue_offload_capa = rx_feat;
2050         dev_info->tx_offload_capa = tx_feat;
2051         dev_info->tx_queue_offload_capa = tx_feat;
2052
2053         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2054                                            ETH_RSS_UDP;
2055
2056         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2057         dev_info->max_rx_pktlen  = adapter->max_mtu;
2058         dev_info->max_mac_addrs = 1;
2059
2060         dev_info->max_rx_queues = adapter->max_num_io_queues;
2061         dev_info->max_tx_queues = adapter->max_num_io_queues;
2062         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2063
2064         adapter->tx_supported_offloads = tx_feat;
2065         adapter->rx_supported_offloads = rx_feat;
2066
2067         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2068         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2069         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2070                                         adapter->max_rx_sgl_size);
2071         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2072                                         adapter->max_rx_sgl_size);
2073
2074         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2075         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2076         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2077                                         adapter->max_tx_sgl_size);
2078         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2079                                         adapter->max_tx_sgl_size);
2080
2081         return 0;
2082 }
2083
2084 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2085 {
2086         mbuf->data_len = len;
2087         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2088         mbuf->refcnt = 1;
2089         mbuf->next = NULL;
2090 }
2091
2092 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2093                                     struct ena_com_rx_buf_info *ena_bufs,
2094                                     uint32_t descs,
2095                                     uint16_t *next_to_clean,
2096                                     uint8_t offset)
2097 {
2098         struct rte_mbuf *mbuf;
2099         struct rte_mbuf *mbuf_head;
2100         struct ena_rx_buffer *rx_info;
2101         int rc;
2102         uint16_t ntc, len, req_id, buf = 0;
2103
2104         if (unlikely(descs == 0))
2105                 return NULL;
2106
2107         ntc = *next_to_clean;
2108
2109         len = ena_bufs[buf].len;
2110         req_id = ena_bufs[buf].req_id;
2111         if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2112                 return NULL;
2113
2114         rx_info = &rx_ring->rx_buffer_info[req_id];
2115
2116         mbuf = rx_info->mbuf;
2117         RTE_ASSERT(mbuf != NULL);
2118
2119         ena_init_rx_mbuf(mbuf, len);
2120
2121         /* Fill the mbuf head with the data specific for 1st segment. */
2122         mbuf_head = mbuf;
2123         mbuf_head->nb_segs = descs;
2124         mbuf_head->port = rx_ring->port_id;
2125         mbuf_head->pkt_len = len;
2126         mbuf_head->data_off += offset;
2127
2128         rx_info->mbuf = NULL;
2129         rx_ring->empty_rx_reqs[ntc] = req_id;
2130         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2131
2132         while (--descs) {
2133                 ++buf;
2134                 len = ena_bufs[buf].len;
2135                 req_id = ena_bufs[buf].req_id;
2136                 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2137                         rte_mbuf_raw_free(mbuf_head);
2138                         return NULL;
2139                 }
2140
2141                 rx_info = &rx_ring->rx_buffer_info[req_id];
2142                 RTE_ASSERT(rx_info->mbuf != NULL);
2143
2144                 if (unlikely(len == 0)) {
2145                         /*
2146                          * Some devices can pass descriptor with the length 0.
2147                          * To avoid confusion, the PMD is simply putting the
2148                          * descriptor back, as it was never used. We'll avoid
2149                          * mbuf allocation that way.
2150                          */
2151                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2152                                 rx_info->mbuf, req_id);
2153                         if (unlikely(rc != 0)) {
2154                                 /* Free the mbuf in case of an error. */
2155                                 rte_mbuf_raw_free(rx_info->mbuf);
2156                         } else {
2157                                 /*
2158                                  * If there was no error, just exit the loop as
2159                                  * 0 length descriptor is always the last one.
2160                                  */
2161                                 break;
2162                         }
2163                 } else {
2164                         /* Create an mbuf chain. */
2165                         mbuf->next = rx_info->mbuf;
2166                         mbuf = mbuf->next;
2167
2168                         ena_init_rx_mbuf(mbuf, len);
2169                         mbuf_head->pkt_len += len;
2170                 }
2171
2172                 /*
2173                  * Mark the descriptor as depleted and perform necessary
2174                  * cleanup.
2175                  * This code will execute in two cases:
2176                  *  1. Descriptor len was greater than 0 - normal situation.
2177                  *  2. Descriptor len was 0 and we failed to add the descriptor
2178                  *     to the device. In that situation, we should try to add
2179                  *     the mbuf again in the populate routine and mark the
2180                  *     descriptor as used up by the device.
2181                  */
2182                 rx_info->mbuf = NULL;
2183                 rx_ring->empty_rx_reqs[ntc] = req_id;
2184                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2185         }
2186
2187         *next_to_clean = ntc;
2188
2189         return mbuf_head;
2190 }
2191
2192 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2193                                   uint16_t nb_pkts)
2194 {
2195         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2196         unsigned int free_queue_entries;
2197         unsigned int refill_threshold;
2198         uint16_t next_to_clean = rx_ring->next_to_clean;
2199         uint16_t descs_in_use;
2200         struct rte_mbuf *mbuf;
2201         uint16_t completed;
2202         struct ena_com_rx_ctx ena_rx_ctx;
2203         int i, rc = 0;
2204
2205         /* Check adapter state */
2206         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2207                 PMD_DRV_LOG(ALERT,
2208                         "Trying to receive pkts while device is NOT running\n");
2209                 return 0;
2210         }
2211
2212         descs_in_use = rx_ring->ring_size -
2213                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2214         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2215
2216         for (completed = 0; completed < nb_pkts; completed++) {
2217                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2218                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2219                 ena_rx_ctx.descs = 0;
2220                 ena_rx_ctx.pkt_offset = 0;
2221                 /* receive packet context */
2222                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2223                                     rx_ring->ena_com_io_sq,
2224                                     &ena_rx_ctx);
2225                 if (unlikely(rc)) {
2226                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2227                         rx_ring->adapter->reset_reason =
2228                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2229                         rx_ring->adapter->trigger_reset = true;
2230                         ++rx_ring->rx_stats.bad_desc_num;
2231                         return 0;
2232                 }
2233
2234                 mbuf = ena_rx_mbuf(rx_ring,
2235                         ena_rx_ctx.ena_bufs,
2236                         ena_rx_ctx.descs,
2237                         &next_to_clean,
2238                         ena_rx_ctx.pkt_offset);
2239                 if (unlikely(mbuf == NULL)) {
2240                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2241                                 rx_ring->empty_rx_reqs[next_to_clean] =
2242                                         rx_ring->ena_bufs[i].req_id;
2243                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2244                                         next_to_clean, rx_ring->size_mask);
2245                         }
2246                         break;
2247                 }
2248
2249                 /* fill mbuf attributes if any */
2250                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2251
2252                 if (unlikely(mbuf->ol_flags &
2253                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2254                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2255                         ++rx_ring->rx_stats.bad_csum;
2256                 }
2257
2258                 mbuf->hash.rss = ena_rx_ctx.hash;
2259
2260                 rx_pkts[completed] = mbuf;
2261                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2262         }
2263
2264         rx_ring->rx_stats.cnt += completed;
2265         rx_ring->next_to_clean = next_to_clean;
2266
2267         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2268         refill_threshold =
2269                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2270                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2271
2272         /* Burst refill to save doorbells, memory barriers, const interval */
2273         if (free_queue_entries > refill_threshold) {
2274                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2275                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2276         }
2277
2278         return completed;
2279 }
2280
2281 static uint16_t
2282 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2283                 uint16_t nb_pkts)
2284 {
2285         int32_t ret;
2286         uint32_t i;
2287         struct rte_mbuf *m;
2288         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2289         struct rte_ipv4_hdr *ip_hdr;
2290         uint64_t ol_flags;
2291         uint16_t frag_field;
2292
2293         for (i = 0; i != nb_pkts; i++) {
2294                 m = tx_pkts[i];
2295                 ol_flags = m->ol_flags;
2296
2297                 if (!(ol_flags & PKT_TX_IPV4))
2298                         continue;
2299
2300                 /* If there was not L2 header length specified, assume it is
2301                  * length of the ethernet header.
2302                  */
2303                 if (unlikely(m->l2_len == 0))
2304                         m->l2_len = sizeof(struct rte_ether_hdr);
2305
2306                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2307                                                  m->l2_len);
2308                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2309
2310                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2311                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2312
2313                         /* If IPv4 header has DF flag enabled and TSO support is
2314                          * disabled, partial chcecksum should not be calculated.
2315                          */
2316                         if (!tx_ring->adapter->offloads.tso4_supported)
2317                                 continue;
2318                 }
2319
2320                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2321                                 (ol_flags & PKT_TX_L4_MASK) ==
2322                                 PKT_TX_SCTP_CKSUM) {
2323                         rte_errno = ENOTSUP;
2324                         return i;
2325                 }
2326
2327 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2328                 ret = rte_validate_tx_offload(m);
2329                 if (ret != 0) {
2330                         rte_errno = -ret;
2331                         return i;
2332                 }
2333 #endif
2334
2335                 /* In case we are supposed to TSO and have DF not set (DF=0)
2336                  * hardware must be provided with partial checksum, otherwise
2337                  * it will take care of necessary calculations.
2338                  */
2339
2340                 ret = rte_net_intel_cksum_flags_prepare(m,
2341                         ol_flags & ~PKT_TX_TCP_SEG);
2342                 if (ret != 0) {
2343                         rte_errno = -ret;
2344                         return i;
2345                 }
2346         }
2347
2348         return i;
2349 }
2350
2351 static void ena_update_hints(struct ena_adapter *adapter,
2352                              struct ena_admin_ena_hw_hints *hints)
2353 {
2354         if (hints->admin_completion_tx_timeout)
2355                 adapter->ena_dev.admin_queue.completion_timeout =
2356                         hints->admin_completion_tx_timeout * 1000;
2357
2358         if (hints->mmio_read_timeout)
2359                 /* convert to usec */
2360                 adapter->ena_dev.mmio_read.reg_read_to =
2361                         hints->mmio_read_timeout * 1000;
2362
2363         if (hints->driver_watchdog_timeout) {
2364                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2365                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2366                 else
2367                         // Convert msecs to ticks
2368                         adapter->keep_alive_timeout =
2369                                 (hints->driver_watchdog_timeout *
2370                                 rte_get_timer_hz()) / 1000;
2371         }
2372 }
2373
2374 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2375                                         struct rte_mbuf *mbuf)
2376 {
2377         struct ena_com_dev *ena_dev;
2378         int num_segments, header_len, rc;
2379
2380         ena_dev = &tx_ring->adapter->ena_dev;
2381         num_segments = mbuf->nb_segs;
2382         header_len = mbuf->data_len;
2383
2384         if (likely(num_segments < tx_ring->sgl_size))
2385                 return 0;
2386
2387         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2388             (num_segments == tx_ring->sgl_size) &&
2389             (header_len < tx_ring->tx_max_header_size))
2390                 return 0;
2391
2392         ++tx_ring->tx_stats.linearize;
2393         rc = rte_pktmbuf_linearize(mbuf);
2394         if (unlikely(rc)) {
2395                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2396                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2397                 ++tx_ring->tx_stats.linearize_failed;
2398                 return rc;
2399         }
2400
2401         return rc;
2402 }
2403
2404 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2405         struct ena_tx_buffer *tx_info,
2406         struct rte_mbuf *mbuf,
2407         void **push_header,
2408         uint16_t *header_len)
2409 {
2410         struct ena_com_buf *ena_buf;
2411         uint16_t delta, seg_len, push_len;
2412
2413         delta = 0;
2414         seg_len = mbuf->data_len;
2415
2416         tx_info->mbuf = mbuf;
2417         ena_buf = tx_info->bufs;
2418
2419         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2420                 /*
2421                  * Tx header might be (and will be in most cases) smaller than
2422                  * tx_max_header_size. But it's not an issue to send more data
2423                  * to the device, than actually needed if the mbuf size is
2424                  * greater than tx_max_header_size.
2425                  */
2426                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2427                 *header_len = push_len;
2428
2429                 if (likely(push_len <= seg_len)) {
2430                         /* If the push header is in the single segment, then
2431                          * just point it to the 1st mbuf data.
2432                          */
2433                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2434                 } else {
2435                         /* If the push header lays in the several segments, copy
2436                          * it to the intermediate buffer.
2437                          */
2438                         rte_pktmbuf_read(mbuf, 0, push_len,
2439                                 tx_ring->push_buf_intermediate_buf);
2440                         *push_header = tx_ring->push_buf_intermediate_buf;
2441                         delta = push_len - seg_len;
2442                 }
2443         } else {
2444                 *push_header = NULL;
2445                 *header_len = 0;
2446                 push_len = 0;
2447         }
2448
2449         /* Process first segment taking into consideration pushed header */
2450         if (seg_len > push_len) {
2451                 ena_buf->paddr = mbuf->buf_iova +
2452                                 mbuf->data_off +
2453                                 push_len;
2454                 ena_buf->len = seg_len - push_len;
2455                 ena_buf++;
2456                 tx_info->num_of_bufs++;
2457         }
2458
2459         while ((mbuf = mbuf->next) != NULL) {
2460                 seg_len = mbuf->data_len;
2461
2462                 /* Skip mbufs if whole data is pushed as a header */
2463                 if (unlikely(delta > seg_len)) {
2464                         delta -= seg_len;
2465                         continue;
2466                 }
2467
2468                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2469                 ena_buf->len = seg_len - delta;
2470                 ena_buf++;
2471                 tx_info->num_of_bufs++;
2472
2473                 delta = 0;
2474         }
2475 }
2476
2477 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2478 {
2479         struct ena_tx_buffer *tx_info;
2480         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2481         uint16_t next_to_use;
2482         uint16_t header_len;
2483         uint16_t req_id;
2484         void *push_header;
2485         int nb_hw_desc;
2486         int rc;
2487
2488         rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2489         if (unlikely(rc))
2490                 return rc;
2491
2492         next_to_use = tx_ring->next_to_use;
2493
2494         req_id = tx_ring->empty_tx_reqs[next_to_use];
2495         tx_info = &tx_ring->tx_buffer_info[req_id];
2496         tx_info->num_of_bufs = 0;
2497
2498         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2499
2500         ena_tx_ctx.ena_bufs = tx_info->bufs;
2501         ena_tx_ctx.push_header = push_header;
2502         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2503         ena_tx_ctx.req_id = req_id;
2504         ena_tx_ctx.header_len = header_len;
2505
2506         /* Set Tx offloads flags, if applicable */
2507         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2508                 tx_ring->disable_meta_caching);
2509
2510         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2511                         &ena_tx_ctx))) {
2512                 PMD_DRV_LOG(DEBUG,
2513                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2514                         tx_ring->id);
2515                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2516         }
2517
2518         /* prepare the packet's descriptors to dma engine */
2519         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2520                 &nb_hw_desc);
2521         if (unlikely(rc)) {
2522                 ++tx_ring->tx_stats.prepare_ctx_err;
2523                 return rc;
2524         }
2525
2526         tx_info->tx_descs = nb_hw_desc;
2527
2528         tx_ring->tx_stats.cnt++;
2529         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2530
2531         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2532                 tx_ring->size_mask);
2533
2534         return 0;
2535 }
2536
2537 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2538 {
2539         unsigned int cleanup_budget;
2540         unsigned int total_tx_descs = 0;
2541         uint16_t next_to_clean = tx_ring->next_to_clean;
2542
2543         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2544                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2545
2546         while (likely(total_tx_descs < cleanup_budget)) {
2547                 struct rte_mbuf *mbuf;
2548                 struct ena_tx_buffer *tx_info;
2549                 uint16_t req_id;
2550
2551                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2552                         break;
2553
2554                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2555                         break;
2556
2557                 /* Get Tx info & store how many descs were processed  */
2558                 tx_info = &tx_ring->tx_buffer_info[req_id];
2559
2560                 mbuf = tx_info->mbuf;
2561                 rte_pktmbuf_free(mbuf);
2562
2563                 tx_info->mbuf = NULL;
2564                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2565
2566                 total_tx_descs += tx_info->tx_descs;
2567
2568                 /* Put back descriptor to the ring for reuse */
2569                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2570                         tx_ring->size_mask);
2571         }
2572
2573         if (likely(total_tx_descs > 0)) {
2574                 /* acknowledge completion of sent packets */
2575                 tx_ring->next_to_clean = next_to_clean;
2576                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2577                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2578         }
2579 }
2580
2581 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2582                                   uint16_t nb_pkts)
2583 {
2584         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2585         uint16_t sent_idx = 0;
2586
2587         /* Check adapter state */
2588         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2589                 PMD_DRV_LOG(ALERT,
2590                         "Trying to xmit pkts while device is NOT running\n");
2591                 return 0;
2592         }
2593
2594         nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2595                 nb_pkts);
2596
2597         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2598                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2599                         break;
2600
2601                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2602                         tx_ring->size_mask)]);
2603         }
2604
2605         tx_ring->tx_stats.available_desc =
2606                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2607
2608         /* If there are ready packets to be xmitted... */
2609         if (sent_idx > 0) {
2610                 /* ...let HW do its best :-) */
2611                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2612                 tx_ring->tx_stats.doorbells++;
2613         }
2614
2615         ena_tx_cleanup(tx_ring);
2616
2617         tx_ring->tx_stats.available_desc =
2618                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2619         tx_ring->tx_stats.tx_poll++;
2620
2621         return sent_idx;
2622 }
2623
2624 int ena_copy_eni_stats(struct ena_adapter *adapter)
2625 {
2626         struct ena_admin_eni_stats admin_eni_stats;
2627         int rc;
2628
2629         rte_spinlock_lock(&adapter->admin_lock);
2630         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2631         rte_spinlock_unlock(&adapter->admin_lock);
2632         if (rc != 0) {
2633                 if (rc == ENA_COM_UNSUPPORTED) {
2634                         PMD_DRV_LOG(DEBUG,
2635                                 "Retrieving ENI metrics is not supported.\n");
2636                 } else {
2637                         PMD_DRV_LOG(WARNING,
2638                                 "Failed to get ENI metrics: %d\n", rc);
2639                 }
2640                 return rc;
2641         }
2642
2643         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2644                 sizeof(struct ena_stats_eni));
2645
2646         return 0;
2647 }
2648
2649 /**
2650  * DPDK callback to retrieve names of extended device statistics
2651  *
2652  * @param dev
2653  *   Pointer to Ethernet device structure.
2654  * @param[out] xstats_names
2655  *   Buffer to insert names into.
2656  * @param n
2657  *   Number of names.
2658  *
2659  * @return
2660  *   Number of xstats names.
2661  */
2662 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2663                                 struct rte_eth_xstat_name *xstats_names,
2664                                 unsigned int n)
2665 {
2666         unsigned int xstats_count = ena_xstats_calc_num(dev);
2667         unsigned int stat, i, count = 0;
2668
2669         if (n < xstats_count || !xstats_names)
2670                 return xstats_count;
2671
2672         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2673                 strcpy(xstats_names[count].name,
2674                         ena_stats_global_strings[stat].name);
2675
2676         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2677                 strcpy(xstats_names[count].name,
2678                         ena_stats_eni_strings[stat].name);
2679
2680         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2681                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2682                         snprintf(xstats_names[count].name,
2683                                 sizeof(xstats_names[count].name),
2684                                 "rx_q%d_%s", i,
2685                                 ena_stats_rx_strings[stat].name);
2686
2687         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2688                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2689                         snprintf(xstats_names[count].name,
2690                                 sizeof(xstats_names[count].name),
2691                                 "tx_q%d_%s", i,
2692                                 ena_stats_tx_strings[stat].name);
2693
2694         return xstats_count;
2695 }
2696
2697 /**
2698  * DPDK callback to get extended device statistics.
2699  *
2700  * @param dev
2701  *   Pointer to Ethernet device structure.
2702  * @param[out] stats
2703  *   Stats table output buffer.
2704  * @param n
2705  *   The size of the stats table.
2706  *
2707  * @return
2708  *   Number of xstats on success, negative on failure.
2709  */
2710 static int ena_xstats_get(struct rte_eth_dev *dev,
2711                           struct rte_eth_xstat *xstats,
2712                           unsigned int n)
2713 {
2714         struct ena_adapter *adapter = dev->data->dev_private;
2715         unsigned int xstats_count = ena_xstats_calc_num(dev);
2716         unsigned int stat, i, count = 0;
2717         int stat_offset;
2718         void *stats_begin;
2719
2720         if (n < xstats_count)
2721                 return xstats_count;
2722
2723         if (!xstats)
2724                 return 0;
2725
2726         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2727                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2728                 stats_begin = &adapter->dev_stats;
2729
2730                 xstats[count].id = count;
2731                 xstats[count].value = *((uint64_t *)
2732                         ((char *)stats_begin + stat_offset));
2733         }
2734
2735         /* Even if the function below fails, we should copy previous (or initial
2736          * values) to keep structure of rte_eth_xstat consistent.
2737          */
2738         ena_copy_eni_stats(adapter);
2739         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2740                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2741                 stats_begin = &adapter->eni_stats;
2742
2743                 xstats[count].id = count;
2744                 xstats[count].value = *((uint64_t *)
2745                     ((char *)stats_begin + stat_offset));
2746         }
2747
2748         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2749                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2750                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2751                         stats_begin = &adapter->rx_ring[i].rx_stats;
2752
2753                         xstats[count].id = count;
2754                         xstats[count].value = *((uint64_t *)
2755                                 ((char *)stats_begin + stat_offset));
2756                 }
2757         }
2758
2759         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2760                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2761                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2762                         stats_begin = &adapter->tx_ring[i].rx_stats;
2763
2764                         xstats[count].id = count;
2765                         xstats[count].value = *((uint64_t *)
2766                                 ((char *)stats_begin + stat_offset));
2767                 }
2768         }
2769
2770         return count;
2771 }
2772
2773 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2774                                 const uint64_t *ids,
2775                                 uint64_t *values,
2776                                 unsigned int n)
2777 {
2778         struct ena_adapter *adapter = dev->data->dev_private;
2779         uint64_t id;
2780         uint64_t rx_entries, tx_entries;
2781         unsigned int i;
2782         int qid;
2783         int valid = 0;
2784         bool was_eni_copied = false;
2785
2786         for (i = 0; i < n; ++i) {
2787                 id = ids[i];
2788                 /* Check if id belongs to global statistics */
2789                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2790                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2791                         ++valid;
2792                         continue;
2793                 }
2794
2795                 /* Check if id belongs to ENI statistics */
2796                 id -= ENA_STATS_ARRAY_GLOBAL;
2797                 if (id < ENA_STATS_ARRAY_ENI) {
2798                         /* Avoid reading ENI stats multiple times in a single
2799                          * function call, as it requires communication with the
2800                          * admin queue.
2801                          */
2802                         if (!was_eni_copied) {
2803                                 was_eni_copied = true;
2804                                 ena_copy_eni_stats(adapter);
2805                         }
2806                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2807                         ++valid;
2808                         continue;
2809                 }
2810
2811                 /* Check if id belongs to rx queue statistics */
2812                 id -= ENA_STATS_ARRAY_ENI;
2813                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2814                 if (id < rx_entries) {
2815                         qid = id % dev->data->nb_rx_queues;
2816                         id /= dev->data->nb_rx_queues;
2817                         values[i] = *((uint64_t *)
2818                                 &adapter->rx_ring[qid].rx_stats + id);
2819                         ++valid;
2820                         continue;
2821                 }
2822                                 /* Check if id belongs to rx queue statistics */
2823                 id -= rx_entries;
2824                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2825                 if (id < tx_entries) {
2826                         qid = id % dev->data->nb_tx_queues;
2827                         id /= dev->data->nb_tx_queues;
2828                         values[i] = *((uint64_t *)
2829                                 &adapter->tx_ring[qid].tx_stats + id);
2830                         ++valid;
2831                         continue;
2832                 }
2833         }
2834
2835         return valid;
2836 }
2837
2838 static int ena_process_bool_devarg(const char *key,
2839                                    const char *value,
2840                                    void *opaque)
2841 {
2842         struct ena_adapter *adapter = opaque;
2843         bool bool_value;
2844
2845         /* Parse the value. */
2846         if (strcmp(value, "1") == 0) {
2847                 bool_value = true;
2848         } else if (strcmp(value, "0") == 0) {
2849                 bool_value = false;
2850         } else {
2851                 PMD_INIT_LOG(ERR,
2852                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2853                         value, key);
2854                 return -EINVAL;
2855         }
2856
2857         /* Now, assign it to the proper adapter field. */
2858         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2859                 adapter->use_large_llq_hdr = bool_value;
2860
2861         return 0;
2862 }
2863
2864 static int ena_parse_devargs(struct ena_adapter *adapter,
2865                              struct rte_devargs *devargs)
2866 {
2867         static const char * const allowed_args[] = {
2868                 ENA_DEVARG_LARGE_LLQ_HDR,
2869         };
2870         struct rte_kvargs *kvlist;
2871         int rc;
2872
2873         if (devargs == NULL)
2874                 return 0;
2875
2876         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2877         if (kvlist == NULL) {
2878                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2879                         devargs->args);
2880                 return -EINVAL;
2881         }
2882
2883         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2884                 ena_process_bool_devarg, adapter);
2885
2886         rte_kvargs_free(kvlist);
2887
2888         return rc;
2889 }
2890
2891 /*********************************************************************
2892  *  PMD configuration
2893  *********************************************************************/
2894 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2895         struct rte_pci_device *pci_dev)
2896 {
2897         return rte_eth_dev_pci_generic_probe(pci_dev,
2898                 sizeof(struct ena_adapter), eth_ena_dev_init);
2899 }
2900
2901 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2902 {
2903         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2904 }
2905
2906 static struct rte_pci_driver rte_ena_pmd = {
2907         .id_table = pci_id_ena_map,
2908         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2909                      RTE_PCI_DRV_WC_ACTIVATE,
2910         .probe = eth_ena_pci_probe,
2911         .remove = eth_ena_pci_remove,
2912 };
2913
2914 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2915 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2916 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2917 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2918 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE);
2919 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE);
2920 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2921 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE);
2922 #endif
2923 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2924 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE);
2925 #endif
2926 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2927 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE);
2928 #endif
2929 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2930 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE);
2931 #endif
2932
2933 /******************************************************************************
2934  ******************************** AENQ Handlers *******************************
2935  *****************************************************************************/
2936 static void ena_update_on_link_change(void *adapter_data,
2937                                       struct ena_admin_aenq_entry *aenq_e)
2938 {
2939         struct rte_eth_dev *eth_dev;
2940         struct ena_adapter *adapter;
2941         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2942         uint32_t status;
2943
2944         adapter = adapter_data;
2945         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2946         eth_dev = adapter->rte_dev;
2947
2948         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2949         adapter->link_status = status;
2950
2951         ena_link_update(eth_dev, 0);
2952         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2953 }
2954
2955 static void ena_notification(void *data,
2956                              struct ena_admin_aenq_entry *aenq_e)
2957 {
2958         struct ena_adapter *adapter = data;
2959         struct ena_admin_ena_hw_hints *hints;
2960
2961         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2962                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2963                         aenq_e->aenq_common_desc.group,
2964                         ENA_ADMIN_NOTIFICATION);
2965
2966         switch (aenq_e->aenq_common_desc.syndrom) {
2967         case ENA_ADMIN_UPDATE_HINTS:
2968                 hints = (struct ena_admin_ena_hw_hints *)
2969                         (&aenq_e->inline_data_w4);
2970                 ena_update_hints(adapter, hints);
2971                 break;
2972         default:
2973                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2974                         aenq_e->aenq_common_desc.syndrom);
2975         }
2976 }
2977
2978 static void ena_keep_alive(void *adapter_data,
2979                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2980 {
2981         struct ena_adapter *adapter = adapter_data;
2982         struct ena_admin_aenq_keep_alive_desc *desc;
2983         uint64_t rx_drops;
2984         uint64_t tx_drops;
2985
2986         adapter->timestamp_wd = rte_get_timer_cycles();
2987
2988         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2989         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2990         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2991
2992         adapter->drv_stats->rx_drops = rx_drops;
2993         adapter->dev_stats.tx_drops = tx_drops;
2994 }
2995
2996 /**
2997  * This handler will called for unknown event group or unimplemented handlers
2998  **/
2999 static void unimplemented_aenq_handler(__rte_unused void *data,
3000                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3001 {
3002         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3003                           "unimplemented handler\n");
3004 }
3005
3006 static struct ena_aenq_handlers aenq_handlers = {
3007         .handlers = {
3008                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3009                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3010                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3011         },
3012         .unimplemented_handler = unimplemented_aenq_handler
3013 };