drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    4
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 enum ethtool_stringset {
  42         ETH_SS_TEST             = 0,
  43         ETH_SS_STATS,
  44 };
  45
  46 struct ena_stats {
  47         char name[ETH_GSTRING_LEN];
  48         int stat_offset;
  49 };
  50
  51 #define ENA_STAT_ENTRY(stat, stat_type) { \
  52         .name = #stat, \
  53         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  54 }
  55
  56 #define ENA_STAT_RX_ENTRY(stat) \
  57         ENA_STAT_ENTRY(stat, rx)
  58
  59 #define ENA_STAT_TX_ENTRY(stat) \
  60         ENA_STAT_ENTRY(stat, tx)
  61
  62 #define ENA_STAT_ENI_ENTRY(stat) \
  63         ENA_STAT_ENTRY(stat, eni)
  64
  65 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  66         ENA_STAT_ENTRY(stat, dev)
  67
  68 /* Device arguments */
  69 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  70
  71 /*
  72  * Each rte_memzone should have unique name.
  73  * To satisfy it, count number of allocation and add it to name.
  74  */
  75 rte_atomic64_t ena_alloc_cnt;
  76
  77 static const struct ena_stats ena_stats_global_strings[] = {
  78         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  79         ENA_STAT_GLOBAL_ENTRY(dev_start),
  80         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  81         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  82 };
  83
  84 static const struct ena_stats ena_stats_eni_strings[] = {
  85         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  86         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  87         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  88         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  89         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  90 };
  91
  92 static const struct ena_stats ena_stats_tx_strings[] = {
  93         ENA_STAT_TX_ENTRY(cnt),
  94         ENA_STAT_TX_ENTRY(bytes),
  95         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  96         ENA_STAT_TX_ENTRY(linearize),
  97         ENA_STAT_TX_ENTRY(linearize_failed),
  98         ENA_STAT_TX_ENTRY(tx_poll),
  99         ENA_STAT_TX_ENTRY(doorbells),
 100         ENA_STAT_TX_ENTRY(bad_req_id),
 101         ENA_STAT_TX_ENTRY(available_desc),
 102 };
 103
 104 static const struct ena_stats ena_stats_rx_strings[] = {
 105         ENA_STAT_RX_ENTRY(cnt),
 106         ENA_STAT_RX_ENTRY(bytes),
 107         ENA_STAT_RX_ENTRY(refill_partial),
 108         ENA_STAT_RX_ENTRY(bad_csum),
 109         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 110         ENA_STAT_RX_ENTRY(bad_desc_num),
 111         ENA_STAT_RX_ENTRY(bad_req_id),
 112 };
 113
 114 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 115 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 116 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 117 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 118
 119 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 120                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 121                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 122                         DEV_TX_OFFLOAD_TCP_TSO)
 123 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 124                        PKT_TX_IP_CKSUM |\
 125                        PKT_TX_TCP_SEG)
 126
 127 /** Vendor ID used by Amazon devices */
 128 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 129 /** Amazon devices */
 130 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 131 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 132
 133 #define ENA_TX_OFFLOAD_MASK     (\
 134         PKT_TX_L4_MASK |         \
 135         PKT_TX_IPV6 |            \
 136         PKT_TX_IPV4 |            \
 137         PKT_TX_IP_CKSUM |        \
 138         PKT_TX_TCP_SEG)
 139
 140 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 141         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 142
 143 /** HW specific offloads capabilities. */
 144 /* IPv4 checksum offload. */
 145 #define ENA_L3_IPV4_CSUM                0x0001
 146 /* TCP/UDP checksum offload for IPv4 packets. */
 147 #define ENA_L4_IPV4_CSUM                0x0002
 148 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 149 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 150 /* TCP/UDP checksum offload for IPv6 packets. */
 151 #define ENA_L4_IPV6_CSUM                0x0008
 152 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 153 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 154 /* TSO support for IPv4 packets. */
 155 #define ENA_IPV4_TSO                    0x0020
 156
 157 /* Device supports setting RSS hash. */
 158 #define ENA_RX_RSS_HASH                 0x0040
 159
 160 static const struct rte_pci_id pci_id_ena_map[] = {
 161         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 162         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 163         { .device_id = 0 },
 164 };
 165
 166 static struct ena_aenq_handlers aenq_handlers;
 167
 168 static int ena_device_init(struct ena_com_dev *ena_dev,
 169                            struct rte_pci_device *pdev,
 170                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 171                            bool *wd_state);
 172 static int ena_dev_configure(struct rte_eth_dev *dev);
 173 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 174         struct ena_tx_buffer *tx_info,
 175         struct rte_mbuf *mbuf,
 176         void **push_header,
 177         uint16_t *header_len);
 178 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 179 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                                   uint16_t nb_pkts);
 182 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 183                 uint16_t nb_pkts);
 184 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 185                               uint16_t nb_desc, unsigned int socket_id,
 186                               const struct rte_eth_txconf *tx_conf);
 187 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 188                               uint16_t nb_desc, unsigned int socket_id,
 189                               const struct rte_eth_rxconf *rx_conf,
 190                               struct rte_mempool *mp);
 191 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 192 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 193                                     struct ena_com_rx_buf_info *ena_bufs,
 194                                     uint32_t descs,
 195                                     uint16_t *next_to_clean,
 196                                     uint8_t offset);
 197 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 198                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 199 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 200                                   struct rte_mbuf *mbuf, uint16_t id);
 201 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 202 static void ena_init_rings(struct ena_adapter *adapter,
 203                            bool disable_meta_caching);
 204 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 205 static int ena_start(struct rte_eth_dev *dev);
 206 static int ena_stop(struct rte_eth_dev *dev);
 207 static int ena_close(struct rte_eth_dev *dev);
 208 static int ena_dev_reset(struct rte_eth_dev *dev);
 209 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 210 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 211 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 212 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 213 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 214 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 215 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 216 static int ena_link_update(struct rte_eth_dev *dev,
 217                            int wait_to_complete);
 218 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 219 static void ena_queue_stop(struct ena_ring *ring);
 220 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 221                               enum ena_ring_type ring_type);
 222 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 223 static int ena_queue_start_all(struct rte_eth_dev *dev,
 224                                enum ena_ring_type ring_type);
 225 static void ena_stats_restart(struct rte_eth_dev *dev);
 226 static int ena_infos_get(struct rte_eth_dev *dev,
 227                          struct rte_eth_dev_info *dev_info);
 228 static void ena_interrupt_handler_rte(void *cb_arg);
 229 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 230 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 231 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 232 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 233                                 struct rte_eth_xstat_name *xstats_names,
 234                                 unsigned int n);
 235 static int ena_xstats_get(struct rte_eth_dev *dev,
 236                           struct rte_eth_xstat *stats,
 237                           unsigned int n);
 238 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 239                                 const uint64_t *ids,
 240                                 uint64_t *values,
 241                                 unsigned int n);
 242 static int ena_process_bool_devarg(const char *key,
 243                                    const char *value,
 244                                    void *opaque);
 245 static int ena_parse_devargs(struct ena_adapter *adapter,
 246                              struct rte_devargs *devargs);
 247 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 248 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 249 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 250                                     uint16_t queue_id);
 251 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 252                                      uint16_t queue_id);
 253
 254 static const struct eth_dev_ops ena_dev_ops = {
 255         .dev_configure        = ena_dev_configure,
 256         .dev_infos_get        = ena_infos_get,
 257         .rx_queue_setup       = ena_rx_queue_setup,
 258         .tx_queue_setup       = ena_tx_queue_setup,
 259         .dev_start            = ena_start,
 260         .dev_stop             = ena_stop,
 261         .link_update          = ena_link_update,
 262         .stats_get            = ena_stats_get,
 263         .xstats_get_names     = ena_xstats_get_names,
 264         .xstats_get           = ena_xstats_get,
 265         .xstats_get_by_id     = ena_xstats_get_by_id,
 266         .mtu_set              = ena_mtu_set,
 267         .rx_queue_release     = ena_rx_queue_release,
 268         .tx_queue_release     = ena_tx_queue_release,
 269         .dev_close            = ena_close,
 270         .dev_reset            = ena_dev_reset,
 271         .reta_update          = ena_rss_reta_update,
 272         .reta_query           = ena_rss_reta_query,
 273         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 274         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 275         .rss_hash_update      = ena_rss_hash_update,
 276         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 277 };
 278
 279 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 280                                        struct ena_com_rx_ctx *ena_rx_ctx,
 281                                        bool fill_hash)
 282 {
 283         uint64_t ol_flags = 0;
 284         uint32_t packet_type = 0;
 285
 286         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 287                 packet_type |= RTE_PTYPE_L4_TCP;
 288         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 289                 packet_type |= RTE_PTYPE_L4_UDP;
 290
 291         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 292                 packet_type |= RTE_PTYPE_L3_IPV4;
 293                 if (unlikely(ena_rx_ctx->l3_csum_err))
 294                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 295                 else
 296                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 297         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 298                 packet_type |= RTE_PTYPE_L3_IPV6;
 299         }
 300
 301         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 302                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 303         else
 304                 if (unlikely(ena_rx_ctx->l4_csum_err))
 305                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 306                 else
 307                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 308
 309         if (fill_hash &&
 310             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 311                 ol_flags |= PKT_RX_RSS_HASH;
 312                 mbuf->hash.rss = ena_rx_ctx->hash;
 313         }
 314
 315         mbuf->ol_flags = ol_flags;
 316         mbuf->packet_type = packet_type;
 317 }
 318
 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 320                                        struct ena_com_tx_ctx *ena_tx_ctx,
 321                                        uint64_t queue_offloads,
 322                                        bool disable_meta_caching)
 323 {
 324         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 325
 326         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 327             (queue_offloads & QUEUE_OFFLOADS)) {
 328                 /* check if TSO is required */
 329                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 330                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 331                         ena_tx_ctx->tso_enable = true;
 332
 333                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 334                 }
 335
 336                 /* check if L3 checksum is needed */
 337                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 338                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 339                         ena_tx_ctx->l3_csum_enable = true;
 340
 341                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 342                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 343                 } else {
 344                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 345
 346                         /* set don't fragment (DF) flag */
 347                         if (mbuf->packet_type &
 348                                 (RTE_PTYPE_L4_NONFRAG
 349                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 350                                 ena_tx_ctx->df = true;
 351                 }
 352
 353                 /* check if L4 checksum is needed */
 354                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 355                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 357                         ena_tx_ctx->l4_csum_enable = true;
 358                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 359                                 PKT_TX_UDP_CKSUM) &&
 360                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 361                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 362                         ena_tx_ctx->l4_csum_enable = true;
 363                 } else {
 364                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 365                         ena_tx_ctx->l4_csum_enable = false;
 366                 }
 367
 368                 ena_meta->mss = mbuf->tso_segsz;
 369                 ena_meta->l3_hdr_len = mbuf->l3_len;
 370                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 371
 372                 ena_tx_ctx->meta_valid = true;
 373         } else if (disable_meta_caching) {
 374                 memset(ena_meta, 0, sizeof(*ena_meta));
 375                 ena_tx_ctx->meta_valid = true;
 376         } else {
 377                 ena_tx_ctx->meta_valid = false;
 378         }
 379 }
 380
 381 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 382 {
 383         struct ena_tx_buffer *tx_info = NULL;
 384
 385         if (likely(req_id < tx_ring->ring_size)) {
 386                 tx_info = &tx_ring->tx_buffer_info[req_id];
 387                 if (likely(tx_info->mbuf))
 388                         return 0;
 389         }
 390
 391         if (tx_info)
 392                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 393         else
 394                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 395
 396         /* Trigger device reset */
 397         ++tx_ring->tx_stats.bad_req_id;
 398         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 399         tx_ring->adapter->trigger_reset = true;
 400         return -EFAULT;
 401 }
 402
 403 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 404 {
 405         struct ena_admin_host_info *host_info;
 406         int rc;
 407
 408         /* Allocate only the host info */
 409         rc = ena_com_allocate_host_info(ena_dev);
 410         if (rc) {
 411                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 412                 return;
 413         }
 414
 415         host_info = ena_dev->host_attr.host_info;
 416
 417         host_info->os_type = ENA_ADMIN_OS_DPDK;
 418         host_info->kernel_ver = RTE_VERSION;
 419         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 420                 sizeof(host_info->kernel_ver_str));
 421         host_info->os_dist = RTE_VERSION;
 422         strlcpy((char *)host_info->os_dist_str, rte_version(),
 423                 sizeof(host_info->os_dist_str));
 424         host_info->driver_version =
 425                 (DRV_MODULE_VER_MAJOR) |
 426                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 427                 (DRV_MODULE_VER_SUBMINOR <<
 428                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 429         host_info->num_cpus = rte_lcore_count();
 430
 431         host_info->driver_supported_features =
 432                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 433                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 434
 435         rc = ena_com_set_host_attributes(ena_dev);
 436         if (rc) {
 437                 if (rc == -ENA_COM_UNSUPPORTED)
 438                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 439                 else
 440                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 441
 442                 goto err;
 443         }
 444
 445         return;
 446
 447 err:
 448         ena_com_delete_host_info(ena_dev);
 449 }
 450
 451 /* This function calculates the number of xstats based on the current config */
 452 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 453 {
 454         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 455                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 456                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 457 }
 458
 459 static void ena_config_debug_area(struct ena_adapter *adapter)
 460 {
 461         u32 debug_area_size;
 462         int rc, ss_count;
 463
 464         ss_count = ena_xstats_calc_num(adapter->edev_data);
 465
 466         /* allocate 32 bytes for each string and 64bit for the value */
 467         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 468
 469         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 470         if (rc) {
 471                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 472                 return;
 473         }
 474
 475         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 476         if (rc) {
 477                 if (rc == -ENA_COM_UNSUPPORTED)
 478                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 479                 else
 480                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 481
 482                 goto err;
 483         }
 484
 485         return;
 486 err:
 487         ena_com_delete_debug_area(&adapter->ena_dev);
 488 }
 489
 490 static int ena_close(struct rte_eth_dev *dev)
 491 {
 492         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 493         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 494         struct ena_adapter *adapter = dev->data->dev_private;
 495         int ret = 0;
 496
 497         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 498                 return 0;
 499
 500         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 501                 ret = ena_stop(dev);
 502         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 503
 504         ena_rx_queue_release_all(dev);
 505         ena_tx_queue_release_all(dev);
 506
 507         rte_free(adapter->drv_stats);
 508         adapter->drv_stats = NULL;
 509
 510         rte_intr_disable(intr_handle);
 511         rte_intr_callback_unregister(intr_handle,
 512                                      ena_interrupt_handler_rte,
 513                                      dev);
 514
 515         /*
 516          * MAC is not allocated dynamically. Setting NULL should prevent from
 517          * release of the resource in the rte_eth_dev_release_port().
 518          */
 519         dev->data->mac_addrs = NULL;
 520
 521         return ret;
 522 }
 523
 524 static int
 525 ena_dev_reset(struct rte_eth_dev *dev)
 526 {
 527         int rc = 0;
 528
 529         /* Cannot release memory in secondary process */
 530         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 531                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 532                 return -EPERM;
 533         }
 534
 535         ena_destroy_device(dev);
 536         rc = eth_ena_dev_init(dev);
 537         if (rc)
 538                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 539
 540         return rc;
 541 }
 542
 543 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 544 {
 545         int nb_queues = dev->data->nb_rx_queues;
 546         int i;
 547
 548         for (i = 0; i < nb_queues; i++)
 549                 ena_rx_queue_release(dev, i);
 550 }
 551
 552 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 553 {
 554         int nb_queues = dev->data->nb_tx_queues;
 555         int i;
 556
 557         for (i = 0; i < nb_queues; i++)
 558                 ena_tx_queue_release(dev, i);
 559 }
 560
 561 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 562 {
 563         struct ena_ring *ring = dev->data->rx_queues[qid];
 564
 565         /* Free ring resources */
 566         if (ring->rx_buffer_info)
 567                 rte_free(ring->rx_buffer_info);
 568         ring->rx_buffer_info = NULL;
 569
 570         if (ring->rx_refill_buffer)
 571                 rte_free(ring->rx_refill_buffer);
 572         ring->rx_refill_buffer = NULL;
 573
 574         if (ring->empty_rx_reqs)
 575                 rte_free(ring->empty_rx_reqs);
 576         ring->empty_rx_reqs = NULL;
 577
 578         ring->configured = 0;
 579
 580         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 581                 ring->port_id, ring->id);
 582 }
 583
 584 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 585 {
 586         struct ena_ring *ring = dev->data->tx_queues[qid];
 587
 588         /* Free ring resources */
 589         if (ring->push_buf_intermediate_buf)
 590                 rte_free(ring->push_buf_intermediate_buf);
 591
 592         if (ring->tx_buffer_info)
 593                 rte_free(ring->tx_buffer_info);
 594
 595         if (ring->empty_tx_reqs)
 596                 rte_free(ring->empty_tx_reqs);
 597
 598         ring->empty_tx_reqs = NULL;
 599         ring->tx_buffer_info = NULL;
 600         ring->push_buf_intermediate_buf = NULL;
 601
 602         ring->configured = 0;
 603
 604         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 605                 ring->port_id, ring->id);
 606 }
 607
 608 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 609 {
 610         unsigned int i;
 611
 612         for (i = 0; i < ring->ring_size; ++i) {
 613                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 614                 if (rx_info->mbuf) {
 615                         rte_mbuf_raw_free(rx_info->mbuf);
 616                         rx_info->mbuf = NULL;
 617                 }
 618         }
 619 }
 620
 621 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 622 {
 623         unsigned int i;
 624
 625         for (i = 0; i < ring->ring_size; ++i) {
 626                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 627
 628                 if (tx_buf->mbuf) {
 629                         rte_pktmbuf_free(tx_buf->mbuf);
 630                         tx_buf->mbuf = NULL;
 631                 }
 632         }
 633 }
 634
 635 static int ena_link_update(struct rte_eth_dev *dev,
 636                            __rte_unused int wait_to_complete)
 637 {
 638         struct rte_eth_link *link = &dev->data->dev_link;
 639         struct ena_adapter *adapter = dev->data->dev_private;
 640
 641         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 642         link->link_speed = ETH_SPEED_NUM_NONE;
 643         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 644
 645         return 0;
 646 }
 647
 648 static int ena_queue_start_all(struct rte_eth_dev *dev,
 649                                enum ena_ring_type ring_type)
 650 {
 651         struct ena_adapter *adapter = dev->data->dev_private;
 652         struct ena_ring *queues = NULL;
 653         int nb_queues;
 654         int i = 0;
 655         int rc = 0;
 656
 657         if (ring_type == ENA_RING_TYPE_RX) {
 658                 queues = adapter->rx_ring;
 659                 nb_queues = dev->data->nb_rx_queues;
 660         } else {
 661                 queues = adapter->tx_ring;
 662                 nb_queues = dev->data->nb_tx_queues;
 663         }
 664         for (i = 0; i < nb_queues; i++) {
 665                 if (queues[i].configured) {
 666                         if (ring_type == ENA_RING_TYPE_RX) {
 667                                 ena_assert_msg(
 668                                         dev->data->rx_queues[i] == &queues[i],
 669                                         "Inconsistent state of Rx queues\n");
 670                         } else {
 671                                 ena_assert_msg(
 672                                         dev->data->tx_queues[i] == &queues[i],
 673                                         "Inconsistent state of Tx queues\n");
 674                         }
 675
 676                         rc = ena_queue_start(dev, &queues[i]);
 677
 678                         if (rc) {
 679                                 PMD_INIT_LOG(ERR,
 680                                         "Failed to start queue[%d] of type(%d)\n",
 681                                         i, ring_type);
 682                                 goto err;
 683                         }
 684                 }
 685         }
 686
 687         return 0;
 688
 689 err:
 690         while (i--)
 691                 if (queues[i].configured)
 692                         ena_queue_stop(&queues[i]);
 693
 694         return rc;
 695 }
 696
 697 static int ena_check_valid_conf(struct ena_adapter *adapter)
 698 {
 699         uint32_t mtu = adapter->edev_data->mtu;
 700
 701         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 702                 PMD_INIT_LOG(ERR,
 703                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 704                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 705                 return ENA_COM_UNSUPPORTED;
 706         }
 707
 708         return 0;
 709 }
 710
 711 static int
 712 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 713                        bool use_large_llq_hdr)
 714 {
 715         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 716         struct ena_com_dev *ena_dev = ctx->ena_dev;
 717         uint32_t max_tx_queue_size;
 718         uint32_t max_rx_queue_size;
 719
 720         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 721                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 722                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 723                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 724                         max_queue_ext->max_rx_sq_depth);
 725                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 726
 727                 if (ena_dev->tx_mem_queue_type ==
 728                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 729                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 730                                 llq->max_llq_depth);
 731                 } else {
 732                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 733                                 max_queue_ext->max_tx_sq_depth);
 734                 }
 735
 736                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 737                         max_queue_ext->max_per_packet_rx_descs);
 738                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 739                         max_queue_ext->max_per_packet_tx_descs);
 740         } else {
 741                 struct ena_admin_queue_feature_desc *max_queues =
 742                         &ctx->get_feat_ctx->max_queues;
 743                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 744                         max_queues->max_sq_depth);
 745                 max_tx_queue_size = max_queues->max_cq_depth;
 746
 747                 if (ena_dev->tx_mem_queue_type ==
 748                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 749                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 750                                 llq->max_llq_depth);
 751                 } else {
 752                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 753                                 max_queues->max_sq_depth);
 754                 }
 755
 756                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 757                         max_queues->max_packet_rx_descs);
 758                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 759                         max_queues->max_packet_tx_descs);
 760         }
 761
 762         /* Round down to the nearest power of 2 */
 763         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 764         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 765
 766         if (use_large_llq_hdr) {
 767                 if ((llq->entry_size_ctrl_supported &
 768                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 769                     (ena_dev->tx_mem_queue_type ==
 770                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 771                         max_tx_queue_size /= 2;
 772                         PMD_INIT_LOG(INFO,
 773                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
 774                                 max_tx_queue_size);
 775                 } else {
 776                         PMD_INIT_LOG(ERR,
 777                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 778                 }
 779         }
 780
 781         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 782                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 783                 return -EFAULT;
 784         }
 785
 786         ctx->max_tx_queue_size = max_tx_queue_size;
 787         ctx->max_rx_queue_size = max_rx_queue_size;
 788
 789         return 0;
 790 }
 791
 792 static void ena_stats_restart(struct rte_eth_dev *dev)
 793 {
 794         struct ena_adapter *adapter = dev->data->dev_private;
 795
 796         rte_atomic64_init(&adapter->drv_stats->ierrors);
 797         rte_atomic64_init(&adapter->drv_stats->oerrors);
 798         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 799         adapter->drv_stats->rx_drops = 0;
 800 }
 801
 802 static int ena_stats_get(struct rte_eth_dev *dev,
 803                           struct rte_eth_stats *stats)
 804 {
 805         struct ena_admin_basic_stats ena_stats;
 806         struct ena_adapter *adapter = dev->data->dev_private;
 807         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 808         int rc;
 809         int i;
 810         int max_rings_stats;
 811
 812         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 813                 return -ENOTSUP;
 814
 815         memset(&ena_stats, 0, sizeof(ena_stats));
 816
 817         rte_spinlock_lock(&adapter->admin_lock);
 818         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 819         rte_spinlock_unlock(&adapter->admin_lock);
 820         if (unlikely(rc)) {
 821                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 822                 return rc;
 823         }
 824
 825         /* Set of basic statistics from ENA */
 826         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 827                                           ena_stats.rx_pkts_low);
 828         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 829                                           ena_stats.tx_pkts_low);
 830         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 831                                         ena_stats.rx_bytes_low);
 832         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 833                                         ena_stats.tx_bytes_low);
 834
 835         /* Driver related stats */
 836         stats->imissed = adapter->drv_stats->rx_drops;
 837         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 838         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 839         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 840
 841         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 842                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 843         for (i = 0; i < max_rings_stats; ++i) {
 844                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 845
 846                 stats->q_ibytes[i] = rx_stats->bytes;
 847                 stats->q_ipackets[i] = rx_stats->cnt;
 848                 stats->q_errors[i] = rx_stats->bad_desc_num +
 849                         rx_stats->bad_req_id;
 850         }
 851
 852         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 853                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 854         for (i = 0; i < max_rings_stats; ++i) {
 855                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 856
 857                 stats->q_obytes[i] = tx_stats->bytes;
 858                 stats->q_opackets[i] = tx_stats->cnt;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 865 {
 866         struct ena_adapter *adapter;
 867         struct ena_com_dev *ena_dev;
 868         int rc = 0;
 869
 870         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 871         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 872         adapter = dev->data->dev_private;
 873
 874         ena_dev = &adapter->ena_dev;
 875         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 876
 877         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 878                 PMD_DRV_LOG(ERR,
 879                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
 880                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 881                 return -EINVAL;
 882         }
 883
 884         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 885         if (rc)
 886                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 887         else
 888                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
 889
 890         return rc;
 891 }
 892
 893 static int ena_start(struct rte_eth_dev *dev)
 894 {
 895         struct ena_adapter *adapter = dev->data->dev_private;
 896         uint64_t ticks;
 897         int rc = 0;
 898
 899         /* Cannot allocate memory in secondary process */
 900         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 901                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
 902                 return -EPERM;
 903         }
 904
 905         rc = ena_check_valid_conf(adapter);
 906         if (rc)
 907                 return rc;
 908
 909         rc = ena_setup_rx_intr(dev);
 910         if (rc)
 911                 return rc;
 912
 913         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
 914         if (rc)
 915                 return rc;
 916
 917         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
 918         if (rc)
 919                 goto err_start_tx;
 920
 921         if (adapter->edev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 922                 rc = ena_rss_configure(adapter);
 923                 if (rc)
 924                         goto err_rss_init;
 925         }
 926
 927         ena_stats_restart(dev);
 928
 929         adapter->timestamp_wd = rte_get_timer_cycles();
 930         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
 931
 932         ticks = rte_get_timer_hz();
 933         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
 934                         ena_timer_wd_callback, dev);
 935
 936         ++adapter->dev_stats.dev_start;
 937         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 938
 939         return 0;
 940
 941 err_rss_init:
 942         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 943 err_start_tx:
 944         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 945         return rc;
 946 }
 947
 948 static int ena_stop(struct rte_eth_dev *dev)
 949 {
 950         struct ena_adapter *adapter = dev->data->dev_private;
 951         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 952         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 953         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 954         int rc;
 955
 956         /* Cannot free memory in secondary process */
 957         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 958                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
 959                 return -EPERM;
 960         }
 961
 962         rte_timer_stop_sync(&adapter->timer_wd);
 963         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 964         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 965
 966         if (adapter->trigger_reset) {
 967                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 968                 if (rc)
 969                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
 970         }
 971
 972         rte_intr_disable(intr_handle);
 973
 974         rte_intr_efd_disable(intr_handle);
 975         if (intr_handle->intr_vec != NULL) {
 976                 rte_free(intr_handle->intr_vec);
 977                 intr_handle->intr_vec = NULL;
 978         }
 979
 980         rte_intr_enable(intr_handle);
 981
 982         ++adapter->dev_stats.dev_stop;
 983         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 984         dev->data->dev_started = 0;
 985
 986         return 0;
 987 }
 988
 989 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
 990 {
 991         struct ena_adapter *adapter = ring->adapter;
 992         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 994         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 995         struct ena_com_create_io_ctx ctx =
 996                 /* policy set to _HOST just to satisfy icc compiler */
 997                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 998                   0, 0, 0, 0, 0 };
 999         uint16_t ena_qid;
1000         unsigned int i;
1001         int rc;
1002
1003         ctx.msix_vector = -1;
1004         if (ring->type == ENA_RING_TYPE_TX) {
1005                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1006                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1007                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1008                 for (i = 0; i < ring->ring_size; i++)
1009                         ring->empty_tx_reqs[i] = i;
1010         } else {
1011                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1012                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1013                 if (rte_intr_dp_is_en(intr_handle))
1014                         ctx.msix_vector = intr_handle->intr_vec[ring->id];
1015                 for (i = 0; i < ring->ring_size; i++)
1016                         ring->empty_rx_reqs[i] = i;
1017         }
1018         ctx.queue_size = ring->ring_size;
1019         ctx.qid = ena_qid;
1020         ctx.numa_node = ring->numa_socket_id;
1021
1022         rc = ena_com_create_io_queue(ena_dev, &ctx);
1023         if (rc) {
1024                 PMD_DRV_LOG(ERR,
1025                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1026                         ring->id, ena_qid, rc);
1027                 return rc;
1028         }
1029
1030         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1031                                      &ring->ena_com_io_sq,
1032                                      &ring->ena_com_io_cq);
1033         if (rc) {
1034                 PMD_DRV_LOG(ERR,
1035                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1036                         ring->id, rc);
1037                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1038                 return rc;
1039         }
1040
1041         if (ring->type == ENA_RING_TYPE_TX)
1042                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1043
1044         /* Start with Rx interrupts being masked. */
1045         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1046                 ena_rx_queue_intr_disable(dev, ring->id);
1047
1048         return 0;
1049 }
1050
1051 static void ena_queue_stop(struct ena_ring *ring)
1052 {
1053         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1054
1055         if (ring->type == ENA_RING_TYPE_RX) {
1056                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1057                 ena_rx_queue_release_bufs(ring);
1058         } else {
1059                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1060                 ena_tx_queue_release_bufs(ring);
1061         }
1062 }
1063
1064 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1065                               enum ena_ring_type ring_type)
1066 {
1067         struct ena_adapter *adapter = dev->data->dev_private;
1068         struct ena_ring *queues = NULL;
1069         uint16_t nb_queues, i;
1070
1071         if (ring_type == ENA_RING_TYPE_RX) {
1072                 queues = adapter->rx_ring;
1073                 nb_queues = dev->data->nb_rx_queues;
1074         } else {
1075                 queues = adapter->tx_ring;
1076                 nb_queues = dev->data->nb_tx_queues;
1077         }
1078
1079         for (i = 0; i < nb_queues; ++i)
1080                 if (queues[i].configured)
1081                         ena_queue_stop(&queues[i]);
1082 }
1083
1084 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1085 {
1086         int rc, bufs_num;
1087
1088         ena_assert_msg(ring->configured == 1,
1089                        "Trying to start unconfigured queue\n");
1090
1091         rc = ena_create_io_queue(dev, ring);
1092         if (rc) {
1093                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1094                 return rc;
1095         }
1096
1097         ring->next_to_clean = 0;
1098         ring->next_to_use = 0;
1099
1100         if (ring->type == ENA_RING_TYPE_TX) {
1101                 ring->tx_stats.available_desc =
1102                         ena_com_free_q_entries(ring->ena_com_io_sq);
1103                 return 0;
1104         }
1105
1106         bufs_num = ring->ring_size - 1;
1107         rc = ena_populate_rx_queue(ring, bufs_num);
1108         if (rc != bufs_num) {
1109                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1110                                          ENA_IO_RXQ_IDX(ring->id));
1111                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1112                 return ENA_COM_FAULT;
1113         }
1114         /* Flush per-core RX buffers pools cache as they can be used on other
1115          * cores as well.
1116          */
1117         rte_mempool_cache_flush(NULL, ring->mb_pool);
1118
1119         return 0;
1120 }
1121
1122 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1123                               uint16_t queue_idx,
1124                               uint16_t nb_desc,
1125                               unsigned int socket_id,
1126                               const struct rte_eth_txconf *tx_conf)
1127 {
1128         struct ena_ring *txq = NULL;
1129         struct ena_adapter *adapter = dev->data->dev_private;
1130         unsigned int i;
1131
1132         txq = &adapter->tx_ring[queue_idx];
1133
1134         if (txq->configured) {
1135                 PMD_DRV_LOG(CRIT,
1136                         "API violation. Queue[%d] is already configured\n",
1137                         queue_idx);
1138                 return ENA_COM_FAULT;
1139         }
1140
1141         if (!rte_is_power_of_2(nb_desc)) {
1142                 PMD_DRV_LOG(ERR,
1143                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1144                         nb_desc);
1145                 return -EINVAL;
1146         }
1147
1148         if (nb_desc > adapter->max_tx_ring_size) {
1149                 PMD_DRV_LOG(ERR,
1150                         "Unsupported size of Tx queue (max size: %d)\n",
1151                         adapter->max_tx_ring_size);
1152                 return -EINVAL;
1153         }
1154
1155         txq->port_id = dev->data->port_id;
1156         txq->next_to_clean = 0;
1157         txq->next_to_use = 0;
1158         txq->ring_size = nb_desc;
1159         txq->size_mask = nb_desc - 1;
1160         txq->numa_socket_id = socket_id;
1161         txq->pkts_without_db = false;
1162
1163         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1164                                           sizeof(struct ena_tx_buffer) *
1165                                           txq->ring_size,
1166                                           RTE_CACHE_LINE_SIZE);
1167         if (!txq->tx_buffer_info) {
1168                 PMD_DRV_LOG(ERR,
1169                         "Failed to allocate memory for Tx buffer info\n");
1170                 return -ENOMEM;
1171         }
1172
1173         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1174                                          sizeof(u16) * txq->ring_size,
1175                                          RTE_CACHE_LINE_SIZE);
1176         if (!txq->empty_tx_reqs) {
1177                 PMD_DRV_LOG(ERR,
1178                         "Failed to allocate memory for empty Tx requests\n");
1179                 rte_free(txq->tx_buffer_info);
1180                 return -ENOMEM;
1181         }
1182
1183         txq->push_buf_intermediate_buf =
1184                 rte_zmalloc("txq->push_buf_intermediate_buf",
1185                             txq->tx_max_header_size,
1186                             RTE_CACHE_LINE_SIZE);
1187         if (!txq->push_buf_intermediate_buf) {
1188                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1189                 rte_free(txq->tx_buffer_info);
1190                 rte_free(txq->empty_tx_reqs);
1191                 return -ENOMEM;
1192         }
1193
1194         for (i = 0; i < txq->ring_size; i++)
1195                 txq->empty_tx_reqs[i] = i;
1196
1197         if (tx_conf != NULL) {
1198                 txq->offloads =
1199                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1200         }
1201         /* Store pointer to this queue in upper layer */
1202         txq->configured = 1;
1203         dev->data->tx_queues[queue_idx] = txq;
1204
1205         return 0;
1206 }
1207
1208 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1209                               uint16_t queue_idx,
1210                               uint16_t nb_desc,
1211                               unsigned int socket_id,
1212                               const struct rte_eth_rxconf *rx_conf,
1213                               struct rte_mempool *mp)
1214 {
1215         struct ena_adapter *adapter = dev->data->dev_private;
1216         struct ena_ring *rxq = NULL;
1217         size_t buffer_size;
1218         int i;
1219
1220         rxq = &adapter->rx_ring[queue_idx];
1221         if (rxq->configured) {
1222                 PMD_DRV_LOG(CRIT,
1223                         "API violation. Queue[%d] is already configured\n",
1224                         queue_idx);
1225                 return ENA_COM_FAULT;
1226         }
1227
1228         if (!rte_is_power_of_2(nb_desc)) {
1229                 PMD_DRV_LOG(ERR,
1230                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1231                         nb_desc);
1232                 return -EINVAL;
1233         }
1234
1235         if (nb_desc > adapter->max_rx_ring_size) {
1236                 PMD_DRV_LOG(ERR,
1237                         "Unsupported size of Rx queue (max size: %d)\n",
1238                         adapter->max_rx_ring_size);
1239                 return -EINVAL;
1240         }
1241
1242         /* ENA isn't supporting buffers smaller than 1400 bytes */
1243         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1244         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1245                 PMD_DRV_LOG(ERR,
1246                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1247                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1248                 return -EINVAL;
1249         }
1250
1251         rxq->port_id = dev->data->port_id;
1252         rxq->next_to_clean = 0;
1253         rxq->next_to_use = 0;
1254         rxq->ring_size = nb_desc;
1255         rxq->size_mask = nb_desc - 1;
1256         rxq->numa_socket_id = socket_id;
1257         rxq->mb_pool = mp;
1258
1259         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1260                 sizeof(struct ena_rx_buffer) * nb_desc,
1261                 RTE_CACHE_LINE_SIZE);
1262         if (!rxq->rx_buffer_info) {
1263                 PMD_DRV_LOG(ERR,
1264                         "Failed to allocate memory for Rx buffer info\n");
1265                 return -ENOMEM;
1266         }
1267
1268         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1269                                             sizeof(struct rte_mbuf *) * nb_desc,
1270                                             RTE_CACHE_LINE_SIZE);
1271
1272         if (!rxq->rx_refill_buffer) {
1273                 PMD_DRV_LOG(ERR,
1274                         "Failed to allocate memory for Rx refill buffer\n");
1275                 rte_free(rxq->rx_buffer_info);
1276                 rxq->rx_buffer_info = NULL;
1277                 return -ENOMEM;
1278         }
1279
1280         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1281                                          sizeof(uint16_t) * nb_desc,
1282                                          RTE_CACHE_LINE_SIZE);
1283         if (!rxq->empty_rx_reqs) {
1284                 PMD_DRV_LOG(ERR,
1285                         "Failed to allocate memory for empty Rx requests\n");
1286                 rte_free(rxq->rx_buffer_info);
1287                 rxq->rx_buffer_info = NULL;
1288                 rte_free(rxq->rx_refill_buffer);
1289                 rxq->rx_refill_buffer = NULL;
1290                 return -ENOMEM;
1291         }
1292
1293         for (i = 0; i < nb_desc; i++)
1294                 rxq->empty_rx_reqs[i] = i;
1295
1296         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1297
1298         /* Store pointer to this queue in upper layer */
1299         rxq->configured = 1;
1300         dev->data->rx_queues[queue_idx] = rxq;
1301
1302         return 0;
1303 }
1304
1305 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1306                                   struct rte_mbuf *mbuf, uint16_t id)
1307 {
1308         struct ena_com_buf ebuf;
1309         int rc;
1310
1311         /* prepare physical address for DMA transaction */
1312         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1313         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1314
1315         /* pass resource to device */
1316         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1317         if (unlikely(rc != 0))
1318                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1319
1320         return rc;
1321 }
1322
1323 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1324 {
1325         unsigned int i;
1326         int rc;
1327         uint16_t next_to_use = rxq->next_to_use;
1328         uint16_t req_id;
1329 #ifdef RTE_ETHDEV_DEBUG_RX
1330         uint16_t in_use;
1331 #endif
1332         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1333
1334         if (unlikely(!count))
1335                 return 0;
1336
1337 #ifdef RTE_ETHDEV_DEBUG_RX
1338         in_use = rxq->ring_size - 1 -
1339                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1340         if (unlikely((in_use + count) >= rxq->ring_size))
1341                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1342 #endif
1343
1344         /* get resources for incoming packets */
1345         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1346         if (unlikely(rc < 0)) {
1347                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1348                 ++rxq->rx_stats.mbuf_alloc_fail;
1349                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1350                 return 0;
1351         }
1352
1353         for (i = 0; i < count; i++) {
1354                 struct rte_mbuf *mbuf = mbufs[i];
1355                 struct ena_rx_buffer *rx_info;
1356
1357                 if (likely((i + 4) < count))
1358                         rte_prefetch0(mbufs[i + 4]);
1359
1360                 req_id = rxq->empty_rx_reqs[next_to_use];
1361                 rx_info = &rxq->rx_buffer_info[req_id];
1362
1363                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1364                 if (unlikely(rc != 0))
1365                         break;
1366
1367                 rx_info->mbuf = mbuf;
1368                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1369         }
1370
1371         if (unlikely(i < count)) {
1372                 PMD_RX_LOG(WARNING,
1373                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1374                         rxq->id, i, count);
1375                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1376                 ++rxq->rx_stats.refill_partial;
1377         }
1378
1379         /* When we submitted free recources to device... */
1380         if (likely(i > 0)) {
1381                 /* ...let HW know that it can fill buffers with data. */
1382                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1383
1384                 rxq->next_to_use = next_to_use;
1385         }
1386
1387         return i;
1388 }
1389
1390 static int ena_device_init(struct ena_com_dev *ena_dev,
1391                            struct rte_pci_device *pdev,
1392                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1393                            bool *wd_state)
1394 {
1395         uint32_t aenq_groups;
1396         int rc;
1397         bool readless_supported;
1398
1399         /* Initialize mmio registers */
1400         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1401         if (rc) {
1402                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1403                 return rc;
1404         }
1405
1406         /* The PCIe configuration space revision id indicate if mmio reg
1407          * read is disabled.
1408          */
1409         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1410         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1411
1412         /* reset device */
1413         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1414         if (rc) {
1415                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1416                 goto err_mmio_read_less;
1417         }
1418
1419         /* check FW version */
1420         rc = ena_com_validate_version(ena_dev);
1421         if (rc) {
1422                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1423                 goto err_mmio_read_less;
1424         }
1425
1426         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1427
1428         /* ENA device administration layer init */
1429         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1430         if (rc) {
1431                 PMD_DRV_LOG(ERR,
1432                         "Cannot initialize ENA admin queue\n");
1433                 goto err_mmio_read_less;
1434         }
1435
1436         /* To enable the msix interrupts the driver needs to know the number
1437          * of queues. So the driver uses polling mode to retrieve this
1438          * information.
1439          */
1440         ena_com_set_admin_polling_mode(ena_dev, true);
1441
1442         ena_config_host_info(ena_dev);
1443
1444         /* Get Device Attributes and features */
1445         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1446         if (rc) {
1447                 PMD_DRV_LOG(ERR,
1448                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1449                 goto err_admin_init;
1450         }
1451
1452         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1453                       BIT(ENA_ADMIN_NOTIFICATION) |
1454                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1455                       BIT(ENA_ADMIN_FATAL_ERROR) |
1456                       BIT(ENA_ADMIN_WARNING);
1457
1458         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1459         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1460         if (rc) {
1461                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc);
1462                 goto err_admin_init;
1463         }
1464
1465         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1466
1467         return 0;
1468
1469 err_admin_init:
1470         ena_com_admin_destroy(ena_dev);
1471
1472 err_mmio_read_less:
1473         ena_com_mmio_reg_read_request_destroy(ena_dev);
1474
1475         return rc;
1476 }
1477
1478 static void ena_interrupt_handler_rte(void *cb_arg)
1479 {
1480         struct rte_eth_dev *dev = cb_arg;
1481         struct ena_adapter *adapter = dev->data->dev_private;
1482         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1483
1484         ena_com_admin_q_comp_intr_handler(ena_dev);
1485         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1486                 ena_com_aenq_intr_handler(ena_dev, dev);
1487 }
1488
1489 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1490 {
1491         if (!adapter->wd_state)
1492                 return;
1493
1494         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1495                 return;
1496
1497         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1498             adapter->keep_alive_timeout)) {
1499                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1500                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1501                 adapter->trigger_reset = true;
1502                 ++adapter->dev_stats.wd_expired;
1503         }
1504 }
1505
1506 /* Check if admin queue is enabled */
1507 static void check_for_admin_com_state(struct ena_adapter *adapter)
1508 {
1509         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1510                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1511                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1512                 adapter->trigger_reset = true;
1513         }
1514 }
1515
1516 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1517                                   void *arg)
1518 {
1519         struct rte_eth_dev *dev = arg;
1520         struct ena_adapter *adapter = dev->data->dev_private;
1521
1522         check_for_missing_keep_alive(adapter);
1523         check_for_admin_com_state(adapter);
1524
1525         if (unlikely(adapter->trigger_reset)) {
1526                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1527                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1528                         NULL);
1529         }
1530 }
1531
1532 static inline void
1533 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1534                                struct ena_admin_feature_llq_desc *llq,
1535                                bool use_large_llq_hdr)
1536 {
1537         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1538         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1539         llq_config->llq_num_decs_before_header =
1540                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1541
1542         if (use_large_llq_hdr &&
1543             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1544                 llq_config->llq_ring_entry_size =
1545                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1546                 llq_config->llq_ring_entry_size_value = 256;
1547         } else {
1548                 llq_config->llq_ring_entry_size =
1549                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1550                 llq_config->llq_ring_entry_size_value = 128;
1551         }
1552 }
1553
1554 static int
1555 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1556                                 struct ena_com_dev *ena_dev,
1557                                 struct ena_admin_feature_llq_desc *llq,
1558                                 struct ena_llq_configurations *llq_default_configurations)
1559 {
1560         int rc;
1561         u32 llq_feature_mask;
1562
1563         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1564         if (!(ena_dev->supported_features & llq_feature_mask)) {
1565                 PMD_DRV_LOG(INFO,
1566                         "LLQ is not supported. Fallback to host mode policy.\n");
1567                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1568                 return 0;
1569         }
1570
1571         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1572         if (unlikely(rc)) {
1573                 PMD_INIT_LOG(WARNING,
1574                         "Failed to config dev mode. Fallback to host mode policy.\n");
1575                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1576                 return 0;
1577         }
1578
1579         /* Nothing to config, exit */
1580         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1581                 return 0;
1582
1583         if (!adapter->dev_mem_base) {
1584                 PMD_DRV_LOG(ERR,
1585                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1586                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1587                 return 0;
1588         }
1589
1590         ena_dev->mem_bar = adapter->dev_mem_base;
1591
1592         return 0;
1593 }
1594
1595 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1596         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1597 {
1598         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1599
1600         /* Regular queues capabilities */
1601         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1602                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1603                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1604                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1605                                     max_queue_ext->max_rx_cq_num);
1606                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1607                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1608         } else {
1609                 struct ena_admin_queue_feature_desc *max_queues =
1610                         &get_feat_ctx->max_queues;
1611                 io_tx_sq_num = max_queues->max_sq_num;
1612                 io_tx_cq_num = max_queues->max_cq_num;
1613                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1614         }
1615
1616         /* In case of LLQ use the llq number in the get feature cmd */
1617         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1618                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1619
1620         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1621         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1622         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1623
1624         if (unlikely(max_num_io_queues == 0)) {
1625                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1626                 return -EFAULT;
1627         }
1628
1629         return max_num_io_queues;
1630 }
1631
1632 static void
1633 ena_set_offloads(struct ena_offloads *offloads,
1634                  struct ena_admin_feature_offload_desc *offload_desc)
1635 {
1636         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1637                 offloads->tx_offloads |= ENA_IPV4_TSO;
1638
1639         /* Tx IPv4 checksum offloads */
1640         if (offload_desc->tx &
1641             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
1642                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
1643         if (offload_desc->tx &
1644             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
1645                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
1646         if (offload_desc->tx &
1647             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1648                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
1649
1650         /* Tx IPv6 checksum offloads */
1651         if (offload_desc->tx &
1652             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
1653                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
1654         if (offload_desc->tx &
1655              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
1656                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
1657
1658         /* Rx IPv4 checksum offloads */
1659         if (offload_desc->rx_supported &
1660             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
1661                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
1662         if (offload_desc->rx_supported &
1663             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1664                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
1665
1666         /* Rx IPv6 checksum offloads */
1667         if (offload_desc->rx_supported &
1668             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
1669                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
1670
1671         if (offload_desc->rx_supported &
1672             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
1673                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
1674 }
1675
1676 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1677 {
1678         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1679         struct rte_pci_device *pci_dev;
1680         struct rte_intr_handle *intr_handle;
1681         struct ena_adapter *adapter = eth_dev->data->dev_private;
1682         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1683         struct ena_com_dev_get_features_ctx get_feat_ctx;
1684         struct ena_llq_configurations llq_config;
1685         const char *queue_type_str;
1686         uint32_t max_num_io_queues;
1687         int rc;
1688         static int adapters_found;
1689         bool disable_meta_caching;
1690         bool wd_state = false;
1691
1692         eth_dev->dev_ops = &ena_dev_ops;
1693         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1694         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1695         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1696
1697         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698                 return 0;
1699
1700         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1701
1702         memset(adapter, 0, sizeof(struct ena_adapter));
1703         ena_dev = &adapter->ena_dev;
1704
1705         adapter->edev_data = eth_dev->data;
1706
1707         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1708
1709         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1710                      pci_dev->addr.domain,
1711                      pci_dev->addr.bus,
1712                      pci_dev->addr.devid,
1713                      pci_dev->addr.function);
1714
1715         intr_handle = &pci_dev->intr_handle;
1716
1717         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1718         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1719
1720         if (!adapter->regs) {
1721                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1722                              ENA_REGS_BAR);
1723                 return -ENXIO;
1724         }
1725
1726         ena_dev->reg_bar = adapter->regs;
1727         /* This is a dummy pointer for ena_com functions. */
1728         ena_dev->dmadev = adapter;
1729
1730         adapter->id_number = adapters_found;
1731
1732         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1733                  adapter->id_number);
1734
1735         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1736         if (rc != 0) {
1737                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1738                 goto err;
1739         }
1740
1741         /* device specific initialization routine */
1742         rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1743         if (rc) {
1744                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1745                 goto err;
1746         }
1747         adapter->wd_state = wd_state;
1748
1749         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1750                 adapter->use_large_llq_hdr);
1751         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1752                                              &get_feat_ctx.llq, &llq_config);
1753         if (unlikely(rc)) {
1754                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1755                 return rc;
1756         }
1757
1758         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1759                 queue_type_str = "Regular";
1760         else
1761                 queue_type_str = "Low latency";
1762         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1763
1764         calc_queue_ctx.ena_dev = ena_dev;
1765         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1766
1767         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1768         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1769                 adapter->use_large_llq_hdr);
1770         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1771                 rc = -EFAULT;
1772                 goto err_device_destroy;
1773         }
1774
1775         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1776         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1777         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1778         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1779         adapter->max_num_io_queues = max_num_io_queues;
1780
1781         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1782                 disable_meta_caching =
1783                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1784                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1785         } else {
1786                 disable_meta_caching = false;
1787         }
1788
1789         /* prepare ring structures */
1790         ena_init_rings(adapter, disable_meta_caching);
1791
1792         ena_config_debug_area(adapter);
1793
1794         /* Set max MTU for this device */
1795         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1796
1797         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
1798
1799         /* Copy MAC address and point DPDK to it */
1800         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1801         rte_ether_addr_copy((struct rte_ether_addr *)
1802                         get_feat_ctx.dev_attr.mac_addr,
1803                         (struct rte_ether_addr *)adapter->mac_addr);
1804
1805         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1806         if (unlikely(rc != 0)) {
1807                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1808                 goto err_delete_debug_area;
1809         }
1810
1811         adapter->drv_stats = rte_zmalloc("adapter stats",
1812                                          sizeof(*adapter->drv_stats),
1813                                          RTE_CACHE_LINE_SIZE);
1814         if (!adapter->drv_stats) {
1815                 PMD_DRV_LOG(ERR,
1816                         "Failed to allocate memory for adapter statistics\n");
1817                 rc = -ENOMEM;
1818                 goto err_rss_destroy;
1819         }
1820
1821         rte_spinlock_init(&adapter->admin_lock);
1822
1823         rte_intr_callback_register(intr_handle,
1824                                    ena_interrupt_handler_rte,
1825                                    eth_dev);
1826         rte_intr_enable(intr_handle);
1827         ena_com_set_admin_polling_mode(ena_dev, false);
1828         ena_com_admin_aenq_enable(ena_dev);
1829
1830         if (adapters_found == 0)
1831                 rte_timer_subsystem_init();
1832         rte_timer_init(&adapter->timer_wd);
1833
1834         adapters_found++;
1835         adapter->state = ENA_ADAPTER_STATE_INIT;
1836
1837         return 0;
1838
1839 err_rss_destroy:
1840         ena_com_rss_destroy(ena_dev);
1841 err_delete_debug_area:
1842         ena_com_delete_debug_area(ena_dev);
1843
1844 err_device_destroy:
1845         ena_com_delete_host_info(ena_dev);
1846         ena_com_admin_destroy(ena_dev);
1847
1848 err:
1849         return rc;
1850 }
1851
1852 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1853 {
1854         struct ena_adapter *adapter = eth_dev->data->dev_private;
1855         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1856
1857         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1858                 return;
1859
1860         ena_com_set_admin_running_state(ena_dev, false);
1861
1862         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1863                 ena_close(eth_dev);
1864
1865         ena_com_rss_destroy(ena_dev);
1866
1867         ena_com_delete_debug_area(ena_dev);
1868         ena_com_delete_host_info(ena_dev);
1869
1870         ena_com_abort_admin_commands(ena_dev);
1871         ena_com_wait_for_abort_completion(ena_dev);
1872         ena_com_admin_destroy(ena_dev);
1873         ena_com_mmio_reg_read_request_destroy(ena_dev);
1874
1875         adapter->state = ENA_ADAPTER_STATE_FREE;
1876 }
1877
1878 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1879 {
1880         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1881                 return 0;
1882
1883         ena_destroy_device(eth_dev);
1884
1885         return 0;
1886 }
1887
1888 static int ena_dev_configure(struct rte_eth_dev *dev)
1889 {
1890         struct ena_adapter *adapter = dev->data->dev_private;
1891
1892         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1893
1894         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1895                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1896         dev->data->dev_conf.txmode.offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
1897
1898         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1899         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1900         return 0;
1901 }
1902
1903 static void ena_init_rings(struct ena_adapter *adapter,
1904                            bool disable_meta_caching)
1905 {
1906         size_t i;
1907
1908         for (i = 0; i < adapter->max_num_io_queues; i++) {
1909                 struct ena_ring *ring = &adapter->tx_ring[i];
1910
1911                 ring->configured = 0;
1912                 ring->type = ENA_RING_TYPE_TX;
1913                 ring->adapter = adapter;
1914                 ring->id = i;
1915                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1916                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1917                 ring->sgl_size = adapter->max_tx_sgl_size;
1918                 ring->disable_meta_caching = disable_meta_caching;
1919         }
1920
1921         for (i = 0; i < adapter->max_num_io_queues; i++) {
1922                 struct ena_ring *ring = &adapter->rx_ring[i];
1923
1924                 ring->configured = 0;
1925                 ring->type = ENA_RING_TYPE_RX;
1926                 ring->adapter = adapter;
1927                 ring->id = i;
1928                 ring->sgl_size = adapter->max_rx_sgl_size;
1929         }
1930 }
1931
1932 static int ena_infos_get(struct rte_eth_dev *dev,
1933                           struct rte_eth_dev_info *dev_info)
1934 {
1935         struct ena_adapter *adapter;
1936         struct ena_com_dev *ena_dev;
1937         uint64_t rx_feat = 0, tx_feat = 0;
1938
1939         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1940         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1941         adapter = dev->data->dev_private;
1942
1943         ena_dev = &adapter->ena_dev;
1944         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1945
1946         dev_info->speed_capa =
1947                         ETH_LINK_SPEED_1G   |
1948                         ETH_LINK_SPEED_2_5G |
1949                         ETH_LINK_SPEED_5G   |
1950                         ETH_LINK_SPEED_10G  |
1951                         ETH_LINK_SPEED_25G  |
1952                         ETH_LINK_SPEED_40G  |
1953                         ETH_LINK_SPEED_50G  |
1954                         ETH_LINK_SPEED_100G;
1955
1956         /* Set Tx & Rx features available for device */
1957         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
1958                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1959
1960         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
1961                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM;
1962         if (adapter->offloads.tx_offloads &
1963             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
1964              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
1965                 tx_feat |= DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM;
1966
1967         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
1968                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM;
1969         if (adapter->offloads.rx_offloads &
1970             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
1971                 rx_feat |= DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM;
1972
1973         tx_feat |= DEV_TX_OFFLOAD_MULTI_SEGS;
1974
1975         /* Inform framework about available features */
1976         dev_info->rx_offload_capa = rx_feat;
1977         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
1978                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1979         dev_info->rx_queue_offload_capa = rx_feat;
1980         dev_info->tx_offload_capa = tx_feat;
1981         dev_info->tx_queue_offload_capa = tx_feat;
1982
1983         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
1984         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
1985
1986         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1987         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
1988                 RTE_ETHER_CRC_LEN;
1989         dev_info->min_mtu = ENA_MIN_MTU;
1990         dev_info->max_mtu = adapter->max_mtu;
1991         dev_info->max_mac_addrs = 1;
1992
1993         dev_info->max_rx_queues = adapter->max_num_io_queues;
1994         dev_info->max_tx_queues = adapter->max_num_io_queues;
1995         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1996
1997         adapter->tx_supported_offloads = tx_feat;
1998         adapter->rx_supported_offloads = rx_feat;
1999
2000         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2001         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2002         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2003                                         adapter->max_rx_sgl_size);
2004         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2005                                         adapter->max_rx_sgl_size);
2006
2007         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2008         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2009         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2010                                         adapter->max_tx_sgl_size);
2011         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2012                                         adapter->max_tx_sgl_size);
2013
2014         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2015         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2016
2017         return 0;
2018 }
2019
2020 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2021 {
2022         mbuf->data_len = len;
2023         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2024         mbuf->refcnt = 1;
2025         mbuf->next = NULL;
2026 }
2027
2028 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2029                                     struct ena_com_rx_buf_info *ena_bufs,
2030                                     uint32_t descs,
2031                                     uint16_t *next_to_clean,
2032                                     uint8_t offset)
2033 {
2034         struct rte_mbuf *mbuf;
2035         struct rte_mbuf *mbuf_head;
2036         struct ena_rx_buffer *rx_info;
2037         int rc;
2038         uint16_t ntc, len, req_id, buf = 0;
2039
2040         if (unlikely(descs == 0))
2041                 return NULL;
2042
2043         ntc = *next_to_clean;
2044
2045         len = ena_bufs[buf].len;
2046         req_id = ena_bufs[buf].req_id;
2047
2048         rx_info = &rx_ring->rx_buffer_info[req_id];
2049
2050         mbuf = rx_info->mbuf;
2051         RTE_ASSERT(mbuf != NULL);
2052
2053         ena_init_rx_mbuf(mbuf, len);
2054
2055         /* Fill the mbuf head with the data specific for 1st segment. */
2056         mbuf_head = mbuf;
2057         mbuf_head->nb_segs = descs;
2058         mbuf_head->port = rx_ring->port_id;
2059         mbuf_head->pkt_len = len;
2060         mbuf_head->data_off += offset;
2061
2062         rx_info->mbuf = NULL;
2063         rx_ring->empty_rx_reqs[ntc] = req_id;
2064         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2065
2066         while (--descs) {
2067                 ++buf;
2068                 len = ena_bufs[buf].len;
2069                 req_id = ena_bufs[buf].req_id;
2070
2071                 rx_info = &rx_ring->rx_buffer_info[req_id];
2072                 RTE_ASSERT(rx_info->mbuf != NULL);
2073
2074                 if (unlikely(len == 0)) {
2075                         /*
2076                          * Some devices can pass descriptor with the length 0.
2077                          * To avoid confusion, the PMD is simply putting the
2078                          * descriptor back, as it was never used. We'll avoid
2079                          * mbuf allocation that way.
2080                          */
2081                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2082                                 rx_info->mbuf, req_id);
2083                         if (unlikely(rc != 0)) {
2084                                 /* Free the mbuf in case of an error. */
2085                                 rte_mbuf_raw_free(rx_info->mbuf);
2086                         } else {
2087                                 /*
2088                                  * If there was no error, just exit the loop as
2089                                  * 0 length descriptor is always the last one.
2090                                  */
2091                                 break;
2092                         }
2093                 } else {
2094                         /* Create an mbuf chain. */
2095                         mbuf->next = rx_info->mbuf;
2096                         mbuf = mbuf->next;
2097
2098                         ena_init_rx_mbuf(mbuf, len);
2099                         mbuf_head->pkt_len += len;
2100                 }
2101
2102                 /*
2103                  * Mark the descriptor as depleted and perform necessary
2104                  * cleanup.
2105                  * This code will execute in two cases:
2106                  *  1. Descriptor len was greater than 0 - normal situation.
2107                  *  2. Descriptor len was 0 and we failed to add the descriptor
2108                  *     to the device. In that situation, we should try to add
2109                  *     the mbuf again in the populate routine and mark the
2110                  *     descriptor as used up by the device.
2111                  */
2112                 rx_info->mbuf = NULL;
2113                 rx_ring->empty_rx_reqs[ntc] = req_id;
2114                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2115         }
2116
2117         *next_to_clean = ntc;
2118
2119         return mbuf_head;
2120 }
2121
2122 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2123                                   uint16_t nb_pkts)
2124 {
2125         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2126         unsigned int free_queue_entries;
2127         unsigned int refill_threshold;
2128         uint16_t next_to_clean = rx_ring->next_to_clean;
2129         uint16_t descs_in_use;
2130         struct rte_mbuf *mbuf;
2131         uint16_t completed;
2132         struct ena_com_rx_ctx ena_rx_ctx;
2133         int i, rc = 0;
2134         bool fill_hash;
2135
2136 #ifdef RTE_ETHDEV_DEBUG_RX
2137         /* Check adapter state */
2138         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2139                 PMD_RX_LOG(ALERT,
2140                         "Trying to receive pkts while device is NOT running\n");
2141                 return 0;
2142         }
2143 #endif
2144
2145         fill_hash = rx_ring->offloads & DEV_RX_OFFLOAD_RSS_HASH;
2146
2147         descs_in_use = rx_ring->ring_size -
2148                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2149         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2150
2151         for (completed = 0; completed < nb_pkts; completed++) {
2152                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2153                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2154                 ena_rx_ctx.descs = 0;
2155                 ena_rx_ctx.pkt_offset = 0;
2156                 /* receive packet context */
2157                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2158                                     rx_ring->ena_com_io_sq,
2159                                     &ena_rx_ctx);
2160                 if (unlikely(rc)) {
2161                         PMD_RX_LOG(ERR,
2162                                 "Failed to get the packet from the device, rc: %d\n",
2163                                 rc);
2164                         if (rc == ENA_COM_NO_SPACE) {
2165                                 ++rx_ring->rx_stats.bad_desc_num;
2166                                 rx_ring->adapter->reset_reason =
2167                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2168                         } else {
2169                                 ++rx_ring->rx_stats.bad_req_id;
2170                                 rx_ring->adapter->reset_reason =
2171                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2172                         }
2173                         rx_ring->adapter->trigger_reset = true;
2174                         return 0;
2175                 }
2176
2177                 mbuf = ena_rx_mbuf(rx_ring,
2178                         ena_rx_ctx.ena_bufs,
2179                         ena_rx_ctx.descs,
2180                         &next_to_clean,
2181                         ena_rx_ctx.pkt_offset);
2182                 if (unlikely(mbuf == NULL)) {
2183                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2184                                 rx_ring->empty_rx_reqs[next_to_clean] =
2185                                         rx_ring->ena_bufs[i].req_id;
2186                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2187                                         next_to_clean, rx_ring->size_mask);
2188                         }
2189                         break;
2190                 }
2191
2192                 /* fill mbuf attributes if any */
2193                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash);
2194
2195                 if (unlikely(mbuf->ol_flags &
2196                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2197                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2198                         ++rx_ring->rx_stats.bad_csum;
2199                 }
2200
2201                 rx_pkts[completed] = mbuf;
2202                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2203         }
2204
2205         rx_ring->rx_stats.cnt += completed;
2206         rx_ring->next_to_clean = next_to_clean;
2207
2208         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2209         refill_threshold =
2210                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2211                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2212
2213         /* Burst refill to save doorbells, memory barriers, const interval */
2214         if (free_queue_entries > refill_threshold) {
2215                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2216                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2217         }
2218
2219         return completed;
2220 }
2221
2222 static uint16_t
2223 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2224                 uint16_t nb_pkts)
2225 {
2226         int32_t ret;
2227         uint32_t i;
2228         struct rte_mbuf *m;
2229         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2230         struct ena_adapter *adapter = tx_ring->adapter;
2231         struct rte_ipv4_hdr *ip_hdr;
2232         uint64_t ol_flags;
2233         uint64_t l4_csum_flag;
2234         uint64_t dev_offload_capa;
2235         uint16_t frag_field;
2236         bool need_pseudo_csum;
2237
2238         dev_offload_capa = adapter->offloads.tx_offloads;
2239         for (i = 0; i != nb_pkts; i++) {
2240                 m = tx_pkts[i];
2241                 ol_flags = m->ol_flags;
2242
2243                 /* Check if any offload flag was set */
2244                 if (ol_flags == 0)
2245                         continue;
2246
2247                 l4_csum_flag = ol_flags & PKT_TX_L4_MASK;
2248                 /* SCTP checksum offload is not supported by the ENA. */
2249                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2250                     l4_csum_flag == PKT_TX_SCTP_CKSUM) {
2251                         PMD_TX_LOG(DEBUG,
2252                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2253                                 i, ol_flags);
2254                         rte_errno = ENOTSUP;
2255                         return i;
2256                 }
2257
2258 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2259                 /* Check if requested offload is also enabled for the queue */
2260                 if ((ol_flags & PKT_TX_IP_CKSUM &&
2261                      !(tx_ring->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) ||
2262                     (l4_csum_flag == PKT_TX_TCP_CKSUM &&
2263                      !(tx_ring->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) ||
2264                     (l4_csum_flag == PKT_TX_UDP_CKSUM &&
2265                      !(tx_ring->offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) {
2266                         PMD_TX_LOG(DEBUG,
2267                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2268                                 i, m->nb_segs, tx_ring->id);
2269                         rte_errno = EINVAL;
2270                         return i;
2271                 }
2272
2273                 /* The caller is obligated to set l2 and l3 len if any cksum
2274                  * offload is enabled.
2275                  */
2276                 if (unlikely(ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK) &&
2277                     (m->l2_len == 0 || m->l3_len == 0))) {
2278                         PMD_TX_LOG(DEBUG,
2279                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2280                                 i);
2281                         rte_errno = EINVAL;
2282                         return i;
2283                 }
2284                 ret = rte_validate_tx_offload(m);
2285                 if (ret != 0) {
2286                         rte_errno = -ret;
2287                         return i;
2288                 }
2289 #endif
2290
2291                 /* Verify HW support for requested offloads and determine if
2292                  * pseudo header checksum is needed.
2293                  */
2294                 need_pseudo_csum = false;
2295                 if (ol_flags & PKT_TX_IPV4) {
2296                         if (ol_flags & PKT_TX_IP_CKSUM &&
2297                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2298                                 rte_errno = ENOTSUP;
2299                                 return i;
2300                         }
2301
2302                         if (ol_flags & PKT_TX_TCP_SEG &&
2303                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2304                                 rte_errno = ENOTSUP;
2305                                 return i;
2306                         }
2307
2308                         /* Check HW capabilities and if pseudo csum is needed
2309                          * for L4 offloads.
2310                          */
2311                         if (l4_csum_flag != PKT_TX_L4_NO_CKSUM &&
2312                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2313                                 if (dev_offload_capa &
2314                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2315                                         need_pseudo_csum = true;
2316                                 } else {
2317                                         rte_errno = ENOTSUP;
2318                                         return i;
2319                                 }
2320                         }
2321
2322                         /* Parse the DF flag */
2323                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2324                                 struct rte_ipv4_hdr *, m->l2_len);
2325                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2326                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2327                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2328                         } else if (ol_flags & PKT_TX_TCP_SEG) {
2329                                 /* In case we are supposed to TSO and have DF
2330                                  * not set (DF=0) hardware must be provided with
2331                                  * partial checksum.
2332                                  */
2333                                 need_pseudo_csum = true;
2334                         }
2335                 } else if (ol_flags & PKT_TX_IPV6) {
2336                         /* There is no support for IPv6 TSO as for now. */
2337                         if (ol_flags & PKT_TX_TCP_SEG) {
2338                                 rte_errno = ENOTSUP;
2339                                 return i;
2340                         }
2341
2342                         /* Check HW capabilities and if pseudo csum is needed */
2343                         if (l4_csum_flag != PKT_TX_L4_NO_CKSUM &&
2344                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2345                                 if (dev_offload_capa &
2346                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2347                                         need_pseudo_csum = true;
2348                                 } else {
2349                                         rte_errno = ENOTSUP;
2350                                         return i;
2351                                 }
2352                         }
2353                 }
2354
2355                 if (need_pseudo_csum) {
2356                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2357                         if (ret != 0) {
2358                                 rte_errno = -ret;
2359                                 return i;
2360                         }
2361                 }
2362         }
2363
2364         return i;
2365 }
2366
2367 static void ena_update_hints(struct ena_adapter *adapter,
2368                              struct ena_admin_ena_hw_hints *hints)
2369 {
2370         if (hints->admin_completion_tx_timeout)
2371                 adapter->ena_dev.admin_queue.completion_timeout =
2372                         hints->admin_completion_tx_timeout * 1000;
2373
2374         if (hints->mmio_read_timeout)
2375                 /* convert to usec */
2376                 adapter->ena_dev.mmio_read.reg_read_to =
2377                         hints->mmio_read_timeout * 1000;
2378
2379         if (hints->driver_watchdog_timeout) {
2380                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2381                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2382                 else
2383                         // Convert msecs to ticks
2384                         adapter->keep_alive_timeout =
2385                                 (hints->driver_watchdog_timeout *
2386                                 rte_get_timer_hz()) / 1000;
2387         }
2388 }
2389
2390 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2391                                               struct rte_mbuf *mbuf)
2392 {
2393         struct ena_com_dev *ena_dev;
2394         int num_segments, header_len, rc;
2395
2396         ena_dev = &tx_ring->adapter->ena_dev;
2397         num_segments = mbuf->nb_segs;
2398         header_len = mbuf->data_len;
2399
2400         if (likely(num_segments < tx_ring->sgl_size))
2401                 goto checkspace;
2402
2403         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2404             (num_segments == tx_ring->sgl_size) &&
2405             (header_len < tx_ring->tx_max_header_size))
2406                 goto checkspace;
2407
2408         /* Checking for space for 2 additional metadata descriptors due to
2409          * possible header split and metadata descriptor. Linearization will
2410          * be needed so we reduce the segments number from num_segments to 1
2411          */
2412         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2413                 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2414                 return ENA_COM_NO_MEM;
2415         }
2416         ++tx_ring->tx_stats.linearize;
2417         rc = rte_pktmbuf_linearize(mbuf);
2418         if (unlikely(rc)) {
2419                 PMD_TX_LOG(WARNING, "Mbuf linearize failed\n");
2420                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2421                 ++tx_ring->tx_stats.linearize_failed;
2422                 return rc;
2423         }
2424
2425         return 0;
2426
2427 checkspace:
2428         /* Checking for space for 2 additional metadata descriptors due to
2429          * possible header split and metadata descriptor
2430          */
2431         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2432                                           num_segments + 2)) {
2433                 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2434                 return ENA_COM_NO_MEM;
2435         }
2436
2437         return 0;
2438 }
2439
2440 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2441         struct ena_tx_buffer *tx_info,
2442         struct rte_mbuf *mbuf,
2443         void **push_header,
2444         uint16_t *header_len)
2445 {
2446         struct ena_com_buf *ena_buf;
2447         uint16_t delta, seg_len, push_len;
2448
2449         delta = 0;
2450         seg_len = mbuf->data_len;
2451
2452         tx_info->mbuf = mbuf;
2453         ena_buf = tx_info->bufs;
2454
2455         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2456                 /*
2457                  * Tx header might be (and will be in most cases) smaller than
2458                  * tx_max_header_size. But it's not an issue to send more data
2459                  * to the device, than actually needed if the mbuf size is
2460                  * greater than tx_max_header_size.
2461                  */
2462                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2463                 *header_len = push_len;
2464
2465                 if (likely(push_len <= seg_len)) {
2466                         /* If the push header is in the single segment, then
2467                          * just point it to the 1st mbuf data.
2468                          */
2469                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2470                 } else {
2471                         /* If the push header lays in the several segments, copy
2472                          * it to the intermediate buffer.
2473                          */
2474                         rte_pktmbuf_read(mbuf, 0, push_len,
2475                                 tx_ring->push_buf_intermediate_buf);
2476                         *push_header = tx_ring->push_buf_intermediate_buf;
2477                         delta = push_len - seg_len;
2478                 }
2479         } else {
2480                 *push_header = NULL;
2481                 *header_len = 0;
2482                 push_len = 0;
2483         }
2484
2485         /* Process first segment taking into consideration pushed header */
2486         if (seg_len > push_len) {
2487                 ena_buf->paddr = mbuf->buf_iova +
2488                                 mbuf->data_off +
2489                                 push_len;
2490                 ena_buf->len = seg_len - push_len;
2491                 ena_buf++;
2492                 tx_info->num_of_bufs++;
2493         }
2494
2495         while ((mbuf = mbuf->next) != NULL) {
2496                 seg_len = mbuf->data_len;
2497
2498                 /* Skip mbufs if whole data is pushed as a header */
2499                 if (unlikely(delta > seg_len)) {
2500                         delta -= seg_len;
2501                         continue;
2502                 }
2503
2504                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2505                 ena_buf->len = seg_len - delta;
2506                 ena_buf++;
2507                 tx_info->num_of_bufs++;
2508
2509                 delta = 0;
2510         }
2511 }
2512
2513 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2514 {
2515         struct ena_tx_buffer *tx_info;
2516         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2517         uint16_t next_to_use;
2518         uint16_t header_len;
2519         uint16_t req_id;
2520         void *push_header;
2521         int nb_hw_desc;
2522         int rc;
2523
2524         rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2525         if (unlikely(rc))
2526                 return rc;
2527
2528         next_to_use = tx_ring->next_to_use;
2529
2530         req_id = tx_ring->empty_tx_reqs[next_to_use];
2531         tx_info = &tx_ring->tx_buffer_info[req_id];
2532         tx_info->num_of_bufs = 0;
2533
2534         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2535
2536         ena_tx_ctx.ena_bufs = tx_info->bufs;
2537         ena_tx_ctx.push_header = push_header;
2538         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2539         ena_tx_ctx.req_id = req_id;
2540         ena_tx_ctx.header_len = header_len;
2541
2542         /* Set Tx offloads flags, if applicable */
2543         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2544                 tx_ring->disable_meta_caching);
2545
2546         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2547                         &ena_tx_ctx))) {
2548                 PMD_TX_LOG(DEBUG,
2549                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2550                         tx_ring->id);
2551                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2552                 tx_ring->tx_stats.doorbells++;
2553                 tx_ring->pkts_without_db = false;
2554         }
2555
2556         /* prepare the packet's descriptors to dma engine */
2557         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2558                 &nb_hw_desc);
2559         if (unlikely(rc)) {
2560                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2561                 ++tx_ring->tx_stats.prepare_ctx_err;
2562                 tx_ring->adapter->reset_reason =
2563                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2564                 tx_ring->adapter->trigger_reset = true;
2565                 return rc;
2566         }
2567
2568         tx_info->tx_descs = nb_hw_desc;
2569
2570         tx_ring->tx_stats.cnt++;
2571         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2572
2573         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2574                 tx_ring->size_mask);
2575
2576         return 0;
2577 }
2578
2579 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2580 {
2581         unsigned int cleanup_budget;
2582         unsigned int total_tx_descs = 0;
2583         uint16_t next_to_clean = tx_ring->next_to_clean;
2584
2585         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2586                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2587
2588         while (likely(total_tx_descs < cleanup_budget)) {
2589                 struct rte_mbuf *mbuf;
2590                 struct ena_tx_buffer *tx_info;
2591                 uint16_t req_id;
2592
2593                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2594                         break;
2595
2596                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2597                         break;
2598
2599                 /* Get Tx info & store how many descs were processed  */
2600                 tx_info = &tx_ring->tx_buffer_info[req_id];
2601
2602                 mbuf = tx_info->mbuf;
2603                 rte_pktmbuf_free(mbuf);
2604
2605                 tx_info->mbuf = NULL;
2606                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2607
2608                 total_tx_descs += tx_info->tx_descs;
2609
2610                 /* Put back descriptor to the ring for reuse */
2611                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2612                         tx_ring->size_mask);
2613         }
2614
2615         if (likely(total_tx_descs > 0)) {
2616                 /* acknowledge completion of sent packets */
2617                 tx_ring->next_to_clean = next_to_clean;
2618                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2619                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2620         }
2621 }
2622
2623 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2624                                   uint16_t nb_pkts)
2625 {
2626         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2627         uint16_t sent_idx = 0;
2628
2629 #ifdef RTE_ETHDEV_DEBUG_TX
2630         /* Check adapter state */
2631         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2632                 PMD_TX_LOG(ALERT,
2633                         "Trying to xmit pkts while device is NOT running\n");
2634                 return 0;
2635         }
2636 #endif
2637
2638         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2639                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2640                         break;
2641                 tx_ring->pkts_without_db = true;
2642                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2643                         tx_ring->size_mask)]);
2644         }
2645
2646         tx_ring->tx_stats.available_desc =
2647                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2648
2649         /* If there are ready packets to be xmitted... */
2650         if (likely(tx_ring->pkts_without_db)) {
2651                 /* ...let HW do its best :-) */
2652                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2653                 tx_ring->tx_stats.doorbells++;
2654                 tx_ring->pkts_without_db = false;
2655         }
2656
2657         ena_tx_cleanup(tx_ring);
2658
2659         tx_ring->tx_stats.available_desc =
2660                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2661         tx_ring->tx_stats.tx_poll++;
2662
2663         return sent_idx;
2664 }
2665
2666 int ena_copy_eni_stats(struct ena_adapter *adapter)
2667 {
2668         struct ena_admin_eni_stats admin_eni_stats;
2669         int rc;
2670
2671         rte_spinlock_lock(&adapter->admin_lock);
2672         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2673         rte_spinlock_unlock(&adapter->admin_lock);
2674         if (rc != 0) {
2675                 if (rc == ENA_COM_UNSUPPORTED) {
2676                         PMD_DRV_LOG(DEBUG,
2677                                 "Retrieving ENI metrics is not supported\n");
2678                 } else {
2679                         PMD_DRV_LOG(WARNING,
2680                                 "Failed to get ENI metrics, rc: %d\n", rc);
2681                 }
2682                 return rc;
2683         }
2684
2685         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2686                 sizeof(struct ena_stats_eni));
2687
2688         return 0;
2689 }
2690
2691 /**
2692  * DPDK callback to retrieve names of extended device statistics
2693  *
2694  * @param dev
2695  *   Pointer to Ethernet device structure.
2696  * @param[out] xstats_names
2697  *   Buffer to insert names into.
2698  * @param n
2699  *   Number of names.
2700  *
2701  * @return
2702  *   Number of xstats names.
2703  */
2704 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2705                                 struct rte_eth_xstat_name *xstats_names,
2706                                 unsigned int n)
2707 {
2708         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2709         unsigned int stat, i, count = 0;
2710
2711         if (n < xstats_count || !xstats_names)
2712                 return xstats_count;
2713
2714         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2715                 strcpy(xstats_names[count].name,
2716                         ena_stats_global_strings[stat].name);
2717
2718         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2719                 strcpy(xstats_names[count].name,
2720                         ena_stats_eni_strings[stat].name);
2721
2722         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2723                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2724                         snprintf(xstats_names[count].name,
2725                                 sizeof(xstats_names[count].name),
2726                                 "rx_q%d_%s", i,
2727                                 ena_stats_rx_strings[stat].name);
2728
2729         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2730                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2731                         snprintf(xstats_names[count].name,
2732                                 sizeof(xstats_names[count].name),
2733                                 "tx_q%d_%s", i,
2734                                 ena_stats_tx_strings[stat].name);
2735
2736         return xstats_count;
2737 }
2738
2739 /**
2740  * DPDK callback to get extended device statistics.
2741  *
2742  * @param dev
2743  *   Pointer to Ethernet device structure.
2744  * @param[out] stats
2745  *   Stats table output buffer.
2746  * @param n
2747  *   The size of the stats table.
2748  *
2749  * @return
2750  *   Number of xstats on success, negative on failure.
2751  */
2752 static int ena_xstats_get(struct rte_eth_dev *dev,
2753                           struct rte_eth_xstat *xstats,
2754                           unsigned int n)
2755 {
2756         struct ena_adapter *adapter = dev->data->dev_private;
2757         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2758         unsigned int stat, i, count = 0;
2759         int stat_offset;
2760         void *stats_begin;
2761
2762         if (n < xstats_count)
2763                 return xstats_count;
2764
2765         if (!xstats)
2766                 return 0;
2767
2768         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2769                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2770                 stats_begin = &adapter->dev_stats;
2771
2772                 xstats[count].id = count;
2773                 xstats[count].value = *((uint64_t *)
2774                         ((char *)stats_begin + stat_offset));
2775         }
2776
2777         /* Even if the function below fails, we should copy previous (or initial
2778          * values) to keep structure of rte_eth_xstat consistent.
2779          */
2780         ena_copy_eni_stats(adapter);
2781         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2782                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2783                 stats_begin = &adapter->eni_stats;
2784
2785                 xstats[count].id = count;
2786                 xstats[count].value = *((uint64_t *)
2787                     ((char *)stats_begin + stat_offset));
2788         }
2789
2790         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2791                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2792                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2793                         stats_begin = &adapter->rx_ring[i].rx_stats;
2794
2795                         xstats[count].id = count;
2796                         xstats[count].value = *((uint64_t *)
2797                                 ((char *)stats_begin + stat_offset));
2798                 }
2799         }
2800
2801         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2802                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2803                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2804                         stats_begin = &adapter->tx_ring[i].rx_stats;
2805
2806                         xstats[count].id = count;
2807                         xstats[count].value = *((uint64_t *)
2808                                 ((char *)stats_begin + stat_offset));
2809                 }
2810         }
2811
2812         return count;
2813 }
2814
2815 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2816                                 const uint64_t *ids,
2817                                 uint64_t *values,
2818                                 unsigned int n)
2819 {
2820         struct ena_adapter *adapter = dev->data->dev_private;
2821         uint64_t id;
2822         uint64_t rx_entries, tx_entries;
2823         unsigned int i;
2824         int qid;
2825         int valid = 0;
2826         bool was_eni_copied = false;
2827
2828         for (i = 0; i < n; ++i) {
2829                 id = ids[i];
2830                 /* Check if id belongs to global statistics */
2831                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2832                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2833                         ++valid;
2834                         continue;
2835                 }
2836
2837                 /* Check if id belongs to ENI statistics */
2838                 id -= ENA_STATS_ARRAY_GLOBAL;
2839                 if (id < ENA_STATS_ARRAY_ENI) {
2840                         /* Avoid reading ENI stats multiple times in a single
2841                          * function call, as it requires communication with the
2842                          * admin queue.
2843                          */
2844                         if (!was_eni_copied) {
2845                                 was_eni_copied = true;
2846                                 ena_copy_eni_stats(adapter);
2847                         }
2848                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2849                         ++valid;
2850                         continue;
2851                 }
2852
2853                 /* Check if id belongs to rx queue statistics */
2854                 id -= ENA_STATS_ARRAY_ENI;
2855                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2856                 if (id < rx_entries) {
2857                         qid = id % dev->data->nb_rx_queues;
2858                         id /= dev->data->nb_rx_queues;
2859                         values[i] = *((uint64_t *)
2860                                 &adapter->rx_ring[qid].rx_stats + id);
2861                         ++valid;
2862                         continue;
2863                 }
2864                                 /* Check if id belongs to rx queue statistics */
2865                 id -= rx_entries;
2866                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2867                 if (id < tx_entries) {
2868                         qid = id % dev->data->nb_tx_queues;
2869                         id /= dev->data->nb_tx_queues;
2870                         values[i] = *((uint64_t *)
2871                                 &adapter->tx_ring[qid].tx_stats + id);
2872                         ++valid;
2873                         continue;
2874                 }
2875         }
2876
2877         return valid;
2878 }
2879
2880 static int ena_process_bool_devarg(const char *key,
2881                                    const char *value,
2882                                    void *opaque)
2883 {
2884         struct ena_adapter *adapter = opaque;
2885         bool bool_value;
2886
2887         /* Parse the value. */
2888         if (strcmp(value, "1") == 0) {
2889                 bool_value = true;
2890         } else if (strcmp(value, "0") == 0) {
2891                 bool_value = false;
2892         } else {
2893                 PMD_INIT_LOG(ERR,
2894                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2895                         value, key);
2896                 return -EINVAL;
2897         }
2898
2899         /* Now, assign it to the proper adapter field. */
2900         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2901                 adapter->use_large_llq_hdr = bool_value;
2902
2903         return 0;
2904 }
2905
2906 static int ena_parse_devargs(struct ena_adapter *adapter,
2907                              struct rte_devargs *devargs)
2908 {
2909         static const char * const allowed_args[] = {
2910                 ENA_DEVARG_LARGE_LLQ_HDR,
2911                 NULL,
2912         };
2913         struct rte_kvargs *kvlist;
2914         int rc;
2915
2916         if (devargs == NULL)
2917                 return 0;
2918
2919         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2920         if (kvlist == NULL) {
2921                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2922                         devargs->args);
2923                 return -EINVAL;
2924         }
2925
2926         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2927                 ena_process_bool_devarg, adapter);
2928
2929         rte_kvargs_free(kvlist);
2930
2931         return rc;
2932 }
2933
2934 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
2935 {
2936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2938         int rc;
2939         uint16_t vectors_nb, i;
2940         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
2941
2942         if (!rx_intr_requested)
2943                 return 0;
2944
2945         if (!rte_intr_cap_multiple(intr_handle)) {
2946                 PMD_DRV_LOG(ERR,
2947                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
2948                 return -ENOTSUP;
2949         }
2950
2951         /* Disable interrupt mapping before the configuration starts. */
2952         rte_intr_disable(intr_handle);
2953
2954         /* Verify if there are enough vectors available. */
2955         vectors_nb = dev->data->nb_rx_queues;
2956         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
2957                 PMD_DRV_LOG(ERR,
2958                         "Too many Rx interrupts requested, maximum number: %d\n",
2959                         RTE_MAX_RXTX_INTR_VEC_ID);
2960                 rc = -ENOTSUP;
2961                 goto enable_intr;
2962         }
2963
2964         intr_handle->intr_vec = rte_zmalloc("intr_vec",
2965                 dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0);
2966         if (intr_handle->intr_vec == NULL) {
2967                 PMD_DRV_LOG(ERR,
2968                         "Failed to allocate interrupt vector for %d queues\n",
2969                         dev->data->nb_rx_queues);
2970                 rc = -ENOMEM;
2971                 goto enable_intr;
2972         }
2973
2974         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
2975         if (rc != 0)
2976                 goto free_intr_vec;
2977
2978         if (!rte_intr_allow_others(intr_handle)) {
2979                 PMD_DRV_LOG(ERR,
2980                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
2981                 goto disable_intr_efd;
2982         }
2983
2984         for (i = 0; i < vectors_nb; ++i)
2985                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i;
2986
2987         rte_intr_enable(intr_handle);
2988         return 0;
2989
2990 disable_intr_efd:
2991         rte_intr_efd_disable(intr_handle);
2992 free_intr_vec:
2993         rte_free(intr_handle->intr_vec);
2994         intr_handle->intr_vec = NULL;
2995 enable_intr:
2996         rte_intr_enable(intr_handle);
2997         return rc;
2998 }
2999
3000 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3001                                  uint16_t queue_id,
3002                                  bool unmask)
3003 {
3004         struct ena_adapter *adapter = dev->data->dev_private;
3005         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3006         struct ena_eth_io_intr_reg intr_reg;
3007
3008         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3009         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3010 }
3011
3012 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3013                                     uint16_t queue_id)
3014 {
3015         ena_rx_queue_intr_set(dev, queue_id, true);
3016
3017         return 0;
3018 }
3019
3020 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3021                                      uint16_t queue_id)
3022 {
3023         ena_rx_queue_intr_set(dev, queue_id, false);
3024
3025         return 0;
3026 }
3027
3028 /*********************************************************************
3029  *  PMD configuration
3030  *********************************************************************/
3031 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3032         struct rte_pci_device *pci_dev)
3033 {
3034         return rte_eth_dev_pci_generic_probe(pci_dev,
3035                 sizeof(struct ena_adapter), eth_ena_dev_init);
3036 }
3037
3038 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3039 {
3040         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3041 }
3042
3043 static struct rte_pci_driver rte_ena_pmd = {
3044         .id_table = pci_id_ena_map,
3045         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3046                      RTE_PCI_DRV_WC_ACTIVATE,
3047         .probe = eth_ena_pci_probe,
3048         .remove = eth_ena_pci_remove,
3049 };
3050
3051 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3052 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3053 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3054 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3055 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3056 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3057 #ifdef RTE_ETHDEV_DEBUG_RX
3058 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3059 #endif
3060 #ifdef RTE_ETHDEV_DEBUG_TX
3061 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3062 #endif
3063 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3064
3065 /******************************************************************************
3066  ******************************** AENQ Handlers *******************************
3067  *****************************************************************************/
3068 static void ena_update_on_link_change(void *adapter_data,
3069                                       struct ena_admin_aenq_entry *aenq_e)
3070 {
3071         struct rte_eth_dev *eth_dev = adapter_data;
3072         struct ena_adapter *adapter = eth_dev->data->dev_private;
3073         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3074         uint32_t status;
3075
3076         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3077
3078         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3079         adapter->link_status = status;
3080
3081         ena_link_update(eth_dev, 0);
3082         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3083 }
3084
3085 static void ena_notification(void *adapter_data,
3086                              struct ena_admin_aenq_entry *aenq_e)
3087 {
3088         struct rte_eth_dev *eth_dev = adapter_data;
3089         struct ena_adapter *adapter = eth_dev->data->dev_private;
3090         struct ena_admin_ena_hw_hints *hints;
3091
3092         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3093                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3094                         aenq_e->aenq_common_desc.group,
3095                         ENA_ADMIN_NOTIFICATION);
3096
3097         switch (aenq_e->aenq_common_desc.syndrome) {
3098         case ENA_ADMIN_UPDATE_HINTS:
3099                 hints = (struct ena_admin_ena_hw_hints *)
3100                         (&aenq_e->inline_data_w4);
3101                 ena_update_hints(adapter, hints);
3102                 break;
3103         default:
3104                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3105                         aenq_e->aenq_common_desc.syndrome);
3106         }
3107 }
3108
3109 static void ena_keep_alive(void *adapter_data,
3110                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3111 {
3112         struct rte_eth_dev *eth_dev = adapter_data;
3113         struct ena_adapter *adapter = eth_dev->data->dev_private;
3114         struct ena_admin_aenq_keep_alive_desc *desc;
3115         uint64_t rx_drops;
3116         uint64_t tx_drops;
3117
3118         adapter->timestamp_wd = rte_get_timer_cycles();
3119
3120         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3121         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3122         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3123
3124         adapter->drv_stats->rx_drops = rx_drops;
3125         adapter->dev_stats.tx_drops = tx_drops;
3126 }
3127
3128 /**
3129  * This handler will called for unknown event group or unimplemented handlers
3130  **/
3131 static void unimplemented_aenq_handler(__rte_unused void *data,
3132                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3133 {
3134         PMD_DRV_LOG(ERR,
3135                 "Unknown event was received or event with unimplemented handler\n");
3136 }
3137
3138 static struct ena_aenq_handlers aenq_handlers = {
3139         .handlers = {
3140                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3141                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3142                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3143         },
3144         .unimplemented_handler = unimplemented_aenq_handler
3145 };