4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 0
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 enum ethtool_stringset {
94 char name[ETH_GSTRING_LEN];
98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
103 #define ENA_STAT_ENTRY(stat, stat_type) { \
105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
108 #define ENA_STAT_RX_ENTRY(stat) \
109 ENA_STAT_ENTRY(stat, rx)
111 #define ENA_STAT_TX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, tx)
114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, dev)
117 static const struct ena_stats ena_stats_global_strings[] = {
118 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
119 ENA_STAT_GLOBAL_ENTRY(io_suspend),
120 ENA_STAT_GLOBAL_ENTRY(io_resume),
121 ENA_STAT_GLOBAL_ENTRY(wd_expired),
122 ENA_STAT_GLOBAL_ENTRY(interface_up),
123 ENA_STAT_GLOBAL_ENTRY(interface_down),
124 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
127 static const struct ena_stats ena_stats_tx_strings[] = {
128 ENA_STAT_TX_ENTRY(cnt),
129 ENA_STAT_TX_ENTRY(bytes),
130 ENA_STAT_TX_ENTRY(queue_stop),
131 ENA_STAT_TX_ENTRY(queue_wakeup),
132 ENA_STAT_TX_ENTRY(dma_mapping_err),
133 ENA_STAT_TX_ENTRY(linearize),
134 ENA_STAT_TX_ENTRY(linearize_failed),
135 ENA_STAT_TX_ENTRY(tx_poll),
136 ENA_STAT_TX_ENTRY(doorbells),
137 ENA_STAT_TX_ENTRY(prepare_ctx_err),
138 ENA_STAT_TX_ENTRY(missing_tx_comp),
139 ENA_STAT_TX_ENTRY(bad_req_id),
142 static const struct ena_stats ena_stats_rx_strings[] = {
143 ENA_STAT_RX_ENTRY(cnt),
144 ENA_STAT_RX_ENTRY(bytes),
145 ENA_STAT_RX_ENTRY(refil_partial),
146 ENA_STAT_RX_ENTRY(bad_csum),
147 ENA_STAT_RX_ENTRY(page_alloc_fail),
148 ENA_STAT_RX_ENTRY(skb_alloc_fail),
149 ENA_STAT_RX_ENTRY(dma_mapping_err),
150 ENA_STAT_RX_ENTRY(bad_desc_num),
151 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
154 static const struct ena_stats ena_stats_ena_com_strings[] = {
155 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
156 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
157 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
158 ENA_STAT_ENA_COM_ENTRY(out_of_space),
159 ENA_STAT_ENA_COM_ENTRY(no_completion),
162 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
163 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
164 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
167 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
168 DEV_TX_OFFLOAD_UDP_CKSUM |\
169 DEV_TX_OFFLOAD_IPV4_CKSUM |\
170 DEV_TX_OFFLOAD_TCP_TSO)
171 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
175 /** Vendor ID used by Amazon devices */
176 #define PCI_VENDOR_ID_AMAZON 0x1D0F
177 /** Amazon devices */
178 #define PCI_DEVICE_ID_ENA_VF 0xEC20
179 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
181 #define ENA_TX_OFFLOAD_MASK (\
186 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
187 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
189 int ena_logtype_init;
190 int ena_logtype_driver;
192 static const struct rte_pci_id pci_id_ena_map[] = {
193 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
194 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
198 static int ena_device_init(struct ena_com_dev *ena_dev,
199 struct ena_com_dev_get_features_ctx *get_feat_ctx);
200 static int ena_dev_configure(struct rte_eth_dev *dev);
201 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
203 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
205 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
206 uint16_t nb_desc, unsigned int socket_id,
207 const struct rte_eth_txconf *tx_conf);
208 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
209 uint16_t nb_desc, unsigned int socket_id,
210 const struct rte_eth_rxconf *rx_conf,
211 struct rte_mempool *mp);
212 static uint16_t eth_ena_recv_pkts(void *rx_queue,
213 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
214 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
215 static void ena_init_rings(struct ena_adapter *adapter);
216 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
217 static int ena_start(struct rte_eth_dev *dev);
218 static void ena_close(struct rte_eth_dev *dev);
219 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
220 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
221 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
222 static void ena_rx_queue_release(void *queue);
223 static void ena_tx_queue_release(void *queue);
224 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
225 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
226 static int ena_link_update(struct rte_eth_dev *dev,
227 int wait_to_complete);
228 static int ena_queue_restart(struct ena_ring *ring);
229 static int ena_queue_restart_all(struct rte_eth_dev *dev,
230 enum ena_ring_type ring_type);
231 static void ena_stats_restart(struct rte_eth_dev *dev);
232 static void ena_infos_get(struct rte_eth_dev *dev,
233 struct rte_eth_dev_info *dev_info);
234 static int ena_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ena_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
241 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
244 static const struct eth_dev_ops ena_dev_ops = {
245 .dev_configure = ena_dev_configure,
246 .dev_infos_get = ena_infos_get,
247 .rx_queue_setup = ena_rx_queue_setup,
248 .tx_queue_setup = ena_tx_queue_setup,
249 .dev_start = ena_start,
250 .link_update = ena_link_update,
251 .stats_get = ena_stats_get,
252 .mtu_set = ena_mtu_set,
253 .rx_queue_release = ena_rx_queue_release,
254 .tx_queue_release = ena_tx_queue_release,
255 .dev_close = ena_close,
256 .reta_update = ena_rss_reta_update,
257 .reta_query = ena_rss_reta_query,
260 #define NUMA_NO_NODE SOCKET_ID_ANY
262 static inline int ena_cpu_to_node(int cpu)
264 struct rte_config *config = rte_eal_get_configuration();
266 if (likely(cpu < RTE_MAX_MEMZONE))
267 return config->mem_config->memzone[cpu].socket_id;
272 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
273 struct ena_com_rx_ctx *ena_rx_ctx)
275 uint64_t ol_flags = 0;
277 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
278 ol_flags |= PKT_TX_TCP_CKSUM;
279 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
280 ol_flags |= PKT_TX_UDP_CKSUM;
282 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
283 ol_flags |= PKT_TX_IPV4;
284 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
285 ol_flags |= PKT_TX_IPV6;
287 if (unlikely(ena_rx_ctx->l4_csum_err))
288 ol_flags |= PKT_RX_L4_CKSUM_BAD;
289 if (unlikely(ena_rx_ctx->l3_csum_err))
290 ol_flags |= PKT_RX_IP_CKSUM_BAD;
292 mbuf->ol_flags = ol_flags;
295 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
296 struct ena_com_tx_ctx *ena_tx_ctx,
297 uint64_t queue_offloads)
299 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
301 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
302 (queue_offloads & QUEUE_OFFLOADS)) {
303 /* check if TSO is required */
304 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
305 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
306 ena_tx_ctx->tso_enable = true;
308 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
311 /* check if L3 checksum is needed */
312 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
313 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
314 ena_tx_ctx->l3_csum_enable = true;
316 if (mbuf->ol_flags & PKT_TX_IPV6) {
317 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
319 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
321 /* set don't fragment (DF) flag */
322 if (mbuf->packet_type &
323 (RTE_PTYPE_L4_NONFRAG
324 | RTE_PTYPE_INNER_L4_NONFRAG))
325 ena_tx_ctx->df = true;
328 /* check if L4 checksum is needed */
329 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
330 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
331 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
332 ena_tx_ctx->l4_csum_enable = true;
333 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
334 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
335 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
336 ena_tx_ctx->l4_csum_enable = true;
338 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
339 ena_tx_ctx->l4_csum_enable = false;
342 ena_meta->mss = mbuf->tso_segsz;
343 ena_meta->l3_hdr_len = mbuf->l3_len;
344 ena_meta->l3_hdr_offset = mbuf->l2_len;
345 /* this param needed only for TSO */
346 ena_meta->l3_outer_hdr_len = 0;
347 ena_meta->l3_outer_hdr_offset = 0;
349 ena_tx_ctx->meta_valid = true;
351 ena_tx_ctx->meta_valid = false;
355 static void ena_config_host_info(struct ena_com_dev *ena_dev)
357 struct ena_admin_host_info *host_info;
360 /* Allocate only the host info */
361 rc = ena_com_allocate_host_info(ena_dev);
363 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
367 host_info = ena_dev->host_attr.host_info;
369 host_info->os_type = ENA_ADMIN_OS_DPDK;
370 host_info->kernel_ver = RTE_VERSION;
371 snprintf((char *)host_info->kernel_ver_str,
372 sizeof(host_info->kernel_ver_str),
373 "%s", rte_version());
374 host_info->os_dist = RTE_VERSION;
375 snprintf((char *)host_info->os_dist_str,
376 sizeof(host_info->os_dist_str),
377 "%s", rte_version());
378 host_info->driver_version =
379 (DRV_MODULE_VER_MAJOR) |
380 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
381 (DRV_MODULE_VER_SUBMINOR <<
382 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
384 rc = ena_com_set_host_attributes(ena_dev);
386 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
394 ena_com_delete_host_info(ena_dev);
398 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
400 if (sset != ETH_SS_STATS)
403 /* Workaround for clang:
404 * touch internal structures to prevent
407 ENA_TOUCH(ena_stats_global_strings);
408 ENA_TOUCH(ena_stats_tx_strings);
409 ENA_TOUCH(ena_stats_rx_strings);
410 ENA_TOUCH(ena_stats_ena_com_strings);
412 return dev->data->nb_tx_queues *
413 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
414 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
417 static void ena_config_debug_area(struct ena_adapter *adapter)
422 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
424 RTE_LOG(ERR, PMD, "SS count is negative\n");
428 /* allocate 32 bytes for each string and 64bit for the value */
429 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
431 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
433 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
437 rc = ena_com_set_host_attributes(&adapter->ena_dev);
439 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
446 ena_com_delete_debug_area(&adapter->ena_dev);
449 static void ena_close(struct rte_eth_dev *dev)
451 struct ena_adapter *adapter =
452 (struct ena_adapter *)(dev->data->dev_private);
454 adapter->state = ENA_ADAPTER_STATE_STOPPED;
456 ena_rx_queue_release_all(dev);
457 ena_tx_queue_release_all(dev);
460 static int ena_rss_reta_update(struct rte_eth_dev *dev,
461 struct rte_eth_rss_reta_entry64 *reta_conf,
464 struct ena_adapter *adapter =
465 (struct ena_adapter *)(dev->data->dev_private);
466 struct ena_com_dev *ena_dev = &adapter->ena_dev;
472 if ((reta_size == 0) || (reta_conf == NULL))
475 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
476 RTE_LOG(WARNING, PMD,
477 "indirection table %d is bigger than supported (%d)\n",
478 reta_size, ENA_RX_RSS_TABLE_SIZE);
483 for (i = 0 ; i < reta_size ; i++) {
484 /* each reta_conf is for 64 entries.
485 * to support 128 we use 2 conf of 64
487 conf_idx = i / RTE_RETA_GROUP_SIZE;
488 idx = i % RTE_RETA_GROUP_SIZE;
489 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
491 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
492 ret = ena_com_indirect_table_fill_entry(ena_dev,
495 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
497 "Cannot fill indirect table\n");
504 ret = ena_com_indirect_table_set(ena_dev);
505 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
506 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
511 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
512 __func__, reta_size, adapter->rte_dev->data->port_id);
517 /* Query redirection table. */
518 static int ena_rss_reta_query(struct rte_eth_dev *dev,
519 struct rte_eth_rss_reta_entry64 *reta_conf,
522 struct ena_adapter *adapter =
523 (struct ena_adapter *)(dev->data->dev_private);
524 struct ena_com_dev *ena_dev = &adapter->ena_dev;
527 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
531 if (reta_size == 0 || reta_conf == NULL ||
532 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
535 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
536 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
537 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
542 for (i = 0 ; i < reta_size ; i++) {
543 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
544 reta_idx = i % RTE_RETA_GROUP_SIZE;
545 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
546 reta_conf[reta_conf_idx].reta[reta_idx] =
547 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
553 static int ena_rss_init_default(struct ena_adapter *adapter)
555 struct ena_com_dev *ena_dev = &adapter->ena_dev;
556 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
560 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
562 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
566 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
567 val = i % nb_rx_queues;
568 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
569 ENA_IO_RXQ_IDX(val));
570 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
571 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
576 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
577 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
578 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
579 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
583 rc = ena_com_set_default_hash_ctrl(ena_dev);
584 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
585 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
589 rc = ena_com_indirect_table_set(ena_dev);
590 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
591 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
594 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
595 adapter->rte_dev->data->port_id);
600 ena_com_rss_destroy(ena_dev);
606 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
608 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
609 int nb_queues = dev->data->nb_rx_queues;
612 for (i = 0; i < nb_queues; i++)
613 ena_rx_queue_release(queues[i]);
616 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
618 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
619 int nb_queues = dev->data->nb_tx_queues;
622 for (i = 0; i < nb_queues; i++)
623 ena_tx_queue_release(queues[i]);
626 static void ena_rx_queue_release(void *queue)
628 struct ena_ring *ring = (struct ena_ring *)queue;
629 struct ena_adapter *adapter = ring->adapter;
632 ena_assert_msg(ring->configured,
633 "API violation - releasing not configured queue");
634 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
637 /* Destroy HW queue */
638 ena_qid = ENA_IO_RXQ_IDX(ring->id);
639 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
642 ena_rx_queue_release_bufs(ring);
644 /* Free ring resources */
645 if (ring->rx_buffer_info)
646 rte_free(ring->rx_buffer_info);
647 ring->rx_buffer_info = NULL;
649 ring->configured = 0;
651 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
652 ring->port_id, ring->id);
655 static void ena_tx_queue_release(void *queue)
657 struct ena_ring *ring = (struct ena_ring *)queue;
658 struct ena_adapter *adapter = ring->adapter;
661 ena_assert_msg(ring->configured,
662 "API violation. Releasing not configured queue");
663 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
666 /* Destroy HW queue */
667 ena_qid = ENA_IO_TXQ_IDX(ring->id);
668 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
671 ena_tx_queue_release_bufs(ring);
673 /* Free ring resources */
674 if (ring->tx_buffer_info)
675 rte_free(ring->tx_buffer_info);
677 if (ring->empty_tx_reqs)
678 rte_free(ring->empty_tx_reqs);
680 ring->empty_tx_reqs = NULL;
681 ring->tx_buffer_info = NULL;
683 ring->configured = 0;
685 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
686 ring->port_id, ring->id);
689 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
691 unsigned int ring_mask = ring->ring_size - 1;
693 while (ring->next_to_clean != ring->next_to_use) {
695 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
698 rte_mbuf_raw_free(m);
700 ring->next_to_clean++;
704 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
708 for (i = 0; i < ring->ring_size; ++i) {
709 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
712 rte_pktmbuf_free(tx_buf->mbuf);
714 ring->next_to_clean++;
718 static int ena_link_update(struct rte_eth_dev *dev,
719 __rte_unused int wait_to_complete)
721 struct rte_eth_link *link = &dev->data->dev_link;
723 link->link_status = 1;
724 link->link_speed = ETH_SPEED_NUM_10G;
725 link->link_duplex = ETH_LINK_FULL_DUPLEX;
730 static int ena_queue_restart_all(struct rte_eth_dev *dev,
731 enum ena_ring_type ring_type)
733 struct ena_adapter *adapter =
734 (struct ena_adapter *)(dev->data->dev_private);
735 struct ena_ring *queues = NULL;
739 queues = (ring_type == ENA_RING_TYPE_RX) ?
740 adapter->rx_ring : adapter->tx_ring;
742 for (i = 0; i < adapter->num_queues; i++) {
743 if (queues[i].configured) {
744 if (ring_type == ENA_RING_TYPE_RX) {
746 dev->data->rx_queues[i] == &queues[i],
747 "Inconsistent state of rx queues\n");
750 dev->data->tx_queues[i] == &queues[i],
751 "Inconsistent state of tx queues\n");
754 rc = ena_queue_restart(&queues[i]);
758 "failed to restart queue %d type(%d)",
768 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
770 uint32_t max_frame_len = adapter->max_mtu;
772 if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
774 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
776 return max_frame_len;
779 static int ena_check_valid_conf(struct ena_adapter *adapter)
781 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
783 if (max_frame_len > adapter->max_mtu) {
784 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
792 ena_calc_queue_size(struct ena_com_dev *ena_dev,
793 struct ena_com_dev_get_features_ctx *get_feat_ctx)
795 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
797 queue_size = RTE_MIN(queue_size,
798 get_feat_ctx->max_queues.max_cq_depth);
799 queue_size = RTE_MIN(queue_size,
800 get_feat_ctx->max_queues.max_sq_depth);
802 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
803 queue_size = RTE_MIN(queue_size,
804 get_feat_ctx->max_queues.max_llq_depth);
806 /* Round down to power of 2 */
807 if (!rte_is_power_of_2(queue_size))
808 queue_size = rte_align32pow2(queue_size >> 1);
810 if (queue_size == 0) {
811 PMD_INIT_LOG(ERR, "Invalid queue size");
818 static void ena_stats_restart(struct rte_eth_dev *dev)
820 struct ena_adapter *adapter =
821 (struct ena_adapter *)(dev->data->dev_private);
823 rte_atomic64_init(&adapter->drv_stats->ierrors);
824 rte_atomic64_init(&adapter->drv_stats->oerrors);
825 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
828 static int ena_stats_get(struct rte_eth_dev *dev,
829 struct rte_eth_stats *stats)
831 struct ena_admin_basic_stats ena_stats;
832 struct ena_adapter *adapter =
833 (struct ena_adapter *)(dev->data->dev_private);
834 struct ena_com_dev *ena_dev = &adapter->ena_dev;
837 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
840 memset(&ena_stats, 0, sizeof(ena_stats));
841 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
843 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
847 /* Set of basic statistics from ENA */
848 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
849 ena_stats.rx_pkts_low);
850 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
851 ena_stats.tx_pkts_low);
852 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
853 ena_stats.rx_bytes_low);
854 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
855 ena_stats.tx_bytes_low);
856 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
857 ena_stats.rx_drops_low);
859 /* Driver related stats */
860 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
861 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
862 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
866 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
868 struct ena_adapter *adapter;
869 struct ena_com_dev *ena_dev;
872 ena_assert_msg(dev->data != NULL, "Uninitialized device");
873 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
874 adapter = (struct ena_adapter *)(dev->data->dev_private);
876 ena_dev = &adapter->ena_dev;
877 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
879 if (mtu > ena_get_mtu_conf(adapter)) {
881 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
882 mtu, ena_get_mtu_conf(adapter));
887 rc = ena_com_set_dev_mtu(ena_dev, mtu);
889 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
891 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
897 static int ena_start(struct rte_eth_dev *dev)
899 struct ena_adapter *adapter =
900 (struct ena_adapter *)(dev->data->dev_private);
903 if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
904 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
905 PMD_INIT_LOG(ERR, "API violation");
909 rc = ena_check_valid_conf(adapter);
913 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
917 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
921 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
922 ETH_MQ_RX_RSS_FLAG) {
923 rc = ena_rss_init_default(adapter);
928 ena_stats_restart(dev);
930 adapter->state = ENA_ADAPTER_STATE_RUNNING;
935 static int ena_queue_restart(struct ena_ring *ring)
939 ena_assert_msg(ring->configured == 1,
940 "Trying to restart unconfigured queue\n");
942 ring->next_to_clean = 0;
943 ring->next_to_use = 0;
945 if (ring->type == ENA_RING_TYPE_TX)
948 bufs_num = ring->ring_size - 1;
949 rc = ena_populate_rx_queue(ring, bufs_num);
950 if (rc != bufs_num) {
951 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
958 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
961 __rte_unused unsigned int socket_id,
962 const struct rte_eth_txconf *tx_conf)
964 struct ena_com_create_io_ctx ctx =
965 /* policy set to _HOST just to satisfy icc compiler */
966 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
967 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
968 struct ena_ring *txq = NULL;
969 struct ena_adapter *adapter =
970 (struct ena_adapter *)(dev->data->dev_private);
974 struct ena_com_dev *ena_dev = &adapter->ena_dev;
976 txq = &adapter->tx_ring[queue_idx];
978 if (txq->configured) {
980 "API violation. Queue %d is already configured\n",
985 if (!rte_is_power_of_2(nb_desc)) {
987 "Unsupported size of RX queue: %d is not a power of 2.",
992 if (nb_desc > adapter->tx_ring_size) {
994 "Unsupported size of TX queue (max size: %d)\n",
995 adapter->tx_ring_size);
999 if (tx_conf->txq_flags == ETH_TXQ_FLAGS_IGNORE &&
1000 !ena_are_tx_queue_offloads_allowed(adapter, tx_conf->offloads)) {
1001 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n");
1005 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1007 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1009 ctx.msix_vector = -1; /* admin interrupts not used */
1010 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1011 ctx.queue_size = adapter->tx_ring_size;
1012 ctx.numa_node = ena_cpu_to_node(queue_idx);
1014 rc = ena_com_create_io_queue(ena_dev, &ctx);
1017 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1018 queue_idx, ena_qid, rc);
1020 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1021 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1023 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1024 &txq->ena_com_io_sq,
1025 &txq->ena_com_io_cq);
1028 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1030 ena_com_destroy_io_queue(ena_dev, ena_qid);
1034 txq->port_id = dev->data->port_id;
1035 txq->next_to_clean = 0;
1036 txq->next_to_use = 0;
1037 txq->ring_size = nb_desc;
1039 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1040 sizeof(struct ena_tx_buffer) *
1042 RTE_CACHE_LINE_SIZE);
1043 if (!txq->tx_buffer_info) {
1044 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1048 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1049 sizeof(u16) * txq->ring_size,
1050 RTE_CACHE_LINE_SIZE);
1051 if (!txq->empty_tx_reqs) {
1052 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1053 rte_free(txq->tx_buffer_info);
1056 for (i = 0; i < txq->ring_size; i++)
1057 txq->empty_tx_reqs[i] = i;
1059 txq->offloads = tx_conf->offloads;
1061 /* Store pointer to this queue in upper layer */
1062 txq->configured = 1;
1063 dev->data->tx_queues[queue_idx] = txq;
1068 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1071 __rte_unused unsigned int socket_id,
1072 __rte_unused const struct rte_eth_rxconf *rx_conf,
1073 struct rte_mempool *mp)
1075 struct ena_com_create_io_ctx ctx =
1076 /* policy set to _HOST just to satisfy icc compiler */
1077 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1078 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1079 struct ena_adapter *adapter =
1080 (struct ena_adapter *)(dev->data->dev_private);
1081 struct ena_ring *rxq = NULL;
1082 uint16_t ena_qid = 0;
1084 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1086 rxq = &adapter->rx_ring[queue_idx];
1087 if (rxq->configured) {
1089 "API violation. Queue %d is already configured\n",
1094 if (!rte_is_power_of_2(nb_desc)) {
1096 "Unsupported size of TX queue: %d is not a power of 2.",
1101 if (nb_desc > adapter->rx_ring_size) {
1103 "Unsupported size of RX queue (max size: %d)\n",
1104 adapter->rx_ring_size);
1108 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1111 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1112 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1113 ctx.msix_vector = -1; /* admin interrupts not used */
1114 ctx.queue_size = adapter->rx_ring_size;
1115 ctx.numa_node = ena_cpu_to_node(queue_idx);
1117 rc = ena_com_create_io_queue(ena_dev, &ctx);
1119 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1122 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1123 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1125 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1126 &rxq->ena_com_io_sq,
1127 &rxq->ena_com_io_cq);
1130 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1132 ena_com_destroy_io_queue(ena_dev, ena_qid);
1135 rxq->port_id = dev->data->port_id;
1136 rxq->next_to_clean = 0;
1137 rxq->next_to_use = 0;
1138 rxq->ring_size = nb_desc;
1141 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1142 sizeof(struct rte_mbuf *) * nb_desc,
1143 RTE_CACHE_LINE_SIZE);
1144 if (!rxq->rx_buffer_info) {
1145 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1149 /* Store pointer to this queue in upper layer */
1150 rxq->configured = 1;
1151 dev->data->rx_queues[queue_idx] = rxq;
1156 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1160 uint16_t ring_size = rxq->ring_size;
1161 uint16_t ring_mask = ring_size - 1;
1162 uint16_t next_to_use = rxq->next_to_use;
1164 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1166 if (unlikely(!count))
1169 in_use = rxq->next_to_use - rxq->next_to_clean;
1170 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1172 count = RTE_MIN(count,
1173 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1175 /* get resources for incoming packets */
1176 rc = rte_mempool_get_bulk(rxq->mb_pool,
1177 (void **)(&mbufs[next_to_use & ring_mask]),
1179 if (unlikely(rc < 0)) {
1180 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1181 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1185 for (i = 0; i < count; i++) {
1186 uint16_t next_to_use_masked = next_to_use & ring_mask;
1187 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1188 struct ena_com_buf ebuf;
1190 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1191 /* prepare physical address for DMA transaction */
1192 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1193 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1194 /* pass resource to device */
1195 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1196 &ebuf, next_to_use_masked);
1198 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1200 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1206 /* When we submitted free recources to device... */
1208 /* ...let HW know that it can fill buffers with data */
1210 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1212 rxq->next_to_use = next_to_use;
1218 static int ena_device_init(struct ena_com_dev *ena_dev,
1219 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1222 bool readless_supported;
1224 /* Initialize mmio registers */
1225 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1227 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1231 /* The PCIe configuration space revision id indicate if mmio reg
1234 readless_supported =
1235 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1236 & ENA_MMIO_DISABLE_REG_READ);
1237 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1240 rc = ena_com_dev_reset(ena_dev);
1242 RTE_LOG(ERR, PMD, "cannot reset device\n");
1243 goto err_mmio_read_less;
1246 /* check FW version */
1247 rc = ena_com_validate_version(ena_dev);
1249 RTE_LOG(ERR, PMD, "device version is too low\n");
1250 goto err_mmio_read_less;
1253 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1255 /* ENA device administration layer init */
1256 rc = ena_com_admin_init(ena_dev, NULL, true);
1259 "cannot initialize ena admin queue with device\n");
1260 goto err_mmio_read_less;
1263 /* To enable the msix interrupts the driver needs to know the number
1264 * of queues. So the driver uses polling mode to retrieve this
1267 ena_com_set_admin_polling_mode(ena_dev, true);
1269 ena_config_host_info(ena_dev);
1271 /* Get Device Attributes and features */
1272 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1275 "cannot get attribute for ena device rc= %d\n", rc);
1276 goto err_admin_init;
1282 ena_com_admin_destroy(ena_dev);
1285 ena_com_mmio_reg_read_request_destroy(ena_dev);
1290 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1292 struct rte_pci_device *pci_dev;
1293 struct ena_adapter *adapter =
1294 (struct ena_adapter *)(eth_dev->data->dev_private);
1295 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1296 struct ena_com_dev_get_features_ctx get_feat_ctx;
1299 static int adapters_found;
1301 memset(adapter, 0, sizeof(struct ena_adapter));
1302 ena_dev = &adapter->ena_dev;
1304 eth_dev->dev_ops = &ena_dev_ops;
1305 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1306 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1307 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1308 adapter->rte_eth_dev_data = eth_dev->data;
1309 adapter->rte_dev = eth_dev;
1311 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1314 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1315 adapter->pdev = pci_dev;
1317 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1318 pci_dev->addr.domain,
1320 pci_dev->addr.devid,
1321 pci_dev->addr.function);
1323 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1324 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1326 /* Present ENA_MEM_BAR indicates available LLQ mode.
1327 * Use corresponding policy
1329 if (adapter->dev_mem_base)
1330 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1331 else if (adapter->regs)
1332 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1334 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1337 ena_dev->reg_bar = adapter->regs;
1338 ena_dev->dmadev = adapter->pdev;
1340 adapter->id_number = adapters_found;
1342 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1343 adapter->id_number);
1345 /* device specific initialization routine */
1346 rc = ena_device_init(ena_dev, &get_feat_ctx);
1348 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1352 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1353 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1355 "Trying to use LLQ but llq_num is 0.\n"
1356 "Fall back into regular queues.");
1357 ena_dev->tx_mem_queue_type =
1358 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1359 adapter->num_queues =
1360 get_feat_ctx.max_queues.max_sq_num;
1362 adapter->num_queues =
1363 get_feat_ctx.max_queues.max_llq_num;
1366 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1369 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1370 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1373 adapter->tx_ring_size = queue_size;
1374 adapter->rx_ring_size = queue_size;
1376 /* prepare ring structures */
1377 ena_init_rings(adapter);
1379 ena_config_debug_area(adapter);
1381 /* Set max MTU for this device */
1382 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1384 /* set device support for TSO */
1385 adapter->tso4_supported = get_feat_ctx.offload.tx &
1386 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1388 /* Copy MAC address and point DPDK to it */
1389 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1390 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1391 (struct ether_addr *)adapter->mac_addr);
1393 adapter->drv_stats = rte_zmalloc("adapter stats",
1394 sizeof(*adapter->drv_stats),
1395 RTE_CACHE_LINE_SIZE);
1396 if (!adapter->drv_stats) {
1397 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1402 adapter->state = ENA_ADAPTER_STATE_INIT;
1407 static int ena_dev_configure(struct rte_eth_dev *dev)
1409 struct ena_adapter *adapter =
1410 (struct ena_adapter *)(dev->data->dev_private);
1411 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
1413 if ((tx_offloads & adapter->tx_supported_offloads) != tx_offloads) {
1414 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported "
1415 "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
1416 tx_offloads, adapter->tx_supported_offloads);
1420 if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1421 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1422 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1427 switch (adapter->state) {
1428 case ENA_ADAPTER_STATE_INIT:
1429 case ENA_ADAPTER_STATE_STOPPED:
1430 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1432 case ENA_ADAPTER_STATE_CONFIG:
1433 RTE_LOG(WARNING, PMD,
1434 "Ivalid driver state while trying to configure device\n");
1440 adapter->tx_selected_offloads = tx_offloads;
1444 static void ena_init_rings(struct ena_adapter *adapter)
1448 for (i = 0; i < adapter->num_queues; i++) {
1449 struct ena_ring *ring = &adapter->tx_ring[i];
1451 ring->configured = 0;
1452 ring->type = ENA_RING_TYPE_TX;
1453 ring->adapter = adapter;
1455 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1456 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1459 for (i = 0; i < adapter->num_queues; i++) {
1460 struct ena_ring *ring = &adapter->rx_ring[i];
1462 ring->configured = 0;
1463 ring->type = ENA_RING_TYPE_RX;
1464 ring->adapter = adapter;
1469 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
1472 uint64_t port_offloads = adapter->tx_selected_offloads;
1474 /* Check if port supports all requested offloads.
1475 * True if all offloads selected for queue are set for port.
1477 if ((offloads & port_offloads) != offloads)
1482 static void ena_infos_get(struct rte_eth_dev *dev,
1483 struct rte_eth_dev_info *dev_info)
1485 struct ena_adapter *adapter;
1486 struct ena_com_dev *ena_dev;
1487 struct ena_com_dev_get_features_ctx feat;
1488 uint64_t rx_feat = 0, tx_feat = 0;
1491 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1492 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1493 adapter = (struct ena_adapter *)(dev->data->dev_private);
1495 ena_dev = &adapter->ena_dev;
1496 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1498 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1500 dev_info->speed_capa =
1502 ETH_LINK_SPEED_2_5G |
1504 ETH_LINK_SPEED_10G |
1505 ETH_LINK_SPEED_25G |
1506 ETH_LINK_SPEED_40G |
1507 ETH_LINK_SPEED_50G |
1508 ETH_LINK_SPEED_100G;
1510 /* Get supported features from HW */
1511 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1514 "Cannot get attribute for ena device rc= %d\n", rc);
1518 /* Set Tx & Rx features available for device */
1519 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1520 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1522 if (feat.offload.tx &
1523 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1524 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1525 DEV_TX_OFFLOAD_UDP_CKSUM |
1526 DEV_TX_OFFLOAD_TCP_CKSUM;
1528 if (feat.offload.rx_supported &
1529 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1530 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1531 DEV_RX_OFFLOAD_UDP_CKSUM |
1532 DEV_RX_OFFLOAD_TCP_CKSUM;
1534 /* Inform framework about available features */
1535 dev_info->rx_offload_capa = rx_feat;
1536 dev_info->tx_offload_capa = tx_feat;
1537 dev_info->tx_queue_offload_capa = tx_feat;
1539 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1540 dev_info->max_rx_pktlen = adapter->max_mtu;
1541 dev_info->max_mac_addrs = 1;
1543 dev_info->max_rx_queues = adapter->num_queues;
1544 dev_info->max_tx_queues = adapter->num_queues;
1545 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1547 adapter->tx_supported_offloads = tx_feat;
1550 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1553 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1554 unsigned int ring_size = rx_ring->ring_size;
1555 unsigned int ring_mask = ring_size - 1;
1556 uint16_t next_to_clean = rx_ring->next_to_clean;
1557 uint16_t desc_in_use = 0;
1558 unsigned int recv_idx = 0;
1559 struct rte_mbuf *mbuf = NULL;
1560 struct rte_mbuf *mbuf_head = NULL;
1561 struct rte_mbuf *mbuf_prev = NULL;
1562 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1563 unsigned int completed;
1565 struct ena_com_rx_ctx ena_rx_ctx;
1568 /* Check adapter state */
1569 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1571 "Trying to receive pkts while device is NOT running\n");
1575 desc_in_use = rx_ring->next_to_use - next_to_clean;
1576 if (unlikely(nb_pkts > desc_in_use))
1577 nb_pkts = desc_in_use;
1579 for (completed = 0; completed < nb_pkts; completed++) {
1582 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1583 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1584 ena_rx_ctx.descs = 0;
1585 /* receive packet context */
1586 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1587 rx_ring->ena_com_io_sq,
1590 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1594 if (unlikely(ena_rx_ctx.descs == 0))
1597 while (segments < ena_rx_ctx.descs) {
1598 mbuf = rx_buff_info[next_to_clean & ring_mask];
1599 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1600 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1603 if (segments == 0) {
1604 mbuf->nb_segs = ena_rx_ctx.descs;
1605 mbuf->port = rx_ring->port_id;
1609 /* for multi-segment pkts create mbuf chain */
1610 mbuf_prev->next = mbuf;
1612 mbuf_head->pkt_len += mbuf->data_len;
1619 /* fill mbuf attributes if any */
1620 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1621 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1623 /* pass to DPDK application head mbuf */
1624 rx_pkts[recv_idx] = mbuf_head;
1628 rx_ring->next_to_clean = next_to_clean;
1630 desc_in_use = desc_in_use - completed + 1;
1631 /* Burst refill to save doorbells, memory barriers, const interval */
1632 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1633 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1639 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1645 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1646 struct ipv4_hdr *ip_hdr;
1648 uint16_t frag_field;
1650 for (i = 0; i != nb_pkts; i++) {
1652 ol_flags = m->ol_flags;
1654 if (!(ol_flags & PKT_TX_IPV4))
1657 /* If there was not L2 header length specified, assume it is
1658 * length of the ethernet header.
1660 if (unlikely(m->l2_len == 0))
1661 m->l2_len = sizeof(struct ether_hdr);
1663 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1665 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1667 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1668 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1670 /* If IPv4 header has DF flag enabled and TSO support is
1671 * disabled, partial chcecksum should not be calculated.
1673 if (!tx_ring->adapter->tso4_supported)
1677 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1678 (ol_flags & PKT_TX_L4_MASK) ==
1679 PKT_TX_SCTP_CKSUM) {
1680 rte_errno = -ENOTSUP;
1684 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1685 ret = rte_validate_tx_offload(m);
1692 /* In case we are supposed to TSO and have DF not set (DF=0)
1693 * hardware must be provided with partial checksum, otherwise
1694 * it will take care of necessary calculations.
1697 ret = rte_net_intel_cksum_flags_prepare(m,
1698 ol_flags & ~PKT_TX_TCP_SEG);
1708 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1711 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1712 uint16_t next_to_use = tx_ring->next_to_use;
1713 uint16_t next_to_clean = tx_ring->next_to_clean;
1714 struct rte_mbuf *mbuf;
1715 unsigned int ring_size = tx_ring->ring_size;
1716 unsigned int ring_mask = ring_size - 1;
1717 struct ena_com_tx_ctx ena_tx_ctx;
1718 struct ena_tx_buffer *tx_info;
1719 struct ena_com_buf *ebuf;
1720 uint16_t rc, req_id, total_tx_descs = 0;
1721 uint16_t sent_idx = 0, empty_tx_reqs;
1724 /* Check adapter state */
1725 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1727 "Trying to xmit pkts while device is NOT running\n");
1731 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1732 if (nb_pkts > empty_tx_reqs)
1733 nb_pkts = empty_tx_reqs;
1735 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1736 mbuf = tx_pkts[sent_idx];
1738 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1739 tx_info = &tx_ring->tx_buffer_info[req_id];
1740 tx_info->mbuf = mbuf;
1741 tx_info->num_of_bufs = 0;
1742 ebuf = tx_info->bufs;
1744 /* Prepare TX context */
1745 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1746 memset(&ena_tx_ctx.ena_meta, 0x0,
1747 sizeof(struct ena_com_tx_meta));
1748 ena_tx_ctx.ena_bufs = ebuf;
1749 ena_tx_ctx.req_id = req_id;
1750 if (tx_ring->tx_mem_queue_type ==
1751 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1752 /* prepare the push buffer with
1753 * virtual address of the data
1755 ena_tx_ctx.header_len =
1756 RTE_MIN(mbuf->data_len,
1757 tx_ring->tx_max_header_size);
1758 ena_tx_ctx.push_header =
1759 (void *)((char *)mbuf->buf_addr +
1761 } /* there's no else as we take advantage of memset zeroing */
1763 /* Set TX offloads flags, if applicable */
1764 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1766 if (unlikely(mbuf->ol_flags &
1767 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1768 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1770 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1772 /* Process first segment taking into
1773 * consideration pushed header
1775 if (mbuf->data_len > ena_tx_ctx.header_len) {
1776 ebuf->paddr = mbuf->buf_iova +
1778 ena_tx_ctx.header_len;
1779 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1781 tx_info->num_of_bufs++;
1784 while ((mbuf = mbuf->next) != NULL) {
1785 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1786 ebuf->len = mbuf->data_len;
1788 tx_info->num_of_bufs++;
1791 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1793 /* Write data to device */
1794 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1795 &ena_tx_ctx, &nb_hw_desc);
1799 tx_info->tx_descs = nb_hw_desc;
1804 /* If there are ready packets to be xmitted... */
1806 /* ...let HW do its best :-) */
1808 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1810 tx_ring->next_to_use = next_to_use;
1813 /* Clear complete packets */
1814 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1815 /* Get Tx info & store how many descs were processed */
1816 tx_info = &tx_ring->tx_buffer_info[req_id];
1817 total_tx_descs += tx_info->tx_descs;
1819 /* Free whole mbuf chain */
1820 mbuf = tx_info->mbuf;
1821 rte_pktmbuf_free(mbuf);
1822 tx_info->mbuf = NULL;
1824 /* Put back descriptor to the ring for reuse */
1825 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1828 /* If too many descs to clean, leave it for another run */
1829 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1833 if (total_tx_descs > 0) {
1834 /* acknowledge completion of sent packets */
1835 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1836 tx_ring->next_to_clean = next_to_clean;
1842 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1843 struct rte_pci_device *pci_dev)
1845 return rte_eth_dev_pci_generic_probe(pci_dev,
1846 sizeof(struct ena_adapter), eth_ena_dev_init);
1849 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1851 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1854 static struct rte_pci_driver rte_ena_pmd = {
1855 .id_table = pci_id_ena_map,
1856 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1857 .probe = eth_ena_pci_probe,
1858 .remove = eth_ena_pci_remove,
1861 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1862 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1863 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1865 RTE_INIT(ena_init_log);
1869 ena_logtype_init = rte_log_register("pmd.ena.init");
1870 if (ena_logtype_init >= 0)
1871 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1872 ena_logtype_driver = rte_log_register("pmd.ena.driver");
1873 if (ena_logtype_driver >= 0)
1874 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);