drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 /*
 118  * Each rte_memzone should have unique name.
 119  * To satisfy it, count number of allocation and add it to name.
 120  */
 121 uint32_t ena_alloc_cnt;
 122
 123 static const struct ena_stats ena_stats_global_strings[] = {
 124         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 125         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 126         ENA_STAT_GLOBAL_ENTRY(io_resume),
 127         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 128         ENA_STAT_GLOBAL_ENTRY(interface_up),
 129         ENA_STAT_GLOBAL_ENTRY(interface_down),
 130         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 131 };
 132
 133 static const struct ena_stats ena_stats_tx_strings[] = {
 134         ENA_STAT_TX_ENTRY(cnt),
 135         ENA_STAT_TX_ENTRY(bytes),
 136         ENA_STAT_TX_ENTRY(queue_stop),
 137         ENA_STAT_TX_ENTRY(queue_wakeup),
 138         ENA_STAT_TX_ENTRY(dma_mapping_err),
 139         ENA_STAT_TX_ENTRY(linearize),
 140         ENA_STAT_TX_ENTRY(linearize_failed),
 141         ENA_STAT_TX_ENTRY(tx_poll),
 142         ENA_STAT_TX_ENTRY(doorbells),
 143         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 144         ENA_STAT_TX_ENTRY(missing_tx_comp),
 145         ENA_STAT_TX_ENTRY(bad_req_id),
 146 };
 147
 148 static const struct ena_stats ena_stats_rx_strings[] = {
 149         ENA_STAT_RX_ENTRY(cnt),
 150         ENA_STAT_RX_ENTRY(bytes),
 151         ENA_STAT_RX_ENTRY(refil_partial),
 152         ENA_STAT_RX_ENTRY(bad_csum),
 153         ENA_STAT_RX_ENTRY(page_alloc_fail),
 154         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 155         ENA_STAT_RX_ENTRY(dma_mapping_err),
 156         ENA_STAT_RX_ENTRY(bad_desc_num),
 157         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 158 };
 159
 160 static const struct ena_stats ena_stats_ena_com_strings[] = {
 161         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 162         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 163         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 165         ENA_STAT_ENA_COM_ENTRY(no_completion),
 166 };
 167
 168 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 169 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 170 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 172
 173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 174                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 175                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 176                         DEV_TX_OFFLOAD_TCP_TSO)
 177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 178                        PKT_TX_IP_CKSUM |\
 179                        PKT_TX_TCP_SEG)
 180
 181 /** Vendor ID used by Amazon devices */
 182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 183 /** Amazon devices */
 184 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 185 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 186
 187 #define ENA_TX_OFFLOAD_MASK     (\
 188         PKT_TX_L4_MASK |         \
 189         PKT_TX_IP_CKSUM |        \
 190         PKT_TX_TCP_SEG)
 191
 192 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 193         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 194
 195 int ena_logtype_init;
 196 int ena_logtype_driver;
 197
 198 static const struct rte_pci_id pci_id_ena_map[] = {
 199         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 200         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 201         { .device_id = 0 },
 202 };
 203
 204 static struct ena_aenq_handlers aenq_handlers;
 205
 206 static int ena_device_init(struct ena_com_dev *ena_dev,
 207                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 208 static int ena_dev_configure(struct rte_eth_dev *dev);
 209 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 210                                   uint16_t nb_pkts);
 211 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 212                 uint16_t nb_pkts);
 213 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 214                               uint16_t nb_desc, unsigned int socket_id,
 215                               const struct rte_eth_txconf *tx_conf);
 216 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 217                               uint16_t nb_desc, unsigned int socket_id,
 218                               const struct rte_eth_rxconf *rx_conf,
 219                               struct rte_mempool *mp);
 220 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 221                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 222 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 223 static void ena_init_rings(struct ena_adapter *adapter);
 224 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 225 static int ena_start(struct rte_eth_dev *dev);
 226 static void ena_stop(struct rte_eth_dev *dev);
 227 static void ena_close(struct rte_eth_dev *dev);
 228 static int ena_dev_reset(struct rte_eth_dev *dev);
 229 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 230 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 231 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 232 static void ena_rx_queue_release(void *queue);
 233 static void ena_tx_queue_release(void *queue);
 234 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 235 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 236 static int ena_link_update(struct rte_eth_dev *dev,
 237                            int wait_to_complete);
 238 static int ena_queue_restart(struct ena_ring *ring);
 239 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 240                                  enum ena_ring_type ring_type);
 241 static void ena_stats_restart(struct rte_eth_dev *dev);
 242 static void ena_infos_get(struct rte_eth_dev *dev,
 243                           struct rte_eth_dev_info *dev_info);
 244 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 245                                struct rte_eth_rss_reta_entry64 *reta_conf,
 246                                uint16_t reta_size);
 247 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 248                               struct rte_eth_rss_reta_entry64 *reta_conf,
 249                               uint16_t reta_size);
 250 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 251 static void ena_interrupt_handler_rte(void *cb_arg);
 252
 253 static const struct eth_dev_ops ena_dev_ops = {
 254         .dev_configure        = ena_dev_configure,
 255         .dev_infos_get        = ena_infos_get,
 256         .rx_queue_setup       = ena_rx_queue_setup,
 257         .tx_queue_setup       = ena_tx_queue_setup,
 258         .dev_start            = ena_start,
 259         .dev_stop             = ena_stop,
 260         .link_update          = ena_link_update,
 261         .stats_get            = ena_stats_get,
 262         .mtu_set              = ena_mtu_set,
 263         .rx_queue_release     = ena_rx_queue_release,
 264         .tx_queue_release     = ena_tx_queue_release,
 265         .dev_close            = ena_close,
 266         .dev_reset            = ena_dev_reset,
 267         .reta_update          = ena_rss_reta_update,
 268         .reta_query           = ena_rss_reta_query,
 269 };
 270
 271 #define NUMA_NO_NODE    SOCKET_ID_ANY
 272
 273 static inline int ena_cpu_to_node(int cpu)
 274 {
 275         struct rte_config *config = rte_eal_get_configuration();
 276         struct rte_fbarray *arr = &config->mem_config->memzones;
 277         const struct rte_memzone *mz;
 278
 279         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 280                 return NUMA_NO_NODE;
 281
 282         mz = rte_fbarray_get(arr, cpu);
 283
 284         return mz->socket_id;
 285 }
 286
 287 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 288                                        struct ena_com_rx_ctx *ena_rx_ctx)
 289 {
 290         uint64_t ol_flags = 0;
 291         uint32_t packet_type = 0;
 292
 293         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 294                 packet_type |= RTE_PTYPE_L4_TCP;
 295         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 296                 packet_type |= RTE_PTYPE_L4_UDP;
 297
 298         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 299                 packet_type |= RTE_PTYPE_L3_IPV4;
 300         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 301                 packet_type |= RTE_PTYPE_L3_IPV6;
 302
 303         if (unlikely(ena_rx_ctx->l4_csum_err))
 304                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 305         if (unlikely(ena_rx_ctx->l3_csum_err))
 306                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 307
 308         mbuf->ol_flags = ol_flags;
 309         mbuf->packet_type = packet_type;
 310 }
 311
 312 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 313                                        struct ena_com_tx_ctx *ena_tx_ctx,
 314                                        uint64_t queue_offloads)
 315 {
 316         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 317
 318         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 319             (queue_offloads & QUEUE_OFFLOADS)) {
 320                 /* check if TSO is required */
 321                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 322                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 323                         ena_tx_ctx->tso_enable = true;
 324
 325                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 326                 }
 327
 328                 /* check if L3 checksum is needed */
 329                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 330                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 331                         ena_tx_ctx->l3_csum_enable = true;
 332
 333                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 334                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 335                 } else {
 336                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 337
 338                         /* set don't fragment (DF) flag */
 339                         if (mbuf->packet_type &
 340                                 (RTE_PTYPE_L4_NONFRAG
 341                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 342                                 ena_tx_ctx->df = true;
 343                 }
 344
 345                 /* check if L4 checksum is needed */
 346                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 347                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 348                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 349                         ena_tx_ctx->l4_csum_enable = true;
 350                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 351                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 352                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 353                         ena_tx_ctx->l4_csum_enable = true;
 354                 } else {
 355                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 356                         ena_tx_ctx->l4_csum_enable = false;
 357                 }
 358
 359                 ena_meta->mss = mbuf->tso_segsz;
 360                 ena_meta->l3_hdr_len = mbuf->l3_len;
 361                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 362
 363                 ena_tx_ctx->meta_valid = true;
 364         } else {
 365                 ena_tx_ctx->meta_valid = false;
 366         }
 367 }
 368
 369 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 370 {
 371         struct ena_admin_host_info *host_info;
 372         int rc;
 373
 374         /* Allocate only the host info */
 375         rc = ena_com_allocate_host_info(ena_dev);
 376         if (rc) {
 377                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 378                 return;
 379         }
 380
 381         host_info = ena_dev->host_attr.host_info;
 382
 383         host_info->os_type = ENA_ADMIN_OS_DPDK;
 384         host_info->kernel_ver = RTE_VERSION;
 385         snprintf((char *)host_info->kernel_ver_str,
 386                  sizeof(host_info->kernel_ver_str),
 387                  "%s", rte_version());
 388         host_info->os_dist = RTE_VERSION;
 389         snprintf((char *)host_info->os_dist_str,
 390                  sizeof(host_info->os_dist_str),
 391                  "%s", rte_version());
 392         host_info->driver_version =
 393                 (DRV_MODULE_VER_MAJOR) |
 394                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 395                 (DRV_MODULE_VER_SUBMINOR <<
 396                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 397
 398         rc = ena_com_set_host_attributes(ena_dev);
 399         if (rc) {
 400                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 401                 if (rc != -ENA_COM_UNSUPPORTED)
 402                         goto err;
 403         }
 404
 405         return;
 406
 407 err:
 408         ena_com_delete_host_info(ena_dev);
 409 }
 410
 411 static int
 412 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 413 {
 414         if (sset != ETH_SS_STATS)
 415                 return -EOPNOTSUPP;
 416
 417          /* Workaround for clang:
 418          * touch internal structures to prevent
 419          * compiler error
 420          */
 421         ENA_TOUCH(ena_stats_global_strings);
 422         ENA_TOUCH(ena_stats_tx_strings);
 423         ENA_TOUCH(ena_stats_rx_strings);
 424         ENA_TOUCH(ena_stats_ena_com_strings);
 425
 426         return  dev->data->nb_tx_queues *
 427                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 428                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 429 }
 430
 431 static void ena_config_debug_area(struct ena_adapter *adapter)
 432 {
 433         u32 debug_area_size;
 434         int rc, ss_count;
 435
 436         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 437         if (ss_count <= 0) {
 438                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 439                 return;
 440         }
 441
 442         /* allocate 32 bytes for each string and 64bit for the value */
 443         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 444
 445         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 446         if (rc) {
 447                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 448                 return;
 449         }
 450
 451         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 452         if (rc) {
 453                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 454                 if (rc != -ENA_COM_UNSUPPORTED)
 455                         goto err;
 456         }
 457
 458         return;
 459 err:
 460         ena_com_delete_debug_area(&adapter->ena_dev);
 461 }
 462
 463 static void ena_close(struct rte_eth_dev *dev)
 464 {
 465         struct ena_adapter *adapter =
 466                 (struct ena_adapter *)(dev->data->dev_private);
 467
 468         ena_stop(dev);
 469         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 470
 471         ena_rx_queue_release_all(dev);
 472         ena_tx_queue_release_all(dev);
 473 }
 474
 475 static int
 476 ena_dev_reset(struct rte_eth_dev *dev)
 477 {
 478         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 479         struct rte_eth_dev *eth_dev;
 480         struct rte_pci_device *pci_dev;
 481         struct rte_intr_handle *intr_handle;
 482         struct ena_com_dev *ena_dev;
 483         struct ena_com_dev_get_features_ctx get_feat_ctx;
 484         struct ena_adapter *adapter;
 485         int nb_queues;
 486         int rc, i;
 487
 488         adapter = (struct ena_adapter *)(dev->data->dev_private);
 489         ena_dev = &adapter->ena_dev;
 490         eth_dev = adapter->rte_dev;
 491         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 492         intr_handle = &pci_dev->intr_handle;
 493         nb_queues = eth_dev->data->nb_rx_queues;
 494
 495         ena_com_set_admin_running_state(ena_dev, false);
 496
 497         ena_com_dev_reset(ena_dev, adapter->reset_reason);
 498
 499         for (i = 0; i < nb_queues; i++)
 500                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 501
 502         ena_rx_queue_release_all(eth_dev);
 503         ena_tx_queue_release_all(eth_dev);
 504
 505         rte_intr_disable(intr_handle);
 506
 507         ena_com_abort_admin_commands(ena_dev);
 508         ena_com_wait_for_abort_completion(ena_dev);
 509         ena_com_admin_destroy(ena_dev);
 510         ena_com_mmio_reg_read_request_destroy(ena_dev);
 511
 512         rc = ena_device_init(ena_dev, &get_feat_ctx);
 513         if (rc) {
 514                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 515                 return rc;
 516         }
 517
 518         rte_intr_enable(intr_handle);
 519         ena_com_set_admin_polling_mode(ena_dev, false);
 520         ena_com_admin_aenq_enable(ena_dev);
 521
 522         for (i = 0; i < nb_queues; ++i)
 523                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 524                         mb_pool_rx[i]);
 525
 526         for (i = 0; i < nb_queues; ++i)
 527                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 528
 529         return 0;
 530 }
 531
 532 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 533                                struct rte_eth_rss_reta_entry64 *reta_conf,
 534                                uint16_t reta_size)
 535 {
 536         struct ena_adapter *adapter =
 537                 (struct ena_adapter *)(dev->data->dev_private);
 538         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 539         int ret, i;
 540         u16 entry_value;
 541         int conf_idx;
 542         int idx;
 543
 544         if ((reta_size == 0) || (reta_conf == NULL))
 545                 return -EINVAL;
 546
 547         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 548                 RTE_LOG(WARNING, PMD,
 549                         "indirection table %d is bigger than supported (%d)\n",
 550                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 551                 ret = -EINVAL;
 552                 goto err;
 553         }
 554
 555         for (i = 0 ; i < reta_size ; i++) {
 556                 /* each reta_conf is for 64 entries.
 557                  * to support 128 we use 2 conf of 64
 558                  */
 559                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 560                 idx = i % RTE_RETA_GROUP_SIZE;
 561                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 562                         entry_value =
 563                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 564                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 565                                                                 i,
 566                                                                 entry_value);
 567                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 568                                 RTE_LOG(ERR, PMD,
 569                                         "Cannot fill indirect table\n");
 570                                 ret = -ENOTSUP;
 571                                 goto err;
 572                         }
 573                 }
 574         }
 575
 576         ret = ena_com_indirect_table_set(ena_dev);
 577         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 578                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 579                 ret = -ENOTSUP;
 580                 goto err;
 581         }
 582
 583         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 584                 __func__, reta_size, adapter->rte_dev->data->port_id);
 585 err:
 586         return ret;
 587 }
 588
 589 /* Query redirection table. */
 590 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 591                               struct rte_eth_rss_reta_entry64 *reta_conf,
 592                               uint16_t reta_size)
 593 {
 594         struct ena_adapter *adapter =
 595                 (struct ena_adapter *)(dev->data->dev_private);
 596         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 597         int ret;
 598         int i;
 599         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 600         int reta_conf_idx;
 601         int reta_idx;
 602
 603         if (reta_size == 0 || reta_conf == NULL ||
 604             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 605                 return -EINVAL;
 606
 607         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 608         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 609                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 610                 ret = -ENOTSUP;
 611                 goto err;
 612         }
 613
 614         for (i = 0 ; i < reta_size ; i++) {
 615                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 616                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 617                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 618                         reta_conf[reta_conf_idx].reta[reta_idx] =
 619                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 620         }
 621 err:
 622         return ret;
 623 }
 624
 625 static int ena_rss_init_default(struct ena_adapter *adapter)
 626 {
 627         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 628         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 629         int rc, i;
 630         u32 val;
 631
 632         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 633         if (unlikely(rc)) {
 634                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 635                 goto err_rss_init;
 636         }
 637
 638         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 639                 val = i % nb_rx_queues;
 640                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 641                                                        ENA_IO_RXQ_IDX(val));
 642                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 643                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 644                         goto err_fill_indir;
 645                 }
 646         }
 647
 648         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 649                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 650         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 651                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 652                 goto err_fill_indir;
 653         }
 654
 655         rc = ena_com_set_default_hash_ctrl(ena_dev);
 656         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 657                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 658                 goto err_fill_indir;
 659         }
 660
 661         rc = ena_com_indirect_table_set(ena_dev);
 662         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 663                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 664                 goto err_fill_indir;
 665         }
 666         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 667                 adapter->rte_dev->data->port_id);
 668
 669         return 0;
 670
 671 err_fill_indir:
 672         ena_com_rss_destroy(ena_dev);
 673 err_rss_init:
 674
 675         return rc;
 676 }
 677
 678 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 679 {
 680         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 681         int nb_queues = dev->data->nb_rx_queues;
 682         int i;
 683
 684         for (i = 0; i < nb_queues; i++)
 685                 ena_rx_queue_release(queues[i]);
 686 }
 687
 688 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 689 {
 690         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 691         int nb_queues = dev->data->nb_tx_queues;
 692         int i;
 693
 694         for (i = 0; i < nb_queues; i++)
 695                 ena_tx_queue_release(queues[i]);
 696 }
 697
 698 static void ena_rx_queue_release(void *queue)
 699 {
 700         struct ena_ring *ring = (struct ena_ring *)queue;
 701         struct ena_adapter *adapter = ring->adapter;
 702         int ena_qid;
 703
 704         ena_assert_msg(ring->configured,
 705                        "API violation - releasing not configured queue");
 706         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 707                        "API violation");
 708
 709         /* Destroy HW queue */
 710         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 711         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 712
 713         /* Free all bufs */
 714         ena_rx_queue_release_bufs(ring);
 715
 716         /* Free ring resources */
 717         if (ring->rx_buffer_info)
 718                 rte_free(ring->rx_buffer_info);
 719         ring->rx_buffer_info = NULL;
 720
 721         ring->configured = 0;
 722
 723         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 724                 ring->port_id, ring->id);
 725 }
 726
 727 static void ena_tx_queue_release(void *queue)
 728 {
 729         struct ena_ring *ring = (struct ena_ring *)queue;
 730         struct ena_adapter *adapter = ring->adapter;
 731         int ena_qid;
 732
 733         ena_assert_msg(ring->configured,
 734                        "API violation. Releasing not configured queue");
 735         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 736                        "API violation");
 737
 738         /* Destroy HW queue */
 739         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 740         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 741
 742         /* Free all bufs */
 743         ena_tx_queue_release_bufs(ring);
 744
 745         /* Free ring resources */
 746         if (ring->tx_buffer_info)
 747                 rte_free(ring->tx_buffer_info);
 748
 749         if (ring->empty_tx_reqs)
 750                 rte_free(ring->empty_tx_reqs);
 751
 752         ring->empty_tx_reqs = NULL;
 753         ring->tx_buffer_info = NULL;
 754
 755         ring->configured = 0;
 756
 757         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 758                 ring->port_id, ring->id);
 759 }
 760
 761 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 762 {
 763         unsigned int ring_mask = ring->ring_size - 1;
 764
 765         while (ring->next_to_clean != ring->next_to_use) {
 766                 struct rte_mbuf *m =
 767                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 768
 769                 if (m)
 770                         rte_mbuf_raw_free(m);
 771
 772                 ring->next_to_clean++;
 773         }
 774 }
 775
 776 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 777 {
 778         unsigned int i;
 779
 780         for (i = 0; i < ring->ring_size; ++i) {
 781                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 782
 783                 if (tx_buf->mbuf)
 784                         rte_pktmbuf_free(tx_buf->mbuf);
 785
 786                 ring->next_to_clean++;
 787         }
 788 }
 789
 790 static int ena_link_update(struct rte_eth_dev *dev,
 791                            __rte_unused int wait_to_complete)
 792 {
 793         struct rte_eth_link *link = &dev->data->dev_link;
 794         struct ena_adapter *adapter;
 795
 796         adapter = (struct ena_adapter *)(dev->data->dev_private);
 797
 798         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 799         link->link_speed = ETH_SPEED_NUM_10G;
 800         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 801
 802         return 0;
 803 }
 804
 805 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 806                                  enum ena_ring_type ring_type)
 807 {
 808         struct ena_adapter *adapter =
 809                 (struct ena_adapter *)(dev->data->dev_private);
 810         struct ena_ring *queues = NULL;
 811         int nb_queues;
 812         int i = 0;
 813         int rc = 0;
 814
 815         if (ring_type == ENA_RING_TYPE_RX) {
 816                 queues = adapter->rx_ring;
 817                 nb_queues = dev->data->nb_rx_queues;
 818         } else {
 819                 queues = adapter->tx_ring;
 820                 nb_queues = dev->data->nb_tx_queues;
 821         }
 822         for (i = 0; i < nb_queues; i++) {
 823                 if (queues[i].configured) {
 824                         if (ring_type == ENA_RING_TYPE_RX) {
 825                                 ena_assert_msg(
 826                                         dev->data->rx_queues[i] == &queues[i],
 827                                         "Inconsistent state of rx queues\n");
 828                         } else {
 829                                 ena_assert_msg(
 830                                         dev->data->tx_queues[i] == &queues[i],
 831                                         "Inconsistent state of tx queues\n");
 832                         }
 833
 834                         rc = ena_queue_restart(&queues[i]);
 835
 836                         if (rc) {
 837                                 PMD_INIT_LOG(ERR,
 838                                              "failed to restart queue %d type(%d)",
 839                                              i, ring_type);
 840                                 return -1;
 841                         }
 842                 }
 843         }
 844
 845         return 0;
 846 }
 847
 848 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 849 {
 850         uint32_t max_frame_len = adapter->max_mtu;
 851
 852         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 853             DEV_RX_OFFLOAD_JUMBO_FRAME)
 854                 max_frame_len =
 855                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 856
 857         return max_frame_len;
 858 }
 859
 860 static int ena_check_valid_conf(struct ena_adapter *adapter)
 861 {
 862         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 863
 864         if (max_frame_len > adapter->max_mtu) {
 865                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 866                 return -1;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int
 873 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 874                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 875 {
 876         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 877
 878         queue_size = RTE_MIN(queue_size,
 879                              get_feat_ctx->max_queues.max_cq_depth);
 880         queue_size = RTE_MIN(queue_size,
 881                              get_feat_ctx->max_queues.max_sq_depth);
 882
 883         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 884                 queue_size = RTE_MIN(queue_size,
 885                                      get_feat_ctx->max_queues.max_llq_depth);
 886
 887         /* Round down to power of 2 */
 888         if (!rte_is_power_of_2(queue_size))
 889                 queue_size = rte_align32pow2(queue_size >> 1);
 890
 891         if (queue_size == 0) {
 892                 PMD_INIT_LOG(ERR, "Invalid queue size");
 893                 return -EFAULT;
 894         }
 895
 896         return queue_size;
 897 }
 898
 899 static void ena_stats_restart(struct rte_eth_dev *dev)
 900 {
 901         struct ena_adapter *adapter =
 902                 (struct ena_adapter *)(dev->data->dev_private);
 903
 904         rte_atomic64_init(&adapter->drv_stats->ierrors);
 905         rte_atomic64_init(&adapter->drv_stats->oerrors);
 906         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 907 }
 908
 909 static int ena_stats_get(struct rte_eth_dev *dev,
 910                           struct rte_eth_stats *stats)
 911 {
 912         struct ena_admin_basic_stats ena_stats;
 913         struct ena_adapter *adapter =
 914                 (struct ena_adapter *)(dev->data->dev_private);
 915         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 916         int rc;
 917
 918         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 919                 return -ENOTSUP;
 920
 921         memset(&ena_stats, 0, sizeof(ena_stats));
 922         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 923         if (unlikely(rc)) {
 924                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 925                 return rc;
 926         }
 927
 928         /* Set of basic statistics from ENA */
 929         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 930                                           ena_stats.rx_pkts_low);
 931         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 932                                           ena_stats.tx_pkts_low);
 933         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 934                                         ena_stats.rx_bytes_low);
 935         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 936                                         ena_stats.tx_bytes_low);
 937         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 938                                          ena_stats.rx_drops_low);
 939
 940         /* Driver related stats */
 941         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 942         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 943         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 944         return 0;
 945 }
 946
 947 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 948 {
 949         struct ena_adapter *adapter;
 950         struct ena_com_dev *ena_dev;
 951         int rc = 0;
 952
 953         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 954         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 955         adapter = (struct ena_adapter *)(dev->data->dev_private);
 956
 957         ena_dev = &adapter->ena_dev;
 958         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 959
 960         if (mtu > ena_get_mtu_conf(adapter)) {
 961                 RTE_LOG(ERR, PMD,
 962                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 963                         mtu, ena_get_mtu_conf(adapter));
 964                 rc = -EINVAL;
 965                 goto err;
 966         }
 967
 968         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 969         if (rc)
 970                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 971         else
 972                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 973
 974 err:
 975         return rc;
 976 }
 977
 978 static int ena_start(struct rte_eth_dev *dev)
 979 {
 980         struct ena_adapter *adapter =
 981                 (struct ena_adapter *)(dev->data->dev_private);
 982         int rc = 0;
 983
 984         rc = ena_check_valid_conf(adapter);
 985         if (rc)
 986                 return rc;
 987
 988         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 989         if (rc)
 990                 return rc;
 991
 992         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 993         if (rc)
 994                 return rc;
 995
 996         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 997             ETH_MQ_RX_RSS_FLAG) {
 998                 rc = ena_rss_init_default(adapter);
 999                 if (rc)
1000                         return rc;
1001         }
1002
1003         ena_stats_restart(dev);
1004
1005         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1006
1007         return 0;
1008 }
1009
1010 static void ena_stop(struct rte_eth_dev *dev)
1011 {
1012         struct ena_adapter *adapter =
1013                 (struct ena_adapter *)(dev->data->dev_private);
1014
1015         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1016 }
1017
1018 static int ena_queue_restart(struct ena_ring *ring)
1019 {
1020         int rc, bufs_num;
1021
1022         ena_assert_msg(ring->configured == 1,
1023                        "Trying to restart unconfigured queue\n");
1024
1025         ring->next_to_clean = 0;
1026         ring->next_to_use = 0;
1027
1028         if (ring->type == ENA_RING_TYPE_TX)
1029                 return 0;
1030
1031         bufs_num = ring->ring_size - 1;
1032         rc = ena_populate_rx_queue(ring, bufs_num);
1033         if (rc != bufs_num) {
1034                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1035                 return (-1);
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1042                               uint16_t queue_idx,
1043                               uint16_t nb_desc,
1044                               __rte_unused unsigned int socket_id,
1045                               const struct rte_eth_txconf *tx_conf)
1046 {
1047         struct ena_com_create_io_ctx ctx =
1048                 /* policy set to _HOST just to satisfy icc compiler */
1049                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1050                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1051         struct ena_ring *txq = NULL;
1052         struct ena_adapter *adapter =
1053                 (struct ena_adapter *)(dev->data->dev_private);
1054         unsigned int i;
1055         int ena_qid;
1056         int rc;
1057         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1058
1059         txq = &adapter->tx_ring[queue_idx];
1060
1061         if (txq->configured) {
1062                 RTE_LOG(CRIT, PMD,
1063                         "API violation. Queue %d is already configured\n",
1064                         queue_idx);
1065                 return -1;
1066         }
1067
1068         if (!rte_is_power_of_2(nb_desc)) {
1069                 RTE_LOG(ERR, PMD,
1070                         "Unsupported size of RX queue: %d is not a power of 2.",
1071                         nb_desc);
1072                 return -EINVAL;
1073         }
1074
1075         if (nb_desc > adapter->tx_ring_size) {
1076                 RTE_LOG(ERR, PMD,
1077                         "Unsupported size of TX queue (max size: %d)\n",
1078                         adapter->tx_ring_size);
1079                 return -EINVAL;
1080         }
1081
1082         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1083
1084         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1085         ctx.qid = ena_qid;
1086         ctx.msix_vector = -1; /* admin interrupts not used */
1087         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1088         ctx.queue_size = adapter->tx_ring_size;
1089         ctx.numa_node = ena_cpu_to_node(queue_idx);
1090
1091         rc = ena_com_create_io_queue(ena_dev, &ctx);
1092         if (rc) {
1093                 RTE_LOG(ERR, PMD,
1094                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1095                         queue_idx, ena_qid, rc);
1096         }
1097         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1098         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1099
1100         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1101                                      &txq->ena_com_io_sq,
1102                                      &txq->ena_com_io_cq);
1103         if (rc) {
1104                 RTE_LOG(ERR, PMD,
1105                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1106                         queue_idx, rc);
1107                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1108                 goto err;
1109         }
1110
1111         txq->port_id = dev->data->port_id;
1112         txq->next_to_clean = 0;
1113         txq->next_to_use = 0;
1114         txq->ring_size = nb_desc;
1115
1116         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1117                                           sizeof(struct ena_tx_buffer) *
1118                                           txq->ring_size,
1119                                           RTE_CACHE_LINE_SIZE);
1120         if (!txq->tx_buffer_info) {
1121                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1122                 return -ENOMEM;
1123         }
1124
1125         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1126                                          sizeof(u16) * txq->ring_size,
1127                                          RTE_CACHE_LINE_SIZE);
1128         if (!txq->empty_tx_reqs) {
1129                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1130                 rte_free(txq->tx_buffer_info);
1131                 return -ENOMEM;
1132         }
1133         for (i = 0; i < txq->ring_size; i++)
1134                 txq->empty_tx_reqs[i] = i;
1135
1136         if (tx_conf != NULL) {
1137                 txq->offloads =
1138                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1139         }
1140
1141         /* Store pointer to this queue in upper layer */
1142         txq->configured = 1;
1143         dev->data->tx_queues[queue_idx] = txq;
1144 err:
1145         return rc;
1146 }
1147
1148 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1149                               uint16_t queue_idx,
1150                               uint16_t nb_desc,
1151                               __rte_unused unsigned int socket_id,
1152                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1153                               struct rte_mempool *mp)
1154 {
1155         struct ena_com_create_io_ctx ctx =
1156                 /* policy set to _HOST just to satisfy icc compiler */
1157                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1158                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1159         struct ena_adapter *adapter =
1160                 (struct ena_adapter *)(dev->data->dev_private);
1161         struct ena_ring *rxq = NULL;
1162         uint16_t ena_qid = 0;
1163         int rc = 0;
1164         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1165
1166         rxq = &adapter->rx_ring[queue_idx];
1167         if (rxq->configured) {
1168                 RTE_LOG(CRIT, PMD,
1169                         "API violation. Queue %d is already configured\n",
1170                         queue_idx);
1171                 return -1;
1172         }
1173
1174         if (!rte_is_power_of_2(nb_desc)) {
1175                 RTE_LOG(ERR, PMD,
1176                         "Unsupported size of TX queue: %d is not a power of 2.",
1177                         nb_desc);
1178                 return -EINVAL;
1179         }
1180
1181         if (nb_desc > adapter->rx_ring_size) {
1182                 RTE_LOG(ERR, PMD,
1183                         "Unsupported size of RX queue (max size: %d)\n",
1184                         adapter->rx_ring_size);
1185                 return -EINVAL;
1186         }
1187
1188         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1189
1190         ctx.qid = ena_qid;
1191         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1192         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1193         ctx.msix_vector = -1; /* admin interrupts not used */
1194         ctx.queue_size = adapter->rx_ring_size;
1195         ctx.numa_node = ena_cpu_to_node(queue_idx);
1196
1197         rc = ena_com_create_io_queue(ena_dev, &ctx);
1198         if (rc)
1199                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1200                         queue_idx, rc);
1201
1202         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1203         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1204
1205         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1206                                      &rxq->ena_com_io_sq,
1207                                      &rxq->ena_com_io_cq);
1208         if (rc) {
1209                 RTE_LOG(ERR, PMD,
1210                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1211                         queue_idx, rc);
1212                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1213         }
1214
1215         rxq->port_id = dev->data->port_id;
1216         rxq->next_to_clean = 0;
1217         rxq->next_to_use = 0;
1218         rxq->ring_size = nb_desc;
1219         rxq->mb_pool = mp;
1220
1221         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1222                                           sizeof(struct rte_mbuf *) * nb_desc,
1223                                           RTE_CACHE_LINE_SIZE);
1224         if (!rxq->rx_buffer_info) {
1225                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1226                 return -ENOMEM;
1227         }
1228
1229         /* Store pointer to this queue in upper layer */
1230         rxq->configured = 1;
1231         dev->data->rx_queues[queue_idx] = rxq;
1232
1233         return rc;
1234 }
1235
1236 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1237 {
1238         unsigned int i;
1239         int rc;
1240         uint16_t ring_size = rxq->ring_size;
1241         uint16_t ring_mask = ring_size - 1;
1242         uint16_t next_to_use = rxq->next_to_use;
1243         uint16_t in_use;
1244         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1245
1246         if (unlikely(!count))
1247                 return 0;
1248
1249         in_use = rxq->next_to_use - rxq->next_to_clean;
1250         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1251
1252         count = RTE_MIN(count,
1253                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1254
1255         /* get resources for incoming packets */
1256         rc = rte_mempool_get_bulk(rxq->mb_pool,
1257                                   (void **)(&mbufs[next_to_use & ring_mask]),
1258                                   count);
1259         if (unlikely(rc < 0)) {
1260                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1261                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1262                 return 0;
1263         }
1264
1265         for (i = 0; i < count; i++) {
1266                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1267                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1268                 struct ena_com_buf ebuf;
1269
1270                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1271                 /* prepare physical address for DMA transaction */
1272                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1273                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1274                 /* pass resource to device */
1275                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1276                                                 &ebuf, next_to_use_masked);
1277                 if (unlikely(rc)) {
1278                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1279                                              count - i);
1280                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1281                         break;
1282                 }
1283                 next_to_use++;
1284         }
1285
1286         /* When we submitted free recources to device... */
1287         if (i > 0) {
1288                 /* ...let HW know that it can fill buffers with data */
1289                 rte_wmb();
1290                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1291
1292                 rxq->next_to_use = next_to_use;
1293         }
1294
1295         return i;
1296 }
1297
1298 static int ena_device_init(struct ena_com_dev *ena_dev,
1299                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1300 {
1301         uint32_t aenq_groups;
1302         int rc;
1303         bool readless_supported;
1304
1305         /* Initialize mmio registers */
1306         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1307         if (rc) {
1308                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1309                 return rc;
1310         }
1311
1312         /* The PCIe configuration space revision id indicate if mmio reg
1313          * read is disabled.
1314          */
1315         readless_supported =
1316                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1317                                & ENA_MMIO_DISABLE_REG_READ);
1318         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1319
1320         /* reset device */
1321         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1322         if (rc) {
1323                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1324                 goto err_mmio_read_less;
1325         }
1326
1327         /* check FW version */
1328         rc = ena_com_validate_version(ena_dev);
1329         if (rc) {
1330                 RTE_LOG(ERR, PMD, "device version is too low\n");
1331                 goto err_mmio_read_less;
1332         }
1333
1334         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1335
1336         /* ENA device administration layer init */
1337         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1338         if (rc) {
1339                 RTE_LOG(ERR, PMD,
1340                         "cannot initialize ena admin queue with device\n");
1341                 goto err_mmio_read_less;
1342         }
1343
1344         /* To enable the msix interrupts the driver needs to know the number
1345          * of queues. So the driver uses polling mode to retrieve this
1346          * information.
1347          */
1348         ena_com_set_admin_polling_mode(ena_dev, true);
1349
1350         ena_config_host_info(ena_dev);
1351
1352         /* Get Device Attributes and features */
1353         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1354         if (rc) {
1355                 RTE_LOG(ERR, PMD,
1356                         "cannot get attribute for ena device rc= %d\n", rc);
1357                 goto err_admin_init;
1358         }
1359
1360         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1361                       BIT(ENA_ADMIN_NOTIFICATION);
1362
1363         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1364         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1365         if (rc) {
1366                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1367                 goto err_admin_init;
1368         }
1369
1370         return 0;
1371
1372 err_admin_init:
1373         ena_com_admin_destroy(ena_dev);
1374
1375 err_mmio_read_less:
1376         ena_com_mmio_reg_read_request_destroy(ena_dev);
1377
1378         return rc;
1379 }
1380
1381 static void ena_interrupt_handler_rte(void *cb_arg)
1382 {
1383         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1384         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1385
1386         ena_com_admin_q_comp_intr_handler(ena_dev);
1387         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1388                 ena_com_aenq_intr_handler(ena_dev, adapter);
1389 }
1390
1391 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1392 {
1393         struct rte_pci_device *pci_dev;
1394         struct rte_intr_handle *intr_handle;
1395         struct ena_adapter *adapter =
1396                 (struct ena_adapter *)(eth_dev->data->dev_private);
1397         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1398         struct ena_com_dev_get_features_ctx get_feat_ctx;
1399         int queue_size, rc;
1400
1401         static int adapters_found;
1402
1403         memset(adapter, 0, sizeof(struct ena_adapter));
1404         ena_dev = &adapter->ena_dev;
1405
1406         eth_dev->dev_ops = &ena_dev_ops;
1407         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1408         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1409         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1410         adapter->rte_eth_dev_data = eth_dev->data;
1411         adapter->rte_dev = eth_dev;
1412
1413         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1414                 return 0;
1415
1416         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1417         adapter->pdev = pci_dev;
1418
1419         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1420                      pci_dev->addr.domain,
1421                      pci_dev->addr.bus,
1422                      pci_dev->addr.devid,
1423                      pci_dev->addr.function);
1424
1425         intr_handle = &pci_dev->intr_handle;
1426
1427         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1428         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1429
1430         if (!adapter->regs) {
1431                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1432                              ENA_REGS_BAR);
1433                 return -ENXIO;
1434         }
1435
1436         ena_dev->reg_bar = adapter->regs;
1437         ena_dev->dmadev = adapter->pdev;
1438
1439         adapter->id_number = adapters_found;
1440
1441         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1442                  adapter->id_number);
1443
1444         /* device specific initialization routine */
1445         rc = ena_device_init(ena_dev, &get_feat_ctx);
1446         if (rc) {
1447                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1448                 return -1;
1449         }
1450
1451         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1452         adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1453
1454         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1455         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1456                 return -EFAULT;
1457
1458         adapter->tx_ring_size = queue_size;
1459         adapter->rx_ring_size = queue_size;
1460
1461         /* prepare ring structures */
1462         ena_init_rings(adapter);
1463
1464         ena_config_debug_area(adapter);
1465
1466         /* Set max MTU for this device */
1467         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1468
1469         /* set device support for TSO */
1470         adapter->tso4_supported = get_feat_ctx.offload.tx &
1471                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1472
1473         /* Copy MAC address and point DPDK to it */
1474         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1475         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1476                         (struct ether_addr *)adapter->mac_addr);
1477
1478         adapter->drv_stats = rte_zmalloc("adapter stats",
1479                                          sizeof(*adapter->drv_stats),
1480                                          RTE_CACHE_LINE_SIZE);
1481         if (!adapter->drv_stats) {
1482                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1483                 return -ENOMEM;
1484         }
1485
1486         rte_intr_callback_register(intr_handle,
1487                                    ena_interrupt_handler_rte,
1488                                    adapter);
1489         rte_intr_enable(intr_handle);
1490         ena_com_set_admin_polling_mode(ena_dev, false);
1491         ena_com_admin_aenq_enable(ena_dev);
1492
1493         adapters_found++;
1494         adapter->state = ENA_ADAPTER_STATE_INIT;
1495
1496         return 0;
1497 }
1498
1499 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1500 {
1501         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1502         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1503         struct ena_adapter *adapter =
1504                 (struct ena_adapter *)(eth_dev->data->dev_private);
1505
1506         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1507                 return -EPERM;
1508
1509         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1510                 ena_close(eth_dev);
1511
1512         eth_dev->dev_ops = NULL;
1513         eth_dev->rx_pkt_burst = NULL;
1514         eth_dev->tx_pkt_burst = NULL;
1515         eth_dev->tx_pkt_prepare = NULL;
1516
1517         rte_free(adapter->drv_stats);
1518         adapter->drv_stats = NULL;
1519
1520         rte_intr_disable(intr_handle);
1521         rte_intr_callback_unregister(intr_handle,
1522                                      ena_interrupt_handler_rte,
1523                                      adapter);
1524
1525         adapter->state = ENA_ADAPTER_STATE_FREE;
1526
1527         return 0;
1528 }
1529
1530 static int ena_dev_configure(struct rte_eth_dev *dev)
1531 {
1532         struct ena_adapter *adapter =
1533                 (struct ena_adapter *)(dev->data->dev_private);
1534
1535         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1536
1537         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1538         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1539         return 0;
1540 }
1541
1542 static void ena_init_rings(struct ena_adapter *adapter)
1543 {
1544         int i;
1545
1546         for (i = 0; i < adapter->num_queues; i++) {
1547                 struct ena_ring *ring = &adapter->tx_ring[i];
1548
1549                 ring->configured = 0;
1550                 ring->type = ENA_RING_TYPE_TX;
1551                 ring->adapter = adapter;
1552                 ring->id = i;
1553                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1554                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1555         }
1556
1557         for (i = 0; i < adapter->num_queues; i++) {
1558                 struct ena_ring *ring = &adapter->rx_ring[i];
1559
1560                 ring->configured = 0;
1561                 ring->type = ENA_RING_TYPE_RX;
1562                 ring->adapter = adapter;
1563                 ring->id = i;
1564         }
1565 }
1566
1567 static void ena_infos_get(struct rte_eth_dev *dev,
1568                           struct rte_eth_dev_info *dev_info)
1569 {
1570         struct ena_adapter *adapter;
1571         struct ena_com_dev *ena_dev;
1572         struct ena_com_dev_get_features_ctx feat;
1573         uint64_t rx_feat = 0, tx_feat = 0;
1574         int rc = 0;
1575
1576         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1577         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1578         adapter = (struct ena_adapter *)(dev->data->dev_private);
1579
1580         ena_dev = &adapter->ena_dev;
1581         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1582
1583         dev_info->speed_capa =
1584                         ETH_LINK_SPEED_1G   |
1585                         ETH_LINK_SPEED_2_5G |
1586                         ETH_LINK_SPEED_5G   |
1587                         ETH_LINK_SPEED_10G  |
1588                         ETH_LINK_SPEED_25G  |
1589                         ETH_LINK_SPEED_40G  |
1590                         ETH_LINK_SPEED_50G  |
1591                         ETH_LINK_SPEED_100G;
1592
1593         /* Get supported features from HW */
1594         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1595         if (unlikely(rc)) {
1596                 RTE_LOG(ERR, PMD,
1597                         "Cannot get attribute for ena device rc= %d\n", rc);
1598                 return;
1599         }
1600
1601         /* Set Tx & Rx features available for device */
1602         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1603                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1604
1605         if (feat.offload.tx &
1606             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1607                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1608                         DEV_TX_OFFLOAD_UDP_CKSUM |
1609                         DEV_TX_OFFLOAD_TCP_CKSUM;
1610
1611         if (feat.offload.rx_supported &
1612             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1613                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1614                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1615                         DEV_RX_OFFLOAD_TCP_CKSUM;
1616
1617         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1618
1619         /* Inform framework about available features */
1620         dev_info->rx_offload_capa = rx_feat;
1621         dev_info->rx_queue_offload_capa = rx_feat;
1622         dev_info->tx_offload_capa = tx_feat;
1623         dev_info->tx_queue_offload_capa = tx_feat;
1624
1625         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1626         dev_info->max_rx_pktlen  = adapter->max_mtu;
1627         dev_info->max_mac_addrs = 1;
1628
1629         dev_info->max_rx_queues = adapter->num_queues;
1630         dev_info->max_tx_queues = adapter->num_queues;
1631         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1632
1633         adapter->tx_supported_offloads = tx_feat;
1634         adapter->rx_supported_offloads = rx_feat;
1635 }
1636
1637 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1638                                   uint16_t nb_pkts)
1639 {
1640         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1641         unsigned int ring_size = rx_ring->ring_size;
1642         unsigned int ring_mask = ring_size - 1;
1643         uint16_t next_to_clean = rx_ring->next_to_clean;
1644         uint16_t desc_in_use = 0;
1645         unsigned int recv_idx = 0;
1646         struct rte_mbuf *mbuf = NULL;
1647         struct rte_mbuf *mbuf_head = NULL;
1648         struct rte_mbuf *mbuf_prev = NULL;
1649         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1650         unsigned int completed;
1651
1652         struct ena_com_rx_ctx ena_rx_ctx;
1653         int rc = 0;
1654
1655         /* Check adapter state */
1656         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1657                 RTE_LOG(ALERT, PMD,
1658                         "Trying to receive pkts while device is NOT running\n");
1659                 return 0;
1660         }
1661
1662         desc_in_use = rx_ring->next_to_use - next_to_clean;
1663         if (unlikely(nb_pkts > desc_in_use))
1664                 nb_pkts = desc_in_use;
1665
1666         for (completed = 0; completed < nb_pkts; completed++) {
1667                 int segments = 0;
1668
1669                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1670                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1671                 ena_rx_ctx.descs = 0;
1672                 /* receive packet context */
1673                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1674                                     rx_ring->ena_com_io_sq,
1675                                     &ena_rx_ctx);
1676                 if (unlikely(rc)) {
1677                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1678                         return 0;
1679                 }
1680
1681                 if (unlikely(ena_rx_ctx.descs == 0))
1682                         break;
1683
1684                 while (segments < ena_rx_ctx.descs) {
1685                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1686                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1687                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1688                         mbuf->refcnt = 1;
1689                         mbuf->next = NULL;
1690                         if (segments == 0) {
1691                                 mbuf->nb_segs = ena_rx_ctx.descs;
1692                                 mbuf->port = rx_ring->port_id;
1693                                 mbuf->pkt_len = 0;
1694                                 mbuf_head = mbuf;
1695                         } else {
1696                                 /* for multi-segment pkts create mbuf chain */
1697                                 mbuf_prev->next = mbuf;
1698                         }
1699                         mbuf_head->pkt_len += mbuf->data_len;
1700
1701                         mbuf_prev = mbuf;
1702                         segments++;
1703                         next_to_clean++;
1704                 }
1705
1706                 /* fill mbuf attributes if any */
1707                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1708                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1709
1710                 /* pass to DPDK application head mbuf */
1711                 rx_pkts[recv_idx] = mbuf_head;
1712                 recv_idx++;
1713         }
1714
1715         rx_ring->next_to_clean = next_to_clean;
1716
1717         desc_in_use = desc_in_use - completed + 1;
1718         /* Burst refill to save doorbells, memory barriers, const interval */
1719         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1720                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1721
1722         return recv_idx;
1723 }
1724
1725 static uint16_t
1726 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1727                 uint16_t nb_pkts)
1728 {
1729         int32_t ret;
1730         uint32_t i;
1731         struct rte_mbuf *m;
1732         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1733         struct ipv4_hdr *ip_hdr;
1734         uint64_t ol_flags;
1735         uint16_t frag_field;
1736
1737         for (i = 0; i != nb_pkts; i++) {
1738                 m = tx_pkts[i];
1739                 ol_flags = m->ol_flags;
1740
1741                 if (!(ol_flags & PKT_TX_IPV4))
1742                         continue;
1743
1744                 /* If there was not L2 header length specified, assume it is
1745                  * length of the ethernet header.
1746                  */
1747                 if (unlikely(m->l2_len == 0))
1748                         m->l2_len = sizeof(struct ether_hdr);
1749
1750                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1751                                                  m->l2_len);
1752                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1753
1754                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1755                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1756
1757                         /* If IPv4 header has DF flag enabled and TSO support is
1758                          * disabled, partial chcecksum should not be calculated.
1759                          */
1760                         if (!tx_ring->adapter->tso4_supported)
1761                                 continue;
1762                 }
1763
1764                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1765                                 (ol_flags & PKT_TX_L4_MASK) ==
1766                                 PKT_TX_SCTP_CKSUM) {
1767                         rte_errno = -ENOTSUP;
1768                         return i;
1769                 }
1770
1771 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1772                 ret = rte_validate_tx_offload(m);
1773                 if (ret != 0) {
1774                         rte_errno = ret;
1775                         return i;
1776                 }
1777 #endif
1778
1779                 /* In case we are supposed to TSO and have DF not set (DF=0)
1780                  * hardware must be provided with partial checksum, otherwise
1781                  * it will take care of necessary calculations.
1782                  */
1783
1784                 ret = rte_net_intel_cksum_flags_prepare(m,
1785                         ol_flags & ~PKT_TX_TCP_SEG);
1786                 if (ret != 0) {
1787                         rte_errno = ret;
1788                         return i;
1789                 }
1790         }
1791
1792         return i;
1793 }
1794
1795 static void ena_update_hints(struct ena_adapter *adapter,
1796                              struct ena_admin_ena_hw_hints *hints)
1797 {
1798         if (hints->admin_completion_tx_timeout)
1799                 adapter->ena_dev.admin_queue.completion_timeout =
1800                         hints->admin_completion_tx_timeout * 1000;
1801
1802         if (hints->mmio_read_timeout)
1803                 /* convert to usec */
1804                 adapter->ena_dev.mmio_read.reg_read_to =
1805                         hints->mmio_read_timeout * 1000;
1806 }
1807
1808 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1809                                   uint16_t nb_pkts)
1810 {
1811         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1812         uint16_t next_to_use = tx_ring->next_to_use;
1813         uint16_t next_to_clean = tx_ring->next_to_clean;
1814         struct rte_mbuf *mbuf;
1815         unsigned int ring_size = tx_ring->ring_size;
1816         unsigned int ring_mask = ring_size - 1;
1817         struct ena_com_tx_ctx ena_tx_ctx;
1818         struct ena_tx_buffer *tx_info;
1819         struct ena_com_buf *ebuf;
1820         uint16_t rc, req_id, total_tx_descs = 0;
1821         uint16_t sent_idx = 0, empty_tx_reqs;
1822         int nb_hw_desc;
1823
1824         /* Check adapter state */
1825         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1826                 RTE_LOG(ALERT, PMD,
1827                         "Trying to xmit pkts while device is NOT running\n");
1828                 return 0;
1829         }
1830
1831         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1832         if (nb_pkts > empty_tx_reqs)
1833                 nb_pkts = empty_tx_reqs;
1834
1835         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1836                 mbuf = tx_pkts[sent_idx];
1837
1838                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1839                 tx_info = &tx_ring->tx_buffer_info[req_id];
1840                 tx_info->mbuf = mbuf;
1841                 tx_info->num_of_bufs = 0;
1842                 ebuf = tx_info->bufs;
1843
1844                 /* Prepare TX context */
1845                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1846                 memset(&ena_tx_ctx.ena_meta, 0x0,
1847                        sizeof(struct ena_com_tx_meta));
1848                 ena_tx_ctx.ena_bufs = ebuf;
1849                 ena_tx_ctx.req_id = req_id;
1850                 if (tx_ring->tx_mem_queue_type ==
1851                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1852                         /* prepare the push buffer with
1853                          * virtual address of the data
1854                          */
1855                         ena_tx_ctx.header_len =
1856                                 RTE_MIN(mbuf->data_len,
1857                                         tx_ring->tx_max_header_size);
1858                         ena_tx_ctx.push_header =
1859                                 (void *)((char *)mbuf->buf_addr +
1860                                          mbuf->data_off);
1861                 } /* there's no else as we take advantage of memset zeroing */
1862
1863                 /* Set TX offloads flags, if applicable */
1864                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1865
1866                 if (unlikely(mbuf->ol_flags &
1867                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1868                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1869
1870                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1871
1872                 /* Process first segment taking into
1873                  * consideration pushed header
1874                  */
1875                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1876                         ebuf->paddr = mbuf->buf_iova +
1877                                       mbuf->data_off +
1878                                       ena_tx_ctx.header_len;
1879                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1880                         ebuf++;
1881                         tx_info->num_of_bufs++;
1882                 }
1883
1884                 while ((mbuf = mbuf->next) != NULL) {
1885                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1886                         ebuf->len = mbuf->data_len;
1887                         ebuf++;
1888                         tx_info->num_of_bufs++;
1889                 }
1890
1891                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1892
1893                 /* Write data to device */
1894                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1895                                         &ena_tx_ctx, &nb_hw_desc);
1896                 if (unlikely(rc))
1897                         break;
1898
1899                 tx_info->tx_descs = nb_hw_desc;
1900
1901                 next_to_use++;
1902         }
1903
1904         /* If there are ready packets to be xmitted... */
1905         if (sent_idx > 0) {
1906                 /* ...let HW do its best :-) */
1907                 rte_wmb();
1908                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1909
1910                 tx_ring->next_to_use = next_to_use;
1911         }
1912
1913         /* Clear complete packets  */
1914         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1915                 /* Get Tx info & store how many descs were processed  */
1916                 tx_info = &tx_ring->tx_buffer_info[req_id];
1917                 total_tx_descs += tx_info->tx_descs;
1918
1919                 /* Free whole mbuf chain  */
1920                 mbuf = tx_info->mbuf;
1921                 rte_pktmbuf_free(mbuf);
1922                 tx_info->mbuf = NULL;
1923
1924                 /* Put back descriptor to the ring for reuse */
1925                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1926                 next_to_clean++;
1927
1928                 /* If too many descs to clean, leave it for another run */
1929                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1930                         break;
1931         }
1932
1933         if (total_tx_descs > 0) {
1934                 /* acknowledge completion of sent packets */
1935                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1936                 tx_ring->next_to_clean = next_to_clean;
1937         }
1938
1939         return sent_idx;
1940 }
1941
1942 /*********************************************************************
1943  *  PMD configuration
1944  *********************************************************************/
1945 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1946         struct rte_pci_device *pci_dev)
1947 {
1948         return rte_eth_dev_pci_generic_probe(pci_dev,
1949                 sizeof(struct ena_adapter), eth_ena_dev_init);
1950 }
1951
1952 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1953 {
1954         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
1955 }
1956
1957 static struct rte_pci_driver rte_ena_pmd = {
1958         .id_table = pci_id_ena_map,
1959         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1960         .probe = eth_ena_pci_probe,
1961         .remove = eth_ena_pci_remove,
1962 };
1963
1964 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1965 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1966 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1967
1968 RTE_INIT(ena_init_log);
1969 static void
1970 ena_init_log(void)
1971 {
1972         ena_logtype_init = rte_log_register("pmd.net.ena.init");
1973         if (ena_logtype_init >= 0)
1974                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1975         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
1976         if (ena_logtype_driver >= 0)
1977                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1978 }
1979
1980 /******************************************************************************
1981  ******************************** AENQ Handlers *******************************
1982  *****************************************************************************/
1983 static void ena_update_on_link_change(void *adapter_data,
1984                                       struct ena_admin_aenq_entry *aenq_e)
1985 {
1986         struct rte_eth_dev *eth_dev;
1987         struct ena_adapter *adapter;
1988         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
1989         uint32_t status;
1990
1991         adapter = (struct ena_adapter *)adapter_data;
1992         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
1993         eth_dev = adapter->rte_dev;
1994
1995         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
1996         adapter->link_status = status;
1997
1998         ena_link_update(eth_dev, 0);
1999         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2000 }
2001
2002 static void ena_notification(void *data,
2003                              struct ena_admin_aenq_entry *aenq_e)
2004 {
2005         struct ena_adapter *adapter = (struct ena_adapter *)data;
2006         struct ena_admin_ena_hw_hints *hints;
2007
2008         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2009                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2010                         aenq_e->aenq_common_desc.group,
2011                         ENA_ADMIN_NOTIFICATION);
2012
2013         switch (aenq_e->aenq_common_desc.syndrom) {
2014         case ENA_ADMIN_UPDATE_HINTS:
2015                 hints = (struct ena_admin_ena_hw_hints *)
2016                         (&aenq_e->inline_data_w4);
2017                 ena_update_hints(adapter, hints);
2018                 break;
2019         default:
2020                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2021                         aenq_e->aenq_common_desc.syndrom);
2022         }
2023 }
2024
2025 /**
2026  * This handler will called for unknown event group or unimplemented handlers
2027  **/
2028 static void unimplemented_aenq_handler(__rte_unused void *data,
2029                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2030 {
2031         // Unimplemented handler
2032 }
2033
2034 static struct ena_aenq_handlers aenq_handlers = {
2035         .handlers = {
2036                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2037                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2038                 [ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler
2039         },
2040         .unimplemented_handler = unimplemented_aenq_handler
2041 };