drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <ethdev_driver.h>
   9 #include <ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    3
  31 #define DRV_MODULE_VER_SUBMINOR 0
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) RTE_DIM(x)
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 enum ethtool_stringset {
  55         ETH_SS_TEST             = 0,
  56         ETH_SS_STATS,
  57 };
  58
  59 struct ena_stats {
  60         char name[ETH_GSTRING_LEN];
  61         int stat_offset;
  62 };
  63
  64 #define ENA_STAT_ENTRY(stat, stat_type) { \
  65         .name = #stat, \
  66         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  67 }
  68
  69 #define ENA_STAT_RX_ENTRY(stat) \
  70         ENA_STAT_ENTRY(stat, rx)
  71
  72 #define ENA_STAT_TX_ENTRY(stat) \
  73         ENA_STAT_ENTRY(stat, tx)
  74
  75 #define ENA_STAT_ENI_ENTRY(stat) \
  76         ENA_STAT_ENTRY(stat, eni)
  77
  78 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  79         ENA_STAT_ENTRY(stat, dev)
  80
  81 /* Device arguments */
  82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  83
  84 /*
  85  * Each rte_memzone should have unique name.
  86  * To satisfy it, count number of allocation and add it to name.
  87  */
  88 rte_atomic64_t ena_alloc_cnt;
  89
  90 static const struct ena_stats ena_stats_global_strings[] = {
  91         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  92         ENA_STAT_GLOBAL_ENTRY(dev_start),
  93         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  94         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  95 };
  96
  97 static const struct ena_stats ena_stats_eni_strings[] = {
  98         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  99         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
 100         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
 101         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
 102         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
 103 };
 104
 105 static const struct ena_stats ena_stats_tx_strings[] = {
 106         ENA_STAT_TX_ENTRY(cnt),
 107         ENA_STAT_TX_ENTRY(bytes),
 108         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 109         ENA_STAT_TX_ENTRY(linearize),
 110         ENA_STAT_TX_ENTRY(linearize_failed),
 111         ENA_STAT_TX_ENTRY(tx_poll),
 112         ENA_STAT_TX_ENTRY(doorbells),
 113         ENA_STAT_TX_ENTRY(bad_req_id),
 114         ENA_STAT_TX_ENTRY(available_desc),
 115 };
 116
 117 static const struct ena_stats ena_stats_rx_strings[] = {
 118         ENA_STAT_RX_ENTRY(cnt),
 119         ENA_STAT_RX_ENTRY(bytes),
 120         ENA_STAT_RX_ENTRY(refill_partial),
 121         ENA_STAT_RX_ENTRY(bad_csum),
 122         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 123         ENA_STAT_RX_ENTRY(bad_desc_num),
 124         ENA_STAT_RX_ENTRY(bad_req_id),
 125 };
 126
 127 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 128 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 129 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 130 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 131
 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 133                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 134                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 135                         DEV_TX_OFFLOAD_TCP_TSO)
 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 137                        PKT_TX_IP_CKSUM |\
 138                        PKT_TX_TCP_SEG)
 139
 140 /** Vendor ID used by Amazon devices */
 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 142 /** Amazon devices */
 143 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 144 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 145
 146 #define ENA_TX_OFFLOAD_MASK     (\
 147         PKT_TX_L4_MASK |         \
 148         PKT_TX_IPV6 |            \
 149         PKT_TX_IPV4 |            \
 150         PKT_TX_IP_CKSUM |        \
 151         PKT_TX_TCP_SEG)
 152
 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 154         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 155
 156 static const struct rte_pci_id pci_id_ena_map[] = {
 157         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 158         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 159         { .device_id = 0 },
 160 };
 161
 162 static struct ena_aenq_handlers aenq_handlers;
 163
 164 static int ena_device_init(struct ena_com_dev *ena_dev,
 165                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 166                            bool *wd_state);
 167 static int ena_dev_configure(struct rte_eth_dev *dev);
 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 169         struct ena_tx_buffer *tx_info,
 170         struct rte_mbuf *mbuf,
 171         void **push_header,
 172         uint16_t *header_len);
 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 174 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 176                                   uint16_t nb_pkts);
 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 178                 uint16_t nb_pkts);
 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 180                               uint16_t nb_desc, unsigned int socket_id,
 181                               const struct rte_eth_txconf *tx_conf);
 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_rxconf *rx_conf,
 185                               struct rte_mempool *mp);
 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 188                                     struct ena_com_rx_buf_info *ena_bufs,
 189                                     uint32_t descs,
 190                                     uint16_t *next_to_clean,
 191                                     uint8_t offset);
 192 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 193                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 195                                   struct rte_mbuf *mbuf, uint16_t id);
 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 197 static void ena_init_rings(struct ena_adapter *adapter,
 198                            bool disable_meta_caching);
 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200 static int ena_start(struct rte_eth_dev *dev);
 201 static int ena_stop(struct rte_eth_dev *dev);
 202 static int ena_close(struct rte_eth_dev *dev);
 203 static int ena_dev_reset(struct rte_eth_dev *dev);
 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 207 static void ena_rx_queue_release(void *queue);
 208 static void ena_tx_queue_release(void *queue);
 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 211 static int ena_link_update(struct rte_eth_dev *dev,
 212                            int wait_to_complete);
 213 static int ena_create_io_queue(struct ena_ring *ring);
 214 static void ena_queue_stop(struct ena_ring *ring);
 215 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 216                               enum ena_ring_type ring_type);
 217 static int ena_queue_start(struct ena_ring *ring);
 218 static int ena_queue_start_all(struct rte_eth_dev *dev,
 219                                enum ena_ring_type ring_type);
 220 static void ena_stats_restart(struct rte_eth_dev *dev);
 221 static int ena_infos_get(struct rte_eth_dev *dev,
 222                          struct rte_eth_dev_info *dev_info);
 223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 224                                struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                uint16_t reta_size);
 226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 227                               struct rte_eth_rss_reta_entry64 *reta_conf,
 228                               uint16_t reta_size);
 229 static void ena_interrupt_handler_rte(void *cb_arg);
 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 233 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 234                                 struct rte_eth_xstat_name *xstats_names,
 235                                 unsigned int n);
 236 static int ena_xstats_get(struct rte_eth_dev *dev,
 237                           struct rte_eth_xstat *stats,
 238                           unsigned int n);
 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 240                                 const uint64_t *ids,
 241                                 uint64_t *values,
 242                                 unsigned int n);
 243 static int ena_process_bool_devarg(const char *key,
 244                                    const char *value,
 245                                    void *opaque);
 246 static int ena_parse_devargs(struct ena_adapter *adapter,
 247                              struct rte_devargs *devargs);
 248 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 249
 250 static const struct eth_dev_ops ena_dev_ops = {
 251         .dev_configure        = ena_dev_configure,
 252         .dev_infos_get        = ena_infos_get,
 253         .rx_queue_setup       = ena_rx_queue_setup,
 254         .tx_queue_setup       = ena_tx_queue_setup,
 255         .dev_start            = ena_start,
 256         .dev_stop             = ena_stop,
 257         .link_update          = ena_link_update,
 258         .stats_get            = ena_stats_get,
 259         .xstats_get_names     = ena_xstats_get_names,
 260         .xstats_get           = ena_xstats_get,
 261         .xstats_get_by_id     = ena_xstats_get_by_id,
 262         .mtu_set              = ena_mtu_set,
 263         .rx_queue_release     = ena_rx_queue_release,
 264         .tx_queue_release     = ena_tx_queue_release,
 265         .dev_close            = ena_close,
 266         .dev_reset            = ena_dev_reset,
 267         .reta_update          = ena_rss_reta_update,
 268         .reta_query           = ena_rss_reta_query,
 269 };
 270
 271 void ena_rss_key_fill(void *key, size_t size)
 272 {
 273         static bool key_generated;
 274         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 275         size_t i;
 276
 277         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 278
 279         if (!key_generated) {
 280                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 281                         default_key[i] = rte_rand() & 0xff;
 282                 key_generated = true;
 283         }
 284
 285         rte_memcpy(key, default_key, size);
 286 }
 287
 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 289                                        struct ena_com_rx_ctx *ena_rx_ctx)
 290 {
 291         uint64_t ol_flags = 0;
 292         uint32_t packet_type = 0;
 293
 294         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 295                 packet_type |= RTE_PTYPE_L4_TCP;
 296         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 297                 packet_type |= RTE_PTYPE_L4_UDP;
 298
 299         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 300                 packet_type |= RTE_PTYPE_L3_IPV4;
 301                 if (unlikely(ena_rx_ctx->l3_csum_err))
 302                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 303                 else
 304                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 305         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 306                 packet_type |= RTE_PTYPE_L3_IPV6;
 307         }
 308
 309         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 310                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 311         else
 312                 if (unlikely(ena_rx_ctx->l4_csum_err))
 313                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 314                 else
 315                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 316
 317         mbuf->ol_flags = ol_flags;
 318         mbuf->packet_type = packet_type;
 319 }
 320
 321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 322                                        struct ena_com_tx_ctx *ena_tx_ctx,
 323                                        uint64_t queue_offloads,
 324                                        bool disable_meta_caching)
 325 {
 326         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 327
 328         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 329             (queue_offloads & QUEUE_OFFLOADS)) {
 330                 /* check if TSO is required */
 331                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 332                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 333                         ena_tx_ctx->tso_enable = true;
 334
 335                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 336                 }
 337
 338                 /* check if L3 checksum is needed */
 339                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 340                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 341                         ena_tx_ctx->l3_csum_enable = true;
 342
 343                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 344                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 345                 } else {
 346                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 347
 348                         /* set don't fragment (DF) flag */
 349                         if (mbuf->packet_type &
 350                                 (RTE_PTYPE_L4_NONFRAG
 351                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 352                                 ena_tx_ctx->df = true;
 353                 }
 354
 355                 /* check if L4 checksum is needed */
 356                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 357                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 358                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 359                         ena_tx_ctx->l4_csum_enable = true;
 360                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 361                                 PKT_TX_UDP_CKSUM) &&
 362                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else {
 366                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 367                         ena_tx_ctx->l4_csum_enable = false;
 368                 }
 369
 370                 ena_meta->mss = mbuf->tso_segsz;
 371                 ena_meta->l3_hdr_len = mbuf->l3_len;
 372                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 373
 374                 ena_tx_ctx->meta_valid = true;
 375         } else if (disable_meta_caching) {
 376                 memset(ena_meta, 0, sizeof(*ena_meta));
 377                 ena_tx_ctx->meta_valid = true;
 378         } else {
 379                 ena_tx_ctx->meta_valid = false;
 380         }
 381 }
 382
 383 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 384 {
 385         struct ena_tx_buffer *tx_info = NULL;
 386
 387         if (likely(req_id < tx_ring->ring_size)) {
 388                 tx_info = &tx_ring->tx_buffer_info[req_id];
 389                 if (likely(tx_info->mbuf))
 390                         return 0;
 391         }
 392
 393         if (tx_info)
 394                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 395         else
 396                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 397
 398         /* Trigger device reset */
 399         ++tx_ring->tx_stats.bad_req_id;
 400         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 401         tx_ring->adapter->trigger_reset = true;
 402         return -EFAULT;
 403 }
 404
 405 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 406 {
 407         struct ena_admin_host_info *host_info;
 408         int rc;
 409
 410         /* Allocate only the host info */
 411         rc = ena_com_allocate_host_info(ena_dev);
 412         if (rc) {
 413                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 414                 return;
 415         }
 416
 417         host_info = ena_dev->host_attr.host_info;
 418
 419         host_info->os_type = ENA_ADMIN_OS_DPDK;
 420         host_info->kernel_ver = RTE_VERSION;
 421         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 422                 sizeof(host_info->kernel_ver_str));
 423         host_info->os_dist = RTE_VERSION;
 424         strlcpy((char *)host_info->os_dist_str, rte_version(),
 425                 sizeof(host_info->os_dist_str));
 426         host_info->driver_version =
 427                 (DRV_MODULE_VER_MAJOR) |
 428                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 429                 (DRV_MODULE_VER_SUBMINOR <<
 430                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 431         host_info->num_cpus = rte_lcore_count();
 432
 433         host_info->driver_supported_features =
 434                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 435
 436         rc = ena_com_set_host_attributes(ena_dev);
 437         if (rc) {
 438                 if (rc == -ENA_COM_UNSUPPORTED)
 439                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 440                 else
 441                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 442
 443                 goto err;
 444         }
 445
 446         return;
 447
 448 err:
 449         ena_com_delete_host_info(ena_dev);
 450 }
 451
 452 /* This function calculates the number of xstats based on the current config */
 453 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 454 {
 455         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 456                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 457                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 458 }
 459
 460 static void ena_config_debug_area(struct ena_adapter *adapter)
 461 {
 462         u32 debug_area_size;
 463         int rc, ss_count;
 464
 465         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 466
 467         /* allocate 32 bytes for each string and 64bit for the value */
 468         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 469
 470         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 471         if (rc) {
 472                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 473                 return;
 474         }
 475
 476         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 477         if (rc) {
 478                 if (rc == -ENA_COM_UNSUPPORTED)
 479                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 480                 else
 481                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 482
 483                 goto err;
 484         }
 485
 486         return;
 487 err:
 488         ena_com_delete_debug_area(&adapter->ena_dev);
 489 }
 490
 491 static int ena_close(struct rte_eth_dev *dev)
 492 {
 493         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 494         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 495         struct ena_adapter *adapter = dev->data->dev_private;
 496         int ret = 0;
 497
 498         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 499                 return 0;
 500
 501         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 502                 ret = ena_stop(dev);
 503         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 504
 505         ena_rx_queue_release_all(dev);
 506         ena_tx_queue_release_all(dev);
 507
 508         rte_free(adapter->drv_stats);
 509         adapter->drv_stats = NULL;
 510
 511         rte_intr_disable(intr_handle);
 512         rte_intr_callback_unregister(intr_handle,
 513                                      ena_interrupt_handler_rte,
 514                                      adapter);
 515
 516         /*
 517          * MAC is not allocated dynamically. Setting NULL should prevent from
 518          * release of the resource in the rte_eth_dev_release_port().
 519          */
 520         dev->data->mac_addrs = NULL;
 521
 522         return ret;
 523 }
 524
 525 static int
 526 ena_dev_reset(struct rte_eth_dev *dev)
 527 {
 528         int rc = 0;
 529
 530         ena_destroy_device(dev);
 531         rc = eth_ena_dev_init(dev);
 532         if (rc)
 533                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 534
 535         return rc;
 536 }
 537
 538 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 539                                struct rte_eth_rss_reta_entry64 *reta_conf,
 540                                uint16_t reta_size)
 541 {
 542         struct ena_adapter *adapter = dev->data->dev_private;
 543         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 544         int rc, i;
 545         u16 entry_value;
 546         int conf_idx;
 547         int idx;
 548
 549         if ((reta_size == 0) || (reta_conf == NULL))
 550                 return -EINVAL;
 551
 552         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 553                 PMD_DRV_LOG(WARNING,
 554                         "indirection table %d is bigger than supported (%d)\n",
 555                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 556                 return -EINVAL;
 557         }
 558
 559         for (i = 0 ; i < reta_size ; i++) {
 560                 /* each reta_conf is for 64 entries.
 561                  * to support 128 we use 2 conf of 64
 562                  */
 563                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 564                 idx = i % RTE_RETA_GROUP_SIZE;
 565                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 566                         entry_value =
 567                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 568
 569                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 570                                                                i,
 571                                                                entry_value);
 572                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 573                                 PMD_DRV_LOG(ERR,
 574                                         "Cannot fill indirect table\n");
 575                                 return rc;
 576                         }
 577                 }
 578         }
 579
 580         rte_spinlock_lock(&adapter->admin_lock);
 581         rc = ena_com_indirect_table_set(ena_dev);
 582         rte_spinlock_unlock(&adapter->admin_lock);
 583         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 584                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 585                 return rc;
 586         }
 587
 588         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 589                 __func__, reta_size, adapter->rte_dev->data->port_id);
 590
 591         return 0;
 592 }
 593
 594 /* Query redirection table. */
 595 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 596                               struct rte_eth_rss_reta_entry64 *reta_conf,
 597                               uint16_t reta_size)
 598 {
 599         struct ena_adapter *adapter = dev->data->dev_private;
 600         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 601         int rc;
 602         int i;
 603         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 604         int reta_conf_idx;
 605         int reta_idx;
 606
 607         if (reta_size == 0 || reta_conf == NULL ||
 608             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 609                 return -EINVAL;
 610
 611         rte_spinlock_lock(&adapter->admin_lock);
 612         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 613         rte_spinlock_unlock(&adapter->admin_lock);
 614         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 615                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 616                 return -ENOTSUP;
 617         }
 618
 619         for (i = 0 ; i < reta_size ; i++) {
 620                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 621                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 622                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 623                         reta_conf[reta_conf_idx].reta[reta_idx] =
 624                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int ena_rss_init_default(struct ena_adapter *adapter)
 631 {
 632         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 633         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 634         int rc, i;
 635         u32 val;
 636
 637         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 638         if (unlikely(rc)) {
 639                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 640                 goto err_rss_init;
 641         }
 642
 643         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 644                 val = i % nb_rx_queues;
 645                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 646                                                        ENA_IO_RXQ_IDX(val));
 647                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 648                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 649                         goto err_fill_indir;
 650                 }
 651         }
 652
 653         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 654                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 655         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 656                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 657                 goto err_fill_indir;
 658         }
 659
 660         rc = ena_com_set_default_hash_ctrl(ena_dev);
 661         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 662                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 663                 goto err_fill_indir;
 664         }
 665
 666         rc = ena_com_indirect_table_set(ena_dev);
 667         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 668                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 669                 goto err_fill_indir;
 670         }
 671         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 672                 adapter->rte_dev->data->port_id);
 673
 674         return 0;
 675
 676 err_fill_indir:
 677         ena_com_rss_destroy(ena_dev);
 678 err_rss_init:
 679
 680         return rc;
 681 }
 682
 683 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 684 {
 685         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 686         int nb_queues = dev->data->nb_rx_queues;
 687         int i;
 688
 689         for (i = 0; i < nb_queues; i++)
 690                 ena_rx_queue_release(queues[i]);
 691 }
 692
 693 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 694 {
 695         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 696         int nb_queues = dev->data->nb_tx_queues;
 697         int i;
 698
 699         for (i = 0; i < nb_queues; i++)
 700                 ena_tx_queue_release(queues[i]);
 701 }
 702
 703 static void ena_rx_queue_release(void *queue)
 704 {
 705         struct ena_ring *ring = (struct ena_ring *)queue;
 706
 707         /* Free ring resources */
 708         if (ring->rx_buffer_info)
 709                 rte_free(ring->rx_buffer_info);
 710         ring->rx_buffer_info = NULL;
 711
 712         if (ring->rx_refill_buffer)
 713                 rte_free(ring->rx_refill_buffer);
 714         ring->rx_refill_buffer = NULL;
 715
 716         if (ring->empty_rx_reqs)
 717                 rte_free(ring->empty_rx_reqs);
 718         ring->empty_rx_reqs = NULL;
 719
 720         ring->configured = 0;
 721
 722         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 723                 ring->port_id, ring->id);
 724 }
 725
 726 static void ena_tx_queue_release(void *queue)
 727 {
 728         struct ena_ring *ring = (struct ena_ring *)queue;
 729
 730         /* Free ring resources */
 731         if (ring->push_buf_intermediate_buf)
 732                 rte_free(ring->push_buf_intermediate_buf);
 733
 734         if (ring->tx_buffer_info)
 735                 rte_free(ring->tx_buffer_info);
 736
 737         if (ring->empty_tx_reqs)
 738                 rte_free(ring->empty_tx_reqs);
 739
 740         ring->empty_tx_reqs = NULL;
 741         ring->tx_buffer_info = NULL;
 742         ring->push_buf_intermediate_buf = NULL;
 743
 744         ring->configured = 0;
 745
 746         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 747                 ring->port_id, ring->id);
 748 }
 749
 750 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 751 {
 752         unsigned int i;
 753
 754         for (i = 0; i < ring->ring_size; ++i) {
 755                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 756                 if (rx_info->mbuf) {
 757                         rte_mbuf_raw_free(rx_info->mbuf);
 758                         rx_info->mbuf = NULL;
 759                 }
 760         }
 761 }
 762
 763 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 764 {
 765         unsigned int i;
 766
 767         for (i = 0; i < ring->ring_size; ++i) {
 768                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 769
 770                 if (tx_buf->mbuf) {
 771                         rte_pktmbuf_free(tx_buf->mbuf);
 772                         tx_buf->mbuf = NULL;
 773                 }
 774         }
 775 }
 776
 777 static int ena_link_update(struct rte_eth_dev *dev,
 778                            __rte_unused int wait_to_complete)
 779 {
 780         struct rte_eth_link *link = &dev->data->dev_link;
 781         struct ena_adapter *adapter = dev->data->dev_private;
 782
 783         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 784         link->link_speed = ETH_SPEED_NUM_NONE;
 785         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 786
 787         return 0;
 788 }
 789
 790 static int ena_queue_start_all(struct rte_eth_dev *dev,
 791                                enum ena_ring_type ring_type)
 792 {
 793         struct ena_adapter *adapter = dev->data->dev_private;
 794         struct ena_ring *queues = NULL;
 795         int nb_queues;
 796         int i = 0;
 797         int rc = 0;
 798
 799         if (ring_type == ENA_RING_TYPE_RX) {
 800                 queues = adapter->rx_ring;
 801                 nb_queues = dev->data->nb_rx_queues;
 802         } else {
 803                 queues = adapter->tx_ring;
 804                 nb_queues = dev->data->nb_tx_queues;
 805         }
 806         for (i = 0; i < nb_queues; i++) {
 807                 if (queues[i].configured) {
 808                         if (ring_type == ENA_RING_TYPE_RX) {
 809                                 ena_assert_msg(
 810                                         dev->data->rx_queues[i] == &queues[i],
 811                                         "Inconsistent state of rx queues\n");
 812                         } else {
 813                                 ena_assert_msg(
 814                                         dev->data->tx_queues[i] == &queues[i],
 815                                         "Inconsistent state of tx queues\n");
 816                         }
 817
 818                         rc = ena_queue_start(&queues[i]);
 819
 820                         if (rc) {
 821                                 PMD_INIT_LOG(ERR,
 822                                              "failed to start queue %d type(%d)",
 823                                              i, ring_type);
 824                                 goto err;
 825                         }
 826                 }
 827         }
 828
 829         return 0;
 830
 831 err:
 832         while (i--)
 833                 if (queues[i].configured)
 834                         ena_queue_stop(&queues[i]);
 835
 836         return rc;
 837 }
 838
 839 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 840 {
 841         uint32_t max_frame_len = adapter->max_mtu;
 842
 843         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 844             DEV_RX_OFFLOAD_JUMBO_FRAME)
 845                 max_frame_len =
 846                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 847
 848         return max_frame_len;
 849 }
 850
 851 static int ena_check_valid_conf(struct ena_adapter *adapter)
 852 {
 853         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 854
 855         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 856                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 857                                   "max mtu: %d, min mtu: %d",
 858                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 859                 return ENA_COM_UNSUPPORTED;
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int
 866 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 867                        bool use_large_llq_hdr)
 868 {
 869         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 870         struct ena_com_dev *ena_dev = ctx->ena_dev;
 871         uint32_t max_tx_queue_size;
 872         uint32_t max_rx_queue_size;
 873
 874         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 875                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 876                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 877                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 878                         max_queue_ext->max_rx_sq_depth);
 879                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 880
 881                 if (ena_dev->tx_mem_queue_type ==
 882                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 883                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 884                                 llq->max_llq_depth);
 885                 } else {
 886                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 887                                 max_queue_ext->max_tx_sq_depth);
 888                 }
 889
 890                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 891                         max_queue_ext->max_per_packet_rx_descs);
 892                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 893                         max_queue_ext->max_per_packet_tx_descs);
 894         } else {
 895                 struct ena_admin_queue_feature_desc *max_queues =
 896                         &ctx->get_feat_ctx->max_queues;
 897                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 898                         max_queues->max_sq_depth);
 899                 max_tx_queue_size = max_queues->max_cq_depth;
 900
 901                 if (ena_dev->tx_mem_queue_type ==
 902                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 903                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 904                                 llq->max_llq_depth);
 905                 } else {
 906                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 907                                 max_queues->max_sq_depth);
 908                 }
 909
 910                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 911                         max_queues->max_packet_rx_descs);
 912                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 913                         max_queues->max_packet_tx_descs);
 914         }
 915
 916         /* Round down to the nearest power of 2 */
 917         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 918         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 919
 920         if (use_large_llq_hdr) {
 921                 if ((llq->entry_size_ctrl_supported &
 922                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 923                     (ena_dev->tx_mem_queue_type ==
 924                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 925                         max_tx_queue_size /= 2;
 926                         PMD_INIT_LOG(INFO,
 927                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 928                                 max_tx_queue_size);
 929                 } else {
 930                         PMD_INIT_LOG(ERR,
 931                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 932                 }
 933         }
 934
 935         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 936                 PMD_INIT_LOG(ERR, "Invalid queue size");
 937                 return -EFAULT;
 938         }
 939
 940         ctx->max_tx_queue_size = max_tx_queue_size;
 941         ctx->max_rx_queue_size = max_rx_queue_size;
 942
 943         return 0;
 944 }
 945
 946 static void ena_stats_restart(struct rte_eth_dev *dev)
 947 {
 948         struct ena_adapter *adapter = dev->data->dev_private;
 949
 950         rte_atomic64_init(&adapter->drv_stats->ierrors);
 951         rte_atomic64_init(&adapter->drv_stats->oerrors);
 952         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 953         adapter->drv_stats->rx_drops = 0;
 954 }
 955
 956 static int ena_stats_get(struct rte_eth_dev *dev,
 957                           struct rte_eth_stats *stats)
 958 {
 959         struct ena_admin_basic_stats ena_stats;
 960         struct ena_adapter *adapter = dev->data->dev_private;
 961         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 962         int rc;
 963         int i;
 964         int max_rings_stats;
 965
 966         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 967                 return -ENOTSUP;
 968
 969         memset(&ena_stats, 0, sizeof(ena_stats));
 970
 971         rte_spinlock_lock(&adapter->admin_lock);
 972         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 973         rte_spinlock_unlock(&adapter->admin_lock);
 974         if (unlikely(rc)) {
 975                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 976                 return rc;
 977         }
 978
 979         /* Set of basic statistics from ENA */
 980         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 981                                           ena_stats.rx_pkts_low);
 982         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 983                                           ena_stats.tx_pkts_low);
 984         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 985                                         ena_stats.rx_bytes_low);
 986         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 987                                         ena_stats.tx_bytes_low);
 988
 989         /* Driver related stats */
 990         stats->imissed = adapter->drv_stats->rx_drops;
 991         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 992         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 993         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 994
 995         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 996                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 997         for (i = 0; i < max_rings_stats; ++i) {
 998                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 999
1000                 stats->q_ibytes[i] = rx_stats->bytes;
1001                 stats->q_ipackets[i] = rx_stats->cnt;
1002                 stats->q_errors[i] = rx_stats->bad_desc_num +
1003                         rx_stats->bad_req_id;
1004         }
1005
1006         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1007                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1008         for (i = 0; i < max_rings_stats; ++i) {
1009                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1010
1011                 stats->q_obytes[i] = tx_stats->bytes;
1012                 stats->q_opackets[i] = tx_stats->cnt;
1013         }
1014
1015         return 0;
1016 }
1017
1018 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1019 {
1020         struct ena_adapter *adapter;
1021         struct ena_com_dev *ena_dev;
1022         int rc = 0;
1023
1024         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1025         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1026         adapter = dev->data->dev_private;
1027
1028         ena_dev = &adapter->ena_dev;
1029         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1030
1031         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1032                 PMD_DRV_LOG(ERR,
1033                         "Invalid MTU setting. new_mtu: %d "
1034                         "max mtu: %d min mtu: %d\n",
1035                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1036                 return -EINVAL;
1037         }
1038
1039         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1040         if (rc)
1041                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1042         else
1043                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1044
1045         return rc;
1046 }
1047
1048 static int ena_start(struct rte_eth_dev *dev)
1049 {
1050         struct ena_adapter *adapter = dev->data->dev_private;
1051         uint64_t ticks;
1052         int rc = 0;
1053
1054         rc = ena_check_valid_conf(adapter);
1055         if (rc)
1056                 return rc;
1057
1058         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1059         if (rc)
1060                 return rc;
1061
1062         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1063         if (rc)
1064                 goto err_start_tx;
1065
1066         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1067             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1068                 rc = ena_rss_init_default(adapter);
1069                 if (rc)
1070                         goto err_rss_init;
1071         }
1072
1073         ena_stats_restart(dev);
1074
1075         adapter->timestamp_wd = rte_get_timer_cycles();
1076         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1077
1078         ticks = rte_get_timer_hz();
1079         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1080                         ena_timer_wd_callback, adapter);
1081
1082         ++adapter->dev_stats.dev_start;
1083         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1084
1085         return 0;
1086
1087 err_rss_init:
1088         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1089 err_start_tx:
1090         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1091         return rc;
1092 }
1093
1094 static int ena_stop(struct rte_eth_dev *dev)
1095 {
1096         struct ena_adapter *adapter = dev->data->dev_private;
1097         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1098         int rc;
1099
1100         rte_timer_stop_sync(&adapter->timer_wd);
1101         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1102         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1103
1104         if (adapter->trigger_reset) {
1105                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1106                 if (rc)
1107                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1108         }
1109
1110         ++adapter->dev_stats.dev_stop;
1111         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1112         dev->data->dev_started = 0;
1113
1114         return 0;
1115 }
1116
1117 static int ena_create_io_queue(struct ena_ring *ring)
1118 {
1119         struct ena_adapter *adapter;
1120         struct ena_com_dev *ena_dev;
1121         struct ena_com_create_io_ctx ctx =
1122                 /* policy set to _HOST just to satisfy icc compiler */
1123                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1124                   0, 0, 0, 0, 0 };
1125         uint16_t ena_qid;
1126         unsigned int i;
1127         int rc;
1128
1129         adapter = ring->adapter;
1130         ena_dev = &adapter->ena_dev;
1131
1132         if (ring->type == ENA_RING_TYPE_TX) {
1133                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1134                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1135                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1136                 for (i = 0; i < ring->ring_size; i++)
1137                         ring->empty_tx_reqs[i] = i;
1138         } else {
1139                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1140                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1141                 for (i = 0; i < ring->ring_size; i++)
1142                         ring->empty_rx_reqs[i] = i;
1143         }
1144         ctx.queue_size = ring->ring_size;
1145         ctx.qid = ena_qid;
1146         ctx.msix_vector = -1; /* interrupts not used */
1147         ctx.numa_node = ring->numa_socket_id;
1148
1149         rc = ena_com_create_io_queue(ena_dev, &ctx);
1150         if (rc) {
1151                 PMD_DRV_LOG(ERR,
1152                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1153                         ring->id, ena_qid, rc);
1154                 return rc;
1155         }
1156
1157         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1158                                      &ring->ena_com_io_sq,
1159                                      &ring->ena_com_io_cq);
1160         if (rc) {
1161                 PMD_DRV_LOG(ERR,
1162                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1163                         ring->id, rc);
1164                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1165                 return rc;
1166         }
1167
1168         if (ring->type == ENA_RING_TYPE_TX)
1169                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1170
1171         return 0;
1172 }
1173
1174 static void ena_queue_stop(struct ena_ring *ring)
1175 {
1176         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1177
1178         if (ring->type == ENA_RING_TYPE_RX) {
1179                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1180                 ena_rx_queue_release_bufs(ring);
1181         } else {
1182                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1183                 ena_tx_queue_release_bufs(ring);
1184         }
1185 }
1186
1187 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1188                               enum ena_ring_type ring_type)
1189 {
1190         struct ena_adapter *adapter = dev->data->dev_private;
1191         struct ena_ring *queues = NULL;
1192         uint16_t nb_queues, i;
1193
1194         if (ring_type == ENA_RING_TYPE_RX) {
1195                 queues = adapter->rx_ring;
1196                 nb_queues = dev->data->nb_rx_queues;
1197         } else {
1198                 queues = adapter->tx_ring;
1199                 nb_queues = dev->data->nb_tx_queues;
1200         }
1201
1202         for (i = 0; i < nb_queues; ++i)
1203                 if (queues[i].configured)
1204                         ena_queue_stop(&queues[i]);
1205 }
1206
1207 static int ena_queue_start(struct ena_ring *ring)
1208 {
1209         int rc, bufs_num;
1210
1211         ena_assert_msg(ring->configured == 1,
1212                        "Trying to start unconfigured queue\n");
1213
1214         rc = ena_create_io_queue(ring);
1215         if (rc) {
1216                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1217                 return rc;
1218         }
1219
1220         ring->next_to_clean = 0;
1221         ring->next_to_use = 0;
1222
1223         if (ring->type == ENA_RING_TYPE_TX) {
1224                 ring->tx_stats.available_desc =
1225                         ena_com_free_q_entries(ring->ena_com_io_sq);
1226                 return 0;
1227         }
1228
1229         bufs_num = ring->ring_size - 1;
1230         rc = ena_populate_rx_queue(ring, bufs_num);
1231         if (rc != bufs_num) {
1232                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1233                                          ENA_IO_RXQ_IDX(ring->id));
1234                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1235                 return ENA_COM_FAULT;
1236         }
1237         /* Flush per-core RX buffers pools cache as they can be used on other
1238          * cores as well.
1239          */
1240         rte_mempool_cache_flush(NULL, ring->mb_pool);
1241
1242         return 0;
1243 }
1244
1245 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1246                               uint16_t queue_idx,
1247                               uint16_t nb_desc,
1248                               unsigned int socket_id,
1249                               const struct rte_eth_txconf *tx_conf)
1250 {
1251         struct ena_ring *txq = NULL;
1252         struct ena_adapter *adapter = dev->data->dev_private;
1253         unsigned int i;
1254
1255         txq = &adapter->tx_ring[queue_idx];
1256
1257         if (txq->configured) {
1258                 PMD_DRV_LOG(CRIT,
1259                         "API violation. Queue %d is already configured\n",
1260                         queue_idx);
1261                 return ENA_COM_FAULT;
1262         }
1263
1264         if (!rte_is_power_of_2(nb_desc)) {
1265                 PMD_DRV_LOG(ERR,
1266                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1267                         nb_desc);
1268                 return -EINVAL;
1269         }
1270
1271         if (nb_desc > adapter->max_tx_ring_size) {
1272                 PMD_DRV_LOG(ERR,
1273                         "Unsupported size of TX queue (max size: %d)\n",
1274                         adapter->max_tx_ring_size);
1275                 return -EINVAL;
1276         }
1277
1278         txq->port_id = dev->data->port_id;
1279         txq->next_to_clean = 0;
1280         txq->next_to_use = 0;
1281         txq->ring_size = nb_desc;
1282         txq->size_mask = nb_desc - 1;
1283         txq->numa_socket_id = socket_id;
1284         txq->pkts_without_db = false;
1285
1286         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1287                                           sizeof(struct ena_tx_buffer) *
1288                                           txq->ring_size,
1289                                           RTE_CACHE_LINE_SIZE);
1290         if (!txq->tx_buffer_info) {
1291                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1292                 return -ENOMEM;
1293         }
1294
1295         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1296                                          sizeof(u16) * txq->ring_size,
1297                                          RTE_CACHE_LINE_SIZE);
1298         if (!txq->empty_tx_reqs) {
1299                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1300                 rte_free(txq->tx_buffer_info);
1301                 return -ENOMEM;
1302         }
1303
1304         txq->push_buf_intermediate_buf =
1305                 rte_zmalloc("txq->push_buf_intermediate_buf",
1306                             txq->tx_max_header_size,
1307                             RTE_CACHE_LINE_SIZE);
1308         if (!txq->push_buf_intermediate_buf) {
1309                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1310                 rte_free(txq->tx_buffer_info);
1311                 rte_free(txq->empty_tx_reqs);
1312                 return -ENOMEM;
1313         }
1314
1315         for (i = 0; i < txq->ring_size; i++)
1316                 txq->empty_tx_reqs[i] = i;
1317
1318         if (tx_conf != NULL) {
1319                 txq->offloads =
1320                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1321         }
1322         /* Store pointer to this queue in upper layer */
1323         txq->configured = 1;
1324         dev->data->tx_queues[queue_idx] = txq;
1325
1326         return 0;
1327 }
1328
1329 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1330                               uint16_t queue_idx,
1331                               uint16_t nb_desc,
1332                               unsigned int socket_id,
1333                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1334                               struct rte_mempool *mp)
1335 {
1336         struct ena_adapter *adapter = dev->data->dev_private;
1337         struct ena_ring *rxq = NULL;
1338         size_t buffer_size;
1339         int i;
1340
1341         rxq = &adapter->rx_ring[queue_idx];
1342         if (rxq->configured) {
1343                 PMD_DRV_LOG(CRIT,
1344                         "API violation. Queue %d is already configured\n",
1345                         queue_idx);
1346                 return ENA_COM_FAULT;
1347         }
1348
1349         if (!rte_is_power_of_2(nb_desc)) {
1350                 PMD_DRV_LOG(ERR,
1351                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1352                         nb_desc);
1353                 return -EINVAL;
1354         }
1355
1356         if (nb_desc > adapter->max_rx_ring_size) {
1357                 PMD_DRV_LOG(ERR,
1358                         "Unsupported size of RX queue (max size: %d)\n",
1359                         adapter->max_rx_ring_size);
1360                 return -EINVAL;
1361         }
1362
1363         /* ENA isn't supporting buffers smaller than 1400 bytes */
1364         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1365         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1366                 PMD_DRV_LOG(ERR,
1367                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1368                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1369                 return -EINVAL;
1370         }
1371
1372         rxq->port_id = dev->data->port_id;
1373         rxq->next_to_clean = 0;
1374         rxq->next_to_use = 0;
1375         rxq->ring_size = nb_desc;
1376         rxq->size_mask = nb_desc - 1;
1377         rxq->numa_socket_id = socket_id;
1378         rxq->mb_pool = mp;
1379
1380         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1381                 sizeof(struct ena_rx_buffer) * nb_desc,
1382                 RTE_CACHE_LINE_SIZE);
1383         if (!rxq->rx_buffer_info) {
1384                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1385                 return -ENOMEM;
1386         }
1387
1388         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1389                                             sizeof(struct rte_mbuf *) * nb_desc,
1390                                             RTE_CACHE_LINE_SIZE);
1391
1392         if (!rxq->rx_refill_buffer) {
1393                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1394                 rte_free(rxq->rx_buffer_info);
1395                 rxq->rx_buffer_info = NULL;
1396                 return -ENOMEM;
1397         }
1398
1399         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1400                                          sizeof(uint16_t) * nb_desc,
1401                                          RTE_CACHE_LINE_SIZE);
1402         if (!rxq->empty_rx_reqs) {
1403                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1404                 rte_free(rxq->rx_buffer_info);
1405                 rxq->rx_buffer_info = NULL;
1406                 rte_free(rxq->rx_refill_buffer);
1407                 rxq->rx_refill_buffer = NULL;
1408                 return -ENOMEM;
1409         }
1410
1411         for (i = 0; i < nb_desc; i++)
1412                 rxq->empty_rx_reqs[i] = i;
1413
1414         /* Store pointer to this queue in upper layer */
1415         rxq->configured = 1;
1416         dev->data->rx_queues[queue_idx] = rxq;
1417
1418         return 0;
1419 }
1420
1421 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1422                                   struct rte_mbuf *mbuf, uint16_t id)
1423 {
1424         struct ena_com_buf ebuf;
1425         int rc;
1426
1427         /* prepare physical address for DMA transaction */
1428         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1429         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1430
1431         /* pass resource to device */
1432         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1433         if (unlikely(rc != 0))
1434                 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1435
1436         return rc;
1437 }
1438
1439 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1440 {
1441         unsigned int i;
1442         int rc;
1443         uint16_t next_to_use = rxq->next_to_use;
1444         uint16_t in_use, req_id;
1445         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1446
1447         if (unlikely(!count))
1448                 return 0;
1449
1450         in_use = rxq->ring_size - 1 -
1451                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1452         ena_assert_msg(((in_use + count) < rxq->ring_size),
1453                 "bad ring state\n");
1454
1455         /* get resources for incoming packets */
1456         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1457         if (unlikely(rc < 0)) {
1458                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1459                 ++rxq->rx_stats.mbuf_alloc_fail;
1460                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1461                 return 0;
1462         }
1463
1464         for (i = 0; i < count; i++) {
1465                 struct rte_mbuf *mbuf = mbufs[i];
1466                 struct ena_rx_buffer *rx_info;
1467
1468                 if (likely((i + 4) < count))
1469                         rte_prefetch0(mbufs[i + 4]);
1470
1471                 req_id = rxq->empty_rx_reqs[next_to_use];
1472                 rx_info = &rxq->rx_buffer_info[req_id];
1473
1474                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1475                 if (unlikely(rc != 0))
1476                         break;
1477
1478                 rx_info->mbuf = mbuf;
1479                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1480         }
1481
1482         if (unlikely(i < count)) {
1483                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1484                         "buffers (from %d)\n", rxq->id, i, count);
1485                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1486                 ++rxq->rx_stats.refill_partial;
1487         }
1488
1489         /* When we submitted free recources to device... */
1490         if (likely(i > 0)) {
1491                 /* ...let HW know that it can fill buffers with data. */
1492                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1493
1494                 rxq->next_to_use = next_to_use;
1495         }
1496
1497         return i;
1498 }
1499
1500 static int ena_device_init(struct ena_com_dev *ena_dev,
1501                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1502                            bool *wd_state)
1503 {
1504         uint32_t aenq_groups;
1505         int rc;
1506         bool readless_supported;
1507
1508         /* Initialize mmio registers */
1509         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1510         if (rc) {
1511                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1512                 return rc;
1513         }
1514
1515         /* The PCIe configuration space revision id indicate if mmio reg
1516          * read is disabled.
1517          */
1518         readless_supported =
1519                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1520                                & ENA_MMIO_DISABLE_REG_READ);
1521         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1522
1523         /* reset device */
1524         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1525         if (rc) {
1526                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1527                 goto err_mmio_read_less;
1528         }
1529
1530         /* check FW version */
1531         rc = ena_com_validate_version(ena_dev);
1532         if (rc) {
1533                 PMD_DRV_LOG(ERR, "device version is too low\n");
1534                 goto err_mmio_read_less;
1535         }
1536
1537         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1538
1539         /* ENA device administration layer init */
1540         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1541         if (rc) {
1542                 PMD_DRV_LOG(ERR,
1543                         "cannot initialize ena admin queue with device\n");
1544                 goto err_mmio_read_less;
1545         }
1546
1547         /* To enable the msix interrupts the driver needs to know the number
1548          * of queues. So the driver uses polling mode to retrieve this
1549          * information.
1550          */
1551         ena_com_set_admin_polling_mode(ena_dev, true);
1552
1553         ena_config_host_info(ena_dev);
1554
1555         /* Get Device Attributes and features */
1556         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1557         if (rc) {
1558                 PMD_DRV_LOG(ERR,
1559                         "cannot get attribute for ena device rc= %d\n", rc);
1560                 goto err_admin_init;
1561         }
1562
1563         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1564                       BIT(ENA_ADMIN_NOTIFICATION) |
1565                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1566                       BIT(ENA_ADMIN_FATAL_ERROR) |
1567                       BIT(ENA_ADMIN_WARNING);
1568
1569         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1570         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1571         if (rc) {
1572                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1573                 goto err_admin_init;
1574         }
1575
1576         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1577
1578         return 0;
1579
1580 err_admin_init:
1581         ena_com_admin_destroy(ena_dev);
1582
1583 err_mmio_read_less:
1584         ena_com_mmio_reg_read_request_destroy(ena_dev);
1585
1586         return rc;
1587 }
1588
1589 static void ena_interrupt_handler_rte(void *cb_arg)
1590 {
1591         struct ena_adapter *adapter = cb_arg;
1592         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1593
1594         ena_com_admin_q_comp_intr_handler(ena_dev);
1595         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1596                 ena_com_aenq_intr_handler(ena_dev, adapter);
1597 }
1598
1599 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1600 {
1601         if (!adapter->wd_state)
1602                 return;
1603
1604         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1605                 return;
1606
1607         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1608             adapter->keep_alive_timeout)) {
1609                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1610                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1611                 adapter->trigger_reset = true;
1612                 ++adapter->dev_stats.wd_expired;
1613         }
1614 }
1615
1616 /* Check if admin queue is enabled */
1617 static void check_for_admin_com_state(struct ena_adapter *adapter)
1618 {
1619         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1620                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1621                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1622                 adapter->trigger_reset = true;
1623         }
1624 }
1625
1626 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1627                                   void *arg)
1628 {
1629         struct ena_adapter *adapter = arg;
1630         struct rte_eth_dev *dev = adapter->rte_dev;
1631
1632         check_for_missing_keep_alive(adapter);
1633         check_for_admin_com_state(adapter);
1634
1635         if (unlikely(adapter->trigger_reset)) {
1636                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1637                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1638                         NULL);
1639         }
1640 }
1641
1642 static inline void
1643 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1644                                struct ena_admin_feature_llq_desc *llq,
1645                                bool use_large_llq_hdr)
1646 {
1647         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1648         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1649         llq_config->llq_num_decs_before_header =
1650                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1651
1652         if (use_large_llq_hdr &&
1653             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1654                 llq_config->llq_ring_entry_size =
1655                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1656                 llq_config->llq_ring_entry_size_value = 256;
1657         } else {
1658                 llq_config->llq_ring_entry_size =
1659                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1660                 llq_config->llq_ring_entry_size_value = 128;
1661         }
1662 }
1663
1664 static int
1665 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1666                                 struct ena_com_dev *ena_dev,
1667                                 struct ena_admin_feature_llq_desc *llq,
1668                                 struct ena_llq_configurations *llq_default_configurations)
1669 {
1670         int rc;
1671         u32 llq_feature_mask;
1672
1673         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1674         if (!(ena_dev->supported_features & llq_feature_mask)) {
1675                 PMD_DRV_LOG(INFO,
1676                         "LLQ is not supported. Fallback to host mode policy.\n");
1677                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1678                 return 0;
1679         }
1680
1681         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1682         if (unlikely(rc)) {
1683                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1684                         "Fallback to host mode policy.");
1685                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1686                 return 0;
1687         }
1688
1689         /* Nothing to config, exit */
1690         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1691                 return 0;
1692
1693         if (!adapter->dev_mem_base) {
1694                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1695                         "Fallback to host mode policy.\n.");
1696                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1697                 return 0;
1698         }
1699
1700         ena_dev->mem_bar = adapter->dev_mem_base;
1701
1702         return 0;
1703 }
1704
1705 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1706         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1707 {
1708         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1709
1710         /* Regular queues capabilities */
1711         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1712                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1713                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1714                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1715                                     max_queue_ext->max_rx_cq_num);
1716                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1717                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1718         } else {
1719                 struct ena_admin_queue_feature_desc *max_queues =
1720                         &get_feat_ctx->max_queues;
1721                 io_tx_sq_num = max_queues->max_sq_num;
1722                 io_tx_cq_num = max_queues->max_cq_num;
1723                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1724         }
1725
1726         /* In case of LLQ use the llq number in the get feature cmd */
1727         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1728                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1729
1730         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1731         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1732         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1733
1734         if (unlikely(max_num_io_queues == 0)) {
1735                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1736                 return -EFAULT;
1737         }
1738
1739         return max_num_io_queues;
1740 }
1741
1742 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1743 {
1744         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1745         struct rte_pci_device *pci_dev;
1746         struct rte_intr_handle *intr_handle;
1747         struct ena_adapter *adapter = eth_dev->data->dev_private;
1748         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1749         struct ena_com_dev_get_features_ctx get_feat_ctx;
1750         struct ena_llq_configurations llq_config;
1751         const char *queue_type_str;
1752         uint32_t max_num_io_queues;
1753         int rc;
1754         static int adapters_found;
1755         bool disable_meta_caching;
1756         bool wd_state = false;
1757
1758         eth_dev->dev_ops = &ena_dev_ops;
1759         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1760         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1761         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1762
1763         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1764                 return 0;
1765
1766         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1767
1768         memset(adapter, 0, sizeof(struct ena_adapter));
1769         ena_dev = &adapter->ena_dev;
1770
1771         adapter->rte_eth_dev_data = eth_dev->data;
1772         adapter->rte_dev = eth_dev;
1773
1774         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1775         adapter->pdev = pci_dev;
1776
1777         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1778                      pci_dev->addr.domain,
1779                      pci_dev->addr.bus,
1780                      pci_dev->addr.devid,
1781                      pci_dev->addr.function);
1782
1783         intr_handle = &pci_dev->intr_handle;
1784
1785         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1786         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1787
1788         if (!adapter->regs) {
1789                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1790                              ENA_REGS_BAR);
1791                 return -ENXIO;
1792         }
1793
1794         ena_dev->reg_bar = adapter->regs;
1795         ena_dev->dmadev = adapter->pdev;
1796
1797         adapter->id_number = adapters_found;
1798
1799         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1800                  adapter->id_number);
1801
1802         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1803         if (rc != 0) {
1804                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1805                 goto err;
1806         }
1807
1808         /* device specific initialization routine */
1809         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1810         if (rc) {
1811                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1812                 goto err;
1813         }
1814         adapter->wd_state = wd_state;
1815
1816         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1817                 adapter->use_large_llq_hdr);
1818         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1819                                              &get_feat_ctx.llq, &llq_config);
1820         if (unlikely(rc)) {
1821                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1822                 return rc;
1823         }
1824
1825         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1826                 queue_type_str = "Regular";
1827         else
1828                 queue_type_str = "Low latency";
1829         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1830
1831         calc_queue_ctx.ena_dev = ena_dev;
1832         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1833
1834         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1835         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1836                 adapter->use_large_llq_hdr);
1837         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1838                 rc = -EFAULT;
1839                 goto err_device_destroy;
1840         }
1841
1842         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1843         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1844         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1845         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1846         adapter->max_num_io_queues = max_num_io_queues;
1847
1848         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1849                 disable_meta_caching =
1850                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1851                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1852         } else {
1853                 disable_meta_caching = false;
1854         }
1855
1856         /* prepare ring structures */
1857         ena_init_rings(adapter, disable_meta_caching);
1858
1859         ena_config_debug_area(adapter);
1860
1861         /* Set max MTU for this device */
1862         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1863
1864         /* set device support for offloads */
1865         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1866                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1867         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1868                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1869         adapter->offloads.rx_csum_supported =
1870                 (get_feat_ctx.offload.rx_supported &
1871                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1872
1873         /* Copy MAC address and point DPDK to it */
1874         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1875         rte_ether_addr_copy((struct rte_ether_addr *)
1876                         get_feat_ctx.dev_attr.mac_addr,
1877                         (struct rte_ether_addr *)adapter->mac_addr);
1878
1879         adapter->drv_stats = rte_zmalloc("adapter stats",
1880                                          sizeof(*adapter->drv_stats),
1881                                          RTE_CACHE_LINE_SIZE);
1882         if (!adapter->drv_stats) {
1883                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1884                 rc = -ENOMEM;
1885                 goto err_delete_debug_area;
1886         }
1887
1888         rte_spinlock_init(&adapter->admin_lock);
1889
1890         rte_intr_callback_register(intr_handle,
1891                                    ena_interrupt_handler_rte,
1892                                    adapter);
1893         rte_intr_enable(intr_handle);
1894         ena_com_set_admin_polling_mode(ena_dev, false);
1895         ena_com_admin_aenq_enable(ena_dev);
1896
1897         if (adapters_found == 0)
1898                 rte_timer_subsystem_init();
1899         rte_timer_init(&adapter->timer_wd);
1900
1901         adapters_found++;
1902         adapter->state = ENA_ADAPTER_STATE_INIT;
1903
1904         return 0;
1905
1906 err_delete_debug_area:
1907         ena_com_delete_debug_area(ena_dev);
1908
1909 err_device_destroy:
1910         ena_com_delete_host_info(ena_dev);
1911         ena_com_admin_destroy(ena_dev);
1912
1913 err:
1914         return rc;
1915 }
1916
1917 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1918 {
1919         struct ena_adapter *adapter = eth_dev->data->dev_private;
1920         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1921
1922         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1923                 return;
1924
1925         ena_com_set_admin_running_state(ena_dev, false);
1926
1927         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1928                 ena_close(eth_dev);
1929
1930         ena_com_delete_debug_area(ena_dev);
1931         ena_com_delete_host_info(ena_dev);
1932
1933         ena_com_abort_admin_commands(ena_dev);
1934         ena_com_wait_for_abort_completion(ena_dev);
1935         ena_com_admin_destroy(ena_dev);
1936         ena_com_mmio_reg_read_request_destroy(ena_dev);
1937
1938         adapter->state = ENA_ADAPTER_STATE_FREE;
1939 }
1940
1941 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1942 {
1943         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1944                 return 0;
1945
1946         ena_destroy_device(eth_dev);
1947
1948         return 0;
1949 }
1950
1951 static int ena_dev_configure(struct rte_eth_dev *dev)
1952 {
1953         struct ena_adapter *adapter = dev->data->dev_private;
1954
1955         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1956
1957         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1958         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1959         return 0;
1960 }
1961
1962 static void ena_init_rings(struct ena_adapter *adapter,
1963                            bool disable_meta_caching)
1964 {
1965         size_t i;
1966
1967         for (i = 0; i < adapter->max_num_io_queues; i++) {
1968                 struct ena_ring *ring = &adapter->tx_ring[i];
1969
1970                 ring->configured = 0;
1971                 ring->type = ENA_RING_TYPE_TX;
1972                 ring->adapter = adapter;
1973                 ring->id = i;
1974                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1975                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1976                 ring->sgl_size = adapter->max_tx_sgl_size;
1977                 ring->disable_meta_caching = disable_meta_caching;
1978         }
1979
1980         for (i = 0; i < adapter->max_num_io_queues; i++) {
1981                 struct ena_ring *ring = &adapter->rx_ring[i];
1982
1983                 ring->configured = 0;
1984                 ring->type = ENA_RING_TYPE_RX;
1985                 ring->adapter = adapter;
1986                 ring->id = i;
1987                 ring->sgl_size = adapter->max_rx_sgl_size;
1988         }
1989 }
1990
1991 static int ena_infos_get(struct rte_eth_dev *dev,
1992                           struct rte_eth_dev_info *dev_info)
1993 {
1994         struct ena_adapter *adapter;
1995         struct ena_com_dev *ena_dev;
1996         uint64_t rx_feat = 0, tx_feat = 0;
1997
1998         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1999         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2000         adapter = dev->data->dev_private;
2001
2002         ena_dev = &adapter->ena_dev;
2003         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2004
2005         dev_info->speed_capa =
2006                         ETH_LINK_SPEED_1G   |
2007                         ETH_LINK_SPEED_2_5G |
2008                         ETH_LINK_SPEED_5G   |
2009                         ETH_LINK_SPEED_10G  |
2010                         ETH_LINK_SPEED_25G  |
2011                         ETH_LINK_SPEED_40G  |
2012                         ETH_LINK_SPEED_50G  |
2013                         ETH_LINK_SPEED_100G;
2014
2015         /* Set Tx & Rx features available for device */
2016         if (adapter->offloads.tso4_supported)
2017                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2018
2019         if (adapter->offloads.tx_csum_supported)
2020                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2021                         DEV_TX_OFFLOAD_UDP_CKSUM |
2022                         DEV_TX_OFFLOAD_TCP_CKSUM;
2023
2024         if (adapter->offloads.rx_csum_supported)
2025                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2026                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2027                         DEV_RX_OFFLOAD_TCP_CKSUM;
2028
2029         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2030
2031         /* Inform framework about available features */
2032         dev_info->rx_offload_capa = rx_feat;
2033         dev_info->rx_queue_offload_capa = rx_feat;
2034         dev_info->tx_offload_capa = tx_feat;
2035         dev_info->tx_queue_offload_capa = tx_feat;
2036
2037         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2038                                            ETH_RSS_UDP;
2039
2040         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2041         dev_info->max_rx_pktlen  = adapter->max_mtu;
2042         dev_info->max_mac_addrs = 1;
2043
2044         dev_info->max_rx_queues = adapter->max_num_io_queues;
2045         dev_info->max_tx_queues = adapter->max_num_io_queues;
2046         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2047
2048         adapter->tx_supported_offloads = tx_feat;
2049         adapter->rx_supported_offloads = rx_feat;
2050
2051         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2052         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2053         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2054                                         adapter->max_rx_sgl_size);
2055         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2056                                         adapter->max_rx_sgl_size);
2057
2058         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2059         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2060         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2061                                         adapter->max_tx_sgl_size);
2062         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2063                                         adapter->max_tx_sgl_size);
2064
2065         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2066         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2067
2068         return 0;
2069 }
2070
2071 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2072 {
2073         mbuf->data_len = len;
2074         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2075         mbuf->refcnt = 1;
2076         mbuf->next = NULL;
2077 }
2078
2079 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2080                                     struct ena_com_rx_buf_info *ena_bufs,
2081                                     uint32_t descs,
2082                                     uint16_t *next_to_clean,
2083                                     uint8_t offset)
2084 {
2085         struct rte_mbuf *mbuf;
2086         struct rte_mbuf *mbuf_head;
2087         struct ena_rx_buffer *rx_info;
2088         int rc;
2089         uint16_t ntc, len, req_id, buf = 0;
2090
2091         if (unlikely(descs == 0))
2092                 return NULL;
2093
2094         ntc = *next_to_clean;
2095
2096         len = ena_bufs[buf].len;
2097         req_id = ena_bufs[buf].req_id;
2098
2099         rx_info = &rx_ring->rx_buffer_info[req_id];
2100
2101         mbuf = rx_info->mbuf;
2102         RTE_ASSERT(mbuf != NULL);
2103
2104         ena_init_rx_mbuf(mbuf, len);
2105
2106         /* Fill the mbuf head with the data specific for 1st segment. */
2107         mbuf_head = mbuf;
2108         mbuf_head->nb_segs = descs;
2109         mbuf_head->port = rx_ring->port_id;
2110         mbuf_head->pkt_len = len;
2111         mbuf_head->data_off += offset;
2112
2113         rx_info->mbuf = NULL;
2114         rx_ring->empty_rx_reqs[ntc] = req_id;
2115         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2116
2117         while (--descs) {
2118                 ++buf;
2119                 len = ena_bufs[buf].len;
2120                 req_id = ena_bufs[buf].req_id;
2121
2122                 rx_info = &rx_ring->rx_buffer_info[req_id];
2123                 RTE_ASSERT(rx_info->mbuf != NULL);
2124
2125                 if (unlikely(len == 0)) {
2126                         /*
2127                          * Some devices can pass descriptor with the length 0.
2128                          * To avoid confusion, the PMD is simply putting the
2129                          * descriptor back, as it was never used. We'll avoid
2130                          * mbuf allocation that way.
2131                          */
2132                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2133                                 rx_info->mbuf, req_id);
2134                         if (unlikely(rc != 0)) {
2135                                 /* Free the mbuf in case of an error. */
2136                                 rte_mbuf_raw_free(rx_info->mbuf);
2137                         } else {
2138                                 /*
2139                                  * If there was no error, just exit the loop as
2140                                  * 0 length descriptor is always the last one.
2141                                  */
2142                                 break;
2143                         }
2144                 } else {
2145                         /* Create an mbuf chain. */
2146                         mbuf->next = rx_info->mbuf;
2147                         mbuf = mbuf->next;
2148
2149                         ena_init_rx_mbuf(mbuf, len);
2150                         mbuf_head->pkt_len += len;
2151                 }
2152
2153                 /*
2154                  * Mark the descriptor as depleted and perform necessary
2155                  * cleanup.
2156                  * This code will execute in two cases:
2157                  *  1. Descriptor len was greater than 0 - normal situation.
2158                  *  2. Descriptor len was 0 and we failed to add the descriptor
2159                  *     to the device. In that situation, we should try to add
2160                  *     the mbuf again in the populate routine and mark the
2161                  *     descriptor as used up by the device.
2162                  */
2163                 rx_info->mbuf = NULL;
2164                 rx_ring->empty_rx_reqs[ntc] = req_id;
2165                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2166         }
2167
2168         *next_to_clean = ntc;
2169
2170         return mbuf_head;
2171 }
2172
2173 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2174                                   uint16_t nb_pkts)
2175 {
2176         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2177         unsigned int free_queue_entries;
2178         unsigned int refill_threshold;
2179         uint16_t next_to_clean = rx_ring->next_to_clean;
2180         uint16_t descs_in_use;
2181         struct rte_mbuf *mbuf;
2182         uint16_t completed;
2183         struct ena_com_rx_ctx ena_rx_ctx;
2184         int i, rc = 0;
2185
2186         /* Check adapter state */
2187         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2188                 PMD_DRV_LOG(ALERT,
2189                         "Trying to receive pkts while device is NOT running\n");
2190                 return 0;
2191         }
2192
2193         descs_in_use = rx_ring->ring_size -
2194                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2195         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2196
2197         for (completed = 0; completed < nb_pkts; completed++) {
2198                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2199                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2200                 ena_rx_ctx.descs = 0;
2201                 ena_rx_ctx.pkt_offset = 0;
2202                 /* receive packet context */
2203                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2204                                     rx_ring->ena_com_io_sq,
2205                                     &ena_rx_ctx);
2206                 if (unlikely(rc)) {
2207                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2208                         if (rc == ENA_COM_NO_SPACE) {
2209                                 ++rx_ring->rx_stats.bad_desc_num;
2210                                 rx_ring->adapter->reset_reason =
2211                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2212                         } else {
2213                                 ++rx_ring->rx_stats.bad_req_id;
2214                                 rx_ring->adapter->reset_reason =
2215                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2216                         }
2217                         rx_ring->adapter->trigger_reset = true;
2218                         return 0;
2219                 }
2220
2221                 mbuf = ena_rx_mbuf(rx_ring,
2222                         ena_rx_ctx.ena_bufs,
2223                         ena_rx_ctx.descs,
2224                         &next_to_clean,
2225                         ena_rx_ctx.pkt_offset);
2226                 if (unlikely(mbuf == NULL)) {
2227                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2228                                 rx_ring->empty_rx_reqs[next_to_clean] =
2229                                         rx_ring->ena_bufs[i].req_id;
2230                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2231                                         next_to_clean, rx_ring->size_mask);
2232                         }
2233                         break;
2234                 }
2235
2236                 /* fill mbuf attributes if any */
2237                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2238
2239                 if (unlikely(mbuf->ol_flags &
2240                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2241                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2242                         ++rx_ring->rx_stats.bad_csum;
2243                 }
2244
2245                 mbuf->hash.rss = ena_rx_ctx.hash;
2246
2247                 rx_pkts[completed] = mbuf;
2248                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2249         }
2250
2251         rx_ring->rx_stats.cnt += completed;
2252         rx_ring->next_to_clean = next_to_clean;
2253
2254         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2255         refill_threshold =
2256                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2257                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2258
2259         /* Burst refill to save doorbells, memory barriers, const interval */
2260         if (free_queue_entries > refill_threshold) {
2261                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2262                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2263         }
2264
2265         return completed;
2266 }
2267
2268 static uint16_t
2269 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2270                 uint16_t nb_pkts)
2271 {
2272         int32_t ret;
2273         uint32_t i;
2274         struct rte_mbuf *m;
2275         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2276         struct rte_ipv4_hdr *ip_hdr;
2277         uint64_t ol_flags;
2278         uint16_t frag_field;
2279
2280         for (i = 0; i != nb_pkts; i++) {
2281                 m = tx_pkts[i];
2282                 ol_flags = m->ol_flags;
2283
2284                 if (!(ol_flags & PKT_TX_IPV4))
2285                         continue;
2286
2287                 /* If there was not L2 header length specified, assume it is
2288                  * length of the ethernet header.
2289                  */
2290                 if (unlikely(m->l2_len == 0))
2291                         m->l2_len = sizeof(struct rte_ether_hdr);
2292
2293                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2294                                                  m->l2_len);
2295                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2296
2297                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2298                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2299
2300                         /* If IPv4 header has DF flag enabled and TSO support is
2301                          * disabled, partial chcecksum should not be calculated.
2302                          */
2303                         if (!tx_ring->adapter->offloads.tso4_supported)
2304                                 continue;
2305                 }
2306
2307                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2308                                 (ol_flags & PKT_TX_L4_MASK) ==
2309                                 PKT_TX_SCTP_CKSUM) {
2310                         rte_errno = ENOTSUP;
2311                         return i;
2312                 }
2313
2314 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2315                 ret = rte_validate_tx_offload(m);
2316                 if (ret != 0) {
2317                         rte_errno = -ret;
2318                         return i;
2319                 }
2320 #endif
2321
2322                 /* In case we are supposed to TSO and have DF not set (DF=0)
2323                  * hardware must be provided with partial checksum, otherwise
2324                  * it will take care of necessary calculations.
2325                  */
2326
2327                 ret = rte_net_intel_cksum_flags_prepare(m,
2328                         ol_flags & ~PKT_TX_TCP_SEG);
2329                 if (ret != 0) {
2330                         rte_errno = -ret;
2331                         return i;
2332                 }
2333         }
2334
2335         return i;
2336 }
2337
2338 static void ena_update_hints(struct ena_adapter *adapter,
2339                              struct ena_admin_ena_hw_hints *hints)
2340 {
2341         if (hints->admin_completion_tx_timeout)
2342                 adapter->ena_dev.admin_queue.completion_timeout =
2343                         hints->admin_completion_tx_timeout * 1000;
2344
2345         if (hints->mmio_read_timeout)
2346                 /* convert to usec */
2347                 adapter->ena_dev.mmio_read.reg_read_to =
2348                         hints->mmio_read_timeout * 1000;
2349
2350         if (hints->driver_watchdog_timeout) {
2351                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2352                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2353                 else
2354                         // Convert msecs to ticks
2355                         adapter->keep_alive_timeout =
2356                                 (hints->driver_watchdog_timeout *
2357                                 rte_get_timer_hz()) / 1000;
2358         }
2359 }
2360
2361 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2362                                               struct rte_mbuf *mbuf)
2363 {
2364         struct ena_com_dev *ena_dev;
2365         int num_segments, header_len, rc;
2366
2367         ena_dev = &tx_ring->adapter->ena_dev;
2368         num_segments = mbuf->nb_segs;
2369         header_len = mbuf->data_len;
2370
2371         if (likely(num_segments < tx_ring->sgl_size))
2372                 goto checkspace;
2373
2374         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2375             (num_segments == tx_ring->sgl_size) &&
2376             (header_len < tx_ring->tx_max_header_size))
2377                 goto checkspace;
2378
2379         /* Checking for space for 2 additional metadata descriptors due to
2380          * possible header split and metadata descriptor. Linearization will
2381          * be needed so we reduce the segments number from num_segments to 1
2382          */
2383         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2384                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2385                 return ENA_COM_NO_MEM;
2386         }
2387         ++tx_ring->tx_stats.linearize;
2388         rc = rte_pktmbuf_linearize(mbuf);
2389         if (unlikely(rc)) {
2390                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2391                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2392                 ++tx_ring->tx_stats.linearize_failed;
2393                 return rc;
2394         }
2395
2396         return 0;
2397
2398 checkspace:
2399         /* Checking for space for 2 additional metadata descriptors due to
2400          * possible header split and metadata descriptor
2401          */
2402         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2403                                           num_segments + 2)) {
2404                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2405                 return ENA_COM_NO_MEM;
2406         }
2407
2408         return 0;
2409 }
2410
2411 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2412         struct ena_tx_buffer *tx_info,
2413         struct rte_mbuf *mbuf,
2414         void **push_header,
2415         uint16_t *header_len)
2416 {
2417         struct ena_com_buf *ena_buf;
2418         uint16_t delta, seg_len, push_len;
2419
2420         delta = 0;
2421         seg_len = mbuf->data_len;
2422
2423         tx_info->mbuf = mbuf;
2424         ena_buf = tx_info->bufs;
2425
2426         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2427                 /*
2428                  * Tx header might be (and will be in most cases) smaller than
2429                  * tx_max_header_size. But it's not an issue to send more data
2430                  * to the device, than actually needed if the mbuf size is
2431                  * greater than tx_max_header_size.
2432                  */
2433                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2434                 *header_len = push_len;
2435
2436                 if (likely(push_len <= seg_len)) {
2437                         /* If the push header is in the single segment, then
2438                          * just point it to the 1st mbuf data.
2439                          */
2440                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2441                 } else {
2442                         /* If the push header lays in the several segments, copy
2443                          * it to the intermediate buffer.
2444                          */
2445                         rte_pktmbuf_read(mbuf, 0, push_len,
2446                                 tx_ring->push_buf_intermediate_buf);
2447                         *push_header = tx_ring->push_buf_intermediate_buf;
2448                         delta = push_len - seg_len;
2449                 }
2450         } else {
2451                 *push_header = NULL;
2452                 *header_len = 0;
2453                 push_len = 0;
2454         }
2455
2456         /* Process first segment taking into consideration pushed header */
2457         if (seg_len > push_len) {
2458                 ena_buf->paddr = mbuf->buf_iova +
2459                                 mbuf->data_off +
2460                                 push_len;
2461                 ena_buf->len = seg_len - push_len;
2462                 ena_buf++;
2463                 tx_info->num_of_bufs++;
2464         }
2465
2466         while ((mbuf = mbuf->next) != NULL) {
2467                 seg_len = mbuf->data_len;
2468
2469                 /* Skip mbufs if whole data is pushed as a header */
2470                 if (unlikely(delta > seg_len)) {
2471                         delta -= seg_len;
2472                         continue;
2473                 }
2474
2475                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2476                 ena_buf->len = seg_len - delta;
2477                 ena_buf++;
2478                 tx_info->num_of_bufs++;
2479
2480                 delta = 0;
2481         }
2482 }
2483
2484 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2485 {
2486         struct ena_tx_buffer *tx_info;
2487         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2488         uint16_t next_to_use;
2489         uint16_t header_len;
2490         uint16_t req_id;
2491         void *push_header;
2492         int nb_hw_desc;
2493         int rc;
2494
2495         rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2496         if (unlikely(rc))
2497                 return rc;
2498
2499         next_to_use = tx_ring->next_to_use;
2500
2501         req_id = tx_ring->empty_tx_reqs[next_to_use];
2502         tx_info = &tx_ring->tx_buffer_info[req_id];
2503         tx_info->num_of_bufs = 0;
2504
2505         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2506
2507         ena_tx_ctx.ena_bufs = tx_info->bufs;
2508         ena_tx_ctx.push_header = push_header;
2509         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2510         ena_tx_ctx.req_id = req_id;
2511         ena_tx_ctx.header_len = header_len;
2512
2513         /* Set Tx offloads flags, if applicable */
2514         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2515                 tx_ring->disable_meta_caching);
2516
2517         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2518                         &ena_tx_ctx))) {
2519                 PMD_DRV_LOG(DEBUG,
2520                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2521                         tx_ring->id);
2522                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2523                 tx_ring->tx_stats.doorbells++;
2524                 tx_ring->pkts_without_db = false;
2525         }
2526
2527         /* prepare the packet's descriptors to dma engine */
2528         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2529                 &nb_hw_desc);
2530         if (unlikely(rc)) {
2531                 ++tx_ring->tx_stats.prepare_ctx_err;
2532                 return rc;
2533         }
2534
2535         tx_info->tx_descs = nb_hw_desc;
2536
2537         tx_ring->tx_stats.cnt++;
2538         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2539
2540         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2541                 tx_ring->size_mask);
2542
2543         return 0;
2544 }
2545
2546 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2547 {
2548         unsigned int cleanup_budget;
2549         unsigned int total_tx_descs = 0;
2550         uint16_t next_to_clean = tx_ring->next_to_clean;
2551
2552         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2553                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2554
2555         while (likely(total_tx_descs < cleanup_budget)) {
2556                 struct rte_mbuf *mbuf;
2557                 struct ena_tx_buffer *tx_info;
2558                 uint16_t req_id;
2559
2560                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2561                         break;
2562
2563                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2564                         break;
2565
2566                 /* Get Tx info & store how many descs were processed  */
2567                 tx_info = &tx_ring->tx_buffer_info[req_id];
2568
2569                 mbuf = tx_info->mbuf;
2570                 rte_pktmbuf_free(mbuf);
2571
2572                 tx_info->mbuf = NULL;
2573                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2574
2575                 total_tx_descs += tx_info->tx_descs;
2576
2577                 /* Put back descriptor to the ring for reuse */
2578                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2579                         tx_ring->size_mask);
2580         }
2581
2582         if (likely(total_tx_descs > 0)) {
2583                 /* acknowledge completion of sent packets */
2584                 tx_ring->next_to_clean = next_to_clean;
2585                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2586                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2587         }
2588 }
2589
2590 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2591                                   uint16_t nb_pkts)
2592 {
2593         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2594         uint16_t sent_idx = 0;
2595
2596         /* Check adapter state */
2597         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2598                 PMD_DRV_LOG(ALERT,
2599                         "Trying to xmit pkts while device is NOT running\n");
2600                 return 0;
2601         }
2602
2603         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2604                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2605                         break;
2606                 tx_ring->pkts_without_db = true;
2607                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2608                         tx_ring->size_mask)]);
2609         }
2610
2611         tx_ring->tx_stats.available_desc =
2612                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2613
2614         /* If there are ready packets to be xmitted... */
2615         if (likely(tx_ring->pkts_without_db)) {
2616                 /* ...let HW do its best :-) */
2617                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2618                 tx_ring->tx_stats.doorbells++;
2619                 tx_ring->pkts_without_db = false;
2620         }
2621
2622         ena_tx_cleanup(tx_ring);
2623
2624         tx_ring->tx_stats.available_desc =
2625                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2626         tx_ring->tx_stats.tx_poll++;
2627
2628         return sent_idx;
2629 }
2630
2631 int ena_copy_eni_stats(struct ena_adapter *adapter)
2632 {
2633         struct ena_admin_eni_stats admin_eni_stats;
2634         int rc;
2635
2636         rte_spinlock_lock(&adapter->admin_lock);
2637         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2638         rte_spinlock_unlock(&adapter->admin_lock);
2639         if (rc != 0) {
2640                 if (rc == ENA_COM_UNSUPPORTED) {
2641                         PMD_DRV_LOG(DEBUG,
2642                                 "Retrieving ENI metrics is not supported.\n");
2643                 } else {
2644                         PMD_DRV_LOG(WARNING,
2645                                 "Failed to get ENI metrics: %d\n", rc);
2646                 }
2647                 return rc;
2648         }
2649
2650         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2651                 sizeof(struct ena_stats_eni));
2652
2653         return 0;
2654 }
2655
2656 /**
2657  * DPDK callback to retrieve names of extended device statistics
2658  *
2659  * @param dev
2660  *   Pointer to Ethernet device structure.
2661  * @param[out] xstats_names
2662  *   Buffer to insert names into.
2663  * @param n
2664  *   Number of names.
2665  *
2666  * @return
2667  *   Number of xstats names.
2668  */
2669 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2670                                 struct rte_eth_xstat_name *xstats_names,
2671                                 unsigned int n)
2672 {
2673         unsigned int xstats_count = ena_xstats_calc_num(dev);
2674         unsigned int stat, i, count = 0;
2675
2676         if (n < xstats_count || !xstats_names)
2677                 return xstats_count;
2678
2679         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2680                 strcpy(xstats_names[count].name,
2681                         ena_stats_global_strings[stat].name);
2682
2683         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2684                 strcpy(xstats_names[count].name,
2685                         ena_stats_eni_strings[stat].name);
2686
2687         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2688                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2689                         snprintf(xstats_names[count].name,
2690                                 sizeof(xstats_names[count].name),
2691                                 "rx_q%d_%s", i,
2692                                 ena_stats_rx_strings[stat].name);
2693
2694         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2695                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2696                         snprintf(xstats_names[count].name,
2697                                 sizeof(xstats_names[count].name),
2698                                 "tx_q%d_%s", i,
2699                                 ena_stats_tx_strings[stat].name);
2700
2701         return xstats_count;
2702 }
2703
2704 /**
2705  * DPDK callback to get extended device statistics.
2706  *
2707  * @param dev
2708  *   Pointer to Ethernet device structure.
2709  * @param[out] stats
2710  *   Stats table output buffer.
2711  * @param n
2712  *   The size of the stats table.
2713  *
2714  * @return
2715  *   Number of xstats on success, negative on failure.
2716  */
2717 static int ena_xstats_get(struct rte_eth_dev *dev,
2718                           struct rte_eth_xstat *xstats,
2719                           unsigned int n)
2720 {
2721         struct ena_adapter *adapter = dev->data->dev_private;
2722         unsigned int xstats_count = ena_xstats_calc_num(dev);
2723         unsigned int stat, i, count = 0;
2724         int stat_offset;
2725         void *stats_begin;
2726
2727         if (n < xstats_count)
2728                 return xstats_count;
2729
2730         if (!xstats)
2731                 return 0;
2732
2733         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2734                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2735                 stats_begin = &adapter->dev_stats;
2736
2737                 xstats[count].id = count;
2738                 xstats[count].value = *((uint64_t *)
2739                         ((char *)stats_begin + stat_offset));
2740         }
2741
2742         /* Even if the function below fails, we should copy previous (or initial
2743          * values) to keep structure of rte_eth_xstat consistent.
2744          */
2745         ena_copy_eni_stats(adapter);
2746         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2747                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2748                 stats_begin = &adapter->eni_stats;
2749
2750                 xstats[count].id = count;
2751                 xstats[count].value = *((uint64_t *)
2752                     ((char *)stats_begin + stat_offset));
2753         }
2754
2755         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2756                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2757                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2758                         stats_begin = &adapter->rx_ring[i].rx_stats;
2759
2760                         xstats[count].id = count;
2761                         xstats[count].value = *((uint64_t *)
2762                                 ((char *)stats_begin + stat_offset));
2763                 }
2764         }
2765
2766         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2767                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2768                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2769                         stats_begin = &adapter->tx_ring[i].rx_stats;
2770
2771                         xstats[count].id = count;
2772                         xstats[count].value = *((uint64_t *)
2773                                 ((char *)stats_begin + stat_offset));
2774                 }
2775         }
2776
2777         return count;
2778 }
2779
2780 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2781                                 const uint64_t *ids,
2782                                 uint64_t *values,
2783                                 unsigned int n)
2784 {
2785         struct ena_adapter *adapter = dev->data->dev_private;
2786         uint64_t id;
2787         uint64_t rx_entries, tx_entries;
2788         unsigned int i;
2789         int qid;
2790         int valid = 0;
2791         bool was_eni_copied = false;
2792
2793         for (i = 0; i < n; ++i) {
2794                 id = ids[i];
2795                 /* Check if id belongs to global statistics */
2796                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2797                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2798                         ++valid;
2799                         continue;
2800                 }
2801
2802                 /* Check if id belongs to ENI statistics */
2803                 id -= ENA_STATS_ARRAY_GLOBAL;
2804                 if (id < ENA_STATS_ARRAY_ENI) {
2805                         /* Avoid reading ENI stats multiple times in a single
2806                          * function call, as it requires communication with the
2807                          * admin queue.
2808                          */
2809                         if (!was_eni_copied) {
2810                                 was_eni_copied = true;
2811                                 ena_copy_eni_stats(adapter);
2812                         }
2813                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2814                         ++valid;
2815                         continue;
2816                 }
2817
2818                 /* Check if id belongs to rx queue statistics */
2819                 id -= ENA_STATS_ARRAY_ENI;
2820                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2821                 if (id < rx_entries) {
2822                         qid = id % dev->data->nb_rx_queues;
2823                         id /= dev->data->nb_rx_queues;
2824                         values[i] = *((uint64_t *)
2825                                 &adapter->rx_ring[qid].rx_stats + id);
2826                         ++valid;
2827                         continue;
2828                 }
2829                                 /* Check if id belongs to rx queue statistics */
2830                 id -= rx_entries;
2831                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2832                 if (id < tx_entries) {
2833                         qid = id % dev->data->nb_tx_queues;
2834                         id /= dev->data->nb_tx_queues;
2835                         values[i] = *((uint64_t *)
2836                                 &adapter->tx_ring[qid].tx_stats + id);
2837                         ++valid;
2838                         continue;
2839                 }
2840         }
2841
2842         return valid;
2843 }
2844
2845 static int ena_process_bool_devarg(const char *key,
2846                                    const char *value,
2847                                    void *opaque)
2848 {
2849         struct ena_adapter *adapter = opaque;
2850         bool bool_value;
2851
2852         /* Parse the value. */
2853         if (strcmp(value, "1") == 0) {
2854                 bool_value = true;
2855         } else if (strcmp(value, "0") == 0) {
2856                 bool_value = false;
2857         } else {
2858                 PMD_INIT_LOG(ERR,
2859                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2860                         value, key);
2861                 return -EINVAL;
2862         }
2863
2864         /* Now, assign it to the proper adapter field. */
2865         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2866                 adapter->use_large_llq_hdr = bool_value;
2867
2868         return 0;
2869 }
2870
2871 static int ena_parse_devargs(struct ena_adapter *adapter,
2872                              struct rte_devargs *devargs)
2873 {
2874         static const char * const allowed_args[] = {
2875                 ENA_DEVARG_LARGE_LLQ_HDR,
2876                 NULL,
2877         };
2878         struct rte_kvargs *kvlist;
2879         int rc;
2880
2881         if (devargs == NULL)
2882                 return 0;
2883
2884         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2885         if (kvlist == NULL) {
2886                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2887                         devargs->args);
2888                 return -EINVAL;
2889         }
2890
2891         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2892                 ena_process_bool_devarg, adapter);
2893
2894         rte_kvargs_free(kvlist);
2895
2896         return rc;
2897 }
2898
2899 /*********************************************************************
2900  *  PMD configuration
2901  *********************************************************************/
2902 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2903         struct rte_pci_device *pci_dev)
2904 {
2905         return rte_eth_dev_pci_generic_probe(pci_dev,
2906                 sizeof(struct ena_adapter), eth_ena_dev_init);
2907 }
2908
2909 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2910 {
2911         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2912 }
2913
2914 static struct rte_pci_driver rte_ena_pmd = {
2915         .id_table = pci_id_ena_map,
2916         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2917                      RTE_PCI_DRV_WC_ACTIVATE,
2918         .probe = eth_ena_pci_probe,
2919         .remove = eth_ena_pci_remove,
2920 };
2921
2922 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2923 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2924 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2925 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2926 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
2927 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
2928 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2929 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, NOTICE);
2930 #endif
2931 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2932 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, NOTICE);
2933 #endif
2934 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2935 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx_free, tx_free, NOTICE);
2936 #endif
2937 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2938 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, NOTICE);
2939 #endif
2940
2941 /******************************************************************************
2942  ******************************** AENQ Handlers *******************************
2943  *****************************************************************************/
2944 static void ena_update_on_link_change(void *adapter_data,
2945                                       struct ena_admin_aenq_entry *aenq_e)
2946 {
2947         struct rte_eth_dev *eth_dev;
2948         struct ena_adapter *adapter;
2949         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2950         uint32_t status;
2951
2952         adapter = adapter_data;
2953         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2954         eth_dev = adapter->rte_dev;
2955
2956         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2957         adapter->link_status = status;
2958
2959         ena_link_update(eth_dev, 0);
2960         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2961 }
2962
2963 static void ena_notification(void *data,
2964                              struct ena_admin_aenq_entry *aenq_e)
2965 {
2966         struct ena_adapter *adapter = data;
2967         struct ena_admin_ena_hw_hints *hints;
2968
2969         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2970                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2971                         aenq_e->aenq_common_desc.group,
2972                         ENA_ADMIN_NOTIFICATION);
2973
2974         switch (aenq_e->aenq_common_desc.syndrome) {
2975         case ENA_ADMIN_UPDATE_HINTS:
2976                 hints = (struct ena_admin_ena_hw_hints *)
2977                         (&aenq_e->inline_data_w4);
2978                 ena_update_hints(adapter, hints);
2979                 break;
2980         default:
2981                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2982                         aenq_e->aenq_common_desc.syndrome);
2983         }
2984 }
2985
2986 static void ena_keep_alive(void *adapter_data,
2987                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2988 {
2989         struct ena_adapter *adapter = adapter_data;
2990         struct ena_admin_aenq_keep_alive_desc *desc;
2991         uint64_t rx_drops;
2992         uint64_t tx_drops;
2993
2994         adapter->timestamp_wd = rte_get_timer_cycles();
2995
2996         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2997         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2998         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2999
3000         adapter->drv_stats->rx_drops = rx_drops;
3001         adapter->dev_stats.tx_drops = tx_drops;
3002 }
3003
3004 /**
3005  * This handler will called for unknown event group or unimplemented handlers
3006  **/
3007 static void unimplemented_aenq_handler(__rte_unused void *data,
3008                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3009 {
3010         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3011                           "unimplemented handler\n");
3012 }
3013
3014 static struct ena_aenq_handlers aenq_handlers = {
3015         .handlers = {
3016                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3017                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3018                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3019         },
3020         .unimplemented_handler = unimplemented_aenq_handler
3021 };