drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <ethdev_driver.h>
   9 #include <ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    2
  31 #define DRV_MODULE_VER_SUBMINOR 0
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 enum ethtool_stringset {
  55         ETH_SS_TEST             = 0,
  56         ETH_SS_STATS,
  57 };
  58
  59 struct ena_stats {
  60         char name[ETH_GSTRING_LEN];
  61         int stat_offset;
  62 };
  63
  64 #define ENA_STAT_ENTRY(stat, stat_type) { \
  65         .name = #stat, \
  66         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  67 }
  68
  69 #define ENA_STAT_RX_ENTRY(stat) \
  70         ENA_STAT_ENTRY(stat, rx)
  71
  72 #define ENA_STAT_TX_ENTRY(stat) \
  73         ENA_STAT_ENTRY(stat, tx)
  74
  75 #define ENA_STAT_ENI_ENTRY(stat) \
  76         ENA_STAT_ENTRY(stat, eni)
  77
  78 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  79         ENA_STAT_ENTRY(stat, dev)
  80
  81 /* Device arguments */
  82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  83
  84 /*
  85  * Each rte_memzone should have unique name.
  86  * To satisfy it, count number of allocation and add it to name.
  87  */
  88 rte_atomic32_t ena_alloc_cnt;
  89
  90 static const struct ena_stats ena_stats_global_strings[] = {
  91         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  92         ENA_STAT_GLOBAL_ENTRY(dev_start),
  93         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  94         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  95 };
  96
  97 static const struct ena_stats ena_stats_eni_strings[] = {
  98         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  99         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
 100         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
 101         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
 102         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
 103 };
 104
 105 static const struct ena_stats ena_stats_tx_strings[] = {
 106         ENA_STAT_TX_ENTRY(cnt),
 107         ENA_STAT_TX_ENTRY(bytes),
 108         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 109         ENA_STAT_TX_ENTRY(linearize),
 110         ENA_STAT_TX_ENTRY(linearize_failed),
 111         ENA_STAT_TX_ENTRY(tx_poll),
 112         ENA_STAT_TX_ENTRY(doorbells),
 113         ENA_STAT_TX_ENTRY(bad_req_id),
 114         ENA_STAT_TX_ENTRY(available_desc),
 115 };
 116
 117 static const struct ena_stats ena_stats_rx_strings[] = {
 118         ENA_STAT_RX_ENTRY(cnt),
 119         ENA_STAT_RX_ENTRY(bytes),
 120         ENA_STAT_RX_ENTRY(refill_partial),
 121         ENA_STAT_RX_ENTRY(bad_csum),
 122         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 123         ENA_STAT_RX_ENTRY(bad_desc_num),
 124         ENA_STAT_RX_ENTRY(bad_req_id),
 125 };
 126
 127 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 128 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 129 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 130 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 131
 132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 133                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 134                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 135                         DEV_TX_OFFLOAD_TCP_TSO)
 136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 137                        PKT_TX_IP_CKSUM |\
 138                        PKT_TX_TCP_SEG)
 139
 140 /** Vendor ID used by Amazon devices */
 141 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 142 /** Amazon devices */
 143 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 144 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 145
 146 #define ENA_TX_OFFLOAD_MASK     (\
 147         PKT_TX_L4_MASK |         \
 148         PKT_TX_IPV6 |            \
 149         PKT_TX_IPV4 |            \
 150         PKT_TX_IP_CKSUM |        \
 151         PKT_TX_TCP_SEG)
 152
 153 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 154         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 155
 156 static const struct rte_pci_id pci_id_ena_map[] = {
 157         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 158         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 159         { .device_id = 0 },
 160 };
 161
 162 static struct ena_aenq_handlers aenq_handlers;
 163
 164 static int ena_device_init(struct ena_com_dev *ena_dev,
 165                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 166                            bool *wd_state);
 167 static int ena_dev_configure(struct rte_eth_dev *dev);
 168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 169         struct ena_tx_buffer *tx_info,
 170         struct rte_mbuf *mbuf,
 171         void **push_header,
 172         uint16_t *header_len);
 173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 174 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 176                                   uint16_t nb_pkts);
 177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 178                 uint16_t nb_pkts);
 179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 180                               uint16_t nb_desc, unsigned int socket_id,
 181                               const struct rte_eth_txconf *tx_conf);
 182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_rxconf *rx_conf,
 185                               struct rte_mempool *mp);
 186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 188                                     struct ena_com_rx_buf_info *ena_bufs,
 189                                     uint32_t descs,
 190                                     uint16_t *next_to_clean,
 191                                     uint8_t offset);
 192 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 193                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 195                                   struct rte_mbuf *mbuf, uint16_t id);
 196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 197 static void ena_init_rings(struct ena_adapter *adapter,
 198                            bool disable_meta_caching);
 199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200 static int ena_start(struct rte_eth_dev *dev);
 201 static int ena_stop(struct rte_eth_dev *dev);
 202 static int ena_close(struct rte_eth_dev *dev);
 203 static int ena_dev_reset(struct rte_eth_dev *dev);
 204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 207 static void ena_rx_queue_release(void *queue);
 208 static void ena_tx_queue_release(void *queue);
 209 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 210 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 211 static int ena_link_update(struct rte_eth_dev *dev,
 212                            int wait_to_complete);
 213 static int ena_create_io_queue(struct ena_ring *ring);
 214 static void ena_queue_stop(struct ena_ring *ring);
 215 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 216                               enum ena_ring_type ring_type);
 217 static int ena_queue_start(struct ena_ring *ring);
 218 static int ena_queue_start_all(struct rte_eth_dev *dev,
 219                                enum ena_ring_type ring_type);
 220 static void ena_stats_restart(struct rte_eth_dev *dev);
 221 static int ena_infos_get(struct rte_eth_dev *dev,
 222                          struct rte_eth_dev_info *dev_info);
 223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 224                                struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                uint16_t reta_size);
 226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 227                               struct rte_eth_rss_reta_entry64 *reta_conf,
 228                               uint16_t reta_size);
 229 static void ena_interrupt_handler_rte(void *cb_arg);
 230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 231 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 233 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 234                                 struct rte_eth_xstat_name *xstats_names,
 235                                 unsigned int n);
 236 static int ena_xstats_get(struct rte_eth_dev *dev,
 237                           struct rte_eth_xstat *stats,
 238                           unsigned int n);
 239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 240                                 const uint64_t *ids,
 241                                 uint64_t *values,
 242                                 unsigned int n);
 243 static int ena_process_bool_devarg(const char *key,
 244                                    const char *value,
 245                                    void *opaque);
 246 static int ena_parse_devargs(struct ena_adapter *adapter,
 247                              struct rte_devargs *devargs);
 248 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 249
 250 static const struct eth_dev_ops ena_dev_ops = {
 251         .dev_configure        = ena_dev_configure,
 252         .dev_infos_get        = ena_infos_get,
 253         .rx_queue_setup       = ena_rx_queue_setup,
 254         .tx_queue_setup       = ena_tx_queue_setup,
 255         .dev_start            = ena_start,
 256         .dev_stop             = ena_stop,
 257         .link_update          = ena_link_update,
 258         .stats_get            = ena_stats_get,
 259         .xstats_get_names     = ena_xstats_get_names,
 260         .xstats_get           = ena_xstats_get,
 261         .xstats_get_by_id     = ena_xstats_get_by_id,
 262         .mtu_set              = ena_mtu_set,
 263         .rx_queue_release     = ena_rx_queue_release,
 264         .tx_queue_release     = ena_tx_queue_release,
 265         .dev_close            = ena_close,
 266         .dev_reset            = ena_dev_reset,
 267         .reta_update          = ena_rss_reta_update,
 268         .reta_query           = ena_rss_reta_query,
 269 };
 270
 271 void ena_rss_key_fill(void *key, size_t size)
 272 {
 273         static bool key_generated;
 274         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 275         size_t i;
 276
 277         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 278
 279         if (!key_generated) {
 280                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 281                         default_key[i] = rte_rand() & 0xff;
 282                 key_generated = true;
 283         }
 284
 285         rte_memcpy(key, default_key, size);
 286 }
 287
 288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 289                                        struct ena_com_rx_ctx *ena_rx_ctx)
 290 {
 291         uint64_t ol_flags = 0;
 292         uint32_t packet_type = 0;
 293
 294         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 295                 packet_type |= RTE_PTYPE_L4_TCP;
 296         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 297                 packet_type |= RTE_PTYPE_L4_UDP;
 298
 299         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 300                 packet_type |= RTE_PTYPE_L3_IPV4;
 301                 if (unlikely(ena_rx_ctx->l3_csum_err))
 302                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 303                 else
 304                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 305         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 306                 packet_type |= RTE_PTYPE_L3_IPV6;
 307         }
 308
 309         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 310                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 311         else
 312                 if (unlikely(ena_rx_ctx->l4_csum_err))
 313                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 314                 else
 315                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 316
 317         mbuf->ol_flags = ol_flags;
 318         mbuf->packet_type = packet_type;
 319 }
 320
 321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 322                                        struct ena_com_tx_ctx *ena_tx_ctx,
 323                                        uint64_t queue_offloads,
 324                                        bool disable_meta_caching)
 325 {
 326         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 327
 328         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 329             (queue_offloads & QUEUE_OFFLOADS)) {
 330                 /* check if TSO is required */
 331                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 332                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 333                         ena_tx_ctx->tso_enable = true;
 334
 335                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 336                 }
 337
 338                 /* check if L3 checksum is needed */
 339                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 340                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 341                         ena_tx_ctx->l3_csum_enable = true;
 342
 343                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 344                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 345                 } else {
 346                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 347
 348                         /* set don't fragment (DF) flag */
 349                         if (mbuf->packet_type &
 350                                 (RTE_PTYPE_L4_NONFRAG
 351                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 352                                 ena_tx_ctx->df = true;
 353                 }
 354
 355                 /* check if L4 checksum is needed */
 356                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 357                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 358                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 359                         ena_tx_ctx->l4_csum_enable = true;
 360                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 361                                 PKT_TX_UDP_CKSUM) &&
 362                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else {
 366                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 367                         ena_tx_ctx->l4_csum_enable = false;
 368                 }
 369
 370                 ena_meta->mss = mbuf->tso_segsz;
 371                 ena_meta->l3_hdr_len = mbuf->l3_len;
 372                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 373
 374                 ena_tx_ctx->meta_valid = true;
 375         } else if (disable_meta_caching) {
 376                 memset(ena_meta, 0, sizeof(*ena_meta));
 377                 ena_tx_ctx->meta_valid = true;
 378         } else {
 379                 ena_tx_ctx->meta_valid = false;
 380         }
 381 }
 382
 383 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 384 {
 385         if (likely(req_id < rx_ring->ring_size))
 386                 return 0;
 387
 388         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 389
 390         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 391         rx_ring->adapter->trigger_reset = true;
 392         ++rx_ring->rx_stats.bad_req_id;
 393
 394         return -EFAULT;
 395 }
 396
 397 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 398 {
 399         struct ena_tx_buffer *tx_info = NULL;
 400
 401         if (likely(req_id < tx_ring->ring_size)) {
 402                 tx_info = &tx_ring->tx_buffer_info[req_id];
 403                 if (likely(tx_info->mbuf))
 404                         return 0;
 405         }
 406
 407         if (tx_info)
 408                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 409         else
 410                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 411
 412         /* Trigger device reset */
 413         ++tx_ring->tx_stats.bad_req_id;
 414         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 415         tx_ring->adapter->trigger_reset = true;
 416         return -EFAULT;
 417 }
 418
 419 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 420 {
 421         struct ena_admin_host_info *host_info;
 422         int rc;
 423
 424         /* Allocate only the host info */
 425         rc = ena_com_allocate_host_info(ena_dev);
 426         if (rc) {
 427                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 428                 return;
 429         }
 430
 431         host_info = ena_dev->host_attr.host_info;
 432
 433         host_info->os_type = ENA_ADMIN_OS_DPDK;
 434         host_info->kernel_ver = RTE_VERSION;
 435         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 436                 sizeof(host_info->kernel_ver_str));
 437         host_info->os_dist = RTE_VERSION;
 438         strlcpy((char *)host_info->os_dist_str, rte_version(),
 439                 sizeof(host_info->os_dist_str));
 440         host_info->driver_version =
 441                 (DRV_MODULE_VER_MAJOR) |
 442                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 443                 (DRV_MODULE_VER_SUBMINOR <<
 444                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 445         host_info->num_cpus = rte_lcore_count();
 446
 447         host_info->driver_supported_features =
 448                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 449
 450         rc = ena_com_set_host_attributes(ena_dev);
 451         if (rc) {
 452                 if (rc == -ENA_COM_UNSUPPORTED)
 453                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 454                 else
 455                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 456
 457                 goto err;
 458         }
 459
 460         return;
 461
 462 err:
 463         ena_com_delete_host_info(ena_dev);
 464 }
 465
 466 /* This function calculates the number of xstats based on the current config */
 467 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 468 {
 469         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 470                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 471                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 472 }
 473
 474 static void ena_config_debug_area(struct ena_adapter *adapter)
 475 {
 476         u32 debug_area_size;
 477         int rc, ss_count;
 478
 479         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 480
 481         /* allocate 32 bytes for each string and 64bit for the value */
 482         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 483
 484         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 485         if (rc) {
 486                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 487                 return;
 488         }
 489
 490         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 491         if (rc) {
 492                 if (rc == -ENA_COM_UNSUPPORTED)
 493                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 494                 else
 495                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 496
 497                 goto err;
 498         }
 499
 500         return;
 501 err:
 502         ena_com_delete_debug_area(&adapter->ena_dev);
 503 }
 504
 505 static int ena_close(struct rte_eth_dev *dev)
 506 {
 507         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 509         struct ena_adapter *adapter = dev->data->dev_private;
 510         int ret = 0;
 511
 512         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 513                 return 0;
 514
 515         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 516                 ret = ena_stop(dev);
 517         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 518
 519         ena_rx_queue_release_all(dev);
 520         ena_tx_queue_release_all(dev);
 521
 522         rte_free(adapter->drv_stats);
 523         adapter->drv_stats = NULL;
 524
 525         rte_intr_disable(intr_handle);
 526         rte_intr_callback_unregister(intr_handle,
 527                                      ena_interrupt_handler_rte,
 528                                      adapter);
 529
 530         /*
 531          * MAC is not allocated dynamically. Setting NULL should prevent from
 532          * release of the resource in the rte_eth_dev_release_port().
 533          */
 534         dev->data->mac_addrs = NULL;
 535
 536         return ret;
 537 }
 538
 539 static int
 540 ena_dev_reset(struct rte_eth_dev *dev)
 541 {
 542         int rc = 0;
 543
 544         ena_destroy_device(dev);
 545         rc = eth_ena_dev_init(dev);
 546         if (rc)
 547                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 548
 549         return rc;
 550 }
 551
 552 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 553                                struct rte_eth_rss_reta_entry64 *reta_conf,
 554                                uint16_t reta_size)
 555 {
 556         struct ena_adapter *adapter = dev->data->dev_private;
 557         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 558         int rc, i;
 559         u16 entry_value;
 560         int conf_idx;
 561         int idx;
 562
 563         if ((reta_size == 0) || (reta_conf == NULL))
 564                 return -EINVAL;
 565
 566         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 567                 PMD_DRV_LOG(WARNING,
 568                         "indirection table %d is bigger than supported (%d)\n",
 569                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 570                 return -EINVAL;
 571         }
 572
 573         for (i = 0 ; i < reta_size ; i++) {
 574                 /* each reta_conf is for 64 entries.
 575                  * to support 128 we use 2 conf of 64
 576                  */
 577                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 578                 idx = i % RTE_RETA_GROUP_SIZE;
 579                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 580                         entry_value =
 581                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 582
 583                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 584                                                                i,
 585                                                                entry_value);
 586                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 587                                 PMD_DRV_LOG(ERR,
 588                                         "Cannot fill indirect table\n");
 589                                 return rc;
 590                         }
 591                 }
 592         }
 593
 594         rte_spinlock_lock(&adapter->admin_lock);
 595         rc = ena_com_indirect_table_set(ena_dev);
 596         rte_spinlock_unlock(&adapter->admin_lock);
 597         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 598                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 599                 return rc;
 600         }
 601
 602         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 603                 __func__, reta_size, adapter->rte_dev->data->port_id);
 604
 605         return 0;
 606 }
 607
 608 /* Query redirection table. */
 609 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 610                               struct rte_eth_rss_reta_entry64 *reta_conf,
 611                               uint16_t reta_size)
 612 {
 613         struct ena_adapter *adapter = dev->data->dev_private;
 614         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 615         int rc;
 616         int i;
 617         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 618         int reta_conf_idx;
 619         int reta_idx;
 620
 621         if (reta_size == 0 || reta_conf == NULL ||
 622             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 623                 return -EINVAL;
 624
 625         rte_spinlock_lock(&adapter->admin_lock);
 626         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 627         rte_spinlock_unlock(&adapter->admin_lock);
 628         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 629                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 630                 return -ENOTSUP;
 631         }
 632
 633         for (i = 0 ; i < reta_size ; i++) {
 634                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 635                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 636                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 637                         reta_conf[reta_conf_idx].reta[reta_idx] =
 638                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int ena_rss_init_default(struct ena_adapter *adapter)
 645 {
 646         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 647         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 648         int rc, i;
 649         u32 val;
 650
 651         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 652         if (unlikely(rc)) {
 653                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 654                 goto err_rss_init;
 655         }
 656
 657         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 658                 val = i % nb_rx_queues;
 659                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 660                                                        ENA_IO_RXQ_IDX(val));
 661                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 662                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 663                         goto err_fill_indir;
 664                 }
 665         }
 666
 667         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 668                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 669         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 670                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 671                 goto err_fill_indir;
 672         }
 673
 674         rc = ena_com_set_default_hash_ctrl(ena_dev);
 675         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 676                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 677                 goto err_fill_indir;
 678         }
 679
 680         rc = ena_com_indirect_table_set(ena_dev);
 681         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 682                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 683                 goto err_fill_indir;
 684         }
 685         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 686                 adapter->rte_dev->data->port_id);
 687
 688         return 0;
 689
 690 err_fill_indir:
 691         ena_com_rss_destroy(ena_dev);
 692 err_rss_init:
 693
 694         return rc;
 695 }
 696
 697 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 698 {
 699         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 700         int nb_queues = dev->data->nb_rx_queues;
 701         int i;
 702
 703         for (i = 0; i < nb_queues; i++)
 704                 ena_rx_queue_release(queues[i]);
 705 }
 706
 707 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 708 {
 709         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 710         int nb_queues = dev->data->nb_tx_queues;
 711         int i;
 712
 713         for (i = 0; i < nb_queues; i++)
 714                 ena_tx_queue_release(queues[i]);
 715 }
 716
 717 static void ena_rx_queue_release(void *queue)
 718 {
 719         struct ena_ring *ring = (struct ena_ring *)queue;
 720
 721         /* Free ring resources */
 722         if (ring->rx_buffer_info)
 723                 rte_free(ring->rx_buffer_info);
 724         ring->rx_buffer_info = NULL;
 725
 726         if (ring->rx_refill_buffer)
 727                 rte_free(ring->rx_refill_buffer);
 728         ring->rx_refill_buffer = NULL;
 729
 730         if (ring->empty_rx_reqs)
 731                 rte_free(ring->empty_rx_reqs);
 732         ring->empty_rx_reqs = NULL;
 733
 734         ring->configured = 0;
 735
 736         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 737                 ring->port_id, ring->id);
 738 }
 739
 740 static void ena_tx_queue_release(void *queue)
 741 {
 742         struct ena_ring *ring = (struct ena_ring *)queue;
 743
 744         /* Free ring resources */
 745         if (ring->push_buf_intermediate_buf)
 746                 rte_free(ring->push_buf_intermediate_buf);
 747
 748         if (ring->tx_buffer_info)
 749                 rte_free(ring->tx_buffer_info);
 750
 751         if (ring->empty_tx_reqs)
 752                 rte_free(ring->empty_tx_reqs);
 753
 754         ring->empty_tx_reqs = NULL;
 755         ring->tx_buffer_info = NULL;
 756         ring->push_buf_intermediate_buf = NULL;
 757
 758         ring->configured = 0;
 759
 760         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 761                 ring->port_id, ring->id);
 762 }
 763
 764 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 765 {
 766         unsigned int i;
 767
 768         for (i = 0; i < ring->ring_size; ++i) {
 769                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 770                 if (rx_info->mbuf) {
 771                         rte_mbuf_raw_free(rx_info->mbuf);
 772                         rx_info->mbuf = NULL;
 773                 }
 774         }
 775 }
 776
 777 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 778 {
 779         unsigned int i;
 780
 781         for (i = 0; i < ring->ring_size; ++i) {
 782                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 783
 784                 if (tx_buf->mbuf)
 785                         rte_pktmbuf_free(tx_buf->mbuf);
 786         }
 787 }
 788
 789 static int ena_link_update(struct rte_eth_dev *dev,
 790                            __rte_unused int wait_to_complete)
 791 {
 792         struct rte_eth_link *link = &dev->data->dev_link;
 793         struct ena_adapter *adapter = dev->data->dev_private;
 794
 795         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 796         link->link_speed = ETH_SPEED_NUM_NONE;
 797         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 798
 799         return 0;
 800 }
 801
 802 static int ena_queue_start_all(struct rte_eth_dev *dev,
 803                                enum ena_ring_type ring_type)
 804 {
 805         struct ena_adapter *adapter = dev->data->dev_private;
 806         struct ena_ring *queues = NULL;
 807         int nb_queues;
 808         int i = 0;
 809         int rc = 0;
 810
 811         if (ring_type == ENA_RING_TYPE_RX) {
 812                 queues = adapter->rx_ring;
 813                 nb_queues = dev->data->nb_rx_queues;
 814         } else {
 815                 queues = adapter->tx_ring;
 816                 nb_queues = dev->data->nb_tx_queues;
 817         }
 818         for (i = 0; i < nb_queues; i++) {
 819                 if (queues[i].configured) {
 820                         if (ring_type == ENA_RING_TYPE_RX) {
 821                                 ena_assert_msg(
 822                                         dev->data->rx_queues[i] == &queues[i],
 823                                         "Inconsistent state of rx queues\n");
 824                         } else {
 825                                 ena_assert_msg(
 826                                         dev->data->tx_queues[i] == &queues[i],
 827                                         "Inconsistent state of tx queues\n");
 828                         }
 829
 830                         rc = ena_queue_start(&queues[i]);
 831
 832                         if (rc) {
 833                                 PMD_INIT_LOG(ERR,
 834                                              "failed to start queue %d type(%d)",
 835                                              i, ring_type);
 836                                 goto err;
 837                         }
 838                 }
 839         }
 840
 841         return 0;
 842
 843 err:
 844         while (i--)
 845                 if (queues[i].configured)
 846                         ena_queue_stop(&queues[i]);
 847
 848         return rc;
 849 }
 850
 851 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 852 {
 853         uint32_t max_frame_len = adapter->max_mtu;
 854
 855         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 856             DEV_RX_OFFLOAD_JUMBO_FRAME)
 857                 max_frame_len =
 858                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 859
 860         return max_frame_len;
 861 }
 862
 863 static int ena_check_valid_conf(struct ena_adapter *adapter)
 864 {
 865         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 866
 867         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 868                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 869                                   "max mtu: %d, min mtu: %d",
 870                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 871                 return ENA_COM_UNSUPPORTED;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int
 878 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 879                        bool use_large_llq_hdr)
 880 {
 881         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 882         struct ena_com_dev *ena_dev = ctx->ena_dev;
 883         uint32_t max_tx_queue_size;
 884         uint32_t max_rx_queue_size;
 885
 886         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 887                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 888                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 889                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 890                         max_queue_ext->max_rx_sq_depth);
 891                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 892
 893                 if (ena_dev->tx_mem_queue_type ==
 894                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 895                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 896                                 llq->max_llq_depth);
 897                 } else {
 898                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 899                                 max_queue_ext->max_tx_sq_depth);
 900                 }
 901
 902                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 903                         max_queue_ext->max_per_packet_rx_descs);
 904                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 905                         max_queue_ext->max_per_packet_tx_descs);
 906         } else {
 907                 struct ena_admin_queue_feature_desc *max_queues =
 908                         &ctx->get_feat_ctx->max_queues;
 909                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 910                         max_queues->max_sq_depth);
 911                 max_tx_queue_size = max_queues->max_cq_depth;
 912
 913                 if (ena_dev->tx_mem_queue_type ==
 914                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 915                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 916                                 llq->max_llq_depth);
 917                 } else {
 918                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 919                                 max_queues->max_sq_depth);
 920                 }
 921
 922                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 923                         max_queues->max_packet_rx_descs);
 924                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 925                         max_queues->max_packet_tx_descs);
 926         }
 927
 928         /* Round down to the nearest power of 2 */
 929         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 930         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 931
 932         if (use_large_llq_hdr) {
 933                 if ((llq->entry_size_ctrl_supported &
 934                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 935                     (ena_dev->tx_mem_queue_type ==
 936                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 937                         max_tx_queue_size /= 2;
 938                         PMD_INIT_LOG(INFO,
 939                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 940                                 max_tx_queue_size);
 941                 } else {
 942                         PMD_INIT_LOG(ERR,
 943                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 944                 }
 945         }
 946
 947         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 948                 PMD_INIT_LOG(ERR, "Invalid queue size");
 949                 return -EFAULT;
 950         }
 951
 952         ctx->max_tx_queue_size = max_tx_queue_size;
 953         ctx->max_rx_queue_size = max_rx_queue_size;
 954
 955         return 0;
 956 }
 957
 958 static void ena_stats_restart(struct rte_eth_dev *dev)
 959 {
 960         struct ena_adapter *adapter = dev->data->dev_private;
 961
 962         rte_atomic64_init(&adapter->drv_stats->ierrors);
 963         rte_atomic64_init(&adapter->drv_stats->oerrors);
 964         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 965         adapter->drv_stats->rx_drops = 0;
 966 }
 967
 968 static int ena_stats_get(struct rte_eth_dev *dev,
 969                           struct rte_eth_stats *stats)
 970 {
 971         struct ena_admin_basic_stats ena_stats;
 972         struct ena_adapter *adapter = dev->data->dev_private;
 973         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 974         int rc;
 975         int i;
 976         int max_rings_stats;
 977
 978         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 979                 return -ENOTSUP;
 980
 981         memset(&ena_stats, 0, sizeof(ena_stats));
 982
 983         rte_spinlock_lock(&adapter->admin_lock);
 984         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 985         rte_spinlock_unlock(&adapter->admin_lock);
 986         if (unlikely(rc)) {
 987                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 988                 return rc;
 989         }
 990
 991         /* Set of basic statistics from ENA */
 992         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 993                                           ena_stats.rx_pkts_low);
 994         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 995                                           ena_stats.tx_pkts_low);
 996         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 997                                         ena_stats.rx_bytes_low);
 998         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 999                                         ena_stats.tx_bytes_low);
1000
1001         /* Driver related stats */
1002         stats->imissed = adapter->drv_stats->rx_drops;
1003         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1004         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1005         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1006
1007         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1008                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1009         for (i = 0; i < max_rings_stats; ++i) {
1010                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1011
1012                 stats->q_ibytes[i] = rx_stats->bytes;
1013                 stats->q_ipackets[i] = rx_stats->cnt;
1014                 stats->q_errors[i] = rx_stats->bad_desc_num +
1015                         rx_stats->bad_req_id;
1016         }
1017
1018         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1019                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1020         for (i = 0; i < max_rings_stats; ++i) {
1021                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1022
1023                 stats->q_obytes[i] = tx_stats->bytes;
1024                 stats->q_opackets[i] = tx_stats->cnt;
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1031 {
1032         struct ena_adapter *adapter;
1033         struct ena_com_dev *ena_dev;
1034         int rc = 0;
1035
1036         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1037         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1038         adapter = dev->data->dev_private;
1039
1040         ena_dev = &adapter->ena_dev;
1041         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1042
1043         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1044                 PMD_DRV_LOG(ERR,
1045                         "Invalid MTU setting. new_mtu: %d "
1046                         "max mtu: %d min mtu: %d\n",
1047                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1048                 return -EINVAL;
1049         }
1050
1051         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1052         if (rc)
1053                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1054         else
1055                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1056
1057         return rc;
1058 }
1059
1060 static int ena_start(struct rte_eth_dev *dev)
1061 {
1062         struct ena_adapter *adapter = dev->data->dev_private;
1063         uint64_t ticks;
1064         int rc = 0;
1065
1066         rc = ena_check_valid_conf(adapter);
1067         if (rc)
1068                 return rc;
1069
1070         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1071         if (rc)
1072                 return rc;
1073
1074         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1075         if (rc)
1076                 goto err_start_tx;
1077
1078         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1079             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1080                 rc = ena_rss_init_default(adapter);
1081                 if (rc)
1082                         goto err_rss_init;
1083         }
1084
1085         ena_stats_restart(dev);
1086
1087         adapter->timestamp_wd = rte_get_timer_cycles();
1088         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1089
1090         ticks = rte_get_timer_hz();
1091         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1092                         ena_timer_wd_callback, adapter);
1093
1094         ++adapter->dev_stats.dev_start;
1095         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1096
1097         return 0;
1098
1099 err_rss_init:
1100         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1101 err_start_tx:
1102         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1103         return rc;
1104 }
1105
1106 static int ena_stop(struct rte_eth_dev *dev)
1107 {
1108         struct ena_adapter *adapter = dev->data->dev_private;
1109         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1110         int rc;
1111
1112         rte_timer_stop_sync(&adapter->timer_wd);
1113         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1114         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1115
1116         if (adapter->trigger_reset) {
1117                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1118                 if (rc)
1119                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1120         }
1121
1122         ++adapter->dev_stats.dev_stop;
1123         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1124         dev->data->dev_started = 0;
1125
1126         return 0;
1127 }
1128
1129 static int ena_create_io_queue(struct ena_ring *ring)
1130 {
1131         struct ena_adapter *adapter;
1132         struct ena_com_dev *ena_dev;
1133         struct ena_com_create_io_ctx ctx =
1134                 /* policy set to _HOST just to satisfy icc compiler */
1135                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1136                   0, 0, 0, 0, 0 };
1137         uint16_t ena_qid;
1138         unsigned int i;
1139         int rc;
1140
1141         adapter = ring->adapter;
1142         ena_dev = &adapter->ena_dev;
1143
1144         if (ring->type == ENA_RING_TYPE_TX) {
1145                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1146                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1147                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1148                 for (i = 0; i < ring->ring_size; i++)
1149                         ring->empty_tx_reqs[i] = i;
1150         } else {
1151                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1152                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1153                 for (i = 0; i < ring->ring_size; i++)
1154                         ring->empty_rx_reqs[i] = i;
1155         }
1156         ctx.queue_size = ring->ring_size;
1157         ctx.qid = ena_qid;
1158         ctx.msix_vector = -1; /* interrupts not used */
1159         ctx.numa_node = ring->numa_socket_id;
1160
1161         rc = ena_com_create_io_queue(ena_dev, &ctx);
1162         if (rc) {
1163                 PMD_DRV_LOG(ERR,
1164                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1165                         ring->id, ena_qid, rc);
1166                 return rc;
1167         }
1168
1169         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1170                                      &ring->ena_com_io_sq,
1171                                      &ring->ena_com_io_cq);
1172         if (rc) {
1173                 PMD_DRV_LOG(ERR,
1174                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1175                         ring->id, rc);
1176                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1177                 return rc;
1178         }
1179
1180         if (ring->type == ENA_RING_TYPE_TX)
1181                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1182
1183         return 0;
1184 }
1185
1186 static void ena_queue_stop(struct ena_ring *ring)
1187 {
1188         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1189
1190         if (ring->type == ENA_RING_TYPE_RX) {
1191                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1192                 ena_rx_queue_release_bufs(ring);
1193         } else {
1194                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1195                 ena_tx_queue_release_bufs(ring);
1196         }
1197 }
1198
1199 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1200                               enum ena_ring_type ring_type)
1201 {
1202         struct ena_adapter *adapter = dev->data->dev_private;
1203         struct ena_ring *queues = NULL;
1204         uint16_t nb_queues, i;
1205
1206         if (ring_type == ENA_RING_TYPE_RX) {
1207                 queues = adapter->rx_ring;
1208                 nb_queues = dev->data->nb_rx_queues;
1209         } else {
1210                 queues = adapter->tx_ring;
1211                 nb_queues = dev->data->nb_tx_queues;
1212         }
1213
1214         for (i = 0; i < nb_queues; ++i)
1215                 if (queues[i].configured)
1216                         ena_queue_stop(&queues[i]);
1217 }
1218
1219 static int ena_queue_start(struct ena_ring *ring)
1220 {
1221         int rc, bufs_num;
1222
1223         ena_assert_msg(ring->configured == 1,
1224                        "Trying to start unconfigured queue\n");
1225
1226         rc = ena_create_io_queue(ring);
1227         if (rc) {
1228                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1229                 return rc;
1230         }
1231
1232         ring->next_to_clean = 0;
1233         ring->next_to_use = 0;
1234
1235         if (ring->type == ENA_RING_TYPE_TX) {
1236                 ring->tx_stats.available_desc =
1237                         ena_com_free_q_entries(ring->ena_com_io_sq);
1238                 return 0;
1239         }
1240
1241         bufs_num = ring->ring_size - 1;
1242         rc = ena_populate_rx_queue(ring, bufs_num);
1243         if (rc != bufs_num) {
1244                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1245                                          ENA_IO_RXQ_IDX(ring->id));
1246                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1247                 return ENA_COM_FAULT;
1248         }
1249         /* Flush per-core RX buffers pools cache as they can be used on other
1250          * cores as well.
1251          */
1252         rte_mempool_cache_flush(NULL, ring->mb_pool);
1253
1254         return 0;
1255 }
1256
1257 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1258                               uint16_t queue_idx,
1259                               uint16_t nb_desc,
1260                               unsigned int socket_id,
1261                               const struct rte_eth_txconf *tx_conf)
1262 {
1263         struct ena_ring *txq = NULL;
1264         struct ena_adapter *adapter = dev->data->dev_private;
1265         unsigned int i;
1266
1267         txq = &adapter->tx_ring[queue_idx];
1268
1269         if (txq->configured) {
1270                 PMD_DRV_LOG(CRIT,
1271                         "API violation. Queue %d is already configured\n",
1272                         queue_idx);
1273                 return ENA_COM_FAULT;
1274         }
1275
1276         if (!rte_is_power_of_2(nb_desc)) {
1277                 PMD_DRV_LOG(ERR,
1278                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1279                         nb_desc);
1280                 return -EINVAL;
1281         }
1282
1283         if (nb_desc > adapter->max_tx_ring_size) {
1284                 PMD_DRV_LOG(ERR,
1285                         "Unsupported size of TX queue (max size: %d)\n",
1286                         adapter->max_tx_ring_size);
1287                 return -EINVAL;
1288         }
1289
1290         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1291                 nb_desc = adapter->max_tx_ring_size;
1292
1293         txq->port_id = dev->data->port_id;
1294         txq->next_to_clean = 0;
1295         txq->next_to_use = 0;
1296         txq->ring_size = nb_desc;
1297         txq->size_mask = nb_desc - 1;
1298         txq->numa_socket_id = socket_id;
1299
1300         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1301                                           sizeof(struct ena_tx_buffer) *
1302                                           txq->ring_size,
1303                                           RTE_CACHE_LINE_SIZE);
1304         if (!txq->tx_buffer_info) {
1305                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1306                 return -ENOMEM;
1307         }
1308
1309         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1310                                          sizeof(u16) * txq->ring_size,
1311                                          RTE_CACHE_LINE_SIZE);
1312         if (!txq->empty_tx_reqs) {
1313                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1314                 rte_free(txq->tx_buffer_info);
1315                 return -ENOMEM;
1316         }
1317
1318         txq->push_buf_intermediate_buf =
1319                 rte_zmalloc("txq->push_buf_intermediate_buf",
1320                             txq->tx_max_header_size,
1321                             RTE_CACHE_LINE_SIZE);
1322         if (!txq->push_buf_intermediate_buf) {
1323                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1324                 rte_free(txq->tx_buffer_info);
1325                 rte_free(txq->empty_tx_reqs);
1326                 return -ENOMEM;
1327         }
1328
1329         for (i = 0; i < txq->ring_size; i++)
1330                 txq->empty_tx_reqs[i] = i;
1331
1332         if (tx_conf != NULL) {
1333                 txq->offloads =
1334                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1335         }
1336         /* Store pointer to this queue in upper layer */
1337         txq->configured = 1;
1338         dev->data->tx_queues[queue_idx] = txq;
1339
1340         return 0;
1341 }
1342
1343 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1344                               uint16_t queue_idx,
1345                               uint16_t nb_desc,
1346                               unsigned int socket_id,
1347                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1348                               struct rte_mempool *mp)
1349 {
1350         struct ena_adapter *adapter = dev->data->dev_private;
1351         struct ena_ring *rxq = NULL;
1352         size_t buffer_size;
1353         int i;
1354
1355         rxq = &adapter->rx_ring[queue_idx];
1356         if (rxq->configured) {
1357                 PMD_DRV_LOG(CRIT,
1358                         "API violation. Queue %d is already configured\n",
1359                         queue_idx);
1360                 return ENA_COM_FAULT;
1361         }
1362
1363         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1364                 nb_desc = adapter->max_rx_ring_size;
1365
1366         if (!rte_is_power_of_2(nb_desc)) {
1367                 PMD_DRV_LOG(ERR,
1368                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1369                         nb_desc);
1370                 return -EINVAL;
1371         }
1372
1373         if (nb_desc > adapter->max_rx_ring_size) {
1374                 PMD_DRV_LOG(ERR,
1375                         "Unsupported size of RX queue (max size: %d)\n",
1376                         adapter->max_rx_ring_size);
1377                 return -EINVAL;
1378         }
1379
1380         /* ENA isn't supporting buffers smaller than 1400 bytes */
1381         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1382         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1383                 PMD_DRV_LOG(ERR,
1384                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1385                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1386                 return -EINVAL;
1387         }
1388
1389         rxq->port_id = dev->data->port_id;
1390         rxq->next_to_clean = 0;
1391         rxq->next_to_use = 0;
1392         rxq->ring_size = nb_desc;
1393         rxq->size_mask = nb_desc - 1;
1394         rxq->numa_socket_id = socket_id;
1395         rxq->mb_pool = mp;
1396
1397         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1398                 sizeof(struct ena_rx_buffer) * nb_desc,
1399                 RTE_CACHE_LINE_SIZE);
1400         if (!rxq->rx_buffer_info) {
1401                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1402                 return -ENOMEM;
1403         }
1404
1405         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1406                                             sizeof(struct rte_mbuf *) * nb_desc,
1407                                             RTE_CACHE_LINE_SIZE);
1408
1409         if (!rxq->rx_refill_buffer) {
1410                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1411                 rte_free(rxq->rx_buffer_info);
1412                 rxq->rx_buffer_info = NULL;
1413                 return -ENOMEM;
1414         }
1415
1416         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1417                                          sizeof(uint16_t) * nb_desc,
1418                                          RTE_CACHE_LINE_SIZE);
1419         if (!rxq->empty_rx_reqs) {
1420                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1421                 rte_free(rxq->rx_buffer_info);
1422                 rxq->rx_buffer_info = NULL;
1423                 rte_free(rxq->rx_refill_buffer);
1424                 rxq->rx_refill_buffer = NULL;
1425                 return -ENOMEM;
1426         }
1427
1428         for (i = 0; i < nb_desc; i++)
1429                 rxq->empty_rx_reqs[i] = i;
1430
1431         /* Store pointer to this queue in upper layer */
1432         rxq->configured = 1;
1433         dev->data->rx_queues[queue_idx] = rxq;
1434
1435         return 0;
1436 }
1437
1438 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1439                                   struct rte_mbuf *mbuf, uint16_t id)
1440 {
1441         struct ena_com_buf ebuf;
1442         int rc;
1443
1444         /* prepare physical address for DMA transaction */
1445         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1446         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1447
1448         /* pass resource to device */
1449         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1450         if (unlikely(rc != 0))
1451                 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1452
1453         return rc;
1454 }
1455
1456 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1457 {
1458         unsigned int i;
1459         int rc;
1460         uint16_t next_to_use = rxq->next_to_use;
1461         uint16_t in_use, req_id;
1462         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1463
1464         if (unlikely(!count))
1465                 return 0;
1466
1467         in_use = rxq->ring_size - 1 -
1468                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1469         ena_assert_msg(((in_use + count) < rxq->ring_size),
1470                 "bad ring state\n");
1471
1472         /* get resources for incoming packets */
1473         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1474         if (unlikely(rc < 0)) {
1475                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1476                 ++rxq->rx_stats.mbuf_alloc_fail;
1477                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1478                 return 0;
1479         }
1480
1481         for (i = 0; i < count; i++) {
1482                 struct rte_mbuf *mbuf = mbufs[i];
1483                 struct ena_rx_buffer *rx_info;
1484
1485                 if (likely((i + 4) < count))
1486                         rte_prefetch0(mbufs[i + 4]);
1487
1488                 req_id = rxq->empty_rx_reqs[next_to_use];
1489                 rc = validate_rx_req_id(rxq, req_id);
1490                 if (unlikely(rc))
1491                         break;
1492
1493                 rx_info = &rxq->rx_buffer_info[req_id];
1494
1495                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1496                 if (unlikely(rc != 0))
1497                         break;
1498
1499                 rx_info->mbuf = mbuf;
1500                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1501         }
1502
1503         if (unlikely(i < count)) {
1504                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1505                         "buffers (from %d)\n", rxq->id, i, count);
1506                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1507                                      count - i);
1508                 ++rxq->rx_stats.refill_partial;
1509         }
1510
1511         /* When we submitted free recources to device... */
1512         if (likely(i > 0)) {
1513                 /* ...let HW know that it can fill buffers with data. */
1514                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1515
1516                 rxq->next_to_use = next_to_use;
1517         }
1518
1519         return i;
1520 }
1521
1522 static int ena_device_init(struct ena_com_dev *ena_dev,
1523                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1524                            bool *wd_state)
1525 {
1526         uint32_t aenq_groups;
1527         int rc;
1528         bool readless_supported;
1529
1530         /* Initialize mmio registers */
1531         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1532         if (rc) {
1533                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1534                 return rc;
1535         }
1536
1537         /* The PCIe configuration space revision id indicate if mmio reg
1538          * read is disabled.
1539          */
1540         readless_supported =
1541                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1542                                & ENA_MMIO_DISABLE_REG_READ);
1543         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1544
1545         /* reset device */
1546         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1547         if (rc) {
1548                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1549                 goto err_mmio_read_less;
1550         }
1551
1552         /* check FW version */
1553         rc = ena_com_validate_version(ena_dev);
1554         if (rc) {
1555                 PMD_DRV_LOG(ERR, "device version is too low\n");
1556                 goto err_mmio_read_less;
1557         }
1558
1559         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1560
1561         /* ENA device administration layer init */
1562         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1563         if (rc) {
1564                 PMD_DRV_LOG(ERR,
1565                         "cannot initialize ena admin queue with device\n");
1566                 goto err_mmio_read_less;
1567         }
1568
1569         /* To enable the msix interrupts the driver needs to know the number
1570          * of queues. So the driver uses polling mode to retrieve this
1571          * information.
1572          */
1573         ena_com_set_admin_polling_mode(ena_dev, true);
1574
1575         ena_config_host_info(ena_dev);
1576
1577         /* Get Device Attributes and features */
1578         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1579         if (rc) {
1580                 PMD_DRV_LOG(ERR,
1581                         "cannot get attribute for ena device rc= %d\n", rc);
1582                 goto err_admin_init;
1583         }
1584
1585         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1586                       BIT(ENA_ADMIN_NOTIFICATION) |
1587                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1588                       BIT(ENA_ADMIN_FATAL_ERROR) |
1589                       BIT(ENA_ADMIN_WARNING);
1590
1591         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1592         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1593         if (rc) {
1594                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1595                 goto err_admin_init;
1596         }
1597
1598         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1599
1600         return 0;
1601
1602 err_admin_init:
1603         ena_com_admin_destroy(ena_dev);
1604
1605 err_mmio_read_less:
1606         ena_com_mmio_reg_read_request_destroy(ena_dev);
1607
1608         return rc;
1609 }
1610
1611 static void ena_interrupt_handler_rte(void *cb_arg)
1612 {
1613         struct ena_adapter *adapter = cb_arg;
1614         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1615
1616         ena_com_admin_q_comp_intr_handler(ena_dev);
1617         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1618                 ena_com_aenq_intr_handler(ena_dev, adapter);
1619 }
1620
1621 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1622 {
1623         if (!adapter->wd_state)
1624                 return;
1625
1626         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1627                 return;
1628
1629         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1630             adapter->keep_alive_timeout)) {
1631                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1632                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1633                 adapter->trigger_reset = true;
1634                 ++adapter->dev_stats.wd_expired;
1635         }
1636 }
1637
1638 /* Check if admin queue is enabled */
1639 static void check_for_admin_com_state(struct ena_adapter *adapter)
1640 {
1641         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1642                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1643                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1644                 adapter->trigger_reset = true;
1645         }
1646 }
1647
1648 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1649                                   void *arg)
1650 {
1651         struct ena_adapter *adapter = arg;
1652         struct rte_eth_dev *dev = adapter->rte_dev;
1653
1654         check_for_missing_keep_alive(adapter);
1655         check_for_admin_com_state(adapter);
1656
1657         if (unlikely(adapter->trigger_reset)) {
1658                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1659                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1660                         NULL);
1661         }
1662 }
1663
1664 static inline void
1665 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1666                                struct ena_admin_feature_llq_desc *llq,
1667                                bool use_large_llq_hdr)
1668 {
1669         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1670         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1671         llq_config->llq_num_decs_before_header =
1672                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1673
1674         if (use_large_llq_hdr &&
1675             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1676                 llq_config->llq_ring_entry_size =
1677                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1678                 llq_config->llq_ring_entry_size_value = 256;
1679         } else {
1680                 llq_config->llq_ring_entry_size =
1681                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1682                 llq_config->llq_ring_entry_size_value = 128;
1683         }
1684 }
1685
1686 static int
1687 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1688                                 struct ena_com_dev *ena_dev,
1689                                 struct ena_admin_feature_llq_desc *llq,
1690                                 struct ena_llq_configurations *llq_default_configurations)
1691 {
1692         int rc;
1693         u32 llq_feature_mask;
1694
1695         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1696         if (!(ena_dev->supported_features & llq_feature_mask)) {
1697                 PMD_DRV_LOG(INFO,
1698                         "LLQ is not supported. Fallback to host mode policy.\n");
1699                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1700                 return 0;
1701         }
1702
1703         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1704         if (unlikely(rc)) {
1705                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1706                         "Fallback to host mode policy.");
1707                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1708                 return 0;
1709         }
1710
1711         /* Nothing to config, exit */
1712         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1713                 return 0;
1714
1715         if (!adapter->dev_mem_base) {
1716                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1717                         "Fallback to host mode policy.\n.");
1718                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1719                 return 0;
1720         }
1721
1722         ena_dev->mem_bar = adapter->dev_mem_base;
1723
1724         return 0;
1725 }
1726
1727 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1728         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1729 {
1730         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1731
1732         /* Regular queues capabilities */
1733         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1734                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1735                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1736                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1737                                     max_queue_ext->max_rx_cq_num);
1738                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1739                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1740         } else {
1741                 struct ena_admin_queue_feature_desc *max_queues =
1742                         &get_feat_ctx->max_queues;
1743                 io_tx_sq_num = max_queues->max_sq_num;
1744                 io_tx_cq_num = max_queues->max_cq_num;
1745                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1746         }
1747
1748         /* In case of LLQ use the llq number in the get feature cmd */
1749         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1750                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1751
1752         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1753         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1754         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1755
1756         if (unlikely(max_num_io_queues == 0)) {
1757                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1758                 return -EFAULT;
1759         }
1760
1761         return max_num_io_queues;
1762 }
1763
1764 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1765 {
1766         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1767         struct rte_pci_device *pci_dev;
1768         struct rte_intr_handle *intr_handle;
1769         struct ena_adapter *adapter = eth_dev->data->dev_private;
1770         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1771         struct ena_com_dev_get_features_ctx get_feat_ctx;
1772         struct ena_llq_configurations llq_config;
1773         const char *queue_type_str;
1774         uint32_t max_num_io_queues;
1775         int rc;
1776         static int adapters_found;
1777         bool disable_meta_caching;
1778         bool wd_state = false;
1779
1780         eth_dev->dev_ops = &ena_dev_ops;
1781         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1782         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1783         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1784
1785         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1786                 return 0;
1787
1788         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1789
1790         memset(adapter, 0, sizeof(struct ena_adapter));
1791         ena_dev = &adapter->ena_dev;
1792
1793         adapter->rte_eth_dev_data = eth_dev->data;
1794         adapter->rte_dev = eth_dev;
1795
1796         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1797         adapter->pdev = pci_dev;
1798
1799         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1800                      pci_dev->addr.domain,
1801                      pci_dev->addr.bus,
1802                      pci_dev->addr.devid,
1803                      pci_dev->addr.function);
1804
1805         intr_handle = &pci_dev->intr_handle;
1806
1807         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1808         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1809
1810         if (!adapter->regs) {
1811                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1812                              ENA_REGS_BAR);
1813                 return -ENXIO;
1814         }
1815
1816         ena_dev->reg_bar = adapter->regs;
1817         ena_dev->dmadev = adapter->pdev;
1818
1819         adapter->id_number = adapters_found;
1820
1821         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1822                  adapter->id_number);
1823
1824         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1825         if (rc != 0) {
1826                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1827                 goto err;
1828         }
1829
1830         /* device specific initialization routine */
1831         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1832         if (rc) {
1833                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1834                 goto err;
1835         }
1836         adapter->wd_state = wd_state;
1837
1838         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1839                 adapter->use_large_llq_hdr);
1840         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1841                                              &get_feat_ctx.llq, &llq_config);
1842         if (unlikely(rc)) {
1843                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1844                 return rc;
1845         }
1846
1847         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1848                 queue_type_str = "Regular";
1849         else
1850                 queue_type_str = "Low latency";
1851         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1852
1853         calc_queue_ctx.ena_dev = ena_dev;
1854         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1855
1856         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1857         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1858                 adapter->use_large_llq_hdr);
1859         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1860                 rc = -EFAULT;
1861                 goto err_device_destroy;
1862         }
1863
1864         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1865         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1866         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1867         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1868         adapter->max_num_io_queues = max_num_io_queues;
1869
1870         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1871                 disable_meta_caching =
1872                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1873                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1874         } else {
1875                 disable_meta_caching = false;
1876         }
1877
1878         /* prepare ring structures */
1879         ena_init_rings(adapter, disable_meta_caching);
1880
1881         ena_config_debug_area(adapter);
1882
1883         /* Set max MTU for this device */
1884         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1885
1886         /* set device support for offloads */
1887         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1888                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1889         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1890                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1891         adapter->offloads.rx_csum_supported =
1892                 (get_feat_ctx.offload.rx_supported &
1893                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1894
1895         /* Copy MAC address and point DPDK to it */
1896         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1897         rte_ether_addr_copy((struct rte_ether_addr *)
1898                         get_feat_ctx.dev_attr.mac_addr,
1899                         (struct rte_ether_addr *)adapter->mac_addr);
1900
1901         adapter->drv_stats = rte_zmalloc("adapter stats",
1902                                          sizeof(*adapter->drv_stats),
1903                                          RTE_CACHE_LINE_SIZE);
1904         if (!adapter->drv_stats) {
1905                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1906                 rc = -ENOMEM;
1907                 goto err_delete_debug_area;
1908         }
1909
1910         rte_spinlock_init(&adapter->admin_lock);
1911
1912         rte_intr_callback_register(intr_handle,
1913                                    ena_interrupt_handler_rte,
1914                                    adapter);
1915         rte_intr_enable(intr_handle);
1916         ena_com_set_admin_polling_mode(ena_dev, false);
1917         ena_com_admin_aenq_enable(ena_dev);
1918
1919         if (adapters_found == 0)
1920                 rte_timer_subsystem_init();
1921         rte_timer_init(&adapter->timer_wd);
1922
1923         adapters_found++;
1924         adapter->state = ENA_ADAPTER_STATE_INIT;
1925
1926         return 0;
1927
1928 err_delete_debug_area:
1929         ena_com_delete_debug_area(ena_dev);
1930
1931 err_device_destroy:
1932         ena_com_delete_host_info(ena_dev);
1933         ena_com_admin_destroy(ena_dev);
1934
1935 err:
1936         return rc;
1937 }
1938
1939 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1940 {
1941         struct ena_adapter *adapter = eth_dev->data->dev_private;
1942         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1943
1944         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1945                 return;
1946
1947         ena_com_set_admin_running_state(ena_dev, false);
1948
1949         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1950                 ena_close(eth_dev);
1951
1952         ena_com_delete_debug_area(ena_dev);
1953         ena_com_delete_host_info(ena_dev);
1954
1955         ena_com_abort_admin_commands(ena_dev);
1956         ena_com_wait_for_abort_completion(ena_dev);
1957         ena_com_admin_destroy(ena_dev);
1958         ena_com_mmio_reg_read_request_destroy(ena_dev);
1959
1960         adapter->state = ENA_ADAPTER_STATE_FREE;
1961 }
1962
1963 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1964 {
1965         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1966                 return 0;
1967
1968         ena_destroy_device(eth_dev);
1969
1970         return 0;
1971 }
1972
1973 static int ena_dev_configure(struct rte_eth_dev *dev)
1974 {
1975         struct ena_adapter *adapter = dev->data->dev_private;
1976
1977         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1978
1979         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1980         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1981         return 0;
1982 }
1983
1984 static void ena_init_rings(struct ena_adapter *adapter,
1985                            bool disable_meta_caching)
1986 {
1987         size_t i;
1988
1989         for (i = 0; i < adapter->max_num_io_queues; i++) {
1990                 struct ena_ring *ring = &adapter->tx_ring[i];
1991
1992                 ring->configured = 0;
1993                 ring->type = ENA_RING_TYPE_TX;
1994                 ring->adapter = adapter;
1995                 ring->id = i;
1996                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1997                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1998                 ring->sgl_size = adapter->max_tx_sgl_size;
1999                 ring->disable_meta_caching = disable_meta_caching;
2000         }
2001
2002         for (i = 0; i < adapter->max_num_io_queues; i++) {
2003                 struct ena_ring *ring = &adapter->rx_ring[i];
2004
2005                 ring->configured = 0;
2006                 ring->type = ENA_RING_TYPE_RX;
2007                 ring->adapter = adapter;
2008                 ring->id = i;
2009                 ring->sgl_size = adapter->max_rx_sgl_size;
2010         }
2011 }
2012
2013 static int ena_infos_get(struct rte_eth_dev *dev,
2014                           struct rte_eth_dev_info *dev_info)
2015 {
2016         struct ena_adapter *adapter;
2017         struct ena_com_dev *ena_dev;
2018         uint64_t rx_feat = 0, tx_feat = 0;
2019
2020         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2021         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2022         adapter = dev->data->dev_private;
2023
2024         ena_dev = &adapter->ena_dev;
2025         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2026
2027         dev_info->speed_capa =
2028                         ETH_LINK_SPEED_1G   |
2029                         ETH_LINK_SPEED_2_5G |
2030                         ETH_LINK_SPEED_5G   |
2031                         ETH_LINK_SPEED_10G  |
2032                         ETH_LINK_SPEED_25G  |
2033                         ETH_LINK_SPEED_40G  |
2034                         ETH_LINK_SPEED_50G  |
2035                         ETH_LINK_SPEED_100G;
2036
2037         /* Set Tx & Rx features available for device */
2038         if (adapter->offloads.tso4_supported)
2039                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2040
2041         if (adapter->offloads.tx_csum_supported)
2042                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2043                         DEV_TX_OFFLOAD_UDP_CKSUM |
2044                         DEV_TX_OFFLOAD_TCP_CKSUM;
2045
2046         if (adapter->offloads.rx_csum_supported)
2047                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2048                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2049                         DEV_RX_OFFLOAD_TCP_CKSUM;
2050
2051         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2052
2053         /* Inform framework about available features */
2054         dev_info->rx_offload_capa = rx_feat;
2055         dev_info->rx_queue_offload_capa = rx_feat;
2056         dev_info->tx_offload_capa = tx_feat;
2057         dev_info->tx_queue_offload_capa = tx_feat;
2058
2059         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2060                                            ETH_RSS_UDP;
2061
2062         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2063         dev_info->max_rx_pktlen  = adapter->max_mtu;
2064         dev_info->max_mac_addrs = 1;
2065
2066         dev_info->max_rx_queues = adapter->max_num_io_queues;
2067         dev_info->max_tx_queues = adapter->max_num_io_queues;
2068         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2069
2070         adapter->tx_supported_offloads = tx_feat;
2071         adapter->rx_supported_offloads = rx_feat;
2072
2073         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2074         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2075         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2076                                         adapter->max_rx_sgl_size);
2077         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2078                                         adapter->max_rx_sgl_size);
2079
2080         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2081         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2082         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2083                                         adapter->max_tx_sgl_size);
2084         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2085                                         adapter->max_tx_sgl_size);
2086
2087         return 0;
2088 }
2089
2090 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2091 {
2092         mbuf->data_len = len;
2093         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2094         mbuf->refcnt = 1;
2095         mbuf->next = NULL;
2096 }
2097
2098 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2099                                     struct ena_com_rx_buf_info *ena_bufs,
2100                                     uint32_t descs,
2101                                     uint16_t *next_to_clean,
2102                                     uint8_t offset)
2103 {
2104         struct rte_mbuf *mbuf;
2105         struct rte_mbuf *mbuf_head;
2106         struct ena_rx_buffer *rx_info;
2107         int rc;
2108         uint16_t ntc, len, req_id, buf = 0;
2109
2110         if (unlikely(descs == 0))
2111                 return NULL;
2112
2113         ntc = *next_to_clean;
2114
2115         len = ena_bufs[buf].len;
2116         req_id = ena_bufs[buf].req_id;
2117         if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2118                 return NULL;
2119
2120         rx_info = &rx_ring->rx_buffer_info[req_id];
2121
2122         mbuf = rx_info->mbuf;
2123         RTE_ASSERT(mbuf != NULL);
2124
2125         ena_init_rx_mbuf(mbuf, len);
2126
2127         /* Fill the mbuf head with the data specific for 1st segment. */
2128         mbuf_head = mbuf;
2129         mbuf_head->nb_segs = descs;
2130         mbuf_head->port = rx_ring->port_id;
2131         mbuf_head->pkt_len = len;
2132         mbuf_head->data_off += offset;
2133
2134         rx_info->mbuf = NULL;
2135         rx_ring->empty_rx_reqs[ntc] = req_id;
2136         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2137
2138         while (--descs) {
2139                 ++buf;
2140                 len = ena_bufs[buf].len;
2141                 req_id = ena_bufs[buf].req_id;
2142                 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2143                         rte_mbuf_raw_free(mbuf_head);
2144                         return NULL;
2145                 }
2146
2147                 rx_info = &rx_ring->rx_buffer_info[req_id];
2148                 RTE_ASSERT(rx_info->mbuf != NULL);
2149
2150                 if (unlikely(len == 0)) {
2151                         /*
2152                          * Some devices can pass descriptor with the length 0.
2153                          * To avoid confusion, the PMD is simply putting the
2154                          * descriptor back, as it was never used. We'll avoid
2155                          * mbuf allocation that way.
2156                          */
2157                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2158                                 rx_info->mbuf, req_id);
2159                         if (unlikely(rc != 0)) {
2160                                 /* Free the mbuf in case of an error. */
2161                                 rte_mbuf_raw_free(rx_info->mbuf);
2162                         } else {
2163                                 /*
2164                                  * If there was no error, just exit the loop as
2165                                  * 0 length descriptor is always the last one.
2166                                  */
2167                                 break;
2168                         }
2169                 } else {
2170                         /* Create an mbuf chain. */
2171                         mbuf->next = rx_info->mbuf;
2172                         mbuf = mbuf->next;
2173
2174                         ena_init_rx_mbuf(mbuf, len);
2175                         mbuf_head->pkt_len += len;
2176                 }
2177
2178                 /*
2179                  * Mark the descriptor as depleted and perform necessary
2180                  * cleanup.
2181                  * This code will execute in two cases:
2182                  *  1. Descriptor len was greater than 0 - normal situation.
2183                  *  2. Descriptor len was 0 and we failed to add the descriptor
2184                  *     to the device. In that situation, we should try to add
2185                  *     the mbuf again in the populate routine and mark the
2186                  *     descriptor as used up by the device.
2187                  */
2188                 rx_info->mbuf = NULL;
2189                 rx_ring->empty_rx_reqs[ntc] = req_id;
2190                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2191         }
2192
2193         *next_to_clean = ntc;
2194
2195         return mbuf_head;
2196 }
2197
2198 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2199                                   uint16_t nb_pkts)
2200 {
2201         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2202         unsigned int free_queue_entries;
2203         unsigned int refill_threshold;
2204         uint16_t next_to_clean = rx_ring->next_to_clean;
2205         uint16_t descs_in_use;
2206         struct rte_mbuf *mbuf;
2207         uint16_t completed;
2208         struct ena_com_rx_ctx ena_rx_ctx;
2209         int i, rc = 0;
2210
2211         /* Check adapter state */
2212         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2213                 PMD_DRV_LOG(ALERT,
2214                         "Trying to receive pkts while device is NOT running\n");
2215                 return 0;
2216         }
2217
2218         descs_in_use = rx_ring->ring_size -
2219                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2220         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2221
2222         for (completed = 0; completed < nb_pkts; completed++) {
2223                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2224                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2225                 ena_rx_ctx.descs = 0;
2226                 ena_rx_ctx.pkt_offset = 0;
2227                 /* receive packet context */
2228                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2229                                     rx_ring->ena_com_io_sq,
2230                                     &ena_rx_ctx);
2231                 if (unlikely(rc)) {
2232                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2233                         rx_ring->adapter->reset_reason =
2234                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2235                         rx_ring->adapter->trigger_reset = true;
2236                         ++rx_ring->rx_stats.bad_desc_num;
2237                         return 0;
2238                 }
2239
2240                 mbuf = ena_rx_mbuf(rx_ring,
2241                         ena_rx_ctx.ena_bufs,
2242                         ena_rx_ctx.descs,
2243                         &next_to_clean,
2244                         ena_rx_ctx.pkt_offset);
2245                 if (unlikely(mbuf == NULL)) {
2246                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2247                                 rx_ring->empty_rx_reqs[next_to_clean] =
2248                                         rx_ring->ena_bufs[i].req_id;
2249                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2250                                         next_to_clean, rx_ring->size_mask);
2251                         }
2252                         break;
2253                 }
2254
2255                 /* fill mbuf attributes if any */
2256                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2257
2258                 if (unlikely(mbuf->ol_flags &
2259                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2260                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2261                         ++rx_ring->rx_stats.bad_csum;
2262                 }
2263
2264                 mbuf->hash.rss = ena_rx_ctx.hash;
2265
2266                 rx_pkts[completed] = mbuf;
2267                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2268         }
2269
2270         rx_ring->rx_stats.cnt += completed;
2271         rx_ring->next_to_clean = next_to_clean;
2272
2273         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2274         refill_threshold =
2275                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2276                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2277
2278         /* Burst refill to save doorbells, memory barriers, const interval */
2279         if (free_queue_entries > refill_threshold) {
2280                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2281                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2282         }
2283
2284         return completed;
2285 }
2286
2287 static uint16_t
2288 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2289                 uint16_t nb_pkts)
2290 {
2291         int32_t ret;
2292         uint32_t i;
2293         struct rte_mbuf *m;
2294         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2295         struct rte_ipv4_hdr *ip_hdr;
2296         uint64_t ol_flags;
2297         uint16_t frag_field;
2298
2299         for (i = 0; i != nb_pkts; i++) {
2300                 m = tx_pkts[i];
2301                 ol_flags = m->ol_flags;
2302
2303                 if (!(ol_flags & PKT_TX_IPV4))
2304                         continue;
2305
2306                 /* If there was not L2 header length specified, assume it is
2307                  * length of the ethernet header.
2308                  */
2309                 if (unlikely(m->l2_len == 0))
2310                         m->l2_len = sizeof(struct rte_ether_hdr);
2311
2312                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2313                                                  m->l2_len);
2314                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2315
2316                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2317                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2318
2319                         /* If IPv4 header has DF flag enabled and TSO support is
2320                          * disabled, partial chcecksum should not be calculated.
2321                          */
2322                         if (!tx_ring->adapter->offloads.tso4_supported)
2323                                 continue;
2324                 }
2325
2326                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2327                                 (ol_flags & PKT_TX_L4_MASK) ==
2328                                 PKT_TX_SCTP_CKSUM) {
2329                         rte_errno = ENOTSUP;
2330                         return i;
2331                 }
2332
2333 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2334                 ret = rte_validate_tx_offload(m);
2335                 if (ret != 0) {
2336                         rte_errno = -ret;
2337                         return i;
2338                 }
2339 #endif
2340
2341                 /* In case we are supposed to TSO and have DF not set (DF=0)
2342                  * hardware must be provided with partial checksum, otherwise
2343                  * it will take care of necessary calculations.
2344                  */
2345
2346                 ret = rte_net_intel_cksum_flags_prepare(m,
2347                         ol_flags & ~PKT_TX_TCP_SEG);
2348                 if (ret != 0) {
2349                         rte_errno = -ret;
2350                         return i;
2351                 }
2352         }
2353
2354         return i;
2355 }
2356
2357 static void ena_update_hints(struct ena_adapter *adapter,
2358                              struct ena_admin_ena_hw_hints *hints)
2359 {
2360         if (hints->admin_completion_tx_timeout)
2361                 adapter->ena_dev.admin_queue.completion_timeout =
2362                         hints->admin_completion_tx_timeout * 1000;
2363
2364         if (hints->mmio_read_timeout)
2365                 /* convert to usec */
2366                 adapter->ena_dev.mmio_read.reg_read_to =
2367                         hints->mmio_read_timeout * 1000;
2368
2369         if (hints->driver_watchdog_timeout) {
2370                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2371                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2372                 else
2373                         // Convert msecs to ticks
2374                         adapter->keep_alive_timeout =
2375                                 (hints->driver_watchdog_timeout *
2376                                 rte_get_timer_hz()) / 1000;
2377         }
2378 }
2379
2380 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2381                                         struct rte_mbuf *mbuf)
2382 {
2383         struct ena_com_dev *ena_dev;
2384         int num_segments, header_len, rc;
2385
2386         ena_dev = &tx_ring->adapter->ena_dev;
2387         num_segments = mbuf->nb_segs;
2388         header_len = mbuf->data_len;
2389
2390         if (likely(num_segments < tx_ring->sgl_size))
2391                 return 0;
2392
2393         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2394             (num_segments == tx_ring->sgl_size) &&
2395             (header_len < tx_ring->tx_max_header_size))
2396                 return 0;
2397
2398         ++tx_ring->tx_stats.linearize;
2399         rc = rte_pktmbuf_linearize(mbuf);
2400         if (unlikely(rc)) {
2401                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2402                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2403                 ++tx_ring->tx_stats.linearize_failed;
2404                 return rc;
2405         }
2406
2407         return rc;
2408 }
2409
2410 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2411         struct ena_tx_buffer *tx_info,
2412         struct rte_mbuf *mbuf,
2413         void **push_header,
2414         uint16_t *header_len)
2415 {
2416         struct ena_com_buf *ena_buf;
2417         uint16_t delta, seg_len, push_len;
2418
2419         delta = 0;
2420         seg_len = mbuf->data_len;
2421
2422         tx_info->mbuf = mbuf;
2423         ena_buf = tx_info->bufs;
2424
2425         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2426                 /*
2427                  * Tx header might be (and will be in most cases) smaller than
2428                  * tx_max_header_size. But it's not an issue to send more data
2429                  * to the device, than actually needed if the mbuf size is
2430                  * greater than tx_max_header_size.
2431                  */
2432                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2433                 *header_len = push_len;
2434
2435                 if (likely(push_len <= seg_len)) {
2436                         /* If the push header is in the single segment, then
2437                          * just point it to the 1st mbuf data.
2438                          */
2439                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2440                 } else {
2441                         /* If the push header lays in the several segments, copy
2442                          * it to the intermediate buffer.
2443                          */
2444                         rte_pktmbuf_read(mbuf, 0, push_len,
2445                                 tx_ring->push_buf_intermediate_buf);
2446                         *push_header = tx_ring->push_buf_intermediate_buf;
2447                         delta = push_len - seg_len;
2448                 }
2449         } else {
2450                 *push_header = NULL;
2451                 *header_len = 0;
2452                 push_len = 0;
2453         }
2454
2455         /* Process first segment taking into consideration pushed header */
2456         if (seg_len > push_len) {
2457                 ena_buf->paddr = mbuf->buf_iova +
2458                                 mbuf->data_off +
2459                                 push_len;
2460                 ena_buf->len = seg_len - push_len;
2461                 ena_buf++;
2462                 tx_info->num_of_bufs++;
2463         }
2464
2465         while ((mbuf = mbuf->next) != NULL) {
2466                 seg_len = mbuf->data_len;
2467
2468                 /* Skip mbufs if whole data is pushed as a header */
2469                 if (unlikely(delta > seg_len)) {
2470                         delta -= seg_len;
2471                         continue;
2472                 }
2473
2474                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2475                 ena_buf->len = seg_len - delta;
2476                 ena_buf++;
2477                 tx_info->num_of_bufs++;
2478
2479                 delta = 0;
2480         }
2481 }
2482
2483 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2484 {
2485         struct ena_tx_buffer *tx_info;
2486         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2487         uint16_t next_to_use;
2488         uint16_t header_len;
2489         uint16_t req_id;
2490         void *push_header;
2491         int nb_hw_desc;
2492         int rc;
2493
2494         rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2495         if (unlikely(rc))
2496                 return rc;
2497
2498         next_to_use = tx_ring->next_to_use;
2499
2500         req_id = tx_ring->empty_tx_reqs[next_to_use];
2501         tx_info = &tx_ring->tx_buffer_info[req_id];
2502         tx_info->num_of_bufs = 0;
2503
2504         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2505
2506         ena_tx_ctx.ena_bufs = tx_info->bufs;
2507         ena_tx_ctx.push_header = push_header;
2508         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2509         ena_tx_ctx.req_id = req_id;
2510         ena_tx_ctx.header_len = header_len;
2511
2512         /* Set Tx offloads flags, if applicable */
2513         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2514                 tx_ring->disable_meta_caching);
2515
2516         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2517                         &ena_tx_ctx))) {
2518                 PMD_DRV_LOG(DEBUG,
2519                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2520                         tx_ring->id);
2521                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2522                 tx_ring->tx_stats.doorbells++;
2523         }
2524
2525         /* prepare the packet's descriptors to dma engine */
2526         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2527                 &nb_hw_desc);
2528         if (unlikely(rc)) {
2529                 ++tx_ring->tx_stats.prepare_ctx_err;
2530                 return rc;
2531         }
2532
2533         tx_info->tx_descs = nb_hw_desc;
2534
2535         tx_ring->tx_stats.cnt++;
2536         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2537
2538         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2539                 tx_ring->size_mask);
2540
2541         return 0;
2542 }
2543
2544 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2545 {
2546         unsigned int cleanup_budget;
2547         unsigned int total_tx_descs = 0;
2548         uint16_t next_to_clean = tx_ring->next_to_clean;
2549
2550         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2551                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2552
2553         while (likely(total_tx_descs < cleanup_budget)) {
2554                 struct rte_mbuf *mbuf;
2555                 struct ena_tx_buffer *tx_info;
2556                 uint16_t req_id;
2557
2558                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2559                         break;
2560
2561                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2562                         break;
2563
2564                 /* Get Tx info & store how many descs were processed  */
2565                 tx_info = &tx_ring->tx_buffer_info[req_id];
2566
2567                 mbuf = tx_info->mbuf;
2568                 rte_pktmbuf_free(mbuf);
2569
2570                 tx_info->mbuf = NULL;
2571                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2572
2573                 total_tx_descs += tx_info->tx_descs;
2574
2575                 /* Put back descriptor to the ring for reuse */
2576                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2577                         tx_ring->size_mask);
2578         }
2579
2580         if (likely(total_tx_descs > 0)) {
2581                 /* acknowledge completion of sent packets */
2582                 tx_ring->next_to_clean = next_to_clean;
2583                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2584                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2585         }
2586 }
2587
2588 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2589                                   uint16_t nb_pkts)
2590 {
2591         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2592         uint16_t sent_idx = 0;
2593
2594         /* Check adapter state */
2595         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2596                 PMD_DRV_LOG(ALERT,
2597                         "Trying to xmit pkts while device is NOT running\n");
2598                 return 0;
2599         }
2600
2601         nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2602                 nb_pkts);
2603
2604         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2605                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2606                         break;
2607
2608                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2609                         tx_ring->size_mask)]);
2610         }
2611
2612         tx_ring->tx_stats.available_desc =
2613                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2614
2615         /* If there are ready packets to be xmitted... */
2616         if (sent_idx > 0) {
2617                 /* ...let HW do its best :-) */
2618                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2619                 tx_ring->tx_stats.doorbells++;
2620         }
2621
2622         ena_tx_cleanup(tx_ring);
2623
2624         tx_ring->tx_stats.available_desc =
2625                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2626         tx_ring->tx_stats.tx_poll++;
2627
2628         return sent_idx;
2629 }
2630
2631 int ena_copy_eni_stats(struct ena_adapter *adapter)
2632 {
2633         struct ena_admin_eni_stats admin_eni_stats;
2634         int rc;
2635
2636         rte_spinlock_lock(&adapter->admin_lock);
2637         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2638         rte_spinlock_unlock(&adapter->admin_lock);
2639         if (rc != 0) {
2640                 if (rc == ENA_COM_UNSUPPORTED) {
2641                         PMD_DRV_LOG(DEBUG,
2642                                 "Retrieving ENI metrics is not supported.\n");
2643                 } else {
2644                         PMD_DRV_LOG(WARNING,
2645                                 "Failed to get ENI metrics: %d\n", rc);
2646                 }
2647                 return rc;
2648         }
2649
2650         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2651                 sizeof(struct ena_stats_eni));
2652
2653         return 0;
2654 }
2655
2656 /**
2657  * DPDK callback to retrieve names of extended device statistics
2658  *
2659  * @param dev
2660  *   Pointer to Ethernet device structure.
2661  * @param[out] xstats_names
2662  *   Buffer to insert names into.
2663  * @param n
2664  *   Number of names.
2665  *
2666  * @return
2667  *   Number of xstats names.
2668  */
2669 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2670                                 struct rte_eth_xstat_name *xstats_names,
2671                                 unsigned int n)
2672 {
2673         unsigned int xstats_count = ena_xstats_calc_num(dev);
2674         unsigned int stat, i, count = 0;
2675
2676         if (n < xstats_count || !xstats_names)
2677                 return xstats_count;
2678
2679         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2680                 strcpy(xstats_names[count].name,
2681                         ena_stats_global_strings[stat].name);
2682
2683         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2684                 strcpy(xstats_names[count].name,
2685                         ena_stats_eni_strings[stat].name);
2686
2687         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2688                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2689                         snprintf(xstats_names[count].name,
2690                                 sizeof(xstats_names[count].name),
2691                                 "rx_q%d_%s", i,
2692                                 ena_stats_rx_strings[stat].name);
2693
2694         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2695                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2696                         snprintf(xstats_names[count].name,
2697                                 sizeof(xstats_names[count].name),
2698                                 "tx_q%d_%s", i,
2699                                 ena_stats_tx_strings[stat].name);
2700
2701         return xstats_count;
2702 }
2703
2704 /**
2705  * DPDK callback to get extended device statistics.
2706  *
2707  * @param dev
2708  *   Pointer to Ethernet device structure.
2709  * @param[out] stats
2710  *   Stats table output buffer.
2711  * @param n
2712  *   The size of the stats table.
2713  *
2714  * @return
2715  *   Number of xstats on success, negative on failure.
2716  */
2717 static int ena_xstats_get(struct rte_eth_dev *dev,
2718                           struct rte_eth_xstat *xstats,
2719                           unsigned int n)
2720 {
2721         struct ena_adapter *adapter = dev->data->dev_private;
2722         unsigned int xstats_count = ena_xstats_calc_num(dev);
2723         unsigned int stat, i, count = 0;
2724         int stat_offset;
2725         void *stats_begin;
2726
2727         if (n < xstats_count)
2728                 return xstats_count;
2729
2730         if (!xstats)
2731                 return 0;
2732
2733         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2734                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2735                 stats_begin = &adapter->dev_stats;
2736
2737                 xstats[count].id = count;
2738                 xstats[count].value = *((uint64_t *)
2739                         ((char *)stats_begin + stat_offset));
2740         }
2741
2742         /* Even if the function below fails, we should copy previous (or initial
2743          * values) to keep structure of rte_eth_xstat consistent.
2744          */
2745         ena_copy_eni_stats(adapter);
2746         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2747                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2748                 stats_begin = &adapter->eni_stats;
2749
2750                 xstats[count].id = count;
2751                 xstats[count].value = *((uint64_t *)
2752                     ((char *)stats_begin + stat_offset));
2753         }
2754
2755         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2756                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2757                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2758                         stats_begin = &adapter->rx_ring[i].rx_stats;
2759
2760                         xstats[count].id = count;
2761                         xstats[count].value = *((uint64_t *)
2762                                 ((char *)stats_begin + stat_offset));
2763                 }
2764         }
2765
2766         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2767                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2768                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2769                         stats_begin = &adapter->tx_ring[i].rx_stats;
2770
2771                         xstats[count].id = count;
2772                         xstats[count].value = *((uint64_t *)
2773                                 ((char *)stats_begin + stat_offset));
2774                 }
2775         }
2776
2777         return count;
2778 }
2779
2780 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2781                                 const uint64_t *ids,
2782                                 uint64_t *values,
2783                                 unsigned int n)
2784 {
2785         struct ena_adapter *adapter = dev->data->dev_private;
2786         uint64_t id;
2787         uint64_t rx_entries, tx_entries;
2788         unsigned int i;
2789         int qid;
2790         int valid = 0;
2791         bool was_eni_copied = false;
2792
2793         for (i = 0; i < n; ++i) {
2794                 id = ids[i];
2795                 /* Check if id belongs to global statistics */
2796                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2797                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2798                         ++valid;
2799                         continue;
2800                 }
2801
2802                 /* Check if id belongs to ENI statistics */
2803                 id -= ENA_STATS_ARRAY_GLOBAL;
2804                 if (id < ENA_STATS_ARRAY_ENI) {
2805                         /* Avoid reading ENI stats multiple times in a single
2806                          * function call, as it requires communication with the
2807                          * admin queue.
2808                          */
2809                         if (!was_eni_copied) {
2810                                 was_eni_copied = true;
2811                                 ena_copy_eni_stats(adapter);
2812                         }
2813                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2814                         ++valid;
2815                         continue;
2816                 }
2817
2818                 /* Check if id belongs to rx queue statistics */
2819                 id -= ENA_STATS_ARRAY_ENI;
2820                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2821                 if (id < rx_entries) {
2822                         qid = id % dev->data->nb_rx_queues;
2823                         id /= dev->data->nb_rx_queues;
2824                         values[i] = *((uint64_t *)
2825                                 &adapter->rx_ring[qid].rx_stats + id);
2826                         ++valid;
2827                         continue;
2828                 }
2829                                 /* Check if id belongs to rx queue statistics */
2830                 id -= rx_entries;
2831                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2832                 if (id < tx_entries) {
2833                         qid = id % dev->data->nb_tx_queues;
2834                         id /= dev->data->nb_tx_queues;
2835                         values[i] = *((uint64_t *)
2836                                 &adapter->tx_ring[qid].tx_stats + id);
2837                         ++valid;
2838                         continue;
2839                 }
2840         }
2841
2842         return valid;
2843 }
2844
2845 static int ena_process_bool_devarg(const char *key,
2846                                    const char *value,
2847                                    void *opaque)
2848 {
2849         struct ena_adapter *adapter = opaque;
2850         bool bool_value;
2851
2852         /* Parse the value. */
2853         if (strcmp(value, "1") == 0) {
2854                 bool_value = true;
2855         } else if (strcmp(value, "0") == 0) {
2856                 bool_value = false;
2857         } else {
2858                 PMD_INIT_LOG(ERR,
2859                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2860                         value, key);
2861                 return -EINVAL;
2862         }
2863
2864         /* Now, assign it to the proper adapter field. */
2865         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2866                 adapter->use_large_llq_hdr = bool_value;
2867
2868         return 0;
2869 }
2870
2871 static int ena_parse_devargs(struct ena_adapter *adapter,
2872                              struct rte_devargs *devargs)
2873 {
2874         static const char * const allowed_args[] = {
2875                 ENA_DEVARG_LARGE_LLQ_HDR,
2876         };
2877         struct rte_kvargs *kvlist;
2878         int rc;
2879
2880         if (devargs == NULL)
2881                 return 0;
2882
2883         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2884         if (kvlist == NULL) {
2885                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2886                         devargs->args);
2887                 return -EINVAL;
2888         }
2889
2890         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2891                 ena_process_bool_devarg, adapter);
2892
2893         rte_kvargs_free(kvlist);
2894
2895         return rc;
2896 }
2897
2898 /*********************************************************************
2899  *  PMD configuration
2900  *********************************************************************/
2901 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2902         struct rte_pci_device *pci_dev)
2903 {
2904         return rte_eth_dev_pci_generic_probe(pci_dev,
2905                 sizeof(struct ena_adapter), eth_ena_dev_init);
2906 }
2907
2908 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2909 {
2910         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2911 }
2912
2913 static struct rte_pci_driver rte_ena_pmd = {
2914         .id_table = pci_id_ena_map,
2915         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2916                      RTE_PCI_DRV_WC_ACTIVATE,
2917         .probe = eth_ena_pci_probe,
2918         .remove = eth_ena_pci_remove,
2919 };
2920
2921 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2922 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2923 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2924 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2925 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE);
2926 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE);
2927 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2928 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE);
2929 #endif
2930 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2931 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE);
2932 #endif
2933 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2934 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE);
2935 #endif
2936 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2937 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE);
2938 #endif
2939
2940 /******************************************************************************
2941  ******************************** AENQ Handlers *******************************
2942  *****************************************************************************/
2943 static void ena_update_on_link_change(void *adapter_data,
2944                                       struct ena_admin_aenq_entry *aenq_e)
2945 {
2946         struct rte_eth_dev *eth_dev;
2947         struct ena_adapter *adapter;
2948         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2949         uint32_t status;
2950
2951         adapter = adapter_data;
2952         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2953         eth_dev = adapter->rte_dev;
2954
2955         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2956         adapter->link_status = status;
2957
2958         ena_link_update(eth_dev, 0);
2959         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2960 }
2961
2962 static void ena_notification(void *data,
2963                              struct ena_admin_aenq_entry *aenq_e)
2964 {
2965         struct ena_adapter *adapter = data;
2966         struct ena_admin_ena_hw_hints *hints;
2967
2968         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2969                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2970                         aenq_e->aenq_common_desc.group,
2971                         ENA_ADMIN_NOTIFICATION);
2972
2973         switch (aenq_e->aenq_common_desc.syndrom) {
2974         case ENA_ADMIN_UPDATE_HINTS:
2975                 hints = (struct ena_admin_ena_hw_hints *)
2976                         (&aenq_e->inline_data_w4);
2977                 ena_update_hints(adapter, hints);
2978                 break;
2979         default:
2980                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2981                         aenq_e->aenq_common_desc.syndrom);
2982         }
2983 }
2984
2985 static void ena_keep_alive(void *adapter_data,
2986                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2987 {
2988         struct ena_adapter *adapter = adapter_data;
2989         struct ena_admin_aenq_keep_alive_desc *desc;
2990         uint64_t rx_drops;
2991         uint64_t tx_drops;
2992
2993         adapter->timestamp_wd = rte_get_timer_cycles();
2994
2995         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2996         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2997         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2998
2999         adapter->drv_stats->rx_drops = rx_drops;
3000         adapter->dev_stats.tx_drops = tx_drops;
3001 }
3002
3003 /**
3004  * This handler will called for unknown event group or unimplemented handlers
3005  **/
3006 static void unimplemented_aenq_handler(__rte_unused void *data,
3007                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3008 {
3009         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3010                           "unimplemented handler\n");
3011 }
3012
3013 static struct ena_aenq_handlers aenq_handlers = {
3014         .handlers = {
3015                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3016                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3017                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3018         },
3019         .unimplemented_handler = unimplemented_aenq_handler
3020 };