drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16
  17 #include "ena_ethdev.h"
  18 #include "ena_logs.h"
  19 #include "ena_platform.h"
  20 #include "ena_com.h"
  21 #include "ena_eth_com.h"
  22
  23 #include <ena_common_defs.h>
  24 #include <ena_regs_defs.h>
  25 #include <ena_admin_defs.h>
  26 #include <ena_eth_io_defs.h>
  27
  28 #define DRV_MODULE_VER_MAJOR    2
  29 #define DRV_MODULE_VER_MINOR    0
  30 #define DRV_MODULE_VER_SUBMINOR 3
  31
  32 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  33 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  34 /*reverse version of ENA_IO_RXQ_IDX*/
  35 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  36
  37 /* While processing submitted and completed descriptors (rx and tx path
  38  * respectively) in a loop it is desired to:
  39  *  - perform batch submissions while populating sumbissmion queue
  40  *  - avoid blocking transmission of other packets during cleanup phase
  41  * Hence the utilization ratio of 1/8 of a queue size.
  42  */
  43 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  44
  45 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  46 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  47
  48 #define GET_L4_HDR_LEN(mbuf)                                    \
  49         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  50                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  51
  52 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  53 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  54 #define ENA_HASH_KEY_SIZE       40
  55 #define ETH_GSTRING_LEN 32
  56
  57 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  58
  59 #define ENA_MIN_RING_DESC       128
  60
  61 enum ethtool_stringset {
  62         ETH_SS_TEST             = 0,
  63         ETH_SS_STATS,
  64 };
  65
  66 struct ena_stats {
  67         char name[ETH_GSTRING_LEN];
  68         int stat_offset;
  69 };
  70
  71 #define ENA_STAT_ENTRY(stat, stat_type) { \
  72         .name = #stat, \
  73         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  74 }
  75
  76 #define ENA_STAT_RX_ENTRY(stat) \
  77         ENA_STAT_ENTRY(stat, rx)
  78
  79 #define ENA_STAT_TX_ENTRY(stat) \
  80         ENA_STAT_ENTRY(stat, tx)
  81
  82 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  83         ENA_STAT_ENTRY(stat, dev)
  84
  85 #define ENA_MAX_RING_SIZE_RX 8192
  86 #define ENA_MAX_RING_SIZE_TX 1024
  87
  88 /*
  89  * Each rte_memzone should have unique name.
  90  * To satisfy it, count number of allocation and add it to name.
  91  */
  92 uint32_t ena_alloc_cnt;
  93
  94 static const struct ena_stats ena_stats_global_strings[] = {
  95         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  96         ENA_STAT_GLOBAL_ENTRY(dev_start),
  97         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  98 };
  99
 100 static const struct ena_stats ena_stats_tx_strings[] = {
 101         ENA_STAT_TX_ENTRY(cnt),
 102         ENA_STAT_TX_ENTRY(bytes),
 103         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 104         ENA_STAT_TX_ENTRY(linearize),
 105         ENA_STAT_TX_ENTRY(linearize_failed),
 106         ENA_STAT_TX_ENTRY(tx_poll),
 107         ENA_STAT_TX_ENTRY(doorbells),
 108         ENA_STAT_TX_ENTRY(bad_req_id),
 109         ENA_STAT_TX_ENTRY(available_desc),
 110 };
 111
 112 static const struct ena_stats ena_stats_rx_strings[] = {
 113         ENA_STAT_RX_ENTRY(cnt),
 114         ENA_STAT_RX_ENTRY(bytes),
 115         ENA_STAT_RX_ENTRY(refill_partial),
 116         ENA_STAT_RX_ENTRY(bad_csum),
 117         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 118         ENA_STAT_RX_ENTRY(bad_desc_num),
 119         ENA_STAT_RX_ENTRY(bad_req_id),
 120 };
 121
 122 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 123 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 124 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 125
 126 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 127                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 128                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 129                         DEV_TX_OFFLOAD_TCP_TSO)
 130 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 131                        PKT_TX_IP_CKSUM |\
 132                        PKT_TX_TCP_SEG)
 133
 134 /** Vendor ID used by Amazon devices */
 135 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 136 /** Amazon devices */
 137 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 138 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 139
 140 #define ENA_TX_OFFLOAD_MASK     (\
 141         PKT_TX_L4_MASK |         \
 142         PKT_TX_IPV6 |            \
 143         PKT_TX_IPV4 |            \
 144         PKT_TX_IP_CKSUM |        \
 145         PKT_TX_TCP_SEG)
 146
 147 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 148         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 149
 150 int ena_logtype_init;
 151 int ena_logtype_driver;
 152
 153 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 154 int ena_logtype_rx;
 155 #endif
 156 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 157 int ena_logtype_tx;
 158 #endif
 159 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 160 int ena_logtype_tx_free;
 161 #endif
 162 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 163 int ena_logtype_com;
 164 #endif
 165
 166 static const struct rte_pci_id pci_id_ena_map[] = {
 167         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 168         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 169         { .device_id = 0 },
 170 };
 171
 172 static struct ena_aenq_handlers aenq_handlers;
 173
 174 static int ena_device_init(struct ena_com_dev *ena_dev,
 175                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 176                            bool *wd_state);
 177 static int ena_dev_configure(struct rte_eth_dev *dev);
 178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 179                                   uint16_t nb_pkts);
 180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                 uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 190                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 192 static void ena_init_rings(struct ena_adapter *adapter);
 193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 194 static int ena_start(struct rte_eth_dev *dev);
 195 static void ena_stop(struct rte_eth_dev *dev);
 196 static void ena_close(struct rte_eth_dev *dev);
 197 static int ena_dev_reset(struct rte_eth_dev *dev);
 198 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 199 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 200 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 201 static void ena_rx_queue_release(void *queue);
 202 static void ena_tx_queue_release(void *queue);
 203 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 204 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 205 static int ena_link_update(struct rte_eth_dev *dev,
 206                            int wait_to_complete);
 207 static int ena_create_io_queue(struct ena_ring *ring);
 208 static void ena_queue_stop(struct ena_ring *ring);
 209 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 210                               enum ena_ring_type ring_type);
 211 static int ena_queue_start(struct ena_ring *ring);
 212 static int ena_queue_start_all(struct rte_eth_dev *dev,
 213                                enum ena_ring_type ring_type);
 214 static void ena_stats_restart(struct rte_eth_dev *dev);
 215 static int ena_infos_get(struct rte_eth_dev *dev,
 216                          struct rte_eth_dev_info *dev_info);
 217 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 218                                struct rte_eth_rss_reta_entry64 *reta_conf,
 219                                uint16_t reta_size);
 220 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 221                               struct rte_eth_rss_reta_entry64 *reta_conf,
 222                               uint16_t reta_size);
 223 static void ena_interrupt_handler_rte(void *cb_arg);
 224 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 225 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 226 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 227 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 228                                 struct rte_eth_xstat_name *xstats_names,
 229                                 unsigned int n);
 230 static int ena_xstats_get(struct rte_eth_dev *dev,
 231                           struct rte_eth_xstat *stats,
 232                           unsigned int n);
 233 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 234                                 const uint64_t *ids,
 235                                 uint64_t *values,
 236                                 unsigned int n);
 237
 238 static const struct eth_dev_ops ena_dev_ops = {
 239         .dev_configure        = ena_dev_configure,
 240         .dev_infos_get        = ena_infos_get,
 241         .rx_queue_setup       = ena_rx_queue_setup,
 242         .tx_queue_setup       = ena_tx_queue_setup,
 243         .dev_start            = ena_start,
 244         .dev_stop             = ena_stop,
 245         .link_update          = ena_link_update,
 246         .stats_get            = ena_stats_get,
 247         .xstats_get_names     = ena_xstats_get_names,
 248         .xstats_get           = ena_xstats_get,
 249         .xstats_get_by_id     = ena_xstats_get_by_id,
 250         .mtu_set              = ena_mtu_set,
 251         .rx_queue_release     = ena_rx_queue_release,
 252         .tx_queue_release     = ena_tx_queue_release,
 253         .dev_close            = ena_close,
 254         .dev_reset            = ena_dev_reset,
 255         .reta_update          = ena_rss_reta_update,
 256         .reta_query           = ena_rss_reta_query,
 257 };
 258
 259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 260                                        struct ena_com_rx_ctx *ena_rx_ctx)
 261 {
 262         uint64_t ol_flags = 0;
 263         uint32_t packet_type = 0;
 264
 265         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 266                 packet_type |= RTE_PTYPE_L4_TCP;
 267         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 268                 packet_type |= RTE_PTYPE_L4_UDP;
 269
 270         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 271                 packet_type |= RTE_PTYPE_L3_IPV4;
 272         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 273                 packet_type |= RTE_PTYPE_L3_IPV6;
 274
 275         if (!ena_rx_ctx->l4_csum_checked)
 276                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 277         else
 278                 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
 279                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 280                 else
 281                         ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 282
 283         if (unlikely(ena_rx_ctx->l3_csum_err))
 284                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 285
 286         mbuf->ol_flags = ol_flags;
 287         mbuf->packet_type = packet_type;
 288 }
 289
 290 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 291                                        struct ena_com_tx_ctx *ena_tx_ctx,
 292                                        uint64_t queue_offloads)
 293 {
 294         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 295
 296         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 297             (queue_offloads & QUEUE_OFFLOADS)) {
 298                 /* check if TSO is required */
 299                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 300                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 301                         ena_tx_ctx->tso_enable = true;
 302
 303                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 304                 }
 305
 306                 /* check if L3 checksum is needed */
 307                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 308                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 309                         ena_tx_ctx->l3_csum_enable = true;
 310
 311                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 312                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 313                 } else {
 314                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 315
 316                         /* set don't fragment (DF) flag */
 317                         if (mbuf->packet_type &
 318                                 (RTE_PTYPE_L4_NONFRAG
 319                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 320                                 ena_tx_ctx->df = true;
 321                 }
 322
 323                 /* check if L4 checksum is needed */
 324                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 325                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 326                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 327                         ena_tx_ctx->l4_csum_enable = true;
 328                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 329                                 PKT_TX_UDP_CKSUM) &&
 330                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 331                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 332                         ena_tx_ctx->l4_csum_enable = true;
 333                 } else {
 334                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 335                         ena_tx_ctx->l4_csum_enable = false;
 336                 }
 337
 338                 ena_meta->mss = mbuf->tso_segsz;
 339                 ena_meta->l3_hdr_len = mbuf->l3_len;
 340                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 341
 342                 ena_tx_ctx->meta_valid = true;
 343         } else {
 344                 ena_tx_ctx->meta_valid = false;
 345         }
 346 }
 347
 348 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 349 {
 350         if (likely(req_id < rx_ring->ring_size))
 351                 return 0;
 352
 353         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 354
 355         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 356         rx_ring->adapter->trigger_reset = true;
 357         ++rx_ring->rx_stats.bad_req_id;
 358
 359         return -EFAULT;
 360 }
 361
 362 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 363 {
 364         struct ena_tx_buffer *tx_info = NULL;
 365
 366         if (likely(req_id < tx_ring->ring_size)) {
 367                 tx_info = &tx_ring->tx_buffer_info[req_id];
 368                 if (likely(tx_info->mbuf))
 369                         return 0;
 370         }
 371
 372         if (tx_info)
 373                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 374         else
 375                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 376
 377         /* Trigger device reset */
 378         ++tx_ring->tx_stats.bad_req_id;
 379         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 380         tx_ring->adapter->trigger_reset = true;
 381         return -EFAULT;
 382 }
 383
 384 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 385 {
 386         struct ena_admin_host_info *host_info;
 387         int rc;
 388
 389         /* Allocate only the host info */
 390         rc = ena_com_allocate_host_info(ena_dev);
 391         if (rc) {
 392                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 393                 return;
 394         }
 395
 396         host_info = ena_dev->host_attr.host_info;
 397
 398         host_info->os_type = ENA_ADMIN_OS_DPDK;
 399         host_info->kernel_ver = RTE_VERSION;
 400         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 401                 sizeof(host_info->kernel_ver_str));
 402         host_info->os_dist = RTE_VERSION;
 403         strlcpy((char *)host_info->os_dist_str, rte_version(),
 404                 sizeof(host_info->os_dist_str));
 405         host_info->driver_version =
 406                 (DRV_MODULE_VER_MAJOR) |
 407                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 408                 (DRV_MODULE_VER_SUBMINOR <<
 409                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 410         host_info->num_cpus = rte_lcore_count();
 411
 412         host_info->driver_supported_features =
 413                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 414
 415         rc = ena_com_set_host_attributes(ena_dev);
 416         if (rc) {
 417                 if (rc == -ENA_COM_UNSUPPORTED)
 418                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 419                 else
 420                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 421
 422                 goto err;
 423         }
 424
 425         return;
 426
 427 err:
 428         ena_com_delete_host_info(ena_dev);
 429 }
 430
 431 /* This function calculates the number of xstats based on the current config */
 432 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 433 {
 434         return ENA_STATS_ARRAY_GLOBAL +
 435                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 436                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 437 }
 438
 439 static void ena_config_debug_area(struct ena_adapter *adapter)
 440 {
 441         u32 debug_area_size;
 442         int rc, ss_count;
 443
 444         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 445
 446         /* allocate 32 bytes for each string and 64bit for the value */
 447         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 448
 449         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 450         if (rc) {
 451                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 452                 return;
 453         }
 454
 455         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 456         if (rc) {
 457                 if (rc == -ENA_COM_UNSUPPORTED)
 458                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 459                 else
 460                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 461
 462                 goto err;
 463         }
 464
 465         return;
 466 err:
 467         ena_com_delete_debug_area(&adapter->ena_dev);
 468 }
 469
 470 static void ena_close(struct rte_eth_dev *dev)
 471 {
 472         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 473         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 474         struct ena_adapter *adapter = dev->data->dev_private;
 475
 476         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 477                 ena_stop(dev);
 478         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 479
 480         ena_rx_queue_release_all(dev);
 481         ena_tx_queue_release_all(dev);
 482
 483         rte_free(adapter->drv_stats);
 484         adapter->drv_stats = NULL;
 485
 486         rte_intr_disable(intr_handle);
 487         rte_intr_callback_unregister(intr_handle,
 488                                      ena_interrupt_handler_rte,
 489                                      adapter);
 490
 491         /*
 492          * MAC is not allocated dynamically. Setting NULL should prevent from
 493          * release of the resource in the rte_eth_dev_release_port().
 494          */
 495         dev->data->mac_addrs = NULL;
 496 }
 497
 498 static int
 499 ena_dev_reset(struct rte_eth_dev *dev)
 500 {
 501         int rc = 0;
 502
 503         ena_destroy_device(dev);
 504         rc = eth_ena_dev_init(dev);
 505         if (rc)
 506                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 507
 508         return rc;
 509 }
 510
 511 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 512                                struct rte_eth_rss_reta_entry64 *reta_conf,
 513                                uint16_t reta_size)
 514 {
 515         struct ena_adapter *adapter = dev->data->dev_private;
 516         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 517         int rc, i;
 518         u16 entry_value;
 519         int conf_idx;
 520         int idx;
 521
 522         if ((reta_size == 0) || (reta_conf == NULL))
 523                 return -EINVAL;
 524
 525         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 526                 PMD_DRV_LOG(WARNING,
 527                         "indirection table %d is bigger than supported (%d)\n",
 528                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 529                 return -EINVAL;
 530         }
 531
 532         for (i = 0 ; i < reta_size ; i++) {
 533                 /* each reta_conf is for 64 entries.
 534                  * to support 128 we use 2 conf of 64
 535                  */
 536                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 537                 idx = i % RTE_RETA_GROUP_SIZE;
 538                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 539                         entry_value =
 540                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 541
 542                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 543                                                                i,
 544                                                                entry_value);
 545                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 546                                 PMD_DRV_LOG(ERR,
 547                                         "Cannot fill indirect table\n");
 548                                 return rc;
 549                         }
 550                 }
 551         }
 552
 553         rc = ena_com_indirect_table_set(ena_dev);
 554         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 555                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 556                 return rc;
 557         }
 558
 559         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 560                 __func__, reta_size, adapter->rte_dev->data->port_id);
 561
 562         return 0;
 563 }
 564
 565 /* Query redirection table. */
 566 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 567                               struct rte_eth_rss_reta_entry64 *reta_conf,
 568                               uint16_t reta_size)
 569 {
 570         struct ena_adapter *adapter = dev->data->dev_private;
 571         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 572         int rc;
 573         int i;
 574         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 575         int reta_conf_idx;
 576         int reta_idx;
 577
 578         if (reta_size == 0 || reta_conf == NULL ||
 579             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 580                 return -EINVAL;
 581
 582         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 583         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 584                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 585                 return -ENOTSUP;
 586         }
 587
 588         for (i = 0 ; i < reta_size ; i++) {
 589                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 590                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 591                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 592                         reta_conf[reta_conf_idx].reta[reta_idx] =
 593                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int ena_rss_init_default(struct ena_adapter *adapter)
 600 {
 601         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 602         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 603         int rc, i;
 604         u32 val;
 605
 606         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 607         if (unlikely(rc)) {
 608                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 609                 goto err_rss_init;
 610         }
 611
 612         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 613                 val = i % nb_rx_queues;
 614                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 615                                                        ENA_IO_RXQ_IDX(val));
 616                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 617                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 618                         goto err_fill_indir;
 619                 }
 620         }
 621
 622         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 623                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 624         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 625                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 626                 goto err_fill_indir;
 627         }
 628
 629         rc = ena_com_set_default_hash_ctrl(ena_dev);
 630         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 631                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 632                 goto err_fill_indir;
 633         }
 634
 635         rc = ena_com_indirect_table_set(ena_dev);
 636         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 637                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 638                 goto err_fill_indir;
 639         }
 640         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 641                 adapter->rte_dev->data->port_id);
 642
 643         return 0;
 644
 645 err_fill_indir:
 646         ena_com_rss_destroy(ena_dev);
 647 err_rss_init:
 648
 649         return rc;
 650 }
 651
 652 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 653 {
 654         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 655         int nb_queues = dev->data->nb_rx_queues;
 656         int i;
 657
 658         for (i = 0; i < nb_queues; i++)
 659                 ena_rx_queue_release(queues[i]);
 660 }
 661
 662 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 663 {
 664         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 665         int nb_queues = dev->data->nb_tx_queues;
 666         int i;
 667
 668         for (i = 0; i < nb_queues; i++)
 669                 ena_tx_queue_release(queues[i]);
 670 }
 671
 672 static void ena_rx_queue_release(void *queue)
 673 {
 674         struct ena_ring *ring = (struct ena_ring *)queue;
 675
 676         /* Free ring resources */
 677         if (ring->rx_buffer_info)
 678                 rte_free(ring->rx_buffer_info);
 679         ring->rx_buffer_info = NULL;
 680
 681         if (ring->rx_refill_buffer)
 682                 rte_free(ring->rx_refill_buffer);
 683         ring->rx_refill_buffer = NULL;
 684
 685         if (ring->empty_rx_reqs)
 686                 rte_free(ring->empty_rx_reqs);
 687         ring->empty_rx_reqs = NULL;
 688
 689         ring->configured = 0;
 690
 691         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 692                 ring->port_id, ring->id);
 693 }
 694
 695 static void ena_tx_queue_release(void *queue)
 696 {
 697         struct ena_ring *ring = (struct ena_ring *)queue;
 698
 699         /* Free ring resources */
 700         if (ring->push_buf_intermediate_buf)
 701                 rte_free(ring->push_buf_intermediate_buf);
 702
 703         if (ring->tx_buffer_info)
 704                 rte_free(ring->tx_buffer_info);
 705
 706         if (ring->empty_tx_reqs)
 707                 rte_free(ring->empty_tx_reqs);
 708
 709         ring->empty_tx_reqs = NULL;
 710         ring->tx_buffer_info = NULL;
 711         ring->push_buf_intermediate_buf = NULL;
 712
 713         ring->configured = 0;
 714
 715         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 716                 ring->port_id, ring->id);
 717 }
 718
 719 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 720 {
 721         unsigned int i;
 722
 723         for (i = 0; i < ring->ring_size; ++i)
 724                 if (ring->rx_buffer_info[i]) {
 725                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 726                         ring->rx_buffer_info[i] = NULL;
 727                 }
 728 }
 729
 730 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 731 {
 732         unsigned int i;
 733
 734         for (i = 0; i < ring->ring_size; ++i) {
 735                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 736
 737                 if (tx_buf->mbuf)
 738                         rte_pktmbuf_free(tx_buf->mbuf);
 739         }
 740 }
 741
 742 static int ena_link_update(struct rte_eth_dev *dev,
 743                            __rte_unused int wait_to_complete)
 744 {
 745         struct rte_eth_link *link = &dev->data->dev_link;
 746         struct ena_adapter *adapter = dev->data->dev_private;
 747
 748         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 749         link->link_speed = ETH_SPEED_NUM_NONE;
 750         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 751
 752         return 0;
 753 }
 754
 755 static int ena_queue_start_all(struct rte_eth_dev *dev,
 756                                enum ena_ring_type ring_type)
 757 {
 758         struct ena_adapter *adapter = dev->data->dev_private;
 759         struct ena_ring *queues = NULL;
 760         int nb_queues;
 761         int i = 0;
 762         int rc = 0;
 763
 764         if (ring_type == ENA_RING_TYPE_RX) {
 765                 queues = adapter->rx_ring;
 766                 nb_queues = dev->data->nb_rx_queues;
 767         } else {
 768                 queues = adapter->tx_ring;
 769                 nb_queues = dev->data->nb_tx_queues;
 770         }
 771         for (i = 0; i < nb_queues; i++) {
 772                 if (queues[i].configured) {
 773                         if (ring_type == ENA_RING_TYPE_RX) {
 774                                 ena_assert_msg(
 775                                         dev->data->rx_queues[i] == &queues[i],
 776                                         "Inconsistent state of rx queues\n");
 777                         } else {
 778                                 ena_assert_msg(
 779                                         dev->data->tx_queues[i] == &queues[i],
 780                                         "Inconsistent state of tx queues\n");
 781                         }
 782
 783                         rc = ena_queue_start(&queues[i]);
 784
 785                         if (rc) {
 786                                 PMD_INIT_LOG(ERR,
 787                                              "failed to start queue %d type(%d)",
 788                                              i, ring_type);
 789                                 goto err;
 790                         }
 791                 }
 792         }
 793
 794         return 0;
 795
 796 err:
 797         while (i--)
 798                 if (queues[i].configured)
 799                         ena_queue_stop(&queues[i]);
 800
 801         return rc;
 802 }
 803
 804 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 805 {
 806         uint32_t max_frame_len = adapter->max_mtu;
 807
 808         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 809             DEV_RX_OFFLOAD_JUMBO_FRAME)
 810                 max_frame_len =
 811                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 812
 813         return max_frame_len;
 814 }
 815
 816 static int ena_check_valid_conf(struct ena_adapter *adapter)
 817 {
 818         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 819
 820         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 821                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 822                                   "max mtu: %d, min mtu: %d",
 823                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 824                 return ENA_COM_UNSUPPORTED;
 825         }
 826
 827         return 0;
 828 }
 829
 830 static int
 831 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 832 {
 833         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 834         struct ena_com_dev *ena_dev = ctx->ena_dev;
 835         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 836         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 837
 838         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 839                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 840                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 841                 rx_queue_size = RTE_MIN(rx_queue_size,
 842                         max_queue_ext->max_rx_cq_depth);
 843                 rx_queue_size = RTE_MIN(rx_queue_size,
 844                         max_queue_ext->max_rx_sq_depth);
 845                 tx_queue_size = RTE_MIN(tx_queue_size,
 846                         max_queue_ext->max_tx_cq_depth);
 847
 848                 if (ena_dev->tx_mem_queue_type ==
 849                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 850                         tx_queue_size = RTE_MIN(tx_queue_size,
 851                                 llq->max_llq_depth);
 852                 } else {
 853                         tx_queue_size = RTE_MIN(tx_queue_size,
 854                                 max_queue_ext->max_tx_sq_depth);
 855                 }
 856
 857                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 858                         max_queue_ext->max_per_packet_rx_descs);
 859                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 860                         max_queue_ext->max_per_packet_tx_descs);
 861         } else {
 862                 struct ena_admin_queue_feature_desc *max_queues =
 863                         &ctx->get_feat_ctx->max_queues;
 864                 rx_queue_size = RTE_MIN(rx_queue_size,
 865                         max_queues->max_cq_depth);
 866                 rx_queue_size = RTE_MIN(rx_queue_size,
 867                         max_queues->max_sq_depth);
 868                 tx_queue_size = RTE_MIN(tx_queue_size,
 869                         max_queues->max_cq_depth);
 870
 871                 if (ena_dev->tx_mem_queue_type ==
 872                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 873                         tx_queue_size = RTE_MIN(tx_queue_size,
 874                                 llq->max_llq_depth);
 875                 } else {
 876                         tx_queue_size = RTE_MIN(tx_queue_size,
 877                                 max_queues->max_sq_depth);
 878                 }
 879
 880                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 881                         max_queues->max_packet_tx_descs);
 882                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 883                         max_queues->max_packet_rx_descs);
 884         }
 885
 886         /* Round down to the nearest power of 2 */
 887         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 888         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 889
 890         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 891                 PMD_INIT_LOG(ERR, "Invalid queue size");
 892                 return -EFAULT;
 893         }
 894
 895         ctx->rx_queue_size = rx_queue_size;
 896         ctx->tx_queue_size = tx_queue_size;
 897
 898         return 0;
 899 }
 900
 901 static void ena_stats_restart(struct rte_eth_dev *dev)
 902 {
 903         struct ena_adapter *adapter = dev->data->dev_private;
 904
 905         rte_atomic64_init(&adapter->drv_stats->ierrors);
 906         rte_atomic64_init(&adapter->drv_stats->oerrors);
 907         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 908         rte_atomic64_init(&adapter->drv_stats->rx_drops);
 909 }
 910
 911 static int ena_stats_get(struct rte_eth_dev *dev,
 912                           struct rte_eth_stats *stats)
 913 {
 914         struct ena_admin_basic_stats ena_stats;
 915         struct ena_adapter *adapter = dev->data->dev_private;
 916         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 917         int rc;
 918         int i;
 919         int max_rings_stats;
 920
 921         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 922                 return -ENOTSUP;
 923
 924         memset(&ena_stats, 0, sizeof(ena_stats));
 925         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 926         if (unlikely(rc)) {
 927                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 928                 return rc;
 929         }
 930
 931         /* Set of basic statistics from ENA */
 932         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 933                                           ena_stats.rx_pkts_low);
 934         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 935                                           ena_stats.tx_pkts_low);
 936         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 937                                         ena_stats.rx_bytes_low);
 938         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 939                                         ena_stats.tx_bytes_low);
 940
 941         /* Driver related stats */
 942         stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops);
 943         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 944         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 945         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 946
 947         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 948                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 949         for (i = 0; i < max_rings_stats; ++i) {
 950                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 951
 952                 stats->q_ibytes[i] = rx_stats->bytes;
 953                 stats->q_ipackets[i] = rx_stats->cnt;
 954                 stats->q_errors[i] = rx_stats->bad_desc_num +
 955                         rx_stats->bad_req_id;
 956         }
 957
 958         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 959                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 960         for (i = 0; i < max_rings_stats; ++i) {
 961                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 962
 963                 stats->q_obytes[i] = tx_stats->bytes;
 964                 stats->q_opackets[i] = tx_stats->cnt;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 971 {
 972         struct ena_adapter *adapter;
 973         struct ena_com_dev *ena_dev;
 974         int rc = 0;
 975
 976         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 977         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 978         adapter = dev->data->dev_private;
 979
 980         ena_dev = &adapter->ena_dev;
 981         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 982
 983         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
 984                 PMD_DRV_LOG(ERR,
 985                         "Invalid MTU setting. new_mtu: %d "
 986                         "max mtu: %d min mtu: %d\n",
 987                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
 988                 return -EINVAL;
 989         }
 990
 991         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 992         if (rc)
 993                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 994         else
 995                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
 996
 997         return rc;
 998 }
 999
1000 static int ena_start(struct rte_eth_dev *dev)
1001 {
1002         struct ena_adapter *adapter = dev->data->dev_private;
1003         uint64_t ticks;
1004         int rc = 0;
1005
1006         rc = ena_check_valid_conf(adapter);
1007         if (rc)
1008                 return rc;
1009
1010         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1011         if (rc)
1012                 return rc;
1013
1014         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1015         if (rc)
1016                 goto err_start_tx;
1017
1018         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1019             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1020                 rc = ena_rss_init_default(adapter);
1021                 if (rc)
1022                         goto err_rss_init;
1023         }
1024
1025         ena_stats_restart(dev);
1026
1027         adapter->timestamp_wd = rte_get_timer_cycles();
1028         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1029
1030         ticks = rte_get_timer_hz();
1031         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1032                         ena_timer_wd_callback, adapter);
1033
1034         ++adapter->dev_stats.dev_start;
1035         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1036
1037         return 0;
1038
1039 err_rss_init:
1040         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1041 err_start_tx:
1042         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1043         return rc;
1044 }
1045
1046 static void ena_stop(struct rte_eth_dev *dev)
1047 {
1048         struct ena_adapter *adapter = dev->data->dev_private;
1049         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1050         int rc;
1051
1052         rte_timer_stop_sync(&adapter->timer_wd);
1053         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1054         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1055
1056         if (adapter->trigger_reset) {
1057                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1058                 if (rc)
1059                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1060         }
1061
1062         ++adapter->dev_stats.dev_stop;
1063         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1064 }
1065
1066 static int ena_create_io_queue(struct ena_ring *ring)
1067 {
1068         struct ena_adapter *adapter;
1069         struct ena_com_dev *ena_dev;
1070         struct ena_com_create_io_ctx ctx =
1071                 /* policy set to _HOST just to satisfy icc compiler */
1072                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1073                   0, 0, 0, 0, 0 };
1074         uint16_t ena_qid;
1075         unsigned int i;
1076         int rc;
1077
1078         adapter = ring->adapter;
1079         ena_dev = &adapter->ena_dev;
1080
1081         if (ring->type == ENA_RING_TYPE_TX) {
1082                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1083                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1084                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1085                 ctx.queue_size = adapter->tx_ring_size;
1086                 for (i = 0; i < ring->ring_size; i++)
1087                         ring->empty_tx_reqs[i] = i;
1088         } else {
1089                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1090                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1091                 ctx.queue_size = adapter->rx_ring_size;
1092                 for (i = 0; i < ring->ring_size; i++)
1093                         ring->empty_rx_reqs[i] = i;
1094         }
1095         ctx.qid = ena_qid;
1096         ctx.msix_vector = -1; /* interrupts not used */
1097         ctx.numa_node = ring->numa_socket_id;
1098
1099         rc = ena_com_create_io_queue(ena_dev, &ctx);
1100         if (rc) {
1101                 PMD_DRV_LOG(ERR,
1102                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1103                         ring->id, ena_qid, rc);
1104                 return rc;
1105         }
1106
1107         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1108                                      &ring->ena_com_io_sq,
1109                                      &ring->ena_com_io_cq);
1110         if (rc) {
1111                 PMD_DRV_LOG(ERR,
1112                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1113                         ring->id, rc);
1114                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1115                 return rc;
1116         }
1117
1118         if (ring->type == ENA_RING_TYPE_TX)
1119                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1120
1121         return 0;
1122 }
1123
1124 static void ena_queue_stop(struct ena_ring *ring)
1125 {
1126         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1127
1128         if (ring->type == ENA_RING_TYPE_RX) {
1129                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1130                 ena_rx_queue_release_bufs(ring);
1131         } else {
1132                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1133                 ena_tx_queue_release_bufs(ring);
1134         }
1135 }
1136
1137 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1138                               enum ena_ring_type ring_type)
1139 {
1140         struct ena_adapter *adapter = dev->data->dev_private;
1141         struct ena_ring *queues = NULL;
1142         uint16_t nb_queues, i;
1143
1144         if (ring_type == ENA_RING_TYPE_RX) {
1145                 queues = adapter->rx_ring;
1146                 nb_queues = dev->data->nb_rx_queues;
1147         } else {
1148                 queues = adapter->tx_ring;
1149                 nb_queues = dev->data->nb_tx_queues;
1150         }
1151
1152         for (i = 0; i < nb_queues; ++i)
1153                 if (queues[i].configured)
1154                         ena_queue_stop(&queues[i]);
1155 }
1156
1157 static int ena_queue_start(struct ena_ring *ring)
1158 {
1159         int rc, bufs_num;
1160
1161         ena_assert_msg(ring->configured == 1,
1162                        "Trying to start unconfigured queue\n");
1163
1164         rc = ena_create_io_queue(ring);
1165         if (rc) {
1166                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1167                 return rc;
1168         }
1169
1170         ring->next_to_clean = 0;
1171         ring->next_to_use = 0;
1172
1173         if (ring->type == ENA_RING_TYPE_TX) {
1174                 ring->tx_stats.available_desc =
1175                         ena_com_free_q_entries(ring->ena_com_io_sq);
1176                 return 0;
1177         }
1178
1179         bufs_num = ring->ring_size - 1;
1180         rc = ena_populate_rx_queue(ring, bufs_num);
1181         if (rc != bufs_num) {
1182                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1183                                          ENA_IO_RXQ_IDX(ring->id));
1184                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1185                 return ENA_COM_FAULT;
1186         }
1187
1188         return 0;
1189 }
1190
1191 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1192                               uint16_t queue_idx,
1193                               uint16_t nb_desc,
1194                               unsigned int socket_id,
1195                               const struct rte_eth_txconf *tx_conf)
1196 {
1197         struct ena_ring *txq = NULL;
1198         struct ena_adapter *adapter = dev->data->dev_private;
1199         unsigned int i;
1200
1201         txq = &adapter->tx_ring[queue_idx];
1202
1203         if (txq->configured) {
1204                 PMD_DRV_LOG(CRIT,
1205                         "API violation. Queue %d is already configured\n",
1206                         queue_idx);
1207                 return ENA_COM_FAULT;
1208         }
1209
1210         if (!rte_is_power_of_2(nb_desc)) {
1211                 PMD_DRV_LOG(ERR,
1212                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1213                         nb_desc);
1214                 return -EINVAL;
1215         }
1216
1217         if (nb_desc > adapter->tx_ring_size) {
1218                 PMD_DRV_LOG(ERR,
1219                         "Unsupported size of TX queue (max size: %d)\n",
1220                         adapter->tx_ring_size);
1221                 return -EINVAL;
1222         }
1223
1224         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1225                 nb_desc = adapter->tx_ring_size;
1226
1227         txq->port_id = dev->data->port_id;
1228         txq->next_to_clean = 0;
1229         txq->next_to_use = 0;
1230         txq->ring_size = nb_desc;
1231         txq->numa_socket_id = socket_id;
1232
1233         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1234                                           sizeof(struct ena_tx_buffer) *
1235                                           txq->ring_size,
1236                                           RTE_CACHE_LINE_SIZE);
1237         if (!txq->tx_buffer_info) {
1238                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1239                 return -ENOMEM;
1240         }
1241
1242         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1243                                          sizeof(u16) * txq->ring_size,
1244                                          RTE_CACHE_LINE_SIZE);
1245         if (!txq->empty_tx_reqs) {
1246                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1247                 rte_free(txq->tx_buffer_info);
1248                 return -ENOMEM;
1249         }
1250
1251         txq->push_buf_intermediate_buf =
1252                 rte_zmalloc("txq->push_buf_intermediate_buf",
1253                             txq->tx_max_header_size,
1254                             RTE_CACHE_LINE_SIZE);
1255         if (!txq->push_buf_intermediate_buf) {
1256                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1257                 rte_free(txq->tx_buffer_info);
1258                 rte_free(txq->empty_tx_reqs);
1259                 return -ENOMEM;
1260         }
1261
1262         for (i = 0; i < txq->ring_size; i++)
1263                 txq->empty_tx_reqs[i] = i;
1264
1265         if (tx_conf != NULL) {
1266                 txq->offloads =
1267                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1268         }
1269         /* Store pointer to this queue in upper layer */
1270         txq->configured = 1;
1271         dev->data->tx_queues[queue_idx] = txq;
1272
1273         return 0;
1274 }
1275
1276 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1277                               uint16_t queue_idx,
1278                               uint16_t nb_desc,
1279                               unsigned int socket_id,
1280                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1281                               struct rte_mempool *mp)
1282 {
1283         struct ena_adapter *adapter = dev->data->dev_private;
1284         struct ena_ring *rxq = NULL;
1285         int i;
1286
1287         rxq = &adapter->rx_ring[queue_idx];
1288         if (rxq->configured) {
1289                 PMD_DRV_LOG(CRIT,
1290                         "API violation. Queue %d is already configured\n",
1291                         queue_idx);
1292                 return ENA_COM_FAULT;
1293         }
1294
1295         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1296                 nb_desc = adapter->rx_ring_size;
1297
1298         if (!rte_is_power_of_2(nb_desc)) {
1299                 PMD_DRV_LOG(ERR,
1300                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1301                         nb_desc);
1302                 return -EINVAL;
1303         }
1304
1305         if (nb_desc > adapter->rx_ring_size) {
1306                 PMD_DRV_LOG(ERR,
1307                         "Unsupported size of RX queue (max size: %d)\n",
1308                         adapter->rx_ring_size);
1309                 return -EINVAL;
1310         }
1311
1312         rxq->port_id = dev->data->port_id;
1313         rxq->next_to_clean = 0;
1314         rxq->next_to_use = 0;
1315         rxq->ring_size = nb_desc;
1316         rxq->numa_socket_id = socket_id;
1317         rxq->mb_pool = mp;
1318
1319         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1320                                           sizeof(struct rte_mbuf *) * nb_desc,
1321                                           RTE_CACHE_LINE_SIZE);
1322         if (!rxq->rx_buffer_info) {
1323                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1324                 return -ENOMEM;
1325         }
1326
1327         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1328                                             sizeof(struct rte_mbuf *) * nb_desc,
1329                                             RTE_CACHE_LINE_SIZE);
1330
1331         if (!rxq->rx_refill_buffer) {
1332                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1333                 rte_free(rxq->rx_buffer_info);
1334                 rxq->rx_buffer_info = NULL;
1335                 return -ENOMEM;
1336         }
1337
1338         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1339                                          sizeof(uint16_t) * nb_desc,
1340                                          RTE_CACHE_LINE_SIZE);
1341         if (!rxq->empty_rx_reqs) {
1342                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1343                 rte_free(rxq->rx_buffer_info);
1344                 rxq->rx_buffer_info = NULL;
1345                 rte_free(rxq->rx_refill_buffer);
1346                 rxq->rx_refill_buffer = NULL;
1347                 return -ENOMEM;
1348         }
1349
1350         for (i = 0; i < nb_desc; i++)
1351                 rxq->empty_rx_reqs[i] = i;
1352
1353         /* Store pointer to this queue in upper layer */
1354         rxq->configured = 1;
1355         dev->data->rx_queues[queue_idx] = rxq;
1356
1357         return 0;
1358 }
1359
1360 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1361 {
1362         unsigned int i;
1363         int rc;
1364         uint16_t ring_size = rxq->ring_size;
1365         uint16_t ring_mask = ring_size - 1;
1366         uint16_t next_to_use = rxq->next_to_use;
1367         uint16_t in_use, req_id;
1368         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1369
1370         if (unlikely(!count))
1371                 return 0;
1372
1373         in_use = rxq->next_to_use - rxq->next_to_clean;
1374         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1375
1376         /* get resources for incoming packets */
1377         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1378         if (unlikely(rc < 0)) {
1379                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1380                 ++rxq->rx_stats.mbuf_alloc_fail;
1381                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1382                 return 0;
1383         }
1384
1385         for (i = 0; i < count; i++) {
1386                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1387                 struct rte_mbuf *mbuf = mbufs[i];
1388                 struct ena_com_buf ebuf;
1389
1390                 if (likely((i + 4) < count))
1391                         rte_prefetch0(mbufs[i + 4]);
1392
1393                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1394                 rc = validate_rx_req_id(rxq, req_id);
1395                 if (unlikely(rc < 0))
1396                         break;
1397                 rxq->rx_buffer_info[req_id] = mbuf;
1398
1399                 /* prepare physical address for DMA transaction */
1400                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1401                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1402                 /* pass resource to device */
1403                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1404                                                 &ebuf, req_id);
1405                 if (unlikely(rc)) {
1406                         PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1407                         rxq->rx_buffer_info[req_id] = NULL;
1408                         break;
1409                 }
1410                 next_to_use++;
1411         }
1412
1413         if (unlikely(i < count)) {
1414                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1415                         "buffers (from %d)\n", rxq->id, i, count);
1416                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1417                                      count - i);
1418                 ++rxq->rx_stats.refill_partial;
1419         }
1420
1421         /* When we submitted free recources to device... */
1422         if (likely(i > 0)) {
1423                 /* ...let HW know that it can fill buffers with data
1424                  *
1425                  * Add memory barrier to make sure the desc were written before
1426                  * issue a doorbell
1427                  */
1428                 rte_wmb();
1429                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1430
1431                 rxq->next_to_use = next_to_use;
1432         }
1433
1434         return i;
1435 }
1436
1437 static int ena_device_init(struct ena_com_dev *ena_dev,
1438                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1439                            bool *wd_state)
1440 {
1441         uint32_t aenq_groups;
1442         int rc;
1443         bool readless_supported;
1444
1445         /* Initialize mmio registers */
1446         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1447         if (rc) {
1448                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1449                 return rc;
1450         }
1451
1452         /* The PCIe configuration space revision id indicate if mmio reg
1453          * read is disabled.
1454          */
1455         readless_supported =
1456                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1457                                & ENA_MMIO_DISABLE_REG_READ);
1458         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1459
1460         /* reset device */
1461         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1462         if (rc) {
1463                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1464                 goto err_mmio_read_less;
1465         }
1466
1467         /* check FW version */
1468         rc = ena_com_validate_version(ena_dev);
1469         if (rc) {
1470                 PMD_DRV_LOG(ERR, "device version is too low\n");
1471                 goto err_mmio_read_less;
1472         }
1473
1474         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1475
1476         /* ENA device administration layer init */
1477         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1478         if (rc) {
1479                 PMD_DRV_LOG(ERR,
1480                         "cannot initialize ena admin queue with device\n");
1481                 goto err_mmio_read_less;
1482         }
1483
1484         /* To enable the msix interrupts the driver needs to know the number
1485          * of queues. So the driver uses polling mode to retrieve this
1486          * information.
1487          */
1488         ena_com_set_admin_polling_mode(ena_dev, true);
1489
1490         ena_config_host_info(ena_dev);
1491
1492         /* Get Device Attributes and features */
1493         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1494         if (rc) {
1495                 PMD_DRV_LOG(ERR,
1496                         "cannot get attribute for ena device rc= %d\n", rc);
1497                 goto err_admin_init;
1498         }
1499
1500         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1501                       BIT(ENA_ADMIN_NOTIFICATION) |
1502                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1503                       BIT(ENA_ADMIN_FATAL_ERROR) |
1504                       BIT(ENA_ADMIN_WARNING);
1505
1506         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1507         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1508         if (rc) {
1509                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1510                 goto err_admin_init;
1511         }
1512
1513         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1514
1515         return 0;
1516
1517 err_admin_init:
1518         ena_com_admin_destroy(ena_dev);
1519
1520 err_mmio_read_less:
1521         ena_com_mmio_reg_read_request_destroy(ena_dev);
1522
1523         return rc;
1524 }
1525
1526 static void ena_interrupt_handler_rte(void *cb_arg)
1527 {
1528         struct ena_adapter *adapter = cb_arg;
1529         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1530
1531         ena_com_admin_q_comp_intr_handler(ena_dev);
1532         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1533                 ena_com_aenq_intr_handler(ena_dev, adapter);
1534 }
1535
1536 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1537 {
1538         if (!adapter->wd_state)
1539                 return;
1540
1541         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1542                 return;
1543
1544         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1545             adapter->keep_alive_timeout)) {
1546                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1547                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1548                 adapter->trigger_reset = true;
1549                 ++adapter->dev_stats.wd_expired;
1550         }
1551 }
1552
1553 /* Check if admin queue is enabled */
1554 static void check_for_admin_com_state(struct ena_adapter *adapter)
1555 {
1556         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1557                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1558                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1559                 adapter->trigger_reset = true;
1560         }
1561 }
1562
1563 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1564                                   void *arg)
1565 {
1566         struct ena_adapter *adapter = arg;
1567         struct rte_eth_dev *dev = adapter->rte_dev;
1568
1569         check_for_missing_keep_alive(adapter);
1570         check_for_admin_com_state(adapter);
1571
1572         if (unlikely(adapter->trigger_reset)) {
1573                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1574                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1575                         NULL);
1576         }
1577 }
1578
1579 static inline void
1580 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1581 {
1582         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1583         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1584         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1585         llq_config->llq_num_decs_before_header =
1586                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1587         llq_config->llq_ring_entry_size_value = 128;
1588 }
1589
1590 static int
1591 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1592                                 struct ena_com_dev *ena_dev,
1593                                 struct ena_admin_feature_llq_desc *llq,
1594                                 struct ena_llq_configurations *llq_default_configurations)
1595 {
1596         int rc;
1597         u32 llq_feature_mask;
1598
1599         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1600         if (!(ena_dev->supported_features & llq_feature_mask)) {
1601                 PMD_DRV_LOG(INFO,
1602                         "LLQ is not supported. Fallback to host mode policy.\n");
1603                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1604                 return 0;
1605         }
1606
1607         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1608         if (unlikely(rc)) {
1609                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1610                         "Fallback to host mode policy.");
1611                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1612                 return 0;
1613         }
1614
1615         /* Nothing to config, exit */
1616         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1617                 return 0;
1618
1619         if (!adapter->dev_mem_base) {
1620                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1621                         "Fallback to host mode policy.\n.");
1622                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1623                 return 0;
1624         }
1625
1626         ena_dev->mem_bar = adapter->dev_mem_base;
1627
1628         return 0;
1629 }
1630
1631 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1632                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1633 {
1634         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1635
1636         /* Regular queues capabilities */
1637         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1638                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1639                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1640                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1641                                     max_queue_ext->max_rx_cq_num);
1642                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1643                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1644         } else {
1645                 struct ena_admin_queue_feature_desc *max_queues =
1646                         &get_feat_ctx->max_queues;
1647                 io_tx_sq_num = max_queues->max_sq_num;
1648                 io_tx_cq_num = max_queues->max_cq_num;
1649                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1650         }
1651
1652         /* In case of LLQ use the llq number in the get feature cmd */
1653         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1654                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1655
1656         io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1657         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1658         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1659
1660         if (unlikely(io_queue_num == 0)) {
1661                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1662                 return -EFAULT;
1663         }
1664
1665         return io_queue_num;
1666 }
1667
1668 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1669 {
1670         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1671         struct rte_pci_device *pci_dev;
1672         struct rte_intr_handle *intr_handle;
1673         struct ena_adapter *adapter = eth_dev->data->dev_private;
1674         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1675         struct ena_com_dev_get_features_ctx get_feat_ctx;
1676         struct ena_llq_configurations llq_config;
1677         const char *queue_type_str;
1678         int rc;
1679
1680         static int adapters_found;
1681         bool wd_state;
1682
1683         eth_dev->dev_ops = &ena_dev_ops;
1684         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1685         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1686         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1687
1688         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1689                 return 0;
1690
1691         memset(adapter, 0, sizeof(struct ena_adapter));
1692         ena_dev = &adapter->ena_dev;
1693
1694         adapter->rte_eth_dev_data = eth_dev->data;
1695         adapter->rte_dev = eth_dev;
1696
1697         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1698         adapter->pdev = pci_dev;
1699
1700         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1701                      pci_dev->addr.domain,
1702                      pci_dev->addr.bus,
1703                      pci_dev->addr.devid,
1704                      pci_dev->addr.function);
1705
1706         intr_handle = &pci_dev->intr_handle;
1707
1708         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1709         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1710
1711         if (!adapter->regs) {
1712                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1713                              ENA_REGS_BAR);
1714                 return -ENXIO;
1715         }
1716
1717         ena_dev->reg_bar = adapter->regs;
1718         ena_dev->dmadev = adapter->pdev;
1719
1720         adapter->id_number = adapters_found;
1721
1722         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1723                  adapter->id_number);
1724
1725         /* device specific initialization routine */
1726         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1727         if (rc) {
1728                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1729                 goto err;
1730         }
1731         adapter->wd_state = wd_state;
1732
1733         set_default_llq_configurations(&llq_config);
1734         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1735                                              &get_feat_ctx.llq, &llq_config);
1736         if (unlikely(rc)) {
1737                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1738                 return rc;
1739         }
1740
1741         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1742                 queue_type_str = "Regular";
1743         else
1744                 queue_type_str = "Low latency";
1745         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1746
1747         calc_queue_ctx.ena_dev = ena_dev;
1748         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1749         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1750                                                     &get_feat_ctx);
1751
1752         rc = ena_calc_queue_size(&calc_queue_ctx);
1753         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1754                 rc = -EFAULT;
1755                 goto err_device_destroy;
1756         }
1757
1758         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1759         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1760
1761         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1762         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1763
1764         /* prepare ring structures */
1765         ena_init_rings(adapter);
1766
1767         ena_config_debug_area(adapter);
1768
1769         /* Set max MTU for this device */
1770         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1771
1772         /* set device support for offloads */
1773         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1774                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1775         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1776                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1777         adapter->offloads.rx_csum_supported =
1778                 (get_feat_ctx.offload.rx_supported &
1779                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1780
1781         /* Copy MAC address and point DPDK to it */
1782         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1783         rte_ether_addr_copy((struct rte_ether_addr *)
1784                         get_feat_ctx.dev_attr.mac_addr,
1785                         (struct rte_ether_addr *)adapter->mac_addr);
1786
1787         /*
1788          * Pass the information to the rte_eth_dev_close() that it should also
1789          * release the private port resources.
1790          */
1791         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1792
1793         adapter->drv_stats = rte_zmalloc("adapter stats",
1794                                          sizeof(*adapter->drv_stats),
1795                                          RTE_CACHE_LINE_SIZE);
1796         if (!adapter->drv_stats) {
1797                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1798                 rc = -ENOMEM;
1799                 goto err_delete_debug_area;
1800         }
1801
1802         rte_intr_callback_register(intr_handle,
1803                                    ena_interrupt_handler_rte,
1804                                    adapter);
1805         rte_intr_enable(intr_handle);
1806         ena_com_set_admin_polling_mode(ena_dev, false);
1807         ena_com_admin_aenq_enable(ena_dev);
1808
1809         if (adapters_found == 0)
1810                 rte_timer_subsystem_init();
1811         rte_timer_init(&adapter->timer_wd);
1812
1813         adapters_found++;
1814         adapter->state = ENA_ADAPTER_STATE_INIT;
1815
1816         return 0;
1817
1818 err_delete_debug_area:
1819         ena_com_delete_debug_area(ena_dev);
1820
1821 err_device_destroy:
1822         ena_com_delete_host_info(ena_dev);
1823         ena_com_admin_destroy(ena_dev);
1824
1825 err:
1826         return rc;
1827 }
1828
1829 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1830 {
1831         struct ena_adapter *adapter = eth_dev->data->dev_private;
1832         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1833
1834         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1835                 return;
1836
1837         ena_com_set_admin_running_state(ena_dev, false);
1838
1839         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1840                 ena_close(eth_dev);
1841
1842         ena_com_delete_debug_area(ena_dev);
1843         ena_com_delete_host_info(ena_dev);
1844
1845         ena_com_abort_admin_commands(ena_dev);
1846         ena_com_wait_for_abort_completion(ena_dev);
1847         ena_com_admin_destroy(ena_dev);
1848         ena_com_mmio_reg_read_request_destroy(ena_dev);
1849
1850         adapter->state = ENA_ADAPTER_STATE_FREE;
1851 }
1852
1853 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1854 {
1855         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1856                 return 0;
1857
1858         ena_destroy_device(eth_dev);
1859
1860         eth_dev->dev_ops = NULL;
1861         eth_dev->rx_pkt_burst = NULL;
1862         eth_dev->tx_pkt_burst = NULL;
1863         eth_dev->tx_pkt_prepare = NULL;
1864
1865         return 0;
1866 }
1867
1868 static int ena_dev_configure(struct rte_eth_dev *dev)
1869 {
1870         struct ena_adapter *adapter = dev->data->dev_private;
1871
1872         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1873
1874         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1875         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1876         return 0;
1877 }
1878
1879 static void ena_init_rings(struct ena_adapter *adapter)
1880 {
1881         int i;
1882
1883         for (i = 0; i < adapter->num_queues; i++) {
1884                 struct ena_ring *ring = &adapter->tx_ring[i];
1885
1886                 ring->configured = 0;
1887                 ring->type = ENA_RING_TYPE_TX;
1888                 ring->adapter = adapter;
1889                 ring->id = i;
1890                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1891                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1892                 ring->sgl_size = adapter->max_tx_sgl_size;
1893         }
1894
1895         for (i = 0; i < adapter->num_queues; i++) {
1896                 struct ena_ring *ring = &adapter->rx_ring[i];
1897
1898                 ring->configured = 0;
1899                 ring->type = ENA_RING_TYPE_RX;
1900                 ring->adapter = adapter;
1901                 ring->id = i;
1902                 ring->sgl_size = adapter->max_rx_sgl_size;
1903         }
1904 }
1905
1906 static int ena_infos_get(struct rte_eth_dev *dev,
1907                           struct rte_eth_dev_info *dev_info)
1908 {
1909         struct ena_adapter *adapter;
1910         struct ena_com_dev *ena_dev;
1911         uint64_t rx_feat = 0, tx_feat = 0;
1912
1913         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1914         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1915         adapter = dev->data->dev_private;
1916
1917         ena_dev = &adapter->ena_dev;
1918         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1919
1920         dev_info->speed_capa =
1921                         ETH_LINK_SPEED_1G   |
1922                         ETH_LINK_SPEED_2_5G |
1923                         ETH_LINK_SPEED_5G   |
1924                         ETH_LINK_SPEED_10G  |
1925                         ETH_LINK_SPEED_25G  |
1926                         ETH_LINK_SPEED_40G  |
1927                         ETH_LINK_SPEED_50G  |
1928                         ETH_LINK_SPEED_100G;
1929
1930         /* Set Tx & Rx features available for device */
1931         if (adapter->offloads.tso4_supported)
1932                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1933
1934         if (adapter->offloads.tx_csum_supported)
1935                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1936                         DEV_TX_OFFLOAD_UDP_CKSUM |
1937                         DEV_TX_OFFLOAD_TCP_CKSUM;
1938
1939         if (adapter->offloads.rx_csum_supported)
1940                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1941                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1942                         DEV_RX_OFFLOAD_TCP_CKSUM;
1943
1944         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1945
1946         /* Inform framework about available features */
1947         dev_info->rx_offload_capa = rx_feat;
1948         dev_info->rx_queue_offload_capa = rx_feat;
1949         dev_info->tx_offload_capa = tx_feat;
1950         dev_info->tx_queue_offload_capa = tx_feat;
1951
1952         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1953                                            ETH_RSS_UDP;
1954
1955         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1956         dev_info->max_rx_pktlen  = adapter->max_mtu;
1957         dev_info->max_mac_addrs = 1;
1958
1959         dev_info->max_rx_queues = adapter->num_queues;
1960         dev_info->max_tx_queues = adapter->num_queues;
1961         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1962
1963         adapter->tx_supported_offloads = tx_feat;
1964         adapter->rx_supported_offloads = rx_feat;
1965
1966         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1967         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1968         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1969                                         adapter->max_rx_sgl_size);
1970         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1971                                         adapter->max_rx_sgl_size);
1972
1973         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1974         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1975         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1976                                         adapter->max_tx_sgl_size);
1977         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1978                                         adapter->max_tx_sgl_size);
1979
1980         return 0;
1981 }
1982
1983 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1984                                   uint16_t nb_pkts)
1985 {
1986         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1987         unsigned int ring_size = rx_ring->ring_size;
1988         unsigned int ring_mask = ring_size - 1;
1989         uint16_t next_to_clean = rx_ring->next_to_clean;
1990         uint16_t desc_in_use = 0;
1991         uint16_t req_id;
1992         unsigned int recv_idx = 0;
1993         struct rte_mbuf *mbuf = NULL;
1994         struct rte_mbuf *mbuf_head = NULL;
1995         struct rte_mbuf *mbuf_prev = NULL;
1996         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1997         unsigned int completed;
1998
1999         struct ena_com_rx_ctx ena_rx_ctx;
2000         int rc = 0;
2001
2002         /* Check adapter state */
2003         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2004                 PMD_DRV_LOG(ALERT,
2005                         "Trying to receive pkts while device is NOT running\n");
2006                 return 0;
2007         }
2008
2009         desc_in_use = rx_ring->next_to_use - next_to_clean;
2010         if (unlikely(nb_pkts > desc_in_use))
2011                 nb_pkts = desc_in_use;
2012
2013         for (completed = 0; completed < nb_pkts; completed++) {
2014                 int segments = 0;
2015
2016                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2017                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2018                 ena_rx_ctx.descs = 0;
2019                 ena_rx_ctx.pkt_offset = 0;
2020                 /* receive packet context */
2021                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2022                                     rx_ring->ena_com_io_sq,
2023                                     &ena_rx_ctx);
2024                 if (unlikely(rc)) {
2025                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2026                         rx_ring->adapter->reset_reason =
2027                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2028                         rx_ring->adapter->trigger_reset = true;
2029                         ++rx_ring->rx_stats.bad_desc_num;
2030                         return 0;
2031                 }
2032
2033                 if (unlikely(ena_rx_ctx.descs == 0))
2034                         break;
2035
2036                 while (segments < ena_rx_ctx.descs) {
2037                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2038                         rc = validate_rx_req_id(rx_ring, req_id);
2039                         if (unlikely(rc)) {
2040                                 if (segments != 0)
2041                                         rte_mbuf_raw_free(mbuf_head);
2042                                 break;
2043                         }
2044
2045                         mbuf = rx_buff_info[req_id];
2046                         rx_buff_info[req_id] = NULL;
2047                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2048                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2049                         mbuf->refcnt = 1;
2050                         mbuf->next = NULL;
2051                         if (unlikely(segments == 0)) {
2052                                 mbuf->nb_segs = ena_rx_ctx.descs;
2053                                 mbuf->port = rx_ring->port_id;
2054                                 mbuf->pkt_len = 0;
2055                                 mbuf->data_off += ena_rx_ctx.pkt_offset;
2056                                 mbuf_head = mbuf;
2057                         } else {
2058                                 /* for multi-segment pkts create mbuf chain */
2059                                 mbuf_prev->next = mbuf;
2060                         }
2061                         mbuf_head->pkt_len += mbuf->data_len;
2062
2063                         mbuf_prev = mbuf;
2064                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2065                                 req_id;
2066                         segments++;
2067                         next_to_clean++;
2068                 }
2069                 if (unlikely(rc))
2070                         break;
2071
2072                 /* fill mbuf attributes if any */
2073                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2074
2075                 if (unlikely(mbuf_head->ol_flags &
2076                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2077                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2078                         ++rx_ring->rx_stats.bad_csum;
2079                 }
2080
2081                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2082
2083                 /* pass to DPDK application head mbuf */
2084                 rx_pkts[recv_idx] = mbuf_head;
2085                 recv_idx++;
2086                 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2087         }
2088
2089         rx_ring->rx_stats.cnt += recv_idx;
2090         rx_ring->next_to_clean = next_to_clean;
2091
2092         desc_in_use = desc_in_use - completed + 1;
2093         /* Burst refill to save doorbells, memory barriers, const interval */
2094         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2095                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2096                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2097         }
2098
2099         return recv_idx;
2100 }
2101
2102 static uint16_t
2103 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2104                 uint16_t nb_pkts)
2105 {
2106         int32_t ret;
2107         uint32_t i;
2108         struct rte_mbuf *m;
2109         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2110         struct rte_ipv4_hdr *ip_hdr;
2111         uint64_t ol_flags;
2112         uint16_t frag_field;
2113
2114         for (i = 0; i != nb_pkts; i++) {
2115                 m = tx_pkts[i];
2116                 ol_flags = m->ol_flags;
2117
2118                 if (!(ol_flags & PKT_TX_IPV4))
2119                         continue;
2120
2121                 /* If there was not L2 header length specified, assume it is
2122                  * length of the ethernet header.
2123                  */
2124                 if (unlikely(m->l2_len == 0))
2125                         m->l2_len = sizeof(struct rte_ether_hdr);
2126
2127                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2128                                                  m->l2_len);
2129                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2130
2131                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2132                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2133
2134                         /* If IPv4 header has DF flag enabled and TSO support is
2135                          * disabled, partial chcecksum should not be calculated.
2136                          */
2137                         if (!tx_ring->adapter->offloads.tso4_supported)
2138                                 continue;
2139                 }
2140
2141                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2142                                 (ol_flags & PKT_TX_L4_MASK) ==
2143                                 PKT_TX_SCTP_CKSUM) {
2144                         rte_errno = ENOTSUP;
2145                         return i;
2146                 }
2147
2148 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2149                 ret = rte_validate_tx_offload(m);
2150                 if (ret != 0) {
2151                         rte_errno = -ret;
2152                         return i;
2153                 }
2154 #endif
2155
2156                 /* In case we are supposed to TSO and have DF not set (DF=0)
2157                  * hardware must be provided with partial checksum, otherwise
2158                  * it will take care of necessary calculations.
2159                  */
2160
2161                 ret = rte_net_intel_cksum_flags_prepare(m,
2162                         ol_flags & ~PKT_TX_TCP_SEG);
2163                 if (ret != 0) {
2164                         rte_errno = -ret;
2165                         return i;
2166                 }
2167         }
2168
2169         return i;
2170 }
2171
2172 static void ena_update_hints(struct ena_adapter *adapter,
2173                              struct ena_admin_ena_hw_hints *hints)
2174 {
2175         if (hints->admin_completion_tx_timeout)
2176                 adapter->ena_dev.admin_queue.completion_timeout =
2177                         hints->admin_completion_tx_timeout * 1000;
2178
2179         if (hints->mmio_read_timeout)
2180                 /* convert to usec */
2181                 adapter->ena_dev.mmio_read.reg_read_to =
2182                         hints->mmio_read_timeout * 1000;
2183
2184         if (hints->driver_watchdog_timeout) {
2185                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2186                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2187                 else
2188                         // Convert msecs to ticks
2189                         adapter->keep_alive_timeout =
2190                                 (hints->driver_watchdog_timeout *
2191                                 rte_get_timer_hz()) / 1000;
2192         }
2193 }
2194
2195 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2196                                         struct rte_mbuf *mbuf)
2197 {
2198         struct ena_com_dev *ena_dev;
2199         int num_segments, header_len, rc;
2200
2201         ena_dev = &tx_ring->adapter->ena_dev;
2202         num_segments = mbuf->nb_segs;
2203         header_len = mbuf->data_len;
2204
2205         if (likely(num_segments < tx_ring->sgl_size))
2206                 return 0;
2207
2208         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2209             (num_segments == tx_ring->sgl_size) &&
2210             (header_len < tx_ring->tx_max_header_size))
2211                 return 0;
2212
2213         ++tx_ring->tx_stats.linearize;
2214         rc = rte_pktmbuf_linearize(mbuf);
2215         if (unlikely(rc)) {
2216                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2217                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2218                 ++tx_ring->tx_stats.linearize_failed;
2219                 return rc;
2220         }
2221
2222         return rc;
2223 }
2224
2225 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2226                                   uint16_t nb_pkts)
2227 {
2228         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2229         uint16_t next_to_use = tx_ring->next_to_use;
2230         uint16_t next_to_clean = tx_ring->next_to_clean;
2231         struct rte_mbuf *mbuf;
2232         uint16_t seg_len;
2233         unsigned int ring_size = tx_ring->ring_size;
2234         unsigned int ring_mask = ring_size - 1;
2235         struct ena_com_tx_ctx ena_tx_ctx;
2236         struct ena_tx_buffer *tx_info;
2237         struct ena_com_buf *ebuf;
2238         uint16_t rc, req_id, total_tx_descs = 0;
2239         uint16_t sent_idx = 0, empty_tx_reqs;
2240         uint16_t push_len = 0;
2241         uint16_t delta = 0;
2242         int nb_hw_desc;
2243         uint32_t total_length;
2244
2245         /* Check adapter state */
2246         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2247                 PMD_DRV_LOG(ALERT,
2248                         "Trying to xmit pkts while device is NOT running\n");
2249                 return 0;
2250         }
2251
2252         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2253         if (nb_pkts > empty_tx_reqs)
2254                 nb_pkts = empty_tx_reqs;
2255
2256         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2257                 mbuf = tx_pkts[sent_idx];
2258                 total_length = 0;
2259
2260                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2261                 if (unlikely(rc))
2262                         break;
2263
2264                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2265                 tx_info = &tx_ring->tx_buffer_info[req_id];
2266                 tx_info->mbuf = mbuf;
2267                 tx_info->num_of_bufs = 0;
2268                 ebuf = tx_info->bufs;
2269
2270                 /* Prepare TX context */
2271                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2272                 memset(&ena_tx_ctx.ena_meta, 0x0,
2273                        sizeof(struct ena_com_tx_meta));
2274                 ena_tx_ctx.ena_bufs = ebuf;
2275                 ena_tx_ctx.req_id = req_id;
2276
2277                 delta = 0;
2278                 seg_len = mbuf->data_len;
2279
2280                 if (tx_ring->tx_mem_queue_type ==
2281                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2282                         push_len = RTE_MIN(mbuf->pkt_len,
2283                                            tx_ring->tx_max_header_size);
2284                         ena_tx_ctx.header_len = push_len;
2285
2286                         if (likely(push_len <= seg_len)) {
2287                                 /* If the push header is in the single segment,
2288                                  * then just point it to the 1st mbuf data.
2289                                  */
2290                                 ena_tx_ctx.push_header =
2291                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2292                         } else {
2293                                 /* If the push header lays in the several
2294                                  * segments, copy it to the intermediate buffer.
2295                                  */
2296                                 rte_pktmbuf_read(mbuf, 0, push_len,
2297                                         tx_ring->push_buf_intermediate_buf);
2298                                 ena_tx_ctx.push_header =
2299                                         tx_ring->push_buf_intermediate_buf;
2300                                 delta = push_len - seg_len;
2301                         }
2302                 } /* there's no else as we take advantage of memset zeroing */
2303
2304                 /* Set TX offloads flags, if applicable */
2305                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2306
2307                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2308
2309                 /* Process first segment taking into
2310                  * consideration pushed header
2311                  */
2312                 if (seg_len > push_len) {
2313                         ebuf->paddr = mbuf->buf_iova +
2314                                       mbuf->data_off +
2315                                       push_len;
2316                         ebuf->len = seg_len - push_len;
2317                         ebuf++;
2318                         tx_info->num_of_bufs++;
2319                 }
2320                 total_length += mbuf->data_len;
2321
2322                 while ((mbuf = mbuf->next) != NULL) {
2323                         seg_len = mbuf->data_len;
2324
2325                         /* Skip mbufs if whole data is pushed as a header */
2326                         if (unlikely(delta > seg_len)) {
2327                                 delta -= seg_len;
2328                                 continue;
2329                         }
2330
2331                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2332                         ebuf->len = seg_len - delta;
2333                         total_length += ebuf->len;
2334                         ebuf++;
2335                         tx_info->num_of_bufs++;
2336
2337                         delta = 0;
2338                 }
2339
2340                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2341
2342                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2343                                                &ena_tx_ctx)) {
2344                         PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2345                                 " achieved, writing doorbell to send burst\n",
2346                                 tx_ring->id);
2347                         rte_wmb();
2348                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2349                 }
2350
2351                 /* prepare the packet's descriptors to dma engine */
2352                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2353                                         &ena_tx_ctx, &nb_hw_desc);
2354                 if (unlikely(rc)) {
2355                         ++tx_ring->tx_stats.prepare_ctx_err;
2356                         break;
2357                 }
2358                 tx_info->tx_descs = nb_hw_desc;
2359
2360                 next_to_use++;
2361                 tx_ring->tx_stats.cnt++;
2362                 tx_ring->tx_stats.bytes += total_length;
2363         }
2364         tx_ring->tx_stats.available_desc =
2365                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2366
2367         /* If there are ready packets to be xmitted... */
2368         if (sent_idx > 0) {
2369                 /* ...let HW do its best :-) */
2370                 rte_wmb();
2371                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2372                 tx_ring->tx_stats.doorbells++;
2373                 tx_ring->next_to_use = next_to_use;
2374         }
2375
2376         /* Clear complete packets  */
2377         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2378                 rc = validate_tx_req_id(tx_ring, req_id);
2379                 if (rc)
2380                         break;
2381
2382                 /* Get Tx info & store how many descs were processed  */
2383                 tx_info = &tx_ring->tx_buffer_info[req_id];
2384                 total_tx_descs += tx_info->tx_descs;
2385
2386                 /* Free whole mbuf chain  */
2387                 mbuf = tx_info->mbuf;
2388                 rte_pktmbuf_free(mbuf);
2389                 tx_info->mbuf = NULL;
2390
2391                 /* Put back descriptor to the ring for reuse */
2392                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2393                 next_to_clean++;
2394
2395                 /* If too many descs to clean, leave it for another run */
2396                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2397                         break;
2398         }
2399         tx_ring->tx_stats.available_desc =
2400                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2401
2402         if (total_tx_descs > 0) {
2403                 /* acknowledge completion of sent packets */
2404                 tx_ring->next_to_clean = next_to_clean;
2405                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2406                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2407         }
2408
2409         tx_ring->tx_stats.tx_poll++;
2410
2411         return sent_idx;
2412 }
2413
2414 /**
2415  * DPDK callback to retrieve names of extended device statistics
2416  *
2417  * @param dev
2418  *   Pointer to Ethernet device structure.
2419  * @param[out] xstats_names
2420  *   Buffer to insert names into.
2421  * @param n
2422  *   Number of names.
2423  *
2424  * @return
2425  *   Number of xstats names.
2426  */
2427 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2428                                 struct rte_eth_xstat_name *xstats_names,
2429                                 unsigned int n)
2430 {
2431         unsigned int xstats_count = ena_xstats_calc_num(dev);
2432         unsigned int stat, i, count = 0;
2433
2434         if (n < xstats_count || !xstats_names)
2435                 return xstats_count;
2436
2437         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2438                 strcpy(xstats_names[count].name,
2439                         ena_stats_global_strings[stat].name);
2440
2441         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2442                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2443                         snprintf(xstats_names[count].name,
2444                                 sizeof(xstats_names[count].name),
2445                                 "rx_q%d_%s", i,
2446                                 ena_stats_rx_strings[stat].name);
2447
2448         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2449                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2450                         snprintf(xstats_names[count].name,
2451                                 sizeof(xstats_names[count].name),
2452                                 "tx_q%d_%s", i,
2453                                 ena_stats_tx_strings[stat].name);
2454
2455         return xstats_count;
2456 }
2457
2458 /**
2459  * DPDK callback to get extended device statistics.
2460  *
2461  * @param dev
2462  *   Pointer to Ethernet device structure.
2463  * @param[out] stats
2464  *   Stats table output buffer.
2465  * @param n
2466  *   The size of the stats table.
2467  *
2468  * @return
2469  *   Number of xstats on success, negative on failure.
2470  */
2471 static int ena_xstats_get(struct rte_eth_dev *dev,
2472                           struct rte_eth_xstat *xstats,
2473                           unsigned int n)
2474 {
2475         struct ena_adapter *adapter = dev->data->dev_private;
2476         unsigned int xstats_count = ena_xstats_calc_num(dev);
2477         unsigned int stat, i, count = 0;
2478         int stat_offset;
2479         void *stats_begin;
2480
2481         if (n < xstats_count)
2482                 return xstats_count;
2483
2484         if (!xstats)
2485                 return 0;
2486
2487         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2488                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2489                 stats_begin = &adapter->dev_stats;
2490
2491                 xstats[count].id = count;
2492                 xstats[count].value = *((uint64_t *)
2493                         ((char *)stats_begin + stat_offset));
2494         }
2495
2496         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2497                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2498                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2499                         stats_begin = &adapter->rx_ring[i].rx_stats;
2500
2501                         xstats[count].id = count;
2502                         xstats[count].value = *((uint64_t *)
2503                                 ((char *)stats_begin + stat_offset));
2504                 }
2505         }
2506
2507         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2508                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2509                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2510                         stats_begin = &adapter->tx_ring[i].rx_stats;
2511
2512                         xstats[count].id = count;
2513                         xstats[count].value = *((uint64_t *)
2514                                 ((char *)stats_begin + stat_offset));
2515                 }
2516         }
2517
2518         return count;
2519 }
2520
2521 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2522                                 const uint64_t *ids,
2523                                 uint64_t *values,
2524                                 unsigned int n)
2525 {
2526         struct ena_adapter *adapter = dev->data->dev_private;
2527         uint64_t id;
2528         uint64_t rx_entries, tx_entries;
2529         unsigned int i;
2530         int qid;
2531         int valid = 0;
2532         for (i = 0; i < n; ++i) {
2533                 id = ids[i];
2534                 /* Check if id belongs to global statistics */
2535                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2536                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2537                         ++valid;
2538                         continue;
2539                 }
2540
2541                 /* Check if id belongs to rx queue statistics */
2542                 id -= ENA_STATS_ARRAY_GLOBAL;
2543                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2544                 if (id < rx_entries) {
2545                         qid = id % dev->data->nb_rx_queues;
2546                         id /= dev->data->nb_rx_queues;
2547                         values[i] = *((uint64_t *)
2548                                 &adapter->rx_ring[qid].rx_stats + id);
2549                         ++valid;
2550                         continue;
2551                 }
2552                                 /* Check if id belongs to rx queue statistics */
2553                 id -= rx_entries;
2554                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2555                 if (id < tx_entries) {
2556                         qid = id % dev->data->nb_tx_queues;
2557                         id /= dev->data->nb_tx_queues;
2558                         values[i] = *((uint64_t *)
2559                                 &adapter->tx_ring[qid].tx_stats + id);
2560                         ++valid;
2561                         continue;
2562                 }
2563         }
2564
2565         return valid;
2566 }
2567
2568 /*********************************************************************
2569  *  PMD configuration
2570  *********************************************************************/
2571 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2572         struct rte_pci_device *pci_dev)
2573 {
2574         return rte_eth_dev_pci_generic_probe(pci_dev,
2575                 sizeof(struct ena_adapter), eth_ena_dev_init);
2576 }
2577
2578 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2579 {
2580         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2581 }
2582
2583 static struct rte_pci_driver rte_ena_pmd = {
2584         .id_table = pci_id_ena_map,
2585         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2586                      RTE_PCI_DRV_WC_ACTIVATE,
2587         .probe = eth_ena_pci_probe,
2588         .remove = eth_ena_pci_remove,
2589 };
2590
2591 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2592 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2593 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2594
2595 RTE_INIT(ena_init_log)
2596 {
2597         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2598         if (ena_logtype_init >= 0)
2599                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2600         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2601         if (ena_logtype_driver >= 0)
2602                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2603
2604 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2605         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2606         if (ena_logtype_rx >= 0)
2607                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2608 #endif
2609
2610 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2611         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2612         if (ena_logtype_tx >= 0)
2613                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2614 #endif
2615
2616 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2617         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2618         if (ena_logtype_tx_free >= 0)
2619                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2620 #endif
2621
2622 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2623         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2624         if (ena_logtype_com >= 0)
2625                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2626 #endif
2627 }
2628
2629 /******************************************************************************
2630  ******************************** AENQ Handlers *******************************
2631  *****************************************************************************/
2632 static void ena_update_on_link_change(void *adapter_data,
2633                                       struct ena_admin_aenq_entry *aenq_e)
2634 {
2635         struct rte_eth_dev *eth_dev;
2636         struct ena_adapter *adapter;
2637         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2638         uint32_t status;
2639
2640         adapter = adapter_data;
2641         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2642         eth_dev = adapter->rte_dev;
2643
2644         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2645         adapter->link_status = status;
2646
2647         ena_link_update(eth_dev, 0);
2648         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2649 }
2650
2651 static void ena_notification(void *data,
2652                              struct ena_admin_aenq_entry *aenq_e)
2653 {
2654         struct ena_adapter *adapter = data;
2655         struct ena_admin_ena_hw_hints *hints;
2656
2657         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2658                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2659                         aenq_e->aenq_common_desc.group,
2660                         ENA_ADMIN_NOTIFICATION);
2661
2662         switch (aenq_e->aenq_common_desc.syndrom) {
2663         case ENA_ADMIN_UPDATE_HINTS:
2664                 hints = (struct ena_admin_ena_hw_hints *)
2665                         (&aenq_e->inline_data_w4);
2666                 ena_update_hints(adapter, hints);
2667                 break;
2668         default:
2669                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2670                         aenq_e->aenq_common_desc.syndrom);
2671         }
2672 }
2673
2674 static void ena_keep_alive(void *adapter_data,
2675                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2676 {
2677         struct ena_adapter *adapter = adapter_data;
2678         struct ena_admin_aenq_keep_alive_desc *desc;
2679         uint64_t rx_drops;
2680
2681         adapter->timestamp_wd = rte_get_timer_cycles();
2682
2683         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2684         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2685         rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops);
2686 }
2687
2688 /**
2689  * This handler will called for unknown event group or unimplemented handlers
2690  **/
2691 static void unimplemented_aenq_handler(__rte_unused void *data,
2692                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2693 {
2694         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2695                           "unimplemented handler\n");
2696 }
2697
2698 static struct ena_aenq_handlers aenq_handlers = {
2699         .handlers = {
2700                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2701                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2702                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2703         },
2704         .unimplemented_handler = unimplemented_aenq_handler
2705 };