1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_ethdev_pci.h>
11 #include <rte_atomic.h>
13 #include <rte_errno.h>
14 #include <rte_version.h>
17 #include "ena_ethdev.h"
19 #include "ena_platform.h"
21 #include "ena_eth_com.h"
23 #include <ena_common_defs.h>
24 #include <ena_regs_defs.h>
25 #include <ena_admin_defs.h>
26 #include <ena_eth_io_defs.h>
28 #define DRV_MODULE_VER_MAJOR 2
29 #define DRV_MODULE_VER_MINOR 0
30 #define DRV_MODULE_VER_SUBMINOR 3
32 #define ENA_IO_TXQ_IDX(q) (2 * (q))
33 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
34 /*reverse version of ENA_IO_RXQ_IDX*/
35 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
37 /* While processing submitted and completed descriptors (rx and tx path
38 * respectively) in a loop it is desired to:
39 * - perform batch submissions while populating sumbissmion queue
40 * - avoid blocking transmission of other packets during cleanup phase
41 * Hence the utilization ratio of 1/8 of a queue size.
43 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
45 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
46 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
48 #define GET_L4_HDR_LEN(mbuf) \
49 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
50 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
52 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
53 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
54 #define ENA_HASH_KEY_SIZE 40
55 #define ETH_GSTRING_LEN 32
57 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
59 #define ENA_MIN_RING_DESC 128
61 enum ethtool_stringset {
67 char name[ETH_GSTRING_LEN];
71 #define ENA_STAT_ENTRY(stat, stat_type) { \
73 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
76 #define ENA_STAT_RX_ENTRY(stat) \
77 ENA_STAT_ENTRY(stat, rx)
79 #define ENA_STAT_TX_ENTRY(stat) \
80 ENA_STAT_ENTRY(stat, tx)
82 #define ENA_STAT_GLOBAL_ENTRY(stat) \
83 ENA_STAT_ENTRY(stat, dev)
85 #define ENA_MAX_RING_SIZE_RX 8192
86 #define ENA_MAX_RING_SIZE_TX 1024
89 * Each rte_memzone should have unique name.
90 * To satisfy it, count number of allocation and add it to name.
92 uint32_t ena_alloc_cnt;
94 static const struct ena_stats ena_stats_global_strings[] = {
95 ENA_STAT_GLOBAL_ENTRY(wd_expired),
96 ENA_STAT_GLOBAL_ENTRY(dev_start),
97 ENA_STAT_GLOBAL_ENTRY(dev_stop),
100 static const struct ena_stats ena_stats_tx_strings[] = {
101 ENA_STAT_TX_ENTRY(cnt),
102 ENA_STAT_TX_ENTRY(bytes),
103 ENA_STAT_TX_ENTRY(prepare_ctx_err),
104 ENA_STAT_TX_ENTRY(linearize),
105 ENA_STAT_TX_ENTRY(linearize_failed),
106 ENA_STAT_TX_ENTRY(tx_poll),
107 ENA_STAT_TX_ENTRY(doorbells),
108 ENA_STAT_TX_ENTRY(bad_req_id),
109 ENA_STAT_TX_ENTRY(available_desc),
112 static const struct ena_stats ena_stats_rx_strings[] = {
113 ENA_STAT_RX_ENTRY(cnt),
114 ENA_STAT_RX_ENTRY(bytes),
115 ENA_STAT_RX_ENTRY(refill_partial),
116 ENA_STAT_RX_ENTRY(bad_csum),
117 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
118 ENA_STAT_RX_ENTRY(bad_desc_num),
119 ENA_STAT_RX_ENTRY(bad_req_id),
122 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
123 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
124 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
126 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
127 DEV_TX_OFFLOAD_UDP_CKSUM |\
128 DEV_TX_OFFLOAD_IPV4_CKSUM |\
129 DEV_TX_OFFLOAD_TCP_TSO)
130 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
134 /** Vendor ID used by Amazon devices */
135 #define PCI_VENDOR_ID_AMAZON 0x1D0F
136 /** Amazon devices */
137 #define PCI_DEVICE_ID_ENA_VF 0xEC20
138 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
140 #define ENA_TX_OFFLOAD_MASK (\
147 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
148 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
150 int ena_logtype_init;
151 int ena_logtype_driver;
153 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
156 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
159 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
160 int ena_logtype_tx_free;
162 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
166 static const struct rte_pci_id pci_id_ena_map[] = {
167 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
168 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
172 static struct ena_aenq_handlers aenq_handlers;
174 static int ena_device_init(struct ena_com_dev *ena_dev,
175 struct ena_com_dev_get_features_ctx *get_feat_ctx,
177 static int ena_dev_configure(struct rte_eth_dev *dev);
178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_txconf *tx_conf);
185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
186 uint16_t nb_desc, unsigned int socket_id,
187 const struct rte_eth_rxconf *rx_conf,
188 struct rte_mempool *mp);
189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
190 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
192 static void ena_init_rings(struct ena_adapter *adapter);
193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
194 static int ena_start(struct rte_eth_dev *dev);
195 static void ena_stop(struct rte_eth_dev *dev);
196 static void ena_close(struct rte_eth_dev *dev);
197 static int ena_dev_reset(struct rte_eth_dev *dev);
198 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
199 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
200 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
201 static void ena_rx_queue_release(void *queue);
202 static void ena_tx_queue_release(void *queue);
203 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
204 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
205 static int ena_link_update(struct rte_eth_dev *dev,
206 int wait_to_complete);
207 static int ena_create_io_queue(struct ena_ring *ring);
208 static void ena_queue_stop(struct ena_ring *ring);
209 static void ena_queue_stop_all(struct rte_eth_dev *dev,
210 enum ena_ring_type ring_type);
211 static int ena_queue_start(struct ena_ring *ring);
212 static int ena_queue_start_all(struct rte_eth_dev *dev,
213 enum ena_ring_type ring_type);
214 static void ena_stats_restart(struct rte_eth_dev *dev);
215 static int ena_infos_get(struct rte_eth_dev *dev,
216 struct rte_eth_dev_info *dev_info);
217 static int ena_rss_reta_update(struct rte_eth_dev *dev,
218 struct rte_eth_rss_reta_entry64 *reta_conf,
220 static int ena_rss_reta_query(struct rte_eth_dev *dev,
221 struct rte_eth_rss_reta_entry64 *reta_conf,
223 static void ena_interrupt_handler_rte(void *cb_arg);
224 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
225 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
226 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
227 static int ena_xstats_get_names(struct rte_eth_dev *dev,
228 struct rte_eth_xstat_name *xstats_names,
230 static int ena_xstats_get(struct rte_eth_dev *dev,
231 struct rte_eth_xstat *stats,
233 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
238 static const struct eth_dev_ops ena_dev_ops = {
239 .dev_configure = ena_dev_configure,
240 .dev_infos_get = ena_infos_get,
241 .rx_queue_setup = ena_rx_queue_setup,
242 .tx_queue_setup = ena_tx_queue_setup,
243 .dev_start = ena_start,
244 .dev_stop = ena_stop,
245 .link_update = ena_link_update,
246 .stats_get = ena_stats_get,
247 .xstats_get_names = ena_xstats_get_names,
248 .xstats_get = ena_xstats_get,
249 .xstats_get_by_id = ena_xstats_get_by_id,
250 .mtu_set = ena_mtu_set,
251 .rx_queue_release = ena_rx_queue_release,
252 .tx_queue_release = ena_tx_queue_release,
253 .dev_close = ena_close,
254 .dev_reset = ena_dev_reset,
255 .reta_update = ena_rss_reta_update,
256 .reta_query = ena_rss_reta_query,
259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
260 struct ena_com_rx_ctx *ena_rx_ctx)
262 uint64_t ol_flags = 0;
263 uint32_t packet_type = 0;
265 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
266 packet_type |= RTE_PTYPE_L4_TCP;
267 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
268 packet_type |= RTE_PTYPE_L4_UDP;
270 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
271 packet_type |= RTE_PTYPE_L3_IPV4;
272 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
273 packet_type |= RTE_PTYPE_L3_IPV6;
275 if (!ena_rx_ctx->l4_csum_checked)
276 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
278 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
279 ol_flags |= PKT_RX_L4_CKSUM_BAD;
281 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
283 if (unlikely(ena_rx_ctx->l3_csum_err))
284 ol_flags |= PKT_RX_IP_CKSUM_BAD;
286 mbuf->ol_flags = ol_flags;
287 mbuf->packet_type = packet_type;
290 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
291 struct ena_com_tx_ctx *ena_tx_ctx,
292 uint64_t queue_offloads)
294 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
296 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
297 (queue_offloads & QUEUE_OFFLOADS)) {
298 /* check if TSO is required */
299 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
300 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
301 ena_tx_ctx->tso_enable = true;
303 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
306 /* check if L3 checksum is needed */
307 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
308 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
309 ena_tx_ctx->l3_csum_enable = true;
311 if (mbuf->ol_flags & PKT_TX_IPV6) {
312 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
314 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
316 /* set don't fragment (DF) flag */
317 if (mbuf->packet_type &
318 (RTE_PTYPE_L4_NONFRAG
319 | RTE_PTYPE_INNER_L4_NONFRAG))
320 ena_tx_ctx->df = true;
323 /* check if L4 checksum is needed */
324 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
325 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
326 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
327 ena_tx_ctx->l4_csum_enable = true;
328 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
330 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
331 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
332 ena_tx_ctx->l4_csum_enable = true;
334 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
335 ena_tx_ctx->l4_csum_enable = false;
338 ena_meta->mss = mbuf->tso_segsz;
339 ena_meta->l3_hdr_len = mbuf->l3_len;
340 ena_meta->l3_hdr_offset = mbuf->l2_len;
342 ena_tx_ctx->meta_valid = true;
344 ena_tx_ctx->meta_valid = false;
348 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
350 if (likely(req_id < rx_ring->ring_size))
353 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
355 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
356 rx_ring->adapter->trigger_reset = true;
357 ++rx_ring->rx_stats.bad_req_id;
362 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
364 struct ena_tx_buffer *tx_info = NULL;
366 if (likely(req_id < tx_ring->ring_size)) {
367 tx_info = &tx_ring->tx_buffer_info[req_id];
368 if (likely(tx_info->mbuf))
373 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
375 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
377 /* Trigger device reset */
378 ++tx_ring->tx_stats.bad_req_id;
379 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
380 tx_ring->adapter->trigger_reset = true;
384 static void ena_config_host_info(struct ena_com_dev *ena_dev)
386 struct ena_admin_host_info *host_info;
389 /* Allocate only the host info */
390 rc = ena_com_allocate_host_info(ena_dev);
392 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
396 host_info = ena_dev->host_attr.host_info;
398 host_info->os_type = ENA_ADMIN_OS_DPDK;
399 host_info->kernel_ver = RTE_VERSION;
400 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
401 sizeof(host_info->kernel_ver_str));
402 host_info->os_dist = RTE_VERSION;
403 strlcpy((char *)host_info->os_dist_str, rte_version(),
404 sizeof(host_info->os_dist_str));
405 host_info->driver_version =
406 (DRV_MODULE_VER_MAJOR) |
407 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
408 (DRV_MODULE_VER_SUBMINOR <<
409 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
410 host_info->num_cpus = rte_lcore_count();
412 host_info->driver_supported_features =
413 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
415 rc = ena_com_set_host_attributes(ena_dev);
417 if (rc == -ENA_COM_UNSUPPORTED)
418 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
420 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
428 ena_com_delete_host_info(ena_dev);
431 /* This function calculates the number of xstats based on the current config */
432 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
434 return ENA_STATS_ARRAY_GLOBAL +
435 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
436 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
439 static void ena_config_debug_area(struct ena_adapter *adapter)
444 ss_count = ena_xstats_calc_num(adapter->rte_dev);
446 /* allocate 32 bytes for each string and 64bit for the value */
447 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
449 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
451 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
455 rc = ena_com_set_host_attributes(&adapter->ena_dev);
457 if (rc == -ENA_COM_UNSUPPORTED)
458 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
460 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
467 ena_com_delete_debug_area(&adapter->ena_dev);
470 static void ena_close(struct rte_eth_dev *dev)
472 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
473 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
474 struct ena_adapter *adapter = dev->data->dev_private;
476 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
478 adapter->state = ENA_ADAPTER_STATE_CLOSED;
480 ena_rx_queue_release_all(dev);
481 ena_tx_queue_release_all(dev);
483 rte_free(adapter->drv_stats);
484 adapter->drv_stats = NULL;
486 rte_intr_disable(intr_handle);
487 rte_intr_callback_unregister(intr_handle,
488 ena_interrupt_handler_rte,
492 * MAC is not allocated dynamically. Setting NULL should prevent from
493 * release of the resource in the rte_eth_dev_release_port().
495 dev->data->mac_addrs = NULL;
499 ena_dev_reset(struct rte_eth_dev *dev)
503 ena_destroy_device(dev);
504 rc = eth_ena_dev_init(dev);
506 PMD_INIT_LOG(CRIT, "Cannot initialize device");
511 static int ena_rss_reta_update(struct rte_eth_dev *dev,
512 struct rte_eth_rss_reta_entry64 *reta_conf,
515 struct ena_adapter *adapter = dev->data->dev_private;
516 struct ena_com_dev *ena_dev = &adapter->ena_dev;
522 if ((reta_size == 0) || (reta_conf == NULL))
525 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
527 "indirection table %d is bigger than supported (%d)\n",
528 reta_size, ENA_RX_RSS_TABLE_SIZE);
532 for (i = 0 ; i < reta_size ; i++) {
533 /* each reta_conf is for 64 entries.
534 * to support 128 we use 2 conf of 64
536 conf_idx = i / RTE_RETA_GROUP_SIZE;
537 idx = i % RTE_RETA_GROUP_SIZE;
538 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
540 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
542 rc = ena_com_indirect_table_fill_entry(ena_dev,
545 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
547 "Cannot fill indirect table\n");
553 rc = ena_com_indirect_table_set(ena_dev);
554 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
555 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
559 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n",
560 __func__, reta_size, adapter->rte_dev->data->port_id);
565 /* Query redirection table. */
566 static int ena_rss_reta_query(struct rte_eth_dev *dev,
567 struct rte_eth_rss_reta_entry64 *reta_conf,
570 struct ena_adapter *adapter = dev->data->dev_private;
571 struct ena_com_dev *ena_dev = &adapter->ena_dev;
574 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
578 if (reta_size == 0 || reta_conf == NULL ||
579 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
582 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
583 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
584 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
588 for (i = 0 ; i < reta_size ; i++) {
589 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
590 reta_idx = i % RTE_RETA_GROUP_SIZE;
591 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
592 reta_conf[reta_conf_idx].reta[reta_idx] =
593 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
599 static int ena_rss_init_default(struct ena_adapter *adapter)
601 struct ena_com_dev *ena_dev = &adapter->ena_dev;
602 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
606 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
608 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
612 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
613 val = i % nb_rx_queues;
614 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
615 ENA_IO_RXQ_IDX(val));
616 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
617 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
622 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
623 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
624 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
625 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
629 rc = ena_com_set_default_hash_ctrl(ena_dev);
630 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
631 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
635 rc = ena_com_indirect_table_set(ena_dev);
636 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
637 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
640 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
641 adapter->rte_dev->data->port_id);
646 ena_com_rss_destroy(ena_dev);
652 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
654 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
655 int nb_queues = dev->data->nb_rx_queues;
658 for (i = 0; i < nb_queues; i++)
659 ena_rx_queue_release(queues[i]);
662 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
664 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
665 int nb_queues = dev->data->nb_tx_queues;
668 for (i = 0; i < nb_queues; i++)
669 ena_tx_queue_release(queues[i]);
672 static void ena_rx_queue_release(void *queue)
674 struct ena_ring *ring = (struct ena_ring *)queue;
676 /* Free ring resources */
677 if (ring->rx_buffer_info)
678 rte_free(ring->rx_buffer_info);
679 ring->rx_buffer_info = NULL;
681 if (ring->rx_refill_buffer)
682 rte_free(ring->rx_refill_buffer);
683 ring->rx_refill_buffer = NULL;
685 if (ring->empty_rx_reqs)
686 rte_free(ring->empty_rx_reqs);
687 ring->empty_rx_reqs = NULL;
689 ring->configured = 0;
691 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
692 ring->port_id, ring->id);
695 static void ena_tx_queue_release(void *queue)
697 struct ena_ring *ring = (struct ena_ring *)queue;
699 /* Free ring resources */
700 if (ring->push_buf_intermediate_buf)
701 rte_free(ring->push_buf_intermediate_buf);
703 if (ring->tx_buffer_info)
704 rte_free(ring->tx_buffer_info);
706 if (ring->empty_tx_reqs)
707 rte_free(ring->empty_tx_reqs);
709 ring->empty_tx_reqs = NULL;
710 ring->tx_buffer_info = NULL;
711 ring->push_buf_intermediate_buf = NULL;
713 ring->configured = 0;
715 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
716 ring->port_id, ring->id);
719 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
723 for (i = 0; i < ring->ring_size; ++i)
724 if (ring->rx_buffer_info[i]) {
725 rte_mbuf_raw_free(ring->rx_buffer_info[i]);
726 ring->rx_buffer_info[i] = NULL;
730 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
734 for (i = 0; i < ring->ring_size; ++i) {
735 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
738 rte_pktmbuf_free(tx_buf->mbuf);
742 static int ena_link_update(struct rte_eth_dev *dev,
743 __rte_unused int wait_to_complete)
745 struct rte_eth_link *link = &dev->data->dev_link;
746 struct ena_adapter *adapter = dev->data->dev_private;
748 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
749 link->link_speed = ETH_SPEED_NUM_NONE;
750 link->link_duplex = ETH_LINK_FULL_DUPLEX;
755 static int ena_queue_start_all(struct rte_eth_dev *dev,
756 enum ena_ring_type ring_type)
758 struct ena_adapter *adapter = dev->data->dev_private;
759 struct ena_ring *queues = NULL;
764 if (ring_type == ENA_RING_TYPE_RX) {
765 queues = adapter->rx_ring;
766 nb_queues = dev->data->nb_rx_queues;
768 queues = adapter->tx_ring;
769 nb_queues = dev->data->nb_tx_queues;
771 for (i = 0; i < nb_queues; i++) {
772 if (queues[i].configured) {
773 if (ring_type == ENA_RING_TYPE_RX) {
775 dev->data->rx_queues[i] == &queues[i],
776 "Inconsistent state of rx queues\n");
779 dev->data->tx_queues[i] == &queues[i],
780 "Inconsistent state of tx queues\n");
783 rc = ena_queue_start(&queues[i]);
787 "failed to start queue %d type(%d)",
798 if (queues[i].configured)
799 ena_queue_stop(&queues[i]);
804 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
806 uint32_t max_frame_len = adapter->max_mtu;
808 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
809 DEV_RX_OFFLOAD_JUMBO_FRAME)
811 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
813 return max_frame_len;
816 static int ena_check_valid_conf(struct ena_adapter *adapter)
818 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
820 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
821 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
822 "max mtu: %d, min mtu: %d",
823 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
824 return ENA_COM_UNSUPPORTED;
831 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
833 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
834 struct ena_com_dev *ena_dev = ctx->ena_dev;
835 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
836 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
838 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
839 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
840 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
841 rx_queue_size = RTE_MIN(rx_queue_size,
842 max_queue_ext->max_rx_cq_depth);
843 rx_queue_size = RTE_MIN(rx_queue_size,
844 max_queue_ext->max_rx_sq_depth);
845 tx_queue_size = RTE_MIN(tx_queue_size,
846 max_queue_ext->max_tx_cq_depth);
848 if (ena_dev->tx_mem_queue_type ==
849 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
850 tx_queue_size = RTE_MIN(tx_queue_size,
853 tx_queue_size = RTE_MIN(tx_queue_size,
854 max_queue_ext->max_tx_sq_depth);
857 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
858 max_queue_ext->max_per_packet_rx_descs);
859 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
860 max_queue_ext->max_per_packet_tx_descs);
862 struct ena_admin_queue_feature_desc *max_queues =
863 &ctx->get_feat_ctx->max_queues;
864 rx_queue_size = RTE_MIN(rx_queue_size,
865 max_queues->max_cq_depth);
866 rx_queue_size = RTE_MIN(rx_queue_size,
867 max_queues->max_sq_depth);
868 tx_queue_size = RTE_MIN(tx_queue_size,
869 max_queues->max_cq_depth);
871 if (ena_dev->tx_mem_queue_type ==
872 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
873 tx_queue_size = RTE_MIN(tx_queue_size,
876 tx_queue_size = RTE_MIN(tx_queue_size,
877 max_queues->max_sq_depth);
880 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
881 max_queues->max_packet_tx_descs);
882 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
883 max_queues->max_packet_rx_descs);
886 /* Round down to the nearest power of 2 */
887 rx_queue_size = rte_align32prevpow2(rx_queue_size);
888 tx_queue_size = rte_align32prevpow2(tx_queue_size);
890 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
891 PMD_INIT_LOG(ERR, "Invalid queue size");
895 ctx->rx_queue_size = rx_queue_size;
896 ctx->tx_queue_size = tx_queue_size;
901 static void ena_stats_restart(struct rte_eth_dev *dev)
903 struct ena_adapter *adapter = dev->data->dev_private;
905 rte_atomic64_init(&adapter->drv_stats->ierrors);
906 rte_atomic64_init(&adapter->drv_stats->oerrors);
907 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
908 rte_atomic64_init(&adapter->drv_stats->rx_drops);
911 static int ena_stats_get(struct rte_eth_dev *dev,
912 struct rte_eth_stats *stats)
914 struct ena_admin_basic_stats ena_stats;
915 struct ena_adapter *adapter = dev->data->dev_private;
916 struct ena_com_dev *ena_dev = &adapter->ena_dev;
921 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
924 memset(&ena_stats, 0, sizeof(ena_stats));
925 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
927 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
931 /* Set of basic statistics from ENA */
932 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
933 ena_stats.rx_pkts_low);
934 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
935 ena_stats.tx_pkts_low);
936 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
937 ena_stats.rx_bytes_low);
938 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
939 ena_stats.tx_bytes_low);
941 /* Driver related stats */
942 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops);
943 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
944 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
945 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
947 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
948 RTE_ETHDEV_QUEUE_STAT_CNTRS);
949 for (i = 0; i < max_rings_stats; ++i) {
950 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
952 stats->q_ibytes[i] = rx_stats->bytes;
953 stats->q_ipackets[i] = rx_stats->cnt;
954 stats->q_errors[i] = rx_stats->bad_desc_num +
955 rx_stats->bad_req_id;
958 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
959 RTE_ETHDEV_QUEUE_STAT_CNTRS);
960 for (i = 0; i < max_rings_stats; ++i) {
961 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
963 stats->q_obytes[i] = tx_stats->bytes;
964 stats->q_opackets[i] = tx_stats->cnt;
970 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
972 struct ena_adapter *adapter;
973 struct ena_com_dev *ena_dev;
976 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
977 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
978 adapter = dev->data->dev_private;
980 ena_dev = &adapter->ena_dev;
981 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
983 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
985 "Invalid MTU setting. new_mtu: %d "
986 "max mtu: %d min mtu: %d\n",
987 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
991 rc = ena_com_set_dev_mtu(ena_dev, mtu);
993 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
995 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1000 static int ena_start(struct rte_eth_dev *dev)
1002 struct ena_adapter *adapter = dev->data->dev_private;
1006 rc = ena_check_valid_conf(adapter);
1010 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1014 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1018 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1019 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1020 rc = ena_rss_init_default(adapter);
1025 ena_stats_restart(dev);
1027 adapter->timestamp_wd = rte_get_timer_cycles();
1028 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1030 ticks = rte_get_timer_hz();
1031 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1032 ena_timer_wd_callback, adapter);
1034 ++adapter->dev_stats.dev_start;
1035 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1040 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1042 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1046 static void ena_stop(struct rte_eth_dev *dev)
1048 struct ena_adapter *adapter = dev->data->dev_private;
1049 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1052 rte_timer_stop_sync(&adapter->timer_wd);
1053 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1054 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1056 if (adapter->trigger_reset) {
1057 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1059 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1062 ++adapter->dev_stats.dev_stop;
1063 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1066 static int ena_create_io_queue(struct ena_ring *ring)
1068 struct ena_adapter *adapter;
1069 struct ena_com_dev *ena_dev;
1070 struct ena_com_create_io_ctx ctx =
1071 /* policy set to _HOST just to satisfy icc compiler */
1072 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1078 adapter = ring->adapter;
1079 ena_dev = &adapter->ena_dev;
1081 if (ring->type == ENA_RING_TYPE_TX) {
1082 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1083 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1084 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1085 ctx.queue_size = adapter->tx_ring_size;
1086 for (i = 0; i < ring->ring_size; i++)
1087 ring->empty_tx_reqs[i] = i;
1089 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1090 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1091 ctx.queue_size = adapter->rx_ring_size;
1092 for (i = 0; i < ring->ring_size; i++)
1093 ring->empty_rx_reqs[i] = i;
1096 ctx.msix_vector = -1; /* interrupts not used */
1097 ctx.numa_node = ring->numa_socket_id;
1099 rc = ena_com_create_io_queue(ena_dev, &ctx);
1102 "failed to create io queue #%d (qid:%d) rc: %d\n",
1103 ring->id, ena_qid, rc);
1107 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1108 &ring->ena_com_io_sq,
1109 &ring->ena_com_io_cq);
1112 "Failed to get io queue handlers. queue num %d rc: %d\n",
1114 ena_com_destroy_io_queue(ena_dev, ena_qid);
1118 if (ring->type == ENA_RING_TYPE_TX)
1119 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1124 static void ena_queue_stop(struct ena_ring *ring)
1126 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1128 if (ring->type == ENA_RING_TYPE_RX) {
1129 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1130 ena_rx_queue_release_bufs(ring);
1132 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1133 ena_tx_queue_release_bufs(ring);
1137 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1138 enum ena_ring_type ring_type)
1140 struct ena_adapter *adapter = dev->data->dev_private;
1141 struct ena_ring *queues = NULL;
1142 uint16_t nb_queues, i;
1144 if (ring_type == ENA_RING_TYPE_RX) {
1145 queues = adapter->rx_ring;
1146 nb_queues = dev->data->nb_rx_queues;
1148 queues = adapter->tx_ring;
1149 nb_queues = dev->data->nb_tx_queues;
1152 for (i = 0; i < nb_queues; ++i)
1153 if (queues[i].configured)
1154 ena_queue_stop(&queues[i]);
1157 static int ena_queue_start(struct ena_ring *ring)
1161 ena_assert_msg(ring->configured == 1,
1162 "Trying to start unconfigured queue\n");
1164 rc = ena_create_io_queue(ring);
1166 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1170 ring->next_to_clean = 0;
1171 ring->next_to_use = 0;
1173 if (ring->type == ENA_RING_TYPE_TX) {
1174 ring->tx_stats.available_desc =
1175 ena_com_free_q_entries(ring->ena_com_io_sq);
1179 bufs_num = ring->ring_size - 1;
1180 rc = ena_populate_rx_queue(ring, bufs_num);
1181 if (rc != bufs_num) {
1182 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1183 ENA_IO_RXQ_IDX(ring->id));
1184 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1185 return ENA_COM_FAULT;
1191 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1194 unsigned int socket_id,
1195 const struct rte_eth_txconf *tx_conf)
1197 struct ena_ring *txq = NULL;
1198 struct ena_adapter *adapter = dev->data->dev_private;
1201 txq = &adapter->tx_ring[queue_idx];
1203 if (txq->configured) {
1205 "API violation. Queue %d is already configured\n",
1207 return ENA_COM_FAULT;
1210 if (!rte_is_power_of_2(nb_desc)) {
1212 "Unsupported size of TX queue: %d is not a power of 2.\n",
1217 if (nb_desc > adapter->tx_ring_size) {
1219 "Unsupported size of TX queue (max size: %d)\n",
1220 adapter->tx_ring_size);
1224 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1225 nb_desc = adapter->tx_ring_size;
1227 txq->port_id = dev->data->port_id;
1228 txq->next_to_clean = 0;
1229 txq->next_to_use = 0;
1230 txq->ring_size = nb_desc;
1231 txq->numa_socket_id = socket_id;
1233 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1234 sizeof(struct ena_tx_buffer) *
1236 RTE_CACHE_LINE_SIZE);
1237 if (!txq->tx_buffer_info) {
1238 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1242 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1243 sizeof(u16) * txq->ring_size,
1244 RTE_CACHE_LINE_SIZE);
1245 if (!txq->empty_tx_reqs) {
1246 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1247 rte_free(txq->tx_buffer_info);
1251 txq->push_buf_intermediate_buf =
1252 rte_zmalloc("txq->push_buf_intermediate_buf",
1253 txq->tx_max_header_size,
1254 RTE_CACHE_LINE_SIZE);
1255 if (!txq->push_buf_intermediate_buf) {
1256 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1257 rte_free(txq->tx_buffer_info);
1258 rte_free(txq->empty_tx_reqs);
1262 for (i = 0; i < txq->ring_size; i++)
1263 txq->empty_tx_reqs[i] = i;
1265 if (tx_conf != NULL) {
1267 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1269 /* Store pointer to this queue in upper layer */
1270 txq->configured = 1;
1271 dev->data->tx_queues[queue_idx] = txq;
1276 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1279 unsigned int socket_id,
1280 __rte_unused const struct rte_eth_rxconf *rx_conf,
1281 struct rte_mempool *mp)
1283 struct ena_adapter *adapter = dev->data->dev_private;
1284 struct ena_ring *rxq = NULL;
1287 rxq = &adapter->rx_ring[queue_idx];
1288 if (rxq->configured) {
1290 "API violation. Queue %d is already configured\n",
1292 return ENA_COM_FAULT;
1295 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1296 nb_desc = adapter->rx_ring_size;
1298 if (!rte_is_power_of_2(nb_desc)) {
1300 "Unsupported size of RX queue: %d is not a power of 2.\n",
1305 if (nb_desc > adapter->rx_ring_size) {
1307 "Unsupported size of RX queue (max size: %d)\n",
1308 adapter->rx_ring_size);
1312 rxq->port_id = dev->data->port_id;
1313 rxq->next_to_clean = 0;
1314 rxq->next_to_use = 0;
1315 rxq->ring_size = nb_desc;
1316 rxq->numa_socket_id = socket_id;
1319 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1320 sizeof(struct rte_mbuf *) * nb_desc,
1321 RTE_CACHE_LINE_SIZE);
1322 if (!rxq->rx_buffer_info) {
1323 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1327 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1328 sizeof(struct rte_mbuf *) * nb_desc,
1329 RTE_CACHE_LINE_SIZE);
1331 if (!rxq->rx_refill_buffer) {
1332 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1333 rte_free(rxq->rx_buffer_info);
1334 rxq->rx_buffer_info = NULL;
1338 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1339 sizeof(uint16_t) * nb_desc,
1340 RTE_CACHE_LINE_SIZE);
1341 if (!rxq->empty_rx_reqs) {
1342 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1343 rte_free(rxq->rx_buffer_info);
1344 rxq->rx_buffer_info = NULL;
1345 rte_free(rxq->rx_refill_buffer);
1346 rxq->rx_refill_buffer = NULL;
1350 for (i = 0; i < nb_desc; i++)
1351 rxq->empty_rx_reqs[i] = i;
1353 /* Store pointer to this queue in upper layer */
1354 rxq->configured = 1;
1355 dev->data->rx_queues[queue_idx] = rxq;
1360 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1364 uint16_t ring_size = rxq->ring_size;
1365 uint16_t ring_mask = ring_size - 1;
1366 uint16_t next_to_use = rxq->next_to_use;
1367 uint16_t in_use, req_id;
1368 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1370 if (unlikely(!count))
1373 in_use = rxq->next_to_use - rxq->next_to_clean;
1374 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1376 /* get resources for incoming packets */
1377 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1378 if (unlikely(rc < 0)) {
1379 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1380 ++rxq->rx_stats.mbuf_alloc_fail;
1381 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1385 for (i = 0; i < count; i++) {
1386 uint16_t next_to_use_masked = next_to_use & ring_mask;
1387 struct rte_mbuf *mbuf = mbufs[i];
1388 struct ena_com_buf ebuf;
1390 if (likely((i + 4) < count))
1391 rte_prefetch0(mbufs[i + 4]);
1393 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1394 rc = validate_rx_req_id(rxq, req_id);
1395 if (unlikely(rc < 0))
1397 rxq->rx_buffer_info[req_id] = mbuf;
1399 /* prepare physical address for DMA transaction */
1400 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1401 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1402 /* pass resource to device */
1403 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1406 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1407 rxq->rx_buffer_info[req_id] = NULL;
1413 if (unlikely(i < count)) {
1414 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1415 "buffers (from %d)\n", rxq->id, i, count);
1416 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1418 ++rxq->rx_stats.refill_partial;
1421 /* When we submitted free recources to device... */
1422 if (likely(i > 0)) {
1423 /* ...let HW know that it can fill buffers with data
1425 * Add memory barrier to make sure the desc were written before
1429 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1431 rxq->next_to_use = next_to_use;
1437 static int ena_device_init(struct ena_com_dev *ena_dev,
1438 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1441 uint32_t aenq_groups;
1443 bool readless_supported;
1445 /* Initialize mmio registers */
1446 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1448 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1452 /* The PCIe configuration space revision id indicate if mmio reg
1455 readless_supported =
1456 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1457 & ENA_MMIO_DISABLE_REG_READ);
1458 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1461 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1463 PMD_DRV_LOG(ERR, "cannot reset device\n");
1464 goto err_mmio_read_less;
1467 /* check FW version */
1468 rc = ena_com_validate_version(ena_dev);
1470 PMD_DRV_LOG(ERR, "device version is too low\n");
1471 goto err_mmio_read_less;
1474 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1476 /* ENA device administration layer init */
1477 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1480 "cannot initialize ena admin queue with device\n");
1481 goto err_mmio_read_less;
1484 /* To enable the msix interrupts the driver needs to know the number
1485 * of queues. So the driver uses polling mode to retrieve this
1488 ena_com_set_admin_polling_mode(ena_dev, true);
1490 ena_config_host_info(ena_dev);
1492 /* Get Device Attributes and features */
1493 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1496 "cannot get attribute for ena device rc= %d\n", rc);
1497 goto err_admin_init;
1500 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1501 BIT(ENA_ADMIN_NOTIFICATION) |
1502 BIT(ENA_ADMIN_KEEP_ALIVE) |
1503 BIT(ENA_ADMIN_FATAL_ERROR) |
1504 BIT(ENA_ADMIN_WARNING);
1506 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1507 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1509 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1510 goto err_admin_init;
1513 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1518 ena_com_admin_destroy(ena_dev);
1521 ena_com_mmio_reg_read_request_destroy(ena_dev);
1526 static void ena_interrupt_handler_rte(void *cb_arg)
1528 struct ena_adapter *adapter = cb_arg;
1529 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1531 ena_com_admin_q_comp_intr_handler(ena_dev);
1532 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1533 ena_com_aenq_intr_handler(ena_dev, adapter);
1536 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1538 if (!adapter->wd_state)
1541 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1544 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1545 adapter->keep_alive_timeout)) {
1546 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1547 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1548 adapter->trigger_reset = true;
1549 ++adapter->dev_stats.wd_expired;
1553 /* Check if admin queue is enabled */
1554 static void check_for_admin_com_state(struct ena_adapter *adapter)
1556 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1557 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1558 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1559 adapter->trigger_reset = true;
1563 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1566 struct ena_adapter *adapter = arg;
1567 struct rte_eth_dev *dev = adapter->rte_dev;
1569 check_for_missing_keep_alive(adapter);
1570 check_for_admin_com_state(adapter);
1572 if (unlikely(adapter->trigger_reset)) {
1573 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1574 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1580 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1582 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1583 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1584 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1585 llq_config->llq_num_decs_before_header =
1586 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1587 llq_config->llq_ring_entry_size_value = 128;
1591 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1592 struct ena_com_dev *ena_dev,
1593 struct ena_admin_feature_llq_desc *llq,
1594 struct ena_llq_configurations *llq_default_configurations)
1597 u32 llq_feature_mask;
1599 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1600 if (!(ena_dev->supported_features & llq_feature_mask)) {
1602 "LLQ is not supported. Fallback to host mode policy.\n");
1603 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1607 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1609 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1610 "Fallback to host mode policy.");
1611 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1615 /* Nothing to config, exit */
1616 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1619 if (!adapter->dev_mem_base) {
1620 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1621 "Fallback to host mode policy.\n.");
1622 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1626 ena_dev->mem_bar = adapter->dev_mem_base;
1631 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1632 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1634 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1636 /* Regular queues capabilities */
1637 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1638 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1639 &get_feat_ctx->max_queue_ext.max_queue_ext;
1640 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1641 max_queue_ext->max_rx_cq_num);
1642 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1643 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1645 struct ena_admin_queue_feature_desc *max_queues =
1646 &get_feat_ctx->max_queues;
1647 io_tx_sq_num = max_queues->max_sq_num;
1648 io_tx_cq_num = max_queues->max_cq_num;
1649 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1652 /* In case of LLQ use the llq number in the get feature cmd */
1653 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1654 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1656 io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1657 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1658 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1660 if (unlikely(io_queue_num == 0)) {
1661 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1665 return io_queue_num;
1668 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1670 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1671 struct rte_pci_device *pci_dev;
1672 struct rte_intr_handle *intr_handle;
1673 struct ena_adapter *adapter = eth_dev->data->dev_private;
1674 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1675 struct ena_com_dev_get_features_ctx get_feat_ctx;
1676 struct ena_llq_configurations llq_config;
1677 const char *queue_type_str;
1680 static int adapters_found;
1683 eth_dev->dev_ops = &ena_dev_ops;
1684 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1685 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1686 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1688 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1691 memset(adapter, 0, sizeof(struct ena_adapter));
1692 ena_dev = &adapter->ena_dev;
1694 adapter->rte_eth_dev_data = eth_dev->data;
1695 adapter->rte_dev = eth_dev;
1697 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1698 adapter->pdev = pci_dev;
1700 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1701 pci_dev->addr.domain,
1703 pci_dev->addr.devid,
1704 pci_dev->addr.function);
1706 intr_handle = &pci_dev->intr_handle;
1708 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1709 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1711 if (!adapter->regs) {
1712 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1717 ena_dev->reg_bar = adapter->regs;
1718 ena_dev->dmadev = adapter->pdev;
1720 adapter->id_number = adapters_found;
1722 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1723 adapter->id_number);
1725 /* device specific initialization routine */
1726 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1728 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1731 adapter->wd_state = wd_state;
1733 set_default_llq_configurations(&llq_config);
1734 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1735 &get_feat_ctx.llq, &llq_config);
1737 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1741 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1742 queue_type_str = "Regular";
1744 queue_type_str = "Low latency";
1745 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1747 calc_queue_ctx.ena_dev = ena_dev;
1748 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1749 adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1752 rc = ena_calc_queue_size(&calc_queue_ctx);
1753 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1755 goto err_device_destroy;
1758 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1759 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1761 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1762 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1764 /* prepare ring structures */
1765 ena_init_rings(adapter);
1767 ena_config_debug_area(adapter);
1769 /* Set max MTU for this device */
1770 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1772 /* set device support for offloads */
1773 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1774 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1775 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1776 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1777 adapter->offloads.rx_csum_supported =
1778 (get_feat_ctx.offload.rx_supported &
1779 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1781 /* Copy MAC address and point DPDK to it */
1782 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1783 rte_ether_addr_copy((struct rte_ether_addr *)
1784 get_feat_ctx.dev_attr.mac_addr,
1785 (struct rte_ether_addr *)adapter->mac_addr);
1788 * Pass the information to the rte_eth_dev_close() that it should also
1789 * release the private port resources.
1791 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1793 adapter->drv_stats = rte_zmalloc("adapter stats",
1794 sizeof(*adapter->drv_stats),
1795 RTE_CACHE_LINE_SIZE);
1796 if (!adapter->drv_stats) {
1797 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1799 goto err_delete_debug_area;
1802 rte_intr_callback_register(intr_handle,
1803 ena_interrupt_handler_rte,
1805 rte_intr_enable(intr_handle);
1806 ena_com_set_admin_polling_mode(ena_dev, false);
1807 ena_com_admin_aenq_enable(ena_dev);
1809 if (adapters_found == 0)
1810 rte_timer_subsystem_init();
1811 rte_timer_init(&adapter->timer_wd);
1814 adapter->state = ENA_ADAPTER_STATE_INIT;
1818 err_delete_debug_area:
1819 ena_com_delete_debug_area(ena_dev);
1822 ena_com_delete_host_info(ena_dev);
1823 ena_com_admin_destroy(ena_dev);
1829 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1831 struct ena_adapter *adapter = eth_dev->data->dev_private;
1832 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1834 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1837 ena_com_set_admin_running_state(ena_dev, false);
1839 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1842 ena_com_delete_debug_area(ena_dev);
1843 ena_com_delete_host_info(ena_dev);
1845 ena_com_abort_admin_commands(ena_dev);
1846 ena_com_wait_for_abort_completion(ena_dev);
1847 ena_com_admin_destroy(ena_dev);
1848 ena_com_mmio_reg_read_request_destroy(ena_dev);
1850 adapter->state = ENA_ADAPTER_STATE_FREE;
1853 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1855 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1858 ena_destroy_device(eth_dev);
1860 eth_dev->dev_ops = NULL;
1861 eth_dev->rx_pkt_burst = NULL;
1862 eth_dev->tx_pkt_burst = NULL;
1863 eth_dev->tx_pkt_prepare = NULL;
1868 static int ena_dev_configure(struct rte_eth_dev *dev)
1870 struct ena_adapter *adapter = dev->data->dev_private;
1872 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1874 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1875 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1879 static void ena_init_rings(struct ena_adapter *adapter)
1883 for (i = 0; i < adapter->num_queues; i++) {
1884 struct ena_ring *ring = &adapter->tx_ring[i];
1886 ring->configured = 0;
1887 ring->type = ENA_RING_TYPE_TX;
1888 ring->adapter = adapter;
1890 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1891 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1892 ring->sgl_size = adapter->max_tx_sgl_size;
1895 for (i = 0; i < adapter->num_queues; i++) {
1896 struct ena_ring *ring = &adapter->rx_ring[i];
1898 ring->configured = 0;
1899 ring->type = ENA_RING_TYPE_RX;
1900 ring->adapter = adapter;
1902 ring->sgl_size = adapter->max_rx_sgl_size;
1906 static int ena_infos_get(struct rte_eth_dev *dev,
1907 struct rte_eth_dev_info *dev_info)
1909 struct ena_adapter *adapter;
1910 struct ena_com_dev *ena_dev;
1911 uint64_t rx_feat = 0, tx_feat = 0;
1913 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1914 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1915 adapter = dev->data->dev_private;
1917 ena_dev = &adapter->ena_dev;
1918 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1920 dev_info->speed_capa =
1922 ETH_LINK_SPEED_2_5G |
1924 ETH_LINK_SPEED_10G |
1925 ETH_LINK_SPEED_25G |
1926 ETH_LINK_SPEED_40G |
1927 ETH_LINK_SPEED_50G |
1928 ETH_LINK_SPEED_100G;
1930 /* Set Tx & Rx features available for device */
1931 if (adapter->offloads.tso4_supported)
1932 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1934 if (adapter->offloads.tx_csum_supported)
1935 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1936 DEV_TX_OFFLOAD_UDP_CKSUM |
1937 DEV_TX_OFFLOAD_TCP_CKSUM;
1939 if (adapter->offloads.rx_csum_supported)
1940 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1941 DEV_RX_OFFLOAD_UDP_CKSUM |
1942 DEV_RX_OFFLOAD_TCP_CKSUM;
1944 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1946 /* Inform framework about available features */
1947 dev_info->rx_offload_capa = rx_feat;
1948 dev_info->rx_queue_offload_capa = rx_feat;
1949 dev_info->tx_offload_capa = tx_feat;
1950 dev_info->tx_queue_offload_capa = tx_feat;
1952 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1955 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1956 dev_info->max_rx_pktlen = adapter->max_mtu;
1957 dev_info->max_mac_addrs = 1;
1959 dev_info->max_rx_queues = adapter->num_queues;
1960 dev_info->max_tx_queues = adapter->num_queues;
1961 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1963 adapter->tx_supported_offloads = tx_feat;
1964 adapter->rx_supported_offloads = rx_feat;
1966 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1967 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1968 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1969 adapter->max_rx_sgl_size);
1970 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1971 adapter->max_rx_sgl_size);
1973 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1974 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1975 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1976 adapter->max_tx_sgl_size);
1977 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1978 adapter->max_tx_sgl_size);
1983 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1986 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1987 unsigned int ring_size = rx_ring->ring_size;
1988 unsigned int ring_mask = ring_size - 1;
1989 uint16_t next_to_clean = rx_ring->next_to_clean;
1990 uint16_t desc_in_use = 0;
1992 unsigned int recv_idx = 0;
1993 struct rte_mbuf *mbuf = NULL;
1994 struct rte_mbuf *mbuf_head = NULL;
1995 struct rte_mbuf *mbuf_prev = NULL;
1996 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1997 unsigned int completed;
1999 struct ena_com_rx_ctx ena_rx_ctx;
2002 /* Check adapter state */
2003 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2005 "Trying to receive pkts while device is NOT running\n");
2009 desc_in_use = rx_ring->next_to_use - next_to_clean;
2010 if (unlikely(nb_pkts > desc_in_use))
2011 nb_pkts = desc_in_use;
2013 for (completed = 0; completed < nb_pkts; completed++) {
2016 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2017 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2018 ena_rx_ctx.descs = 0;
2019 ena_rx_ctx.pkt_offset = 0;
2020 /* receive packet context */
2021 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2022 rx_ring->ena_com_io_sq,
2025 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2026 rx_ring->adapter->reset_reason =
2027 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2028 rx_ring->adapter->trigger_reset = true;
2029 ++rx_ring->rx_stats.bad_desc_num;
2033 if (unlikely(ena_rx_ctx.descs == 0))
2036 while (segments < ena_rx_ctx.descs) {
2037 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2038 rc = validate_rx_req_id(rx_ring, req_id);
2041 rte_mbuf_raw_free(mbuf_head);
2045 mbuf = rx_buff_info[req_id];
2046 rx_buff_info[req_id] = NULL;
2047 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2048 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2051 if (unlikely(segments == 0)) {
2052 mbuf->nb_segs = ena_rx_ctx.descs;
2053 mbuf->port = rx_ring->port_id;
2055 mbuf->data_off += ena_rx_ctx.pkt_offset;
2058 /* for multi-segment pkts create mbuf chain */
2059 mbuf_prev->next = mbuf;
2061 mbuf_head->pkt_len += mbuf->data_len;
2064 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2072 /* fill mbuf attributes if any */
2073 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2075 if (unlikely(mbuf_head->ol_flags &
2076 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2077 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2078 ++rx_ring->rx_stats.bad_csum;
2081 mbuf_head->hash.rss = ena_rx_ctx.hash;
2083 /* pass to DPDK application head mbuf */
2084 rx_pkts[recv_idx] = mbuf_head;
2086 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2089 rx_ring->rx_stats.cnt += recv_idx;
2090 rx_ring->next_to_clean = next_to_clean;
2092 desc_in_use = desc_in_use - completed + 1;
2093 /* Burst refill to save doorbells, memory barriers, const interval */
2094 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2095 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2096 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2103 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2109 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2110 struct rte_ipv4_hdr *ip_hdr;
2112 uint16_t frag_field;
2114 for (i = 0; i != nb_pkts; i++) {
2116 ol_flags = m->ol_flags;
2118 if (!(ol_flags & PKT_TX_IPV4))
2121 /* If there was not L2 header length specified, assume it is
2122 * length of the ethernet header.
2124 if (unlikely(m->l2_len == 0))
2125 m->l2_len = sizeof(struct rte_ether_hdr);
2127 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2129 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2131 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2132 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2134 /* If IPv4 header has DF flag enabled and TSO support is
2135 * disabled, partial chcecksum should not be calculated.
2137 if (!tx_ring->adapter->offloads.tso4_supported)
2141 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2142 (ol_flags & PKT_TX_L4_MASK) ==
2143 PKT_TX_SCTP_CKSUM) {
2144 rte_errno = ENOTSUP;
2148 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2149 ret = rte_validate_tx_offload(m);
2156 /* In case we are supposed to TSO and have DF not set (DF=0)
2157 * hardware must be provided with partial checksum, otherwise
2158 * it will take care of necessary calculations.
2161 ret = rte_net_intel_cksum_flags_prepare(m,
2162 ol_flags & ~PKT_TX_TCP_SEG);
2172 static void ena_update_hints(struct ena_adapter *adapter,
2173 struct ena_admin_ena_hw_hints *hints)
2175 if (hints->admin_completion_tx_timeout)
2176 adapter->ena_dev.admin_queue.completion_timeout =
2177 hints->admin_completion_tx_timeout * 1000;
2179 if (hints->mmio_read_timeout)
2180 /* convert to usec */
2181 adapter->ena_dev.mmio_read.reg_read_to =
2182 hints->mmio_read_timeout * 1000;
2184 if (hints->driver_watchdog_timeout) {
2185 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2186 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2188 // Convert msecs to ticks
2189 adapter->keep_alive_timeout =
2190 (hints->driver_watchdog_timeout *
2191 rte_get_timer_hz()) / 1000;
2195 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2196 struct rte_mbuf *mbuf)
2198 struct ena_com_dev *ena_dev;
2199 int num_segments, header_len, rc;
2201 ena_dev = &tx_ring->adapter->ena_dev;
2202 num_segments = mbuf->nb_segs;
2203 header_len = mbuf->data_len;
2205 if (likely(num_segments < tx_ring->sgl_size))
2208 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2209 (num_segments == tx_ring->sgl_size) &&
2210 (header_len < tx_ring->tx_max_header_size))
2213 ++tx_ring->tx_stats.linearize;
2214 rc = rte_pktmbuf_linearize(mbuf);
2216 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2217 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2218 ++tx_ring->tx_stats.linearize_failed;
2225 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2228 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2229 uint16_t next_to_use = tx_ring->next_to_use;
2230 uint16_t next_to_clean = tx_ring->next_to_clean;
2231 struct rte_mbuf *mbuf;
2233 unsigned int ring_size = tx_ring->ring_size;
2234 unsigned int ring_mask = ring_size - 1;
2235 struct ena_com_tx_ctx ena_tx_ctx;
2236 struct ena_tx_buffer *tx_info;
2237 struct ena_com_buf *ebuf;
2238 uint16_t rc, req_id, total_tx_descs = 0;
2239 uint16_t sent_idx = 0, empty_tx_reqs;
2240 uint16_t push_len = 0;
2243 uint32_t total_length;
2245 /* Check adapter state */
2246 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2248 "Trying to xmit pkts while device is NOT running\n");
2252 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2253 if (nb_pkts > empty_tx_reqs)
2254 nb_pkts = empty_tx_reqs;
2256 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2257 mbuf = tx_pkts[sent_idx];
2260 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2264 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2265 tx_info = &tx_ring->tx_buffer_info[req_id];
2266 tx_info->mbuf = mbuf;
2267 tx_info->num_of_bufs = 0;
2268 ebuf = tx_info->bufs;
2270 /* Prepare TX context */
2271 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2272 memset(&ena_tx_ctx.ena_meta, 0x0,
2273 sizeof(struct ena_com_tx_meta));
2274 ena_tx_ctx.ena_bufs = ebuf;
2275 ena_tx_ctx.req_id = req_id;
2278 seg_len = mbuf->data_len;
2280 if (tx_ring->tx_mem_queue_type ==
2281 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2282 push_len = RTE_MIN(mbuf->pkt_len,
2283 tx_ring->tx_max_header_size);
2284 ena_tx_ctx.header_len = push_len;
2286 if (likely(push_len <= seg_len)) {
2287 /* If the push header is in the single segment,
2288 * then just point it to the 1st mbuf data.
2290 ena_tx_ctx.push_header =
2291 rte_pktmbuf_mtod(mbuf, uint8_t *);
2293 /* If the push header lays in the several
2294 * segments, copy it to the intermediate buffer.
2296 rte_pktmbuf_read(mbuf, 0, push_len,
2297 tx_ring->push_buf_intermediate_buf);
2298 ena_tx_ctx.push_header =
2299 tx_ring->push_buf_intermediate_buf;
2300 delta = push_len - seg_len;
2302 } /* there's no else as we take advantage of memset zeroing */
2304 /* Set TX offloads flags, if applicable */
2305 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2307 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2309 /* Process first segment taking into
2310 * consideration pushed header
2312 if (seg_len > push_len) {
2313 ebuf->paddr = mbuf->buf_iova +
2316 ebuf->len = seg_len - push_len;
2318 tx_info->num_of_bufs++;
2320 total_length += mbuf->data_len;
2322 while ((mbuf = mbuf->next) != NULL) {
2323 seg_len = mbuf->data_len;
2325 /* Skip mbufs if whole data is pushed as a header */
2326 if (unlikely(delta > seg_len)) {
2331 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2332 ebuf->len = seg_len - delta;
2333 total_length += ebuf->len;
2335 tx_info->num_of_bufs++;
2340 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2342 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2344 PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2345 " achieved, writing doorbell to send burst\n",
2348 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2351 /* prepare the packet's descriptors to dma engine */
2352 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2353 &ena_tx_ctx, &nb_hw_desc);
2355 ++tx_ring->tx_stats.prepare_ctx_err;
2358 tx_info->tx_descs = nb_hw_desc;
2361 tx_ring->tx_stats.cnt++;
2362 tx_ring->tx_stats.bytes += total_length;
2364 tx_ring->tx_stats.available_desc =
2365 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2367 /* If there are ready packets to be xmitted... */
2369 /* ...let HW do its best :-) */
2371 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2372 tx_ring->tx_stats.doorbells++;
2373 tx_ring->next_to_use = next_to_use;
2376 /* Clear complete packets */
2377 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2378 rc = validate_tx_req_id(tx_ring, req_id);
2382 /* Get Tx info & store how many descs were processed */
2383 tx_info = &tx_ring->tx_buffer_info[req_id];
2384 total_tx_descs += tx_info->tx_descs;
2386 /* Free whole mbuf chain */
2387 mbuf = tx_info->mbuf;
2388 rte_pktmbuf_free(mbuf);
2389 tx_info->mbuf = NULL;
2391 /* Put back descriptor to the ring for reuse */
2392 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2395 /* If too many descs to clean, leave it for another run */
2396 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2399 tx_ring->tx_stats.available_desc =
2400 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2402 if (total_tx_descs > 0) {
2403 /* acknowledge completion of sent packets */
2404 tx_ring->next_to_clean = next_to_clean;
2405 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2406 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2409 tx_ring->tx_stats.tx_poll++;
2415 * DPDK callback to retrieve names of extended device statistics
2418 * Pointer to Ethernet device structure.
2419 * @param[out] xstats_names
2420 * Buffer to insert names into.
2425 * Number of xstats names.
2427 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2428 struct rte_eth_xstat_name *xstats_names,
2431 unsigned int xstats_count = ena_xstats_calc_num(dev);
2432 unsigned int stat, i, count = 0;
2434 if (n < xstats_count || !xstats_names)
2435 return xstats_count;
2437 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2438 strcpy(xstats_names[count].name,
2439 ena_stats_global_strings[stat].name);
2441 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2442 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2443 snprintf(xstats_names[count].name,
2444 sizeof(xstats_names[count].name),
2446 ena_stats_rx_strings[stat].name);
2448 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2449 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2450 snprintf(xstats_names[count].name,
2451 sizeof(xstats_names[count].name),
2453 ena_stats_tx_strings[stat].name);
2455 return xstats_count;
2459 * DPDK callback to get extended device statistics.
2462 * Pointer to Ethernet device structure.
2464 * Stats table output buffer.
2466 * The size of the stats table.
2469 * Number of xstats on success, negative on failure.
2471 static int ena_xstats_get(struct rte_eth_dev *dev,
2472 struct rte_eth_xstat *xstats,
2475 struct ena_adapter *adapter = dev->data->dev_private;
2476 unsigned int xstats_count = ena_xstats_calc_num(dev);
2477 unsigned int stat, i, count = 0;
2481 if (n < xstats_count)
2482 return xstats_count;
2487 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2488 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2489 stats_begin = &adapter->dev_stats;
2491 xstats[count].id = count;
2492 xstats[count].value = *((uint64_t *)
2493 ((char *)stats_begin + stat_offset));
2496 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2497 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2498 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2499 stats_begin = &adapter->rx_ring[i].rx_stats;
2501 xstats[count].id = count;
2502 xstats[count].value = *((uint64_t *)
2503 ((char *)stats_begin + stat_offset));
2507 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2508 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2509 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2510 stats_begin = &adapter->tx_ring[i].rx_stats;
2512 xstats[count].id = count;
2513 xstats[count].value = *((uint64_t *)
2514 ((char *)stats_begin + stat_offset));
2521 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2522 const uint64_t *ids,
2526 struct ena_adapter *adapter = dev->data->dev_private;
2528 uint64_t rx_entries, tx_entries;
2532 for (i = 0; i < n; ++i) {
2534 /* Check if id belongs to global statistics */
2535 if (id < ENA_STATS_ARRAY_GLOBAL) {
2536 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2541 /* Check if id belongs to rx queue statistics */
2542 id -= ENA_STATS_ARRAY_GLOBAL;
2543 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2544 if (id < rx_entries) {
2545 qid = id % dev->data->nb_rx_queues;
2546 id /= dev->data->nb_rx_queues;
2547 values[i] = *((uint64_t *)
2548 &adapter->rx_ring[qid].rx_stats + id);
2552 /* Check if id belongs to rx queue statistics */
2554 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2555 if (id < tx_entries) {
2556 qid = id % dev->data->nb_tx_queues;
2557 id /= dev->data->nb_tx_queues;
2558 values[i] = *((uint64_t *)
2559 &adapter->tx_ring[qid].tx_stats + id);
2568 /*********************************************************************
2570 *********************************************************************/
2571 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2572 struct rte_pci_device *pci_dev)
2574 return rte_eth_dev_pci_generic_probe(pci_dev,
2575 sizeof(struct ena_adapter), eth_ena_dev_init);
2578 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2580 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2583 static struct rte_pci_driver rte_ena_pmd = {
2584 .id_table = pci_id_ena_map,
2585 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2586 RTE_PCI_DRV_WC_ACTIVATE,
2587 .probe = eth_ena_pci_probe,
2588 .remove = eth_ena_pci_remove,
2591 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2592 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2593 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2595 RTE_INIT(ena_init_log)
2597 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2598 if (ena_logtype_init >= 0)
2599 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2600 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2601 if (ena_logtype_driver >= 0)
2602 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2604 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2605 ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2606 if (ena_logtype_rx >= 0)
2607 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2610 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2611 ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2612 if (ena_logtype_tx >= 0)
2613 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2616 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2617 ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2618 if (ena_logtype_tx_free >= 0)
2619 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2622 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2623 ena_logtype_com = rte_log_register("pmd.net.ena.com");
2624 if (ena_logtype_com >= 0)
2625 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2629 /******************************************************************************
2630 ******************************** AENQ Handlers *******************************
2631 *****************************************************************************/
2632 static void ena_update_on_link_change(void *adapter_data,
2633 struct ena_admin_aenq_entry *aenq_e)
2635 struct rte_eth_dev *eth_dev;
2636 struct ena_adapter *adapter;
2637 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2640 adapter = adapter_data;
2641 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2642 eth_dev = adapter->rte_dev;
2644 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2645 adapter->link_status = status;
2647 ena_link_update(eth_dev, 0);
2648 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2651 static void ena_notification(void *data,
2652 struct ena_admin_aenq_entry *aenq_e)
2654 struct ena_adapter *adapter = data;
2655 struct ena_admin_ena_hw_hints *hints;
2657 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2658 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2659 aenq_e->aenq_common_desc.group,
2660 ENA_ADMIN_NOTIFICATION);
2662 switch (aenq_e->aenq_common_desc.syndrom) {
2663 case ENA_ADMIN_UPDATE_HINTS:
2664 hints = (struct ena_admin_ena_hw_hints *)
2665 (&aenq_e->inline_data_w4);
2666 ena_update_hints(adapter, hints);
2669 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2670 aenq_e->aenq_common_desc.syndrom);
2674 static void ena_keep_alive(void *adapter_data,
2675 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2677 struct ena_adapter *adapter = adapter_data;
2678 struct ena_admin_aenq_keep_alive_desc *desc;
2681 adapter->timestamp_wd = rte_get_timer_cycles();
2683 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2684 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2685 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops);
2689 * This handler will called for unknown event group or unimplemented handlers
2691 static void unimplemented_aenq_handler(__rte_unused void *data,
2692 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2694 PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2695 "unimplemented handler\n");
2698 static struct ena_aenq_handlers aenq_handlers = {
2700 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2701 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2702 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2704 .unimplemented_handler = unimplemented_aenq_handler