4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 0
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 enum ethtool_stringset {
94 char name[ETH_GSTRING_LEN];
98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
103 #define ENA_STAT_ENTRY(stat, stat_type) { \
105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
108 #define ENA_STAT_RX_ENTRY(stat) \
109 ENA_STAT_ENTRY(stat, rx)
111 #define ENA_STAT_TX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, tx)
114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, dev)
117 static const struct ena_stats ena_stats_global_strings[] = {
118 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
119 ENA_STAT_GLOBAL_ENTRY(io_suspend),
120 ENA_STAT_GLOBAL_ENTRY(io_resume),
121 ENA_STAT_GLOBAL_ENTRY(wd_expired),
122 ENA_STAT_GLOBAL_ENTRY(interface_up),
123 ENA_STAT_GLOBAL_ENTRY(interface_down),
124 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
127 static const struct ena_stats ena_stats_tx_strings[] = {
128 ENA_STAT_TX_ENTRY(cnt),
129 ENA_STAT_TX_ENTRY(bytes),
130 ENA_STAT_TX_ENTRY(queue_stop),
131 ENA_STAT_TX_ENTRY(queue_wakeup),
132 ENA_STAT_TX_ENTRY(dma_mapping_err),
133 ENA_STAT_TX_ENTRY(linearize),
134 ENA_STAT_TX_ENTRY(linearize_failed),
135 ENA_STAT_TX_ENTRY(tx_poll),
136 ENA_STAT_TX_ENTRY(doorbells),
137 ENA_STAT_TX_ENTRY(prepare_ctx_err),
138 ENA_STAT_TX_ENTRY(missing_tx_comp),
139 ENA_STAT_TX_ENTRY(bad_req_id),
142 static const struct ena_stats ena_stats_rx_strings[] = {
143 ENA_STAT_RX_ENTRY(cnt),
144 ENA_STAT_RX_ENTRY(bytes),
145 ENA_STAT_RX_ENTRY(refil_partial),
146 ENA_STAT_RX_ENTRY(bad_csum),
147 ENA_STAT_RX_ENTRY(page_alloc_fail),
148 ENA_STAT_RX_ENTRY(skb_alloc_fail),
149 ENA_STAT_RX_ENTRY(dma_mapping_err),
150 ENA_STAT_RX_ENTRY(bad_desc_num),
151 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
154 static const struct ena_stats ena_stats_ena_com_strings[] = {
155 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
156 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
157 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
158 ENA_STAT_ENA_COM_ENTRY(out_of_space),
159 ENA_STAT_ENA_COM_ENTRY(no_completion),
162 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
163 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
164 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
167 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
168 DEV_TX_OFFLOAD_UDP_CKSUM |\
169 DEV_TX_OFFLOAD_IPV4_CKSUM |\
170 DEV_TX_OFFLOAD_TCP_TSO)
171 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
175 /** Vendor ID used by Amazon devices */
176 #define PCI_VENDOR_ID_AMAZON 0x1D0F
177 /** Amazon devices */
178 #define PCI_DEVICE_ID_ENA_VF 0xEC20
179 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
181 #define ENA_TX_OFFLOAD_MASK (\
186 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
187 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
189 int ena_logtype_init;
190 int ena_logtype_driver;
192 static const struct rte_pci_id pci_id_ena_map[] = {
193 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
194 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
198 static int ena_device_init(struct ena_com_dev *ena_dev,
199 struct ena_com_dev_get_features_ctx *get_feat_ctx);
200 static int ena_dev_configure(struct rte_eth_dev *dev);
201 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
203 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
205 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
206 uint16_t nb_desc, unsigned int socket_id,
207 const struct rte_eth_txconf *tx_conf);
208 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
209 uint16_t nb_desc, unsigned int socket_id,
210 const struct rte_eth_rxconf *rx_conf,
211 struct rte_mempool *mp);
212 static uint16_t eth_ena_recv_pkts(void *rx_queue,
213 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
214 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
215 static void ena_init_rings(struct ena_adapter *adapter);
216 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
217 static int ena_start(struct rte_eth_dev *dev);
218 static void ena_close(struct rte_eth_dev *dev);
219 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
220 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
221 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
222 static void ena_rx_queue_release(void *queue);
223 static void ena_tx_queue_release(void *queue);
224 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
225 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
226 static int ena_link_update(struct rte_eth_dev *dev,
227 int wait_to_complete);
228 static int ena_queue_restart(struct ena_ring *ring);
229 static int ena_queue_restart_all(struct rte_eth_dev *dev,
230 enum ena_ring_type ring_type);
231 static void ena_stats_restart(struct rte_eth_dev *dev);
232 static void ena_infos_get(struct rte_eth_dev *dev,
233 struct rte_eth_dev_info *dev_info);
234 static int ena_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ena_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
241 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
243 static bool ena_are_rx_queue_offloads_allowed(struct ena_adapter *adapter,
246 static const struct eth_dev_ops ena_dev_ops = {
247 .dev_configure = ena_dev_configure,
248 .dev_infos_get = ena_infos_get,
249 .rx_queue_setup = ena_rx_queue_setup,
250 .tx_queue_setup = ena_tx_queue_setup,
251 .dev_start = ena_start,
252 .link_update = ena_link_update,
253 .stats_get = ena_stats_get,
254 .mtu_set = ena_mtu_set,
255 .rx_queue_release = ena_rx_queue_release,
256 .tx_queue_release = ena_tx_queue_release,
257 .dev_close = ena_close,
258 .reta_update = ena_rss_reta_update,
259 .reta_query = ena_rss_reta_query,
262 #define NUMA_NO_NODE SOCKET_ID_ANY
264 static inline int ena_cpu_to_node(int cpu)
266 struct rte_config *config = rte_eal_get_configuration();
268 if (likely(cpu < RTE_MAX_MEMZONE))
269 return config->mem_config->memzone[cpu].socket_id;
274 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
275 struct ena_com_rx_ctx *ena_rx_ctx)
277 uint64_t ol_flags = 0;
279 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
280 ol_flags |= PKT_TX_TCP_CKSUM;
281 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
282 ol_flags |= PKT_TX_UDP_CKSUM;
284 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
285 ol_flags |= PKT_TX_IPV4;
286 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
287 ol_flags |= PKT_TX_IPV6;
289 if (unlikely(ena_rx_ctx->l4_csum_err))
290 ol_flags |= PKT_RX_L4_CKSUM_BAD;
291 if (unlikely(ena_rx_ctx->l3_csum_err))
292 ol_flags |= PKT_RX_IP_CKSUM_BAD;
294 mbuf->ol_flags = ol_flags;
297 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
298 struct ena_com_tx_ctx *ena_tx_ctx,
299 uint64_t queue_offloads)
301 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
303 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
304 (queue_offloads & QUEUE_OFFLOADS)) {
305 /* check if TSO is required */
306 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
307 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
308 ena_tx_ctx->tso_enable = true;
310 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
313 /* check if L3 checksum is needed */
314 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
315 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
316 ena_tx_ctx->l3_csum_enable = true;
318 if (mbuf->ol_flags & PKT_TX_IPV6) {
319 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
321 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
323 /* set don't fragment (DF) flag */
324 if (mbuf->packet_type &
325 (RTE_PTYPE_L4_NONFRAG
326 | RTE_PTYPE_INNER_L4_NONFRAG))
327 ena_tx_ctx->df = true;
330 /* check if L4 checksum is needed */
331 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
332 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
333 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
334 ena_tx_ctx->l4_csum_enable = true;
335 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
336 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
337 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
338 ena_tx_ctx->l4_csum_enable = true;
340 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
341 ena_tx_ctx->l4_csum_enable = false;
344 ena_meta->mss = mbuf->tso_segsz;
345 ena_meta->l3_hdr_len = mbuf->l3_len;
346 ena_meta->l3_hdr_offset = mbuf->l2_len;
347 /* this param needed only for TSO */
348 ena_meta->l3_outer_hdr_len = 0;
349 ena_meta->l3_outer_hdr_offset = 0;
351 ena_tx_ctx->meta_valid = true;
353 ena_tx_ctx->meta_valid = false;
357 static void ena_config_host_info(struct ena_com_dev *ena_dev)
359 struct ena_admin_host_info *host_info;
362 /* Allocate only the host info */
363 rc = ena_com_allocate_host_info(ena_dev);
365 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
369 host_info = ena_dev->host_attr.host_info;
371 host_info->os_type = ENA_ADMIN_OS_DPDK;
372 host_info->kernel_ver = RTE_VERSION;
373 snprintf((char *)host_info->kernel_ver_str,
374 sizeof(host_info->kernel_ver_str),
375 "%s", rte_version());
376 host_info->os_dist = RTE_VERSION;
377 snprintf((char *)host_info->os_dist_str,
378 sizeof(host_info->os_dist_str),
379 "%s", rte_version());
380 host_info->driver_version =
381 (DRV_MODULE_VER_MAJOR) |
382 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
383 (DRV_MODULE_VER_SUBMINOR <<
384 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
386 rc = ena_com_set_host_attributes(ena_dev);
388 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
396 ena_com_delete_host_info(ena_dev);
400 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
402 if (sset != ETH_SS_STATS)
405 /* Workaround for clang:
406 * touch internal structures to prevent
409 ENA_TOUCH(ena_stats_global_strings);
410 ENA_TOUCH(ena_stats_tx_strings);
411 ENA_TOUCH(ena_stats_rx_strings);
412 ENA_TOUCH(ena_stats_ena_com_strings);
414 return dev->data->nb_tx_queues *
415 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
416 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
419 static void ena_config_debug_area(struct ena_adapter *adapter)
424 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
426 RTE_LOG(ERR, PMD, "SS count is negative\n");
430 /* allocate 32 bytes for each string and 64bit for the value */
431 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
433 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
435 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
439 rc = ena_com_set_host_attributes(&adapter->ena_dev);
441 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
448 ena_com_delete_debug_area(&adapter->ena_dev);
451 static void ena_close(struct rte_eth_dev *dev)
453 struct ena_adapter *adapter =
454 (struct ena_adapter *)(dev->data->dev_private);
456 adapter->state = ENA_ADAPTER_STATE_STOPPED;
458 ena_rx_queue_release_all(dev);
459 ena_tx_queue_release_all(dev);
462 static int ena_rss_reta_update(struct rte_eth_dev *dev,
463 struct rte_eth_rss_reta_entry64 *reta_conf,
466 struct ena_adapter *adapter =
467 (struct ena_adapter *)(dev->data->dev_private);
468 struct ena_com_dev *ena_dev = &adapter->ena_dev;
474 if ((reta_size == 0) || (reta_conf == NULL))
477 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
478 RTE_LOG(WARNING, PMD,
479 "indirection table %d is bigger than supported (%d)\n",
480 reta_size, ENA_RX_RSS_TABLE_SIZE);
485 for (i = 0 ; i < reta_size ; i++) {
486 /* each reta_conf is for 64 entries.
487 * to support 128 we use 2 conf of 64
489 conf_idx = i / RTE_RETA_GROUP_SIZE;
490 idx = i % RTE_RETA_GROUP_SIZE;
491 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
493 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
494 ret = ena_com_indirect_table_fill_entry(ena_dev,
497 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
499 "Cannot fill indirect table\n");
506 ret = ena_com_indirect_table_set(ena_dev);
507 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
508 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
513 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
514 __func__, reta_size, adapter->rte_dev->data->port_id);
519 /* Query redirection table. */
520 static int ena_rss_reta_query(struct rte_eth_dev *dev,
521 struct rte_eth_rss_reta_entry64 *reta_conf,
524 struct ena_adapter *adapter =
525 (struct ena_adapter *)(dev->data->dev_private);
526 struct ena_com_dev *ena_dev = &adapter->ena_dev;
529 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
533 if (reta_size == 0 || reta_conf == NULL ||
534 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
537 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
538 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
539 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
544 for (i = 0 ; i < reta_size ; i++) {
545 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
546 reta_idx = i % RTE_RETA_GROUP_SIZE;
547 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
548 reta_conf[reta_conf_idx].reta[reta_idx] =
549 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
555 static int ena_rss_init_default(struct ena_adapter *adapter)
557 struct ena_com_dev *ena_dev = &adapter->ena_dev;
558 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
562 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
564 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
568 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
569 val = i % nb_rx_queues;
570 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
571 ENA_IO_RXQ_IDX(val));
572 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
573 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
578 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
579 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
580 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
581 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
585 rc = ena_com_set_default_hash_ctrl(ena_dev);
586 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
587 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
591 rc = ena_com_indirect_table_set(ena_dev);
592 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
593 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
596 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
597 adapter->rte_dev->data->port_id);
602 ena_com_rss_destroy(ena_dev);
608 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
610 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
611 int nb_queues = dev->data->nb_rx_queues;
614 for (i = 0; i < nb_queues; i++)
615 ena_rx_queue_release(queues[i]);
618 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
620 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
621 int nb_queues = dev->data->nb_tx_queues;
624 for (i = 0; i < nb_queues; i++)
625 ena_tx_queue_release(queues[i]);
628 static void ena_rx_queue_release(void *queue)
630 struct ena_ring *ring = (struct ena_ring *)queue;
631 struct ena_adapter *adapter = ring->adapter;
634 ena_assert_msg(ring->configured,
635 "API violation - releasing not configured queue");
636 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
639 /* Destroy HW queue */
640 ena_qid = ENA_IO_RXQ_IDX(ring->id);
641 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
644 ena_rx_queue_release_bufs(ring);
646 /* Free ring resources */
647 if (ring->rx_buffer_info)
648 rte_free(ring->rx_buffer_info);
649 ring->rx_buffer_info = NULL;
651 ring->configured = 0;
653 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
654 ring->port_id, ring->id);
657 static void ena_tx_queue_release(void *queue)
659 struct ena_ring *ring = (struct ena_ring *)queue;
660 struct ena_adapter *adapter = ring->adapter;
663 ena_assert_msg(ring->configured,
664 "API violation. Releasing not configured queue");
665 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
668 /* Destroy HW queue */
669 ena_qid = ENA_IO_TXQ_IDX(ring->id);
670 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
673 ena_tx_queue_release_bufs(ring);
675 /* Free ring resources */
676 if (ring->tx_buffer_info)
677 rte_free(ring->tx_buffer_info);
679 if (ring->empty_tx_reqs)
680 rte_free(ring->empty_tx_reqs);
682 ring->empty_tx_reqs = NULL;
683 ring->tx_buffer_info = NULL;
685 ring->configured = 0;
687 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
688 ring->port_id, ring->id);
691 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
693 unsigned int ring_mask = ring->ring_size - 1;
695 while (ring->next_to_clean != ring->next_to_use) {
697 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
700 rte_mbuf_raw_free(m);
702 ring->next_to_clean++;
706 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
710 for (i = 0; i < ring->ring_size; ++i) {
711 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
714 rte_pktmbuf_free(tx_buf->mbuf);
716 ring->next_to_clean++;
720 static int ena_link_update(struct rte_eth_dev *dev,
721 __rte_unused int wait_to_complete)
723 struct rte_eth_link *link = &dev->data->dev_link;
725 link->link_status = 1;
726 link->link_speed = ETH_SPEED_NUM_10G;
727 link->link_duplex = ETH_LINK_FULL_DUPLEX;
732 static int ena_queue_restart_all(struct rte_eth_dev *dev,
733 enum ena_ring_type ring_type)
735 struct ena_adapter *adapter =
736 (struct ena_adapter *)(dev->data->dev_private);
737 struct ena_ring *queues = NULL;
741 queues = (ring_type == ENA_RING_TYPE_RX) ?
742 adapter->rx_ring : adapter->tx_ring;
744 for (i = 0; i < adapter->num_queues; i++) {
745 if (queues[i].configured) {
746 if (ring_type == ENA_RING_TYPE_RX) {
748 dev->data->rx_queues[i] == &queues[i],
749 "Inconsistent state of rx queues\n");
752 dev->data->tx_queues[i] == &queues[i],
753 "Inconsistent state of tx queues\n");
756 rc = ena_queue_restart(&queues[i]);
760 "failed to restart queue %d type(%d)",
770 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
772 uint32_t max_frame_len = adapter->max_mtu;
774 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
775 DEV_RX_OFFLOAD_JUMBO_FRAME)
777 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
779 return max_frame_len;
782 static int ena_check_valid_conf(struct ena_adapter *adapter)
784 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
786 if (max_frame_len > adapter->max_mtu) {
787 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
795 ena_calc_queue_size(struct ena_com_dev *ena_dev,
796 struct ena_com_dev_get_features_ctx *get_feat_ctx)
798 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
800 queue_size = RTE_MIN(queue_size,
801 get_feat_ctx->max_queues.max_cq_depth);
802 queue_size = RTE_MIN(queue_size,
803 get_feat_ctx->max_queues.max_sq_depth);
805 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
806 queue_size = RTE_MIN(queue_size,
807 get_feat_ctx->max_queues.max_llq_depth);
809 /* Round down to power of 2 */
810 if (!rte_is_power_of_2(queue_size))
811 queue_size = rte_align32pow2(queue_size >> 1);
813 if (queue_size == 0) {
814 PMD_INIT_LOG(ERR, "Invalid queue size");
821 static void ena_stats_restart(struct rte_eth_dev *dev)
823 struct ena_adapter *adapter =
824 (struct ena_adapter *)(dev->data->dev_private);
826 rte_atomic64_init(&adapter->drv_stats->ierrors);
827 rte_atomic64_init(&adapter->drv_stats->oerrors);
828 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
831 static int ena_stats_get(struct rte_eth_dev *dev,
832 struct rte_eth_stats *stats)
834 struct ena_admin_basic_stats ena_stats;
835 struct ena_adapter *adapter =
836 (struct ena_adapter *)(dev->data->dev_private);
837 struct ena_com_dev *ena_dev = &adapter->ena_dev;
840 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
843 memset(&ena_stats, 0, sizeof(ena_stats));
844 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
846 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
850 /* Set of basic statistics from ENA */
851 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
852 ena_stats.rx_pkts_low);
853 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
854 ena_stats.tx_pkts_low);
855 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
856 ena_stats.rx_bytes_low);
857 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
858 ena_stats.tx_bytes_low);
859 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
860 ena_stats.rx_drops_low);
862 /* Driver related stats */
863 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
864 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
865 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
869 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
871 struct ena_adapter *adapter;
872 struct ena_com_dev *ena_dev;
875 ena_assert_msg(dev->data != NULL, "Uninitialized device");
876 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
877 adapter = (struct ena_adapter *)(dev->data->dev_private);
879 ena_dev = &adapter->ena_dev;
880 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
882 if (mtu > ena_get_mtu_conf(adapter)) {
884 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
885 mtu, ena_get_mtu_conf(adapter));
890 rc = ena_com_set_dev_mtu(ena_dev, mtu);
892 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
894 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
900 static int ena_start(struct rte_eth_dev *dev)
902 struct ena_adapter *adapter =
903 (struct ena_adapter *)(dev->data->dev_private);
906 if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
907 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
908 PMD_INIT_LOG(ERR, "API violation");
912 rc = ena_check_valid_conf(adapter);
916 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
920 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
924 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
925 ETH_MQ_RX_RSS_FLAG) {
926 rc = ena_rss_init_default(adapter);
931 ena_stats_restart(dev);
933 adapter->state = ENA_ADAPTER_STATE_RUNNING;
938 static int ena_queue_restart(struct ena_ring *ring)
942 ena_assert_msg(ring->configured == 1,
943 "Trying to restart unconfigured queue\n");
945 ring->next_to_clean = 0;
946 ring->next_to_use = 0;
948 if (ring->type == ENA_RING_TYPE_TX)
951 bufs_num = ring->ring_size - 1;
952 rc = ena_populate_rx_queue(ring, bufs_num);
953 if (rc != bufs_num) {
954 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
961 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
964 __rte_unused unsigned int socket_id,
965 const struct rte_eth_txconf *tx_conf)
967 struct ena_com_create_io_ctx ctx =
968 /* policy set to _HOST just to satisfy icc compiler */
969 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
970 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
971 struct ena_ring *txq = NULL;
972 struct ena_adapter *adapter =
973 (struct ena_adapter *)(dev->data->dev_private);
977 struct ena_com_dev *ena_dev = &adapter->ena_dev;
979 txq = &adapter->tx_ring[queue_idx];
981 if (txq->configured) {
983 "API violation. Queue %d is already configured\n",
988 if (!rte_is_power_of_2(nb_desc)) {
990 "Unsupported size of RX queue: %d is not a power of 2.",
995 if (nb_desc > adapter->tx_ring_size) {
997 "Unsupported size of TX queue (max size: %d)\n",
998 adapter->tx_ring_size);
1002 if (tx_conf->txq_flags == ETH_TXQ_FLAGS_IGNORE &&
1003 !ena_are_tx_queue_offloads_allowed(adapter, tx_conf->offloads)) {
1004 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n");
1008 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1010 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1012 ctx.msix_vector = -1; /* admin interrupts not used */
1013 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1014 ctx.queue_size = adapter->tx_ring_size;
1015 ctx.numa_node = ena_cpu_to_node(queue_idx);
1017 rc = ena_com_create_io_queue(ena_dev, &ctx);
1020 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1021 queue_idx, ena_qid, rc);
1023 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1024 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1026 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1027 &txq->ena_com_io_sq,
1028 &txq->ena_com_io_cq);
1031 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1033 ena_com_destroy_io_queue(ena_dev, ena_qid);
1037 txq->port_id = dev->data->port_id;
1038 txq->next_to_clean = 0;
1039 txq->next_to_use = 0;
1040 txq->ring_size = nb_desc;
1042 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1043 sizeof(struct ena_tx_buffer) *
1045 RTE_CACHE_LINE_SIZE);
1046 if (!txq->tx_buffer_info) {
1047 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1051 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1052 sizeof(u16) * txq->ring_size,
1053 RTE_CACHE_LINE_SIZE);
1054 if (!txq->empty_tx_reqs) {
1055 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1056 rte_free(txq->tx_buffer_info);
1059 for (i = 0; i < txq->ring_size; i++)
1060 txq->empty_tx_reqs[i] = i;
1062 txq->offloads = tx_conf->offloads;
1064 /* Store pointer to this queue in upper layer */
1065 txq->configured = 1;
1066 dev->data->tx_queues[queue_idx] = txq;
1071 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1074 __rte_unused unsigned int socket_id,
1075 const struct rte_eth_rxconf *rx_conf,
1076 struct rte_mempool *mp)
1078 struct ena_com_create_io_ctx ctx =
1079 /* policy set to _HOST just to satisfy icc compiler */
1080 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1081 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1082 struct ena_adapter *adapter =
1083 (struct ena_adapter *)(dev->data->dev_private);
1084 struct ena_ring *rxq = NULL;
1085 uint16_t ena_qid = 0;
1087 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1089 rxq = &adapter->rx_ring[queue_idx];
1090 if (rxq->configured) {
1092 "API violation. Queue %d is already configured\n",
1097 if (!rte_is_power_of_2(nb_desc)) {
1099 "Unsupported size of TX queue: %d is not a power of 2.",
1104 if (nb_desc > adapter->rx_ring_size) {
1106 "Unsupported size of RX queue (max size: %d)\n",
1107 adapter->rx_ring_size);
1111 if (!ena_are_rx_queue_offloads_allowed(adapter, rx_conf->offloads)) {
1112 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n");
1116 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1119 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1120 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1121 ctx.msix_vector = -1; /* admin interrupts not used */
1122 ctx.queue_size = adapter->rx_ring_size;
1123 ctx.numa_node = ena_cpu_to_node(queue_idx);
1125 rc = ena_com_create_io_queue(ena_dev, &ctx);
1127 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1130 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1131 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1133 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1134 &rxq->ena_com_io_sq,
1135 &rxq->ena_com_io_cq);
1138 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1140 ena_com_destroy_io_queue(ena_dev, ena_qid);
1143 rxq->port_id = dev->data->port_id;
1144 rxq->next_to_clean = 0;
1145 rxq->next_to_use = 0;
1146 rxq->ring_size = nb_desc;
1149 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1150 sizeof(struct rte_mbuf *) * nb_desc,
1151 RTE_CACHE_LINE_SIZE);
1152 if (!rxq->rx_buffer_info) {
1153 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1157 /* Store pointer to this queue in upper layer */
1158 rxq->configured = 1;
1159 dev->data->rx_queues[queue_idx] = rxq;
1164 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1168 uint16_t ring_size = rxq->ring_size;
1169 uint16_t ring_mask = ring_size - 1;
1170 uint16_t next_to_use = rxq->next_to_use;
1172 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1174 if (unlikely(!count))
1177 in_use = rxq->next_to_use - rxq->next_to_clean;
1178 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1180 count = RTE_MIN(count,
1181 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1183 /* get resources for incoming packets */
1184 rc = rte_mempool_get_bulk(rxq->mb_pool,
1185 (void **)(&mbufs[next_to_use & ring_mask]),
1187 if (unlikely(rc < 0)) {
1188 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1189 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1193 for (i = 0; i < count; i++) {
1194 uint16_t next_to_use_masked = next_to_use & ring_mask;
1195 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1196 struct ena_com_buf ebuf;
1198 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1199 /* prepare physical address for DMA transaction */
1200 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1201 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1202 /* pass resource to device */
1203 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1204 &ebuf, next_to_use_masked);
1206 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1208 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1214 /* When we submitted free recources to device... */
1216 /* ...let HW know that it can fill buffers with data */
1218 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1220 rxq->next_to_use = next_to_use;
1226 static int ena_device_init(struct ena_com_dev *ena_dev,
1227 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1230 bool readless_supported;
1232 /* Initialize mmio registers */
1233 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1235 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1239 /* The PCIe configuration space revision id indicate if mmio reg
1242 readless_supported =
1243 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1244 & ENA_MMIO_DISABLE_REG_READ);
1245 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1248 rc = ena_com_dev_reset(ena_dev);
1250 RTE_LOG(ERR, PMD, "cannot reset device\n");
1251 goto err_mmio_read_less;
1254 /* check FW version */
1255 rc = ena_com_validate_version(ena_dev);
1257 RTE_LOG(ERR, PMD, "device version is too low\n");
1258 goto err_mmio_read_less;
1261 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1263 /* ENA device administration layer init */
1264 rc = ena_com_admin_init(ena_dev, NULL, true);
1267 "cannot initialize ena admin queue with device\n");
1268 goto err_mmio_read_less;
1271 /* To enable the msix interrupts the driver needs to know the number
1272 * of queues. So the driver uses polling mode to retrieve this
1275 ena_com_set_admin_polling_mode(ena_dev, true);
1277 ena_config_host_info(ena_dev);
1279 /* Get Device Attributes and features */
1280 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1283 "cannot get attribute for ena device rc= %d\n", rc);
1284 goto err_admin_init;
1290 ena_com_admin_destroy(ena_dev);
1293 ena_com_mmio_reg_read_request_destroy(ena_dev);
1298 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1300 struct rte_pci_device *pci_dev;
1301 struct ena_adapter *adapter =
1302 (struct ena_adapter *)(eth_dev->data->dev_private);
1303 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1304 struct ena_com_dev_get_features_ctx get_feat_ctx;
1307 static int adapters_found;
1309 memset(adapter, 0, sizeof(struct ena_adapter));
1310 ena_dev = &adapter->ena_dev;
1312 eth_dev->dev_ops = &ena_dev_ops;
1313 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1314 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1315 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1316 adapter->rte_eth_dev_data = eth_dev->data;
1317 adapter->rte_dev = eth_dev;
1319 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1322 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1323 adapter->pdev = pci_dev;
1325 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1326 pci_dev->addr.domain,
1328 pci_dev->addr.devid,
1329 pci_dev->addr.function);
1331 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1332 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1334 /* Present ENA_MEM_BAR indicates available LLQ mode.
1335 * Use corresponding policy
1337 if (adapter->dev_mem_base)
1338 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1339 else if (adapter->regs)
1340 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1342 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1345 ena_dev->reg_bar = adapter->regs;
1346 ena_dev->dmadev = adapter->pdev;
1348 adapter->id_number = adapters_found;
1350 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1351 adapter->id_number);
1353 /* device specific initialization routine */
1354 rc = ena_device_init(ena_dev, &get_feat_ctx);
1356 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1360 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1361 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1363 "Trying to use LLQ but llq_num is 0.\n"
1364 "Fall back into regular queues.");
1365 ena_dev->tx_mem_queue_type =
1366 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1367 adapter->num_queues =
1368 get_feat_ctx.max_queues.max_sq_num;
1370 adapter->num_queues =
1371 get_feat_ctx.max_queues.max_llq_num;
1374 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1377 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1378 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1381 adapter->tx_ring_size = queue_size;
1382 adapter->rx_ring_size = queue_size;
1384 /* prepare ring structures */
1385 ena_init_rings(adapter);
1387 ena_config_debug_area(adapter);
1389 /* Set max MTU for this device */
1390 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1392 /* set device support for TSO */
1393 adapter->tso4_supported = get_feat_ctx.offload.tx &
1394 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1396 /* Copy MAC address and point DPDK to it */
1397 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1398 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1399 (struct ether_addr *)adapter->mac_addr);
1401 adapter->drv_stats = rte_zmalloc("adapter stats",
1402 sizeof(*adapter->drv_stats),
1403 RTE_CACHE_LINE_SIZE);
1404 if (!adapter->drv_stats) {
1405 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1410 adapter->state = ENA_ADAPTER_STATE_INIT;
1415 static int ena_dev_configure(struct rte_eth_dev *dev)
1417 struct ena_adapter *adapter =
1418 (struct ena_adapter *)(dev->data->dev_private);
1419 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
1420 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1422 if ((tx_offloads & adapter->tx_supported_offloads) != tx_offloads) {
1423 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported "
1424 "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
1425 tx_offloads, adapter->tx_supported_offloads);
1429 if ((rx_offloads & adapter->rx_supported_offloads) != rx_offloads) {
1430 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported "
1431 "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
1432 rx_offloads, adapter->rx_supported_offloads);
1436 if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1437 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1438 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1443 switch (adapter->state) {
1444 case ENA_ADAPTER_STATE_INIT:
1445 case ENA_ADAPTER_STATE_STOPPED:
1446 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1448 case ENA_ADAPTER_STATE_CONFIG:
1449 RTE_LOG(WARNING, PMD,
1450 "Ivalid driver state while trying to configure device\n");
1456 adapter->tx_selected_offloads = tx_offloads;
1457 adapter->rx_selected_offloads = rx_offloads;
1461 static void ena_init_rings(struct ena_adapter *adapter)
1465 for (i = 0; i < adapter->num_queues; i++) {
1466 struct ena_ring *ring = &adapter->tx_ring[i];
1468 ring->configured = 0;
1469 ring->type = ENA_RING_TYPE_TX;
1470 ring->adapter = adapter;
1472 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1473 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1476 for (i = 0; i < adapter->num_queues; i++) {
1477 struct ena_ring *ring = &adapter->rx_ring[i];
1479 ring->configured = 0;
1480 ring->type = ENA_RING_TYPE_RX;
1481 ring->adapter = adapter;
1486 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
1489 uint64_t port_offloads = adapter->tx_selected_offloads;
1491 /* Check if port supports all requested offloads.
1492 * True if all offloads selected for queue are set for port.
1494 if ((offloads & port_offloads) != offloads)
1499 static bool ena_are_rx_queue_offloads_allowed(struct ena_adapter *adapter,
1502 uint64_t port_offloads = adapter->rx_selected_offloads;
1504 /* Check if port supports all requested offloads.
1505 * True if all offloads selected for queue are set for port.
1507 if ((offloads & port_offloads) != offloads)
1512 static void ena_infos_get(struct rte_eth_dev *dev,
1513 struct rte_eth_dev_info *dev_info)
1515 struct ena_adapter *adapter;
1516 struct ena_com_dev *ena_dev;
1517 struct ena_com_dev_get_features_ctx feat;
1518 uint64_t rx_feat = 0, tx_feat = 0;
1521 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1522 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1523 adapter = (struct ena_adapter *)(dev->data->dev_private);
1525 ena_dev = &adapter->ena_dev;
1526 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1528 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1530 dev_info->speed_capa =
1532 ETH_LINK_SPEED_2_5G |
1534 ETH_LINK_SPEED_10G |
1535 ETH_LINK_SPEED_25G |
1536 ETH_LINK_SPEED_40G |
1537 ETH_LINK_SPEED_50G |
1538 ETH_LINK_SPEED_100G;
1540 /* Get supported features from HW */
1541 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1544 "Cannot get attribute for ena device rc= %d\n", rc);
1548 /* Set Tx & Rx features available for device */
1549 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1550 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1552 if (feat.offload.tx &
1553 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1554 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1555 DEV_TX_OFFLOAD_UDP_CKSUM |
1556 DEV_TX_OFFLOAD_TCP_CKSUM;
1558 if (feat.offload.rx_supported &
1559 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1560 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1561 DEV_RX_OFFLOAD_UDP_CKSUM |
1562 DEV_RX_OFFLOAD_TCP_CKSUM;
1564 /* Inform framework about available features */
1565 dev_info->rx_offload_capa = rx_feat;
1566 dev_info->rx_queue_offload_capa = rx_feat;
1567 dev_info->tx_offload_capa = tx_feat;
1568 dev_info->tx_queue_offload_capa = tx_feat;
1570 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1571 dev_info->max_rx_pktlen = adapter->max_mtu;
1572 dev_info->max_mac_addrs = 1;
1574 dev_info->max_rx_queues = adapter->num_queues;
1575 dev_info->max_tx_queues = adapter->num_queues;
1576 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1578 adapter->tx_supported_offloads = tx_feat;
1579 adapter->rx_supported_offloads = rx_feat;
1582 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1585 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1586 unsigned int ring_size = rx_ring->ring_size;
1587 unsigned int ring_mask = ring_size - 1;
1588 uint16_t next_to_clean = rx_ring->next_to_clean;
1589 uint16_t desc_in_use = 0;
1590 unsigned int recv_idx = 0;
1591 struct rte_mbuf *mbuf = NULL;
1592 struct rte_mbuf *mbuf_head = NULL;
1593 struct rte_mbuf *mbuf_prev = NULL;
1594 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1595 unsigned int completed;
1597 struct ena_com_rx_ctx ena_rx_ctx;
1600 /* Check adapter state */
1601 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1603 "Trying to receive pkts while device is NOT running\n");
1607 desc_in_use = rx_ring->next_to_use - next_to_clean;
1608 if (unlikely(nb_pkts > desc_in_use))
1609 nb_pkts = desc_in_use;
1611 for (completed = 0; completed < nb_pkts; completed++) {
1614 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1615 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1616 ena_rx_ctx.descs = 0;
1617 /* receive packet context */
1618 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1619 rx_ring->ena_com_io_sq,
1622 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1626 if (unlikely(ena_rx_ctx.descs == 0))
1629 while (segments < ena_rx_ctx.descs) {
1630 mbuf = rx_buff_info[next_to_clean & ring_mask];
1631 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1632 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1635 if (segments == 0) {
1636 mbuf->nb_segs = ena_rx_ctx.descs;
1637 mbuf->port = rx_ring->port_id;
1641 /* for multi-segment pkts create mbuf chain */
1642 mbuf_prev->next = mbuf;
1644 mbuf_head->pkt_len += mbuf->data_len;
1651 /* fill mbuf attributes if any */
1652 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1653 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1655 /* pass to DPDK application head mbuf */
1656 rx_pkts[recv_idx] = mbuf_head;
1660 rx_ring->next_to_clean = next_to_clean;
1662 desc_in_use = desc_in_use - completed + 1;
1663 /* Burst refill to save doorbells, memory barriers, const interval */
1664 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1665 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1671 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1677 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1678 struct ipv4_hdr *ip_hdr;
1680 uint16_t frag_field;
1682 for (i = 0; i != nb_pkts; i++) {
1684 ol_flags = m->ol_flags;
1686 if (!(ol_flags & PKT_TX_IPV4))
1689 /* If there was not L2 header length specified, assume it is
1690 * length of the ethernet header.
1692 if (unlikely(m->l2_len == 0))
1693 m->l2_len = sizeof(struct ether_hdr);
1695 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1697 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1699 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1700 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1702 /* If IPv4 header has DF flag enabled and TSO support is
1703 * disabled, partial chcecksum should not be calculated.
1705 if (!tx_ring->adapter->tso4_supported)
1709 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1710 (ol_flags & PKT_TX_L4_MASK) ==
1711 PKT_TX_SCTP_CKSUM) {
1712 rte_errno = -ENOTSUP;
1716 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1717 ret = rte_validate_tx_offload(m);
1724 /* In case we are supposed to TSO and have DF not set (DF=0)
1725 * hardware must be provided with partial checksum, otherwise
1726 * it will take care of necessary calculations.
1729 ret = rte_net_intel_cksum_flags_prepare(m,
1730 ol_flags & ~PKT_TX_TCP_SEG);
1740 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1743 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1744 uint16_t next_to_use = tx_ring->next_to_use;
1745 uint16_t next_to_clean = tx_ring->next_to_clean;
1746 struct rte_mbuf *mbuf;
1747 unsigned int ring_size = tx_ring->ring_size;
1748 unsigned int ring_mask = ring_size - 1;
1749 struct ena_com_tx_ctx ena_tx_ctx;
1750 struct ena_tx_buffer *tx_info;
1751 struct ena_com_buf *ebuf;
1752 uint16_t rc, req_id, total_tx_descs = 0;
1753 uint16_t sent_idx = 0, empty_tx_reqs;
1756 /* Check adapter state */
1757 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1759 "Trying to xmit pkts while device is NOT running\n");
1763 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1764 if (nb_pkts > empty_tx_reqs)
1765 nb_pkts = empty_tx_reqs;
1767 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1768 mbuf = tx_pkts[sent_idx];
1770 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1771 tx_info = &tx_ring->tx_buffer_info[req_id];
1772 tx_info->mbuf = mbuf;
1773 tx_info->num_of_bufs = 0;
1774 ebuf = tx_info->bufs;
1776 /* Prepare TX context */
1777 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1778 memset(&ena_tx_ctx.ena_meta, 0x0,
1779 sizeof(struct ena_com_tx_meta));
1780 ena_tx_ctx.ena_bufs = ebuf;
1781 ena_tx_ctx.req_id = req_id;
1782 if (tx_ring->tx_mem_queue_type ==
1783 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1784 /* prepare the push buffer with
1785 * virtual address of the data
1787 ena_tx_ctx.header_len =
1788 RTE_MIN(mbuf->data_len,
1789 tx_ring->tx_max_header_size);
1790 ena_tx_ctx.push_header =
1791 (void *)((char *)mbuf->buf_addr +
1793 } /* there's no else as we take advantage of memset zeroing */
1795 /* Set TX offloads flags, if applicable */
1796 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1798 if (unlikely(mbuf->ol_flags &
1799 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1800 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1802 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1804 /* Process first segment taking into
1805 * consideration pushed header
1807 if (mbuf->data_len > ena_tx_ctx.header_len) {
1808 ebuf->paddr = mbuf->buf_iova +
1810 ena_tx_ctx.header_len;
1811 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1813 tx_info->num_of_bufs++;
1816 while ((mbuf = mbuf->next) != NULL) {
1817 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1818 ebuf->len = mbuf->data_len;
1820 tx_info->num_of_bufs++;
1823 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1825 /* Write data to device */
1826 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1827 &ena_tx_ctx, &nb_hw_desc);
1831 tx_info->tx_descs = nb_hw_desc;
1836 /* If there are ready packets to be xmitted... */
1838 /* ...let HW do its best :-) */
1840 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1842 tx_ring->next_to_use = next_to_use;
1845 /* Clear complete packets */
1846 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1847 /* Get Tx info & store how many descs were processed */
1848 tx_info = &tx_ring->tx_buffer_info[req_id];
1849 total_tx_descs += tx_info->tx_descs;
1851 /* Free whole mbuf chain */
1852 mbuf = tx_info->mbuf;
1853 rte_pktmbuf_free(mbuf);
1854 tx_info->mbuf = NULL;
1856 /* Put back descriptor to the ring for reuse */
1857 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1860 /* If too many descs to clean, leave it for another run */
1861 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1865 if (total_tx_descs > 0) {
1866 /* acknowledge completion of sent packets */
1867 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1868 tx_ring->next_to_clean = next_to_clean;
1874 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1875 struct rte_pci_device *pci_dev)
1877 return rte_eth_dev_pci_generic_probe(pci_dev,
1878 sizeof(struct ena_adapter), eth_ena_dev_init);
1881 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1883 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1886 static struct rte_pci_driver rte_ena_pmd = {
1887 .id_table = pci_id_ena_map,
1888 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1889 .probe = eth_ena_pci_probe,
1890 .remove = eth_ena_pci_remove,
1893 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1894 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1895 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1897 RTE_INIT(ena_init_log);
1901 ena_logtype_init = rte_log_register("pmd.ena.init");
1902 if (ena_logtype_init >= 0)
1903 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1904 ena_logtype_driver = rte_log_register("pmd.ena.driver");
1905 if (ena_logtype_driver >= 0)
1906 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);