1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <ethdev_driver.h>
9 #include <ethdev_pci.h>
11 #include <rte_atomic.h>
13 #include <rte_errno.h>
14 #include <rte_version.h>
16 #include <rte_kvargs.h>
18 #include "ena_ethdev.h"
20 #include "ena_platform.h"
22 #include "ena_eth_com.h"
24 #include <ena_common_defs.h>
25 #include <ena_regs_defs.h>
26 #include <ena_admin_defs.h>
27 #include <ena_eth_io_defs.h>
29 #define DRV_MODULE_VER_MAJOR 2
30 #define DRV_MODULE_VER_MINOR 2
31 #define DRV_MODULE_VER_SUBMINOR 1
33 #define ENA_IO_TXQ_IDX(q) (2 * (q))
34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
35 /*reverse version of ENA_IO_RXQ_IDX*/
36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
41 #define GET_L4_HDR_LEN(mbuf) \
42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
47 #define ENA_HASH_KEY_SIZE 40
48 #define ETH_GSTRING_LEN 32
50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
52 #define ENA_MIN_RING_DESC 128
54 enum ethtool_stringset {
60 char name[ETH_GSTRING_LEN];
64 #define ENA_STAT_ENTRY(stat, stat_type) { \
66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
69 #define ENA_STAT_RX_ENTRY(stat) \
70 ENA_STAT_ENTRY(stat, rx)
72 #define ENA_STAT_TX_ENTRY(stat) \
73 ENA_STAT_ENTRY(stat, tx)
75 #define ENA_STAT_ENI_ENTRY(stat) \
76 ENA_STAT_ENTRY(stat, eni)
78 #define ENA_STAT_GLOBAL_ENTRY(stat) \
79 ENA_STAT_ENTRY(stat, dev)
81 /* Device arguments */
82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
85 * Each rte_memzone should have unique name.
86 * To satisfy it, count number of allocation and add it to name.
88 rte_atomic32_t ena_alloc_cnt;
90 static const struct ena_stats ena_stats_global_strings[] = {
91 ENA_STAT_GLOBAL_ENTRY(wd_expired),
92 ENA_STAT_GLOBAL_ENTRY(dev_start),
93 ENA_STAT_GLOBAL_ENTRY(dev_stop),
94 ENA_STAT_GLOBAL_ENTRY(tx_drops),
97 static const struct ena_stats ena_stats_eni_strings[] = {
98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
105 static const struct ena_stats ena_stats_tx_strings[] = {
106 ENA_STAT_TX_ENTRY(cnt),
107 ENA_STAT_TX_ENTRY(bytes),
108 ENA_STAT_TX_ENTRY(prepare_ctx_err),
109 ENA_STAT_TX_ENTRY(linearize),
110 ENA_STAT_TX_ENTRY(linearize_failed),
111 ENA_STAT_TX_ENTRY(tx_poll),
112 ENA_STAT_TX_ENTRY(doorbells),
113 ENA_STAT_TX_ENTRY(bad_req_id),
114 ENA_STAT_TX_ENTRY(available_desc),
117 static const struct ena_stats ena_stats_rx_strings[] = {
118 ENA_STAT_RX_ENTRY(cnt),
119 ENA_STAT_RX_ENTRY(bytes),
120 ENA_STAT_RX_ENTRY(refill_partial),
121 ENA_STAT_RX_ENTRY(bad_csum),
122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
123 ENA_STAT_RX_ENTRY(bad_desc_num),
124 ENA_STAT_RX_ENTRY(bad_req_id),
127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings)
129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
133 DEV_TX_OFFLOAD_UDP_CKSUM |\
134 DEV_TX_OFFLOAD_IPV4_CKSUM |\
135 DEV_TX_OFFLOAD_TCP_TSO)
136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
140 /** Vendor ID used by Amazon devices */
141 #define PCI_VENDOR_ID_AMAZON 0x1D0F
142 /** Amazon devices */
143 #define PCI_DEVICE_ID_ENA_VF 0xEC20
144 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21
146 #define ENA_TX_OFFLOAD_MASK (\
153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
156 static const struct rte_pci_id pci_id_ena_map[] = {
157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
162 static struct ena_aenq_handlers aenq_handlers;
164 static int ena_device_init(struct ena_com_dev *ena_dev,
165 struct ena_com_dev_get_features_ctx *get_feat_ctx,
167 static int ena_dev_configure(struct rte_eth_dev *dev);
168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
169 struct ena_tx_buffer *tx_info,
170 struct rte_mbuf *mbuf,
172 uint16_t *header_len);
173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
174 static void ena_tx_cleanup(struct ena_ring *tx_ring);
175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
180 uint16_t nb_desc, unsigned int socket_id,
181 const struct rte_eth_txconf *tx_conf);
182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_rxconf *rx_conf,
185 struct rte_mempool *mp);
186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
188 struct ena_com_rx_buf_info *ena_bufs,
190 uint16_t *next_to_clean,
192 static uint16_t eth_ena_recv_pkts(void *rx_queue,
193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
195 struct rte_mbuf *mbuf, uint16_t id);
196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
197 static void ena_init_rings(struct ena_adapter *adapter,
198 bool disable_meta_caching);
199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
200 static int ena_start(struct rte_eth_dev *dev);
201 static int ena_stop(struct rte_eth_dev *dev);
202 static int ena_close(struct rte_eth_dev *dev);
203 static int ena_dev_reset(struct rte_eth_dev *dev);
204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
207 static void ena_rx_queue_release(void *queue);
208 static void ena_tx_queue_release(void *queue);
209 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
210 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
211 static int ena_link_update(struct rte_eth_dev *dev,
212 int wait_to_complete);
213 static int ena_create_io_queue(struct ena_ring *ring);
214 static void ena_queue_stop(struct ena_ring *ring);
215 static void ena_queue_stop_all(struct rte_eth_dev *dev,
216 enum ena_ring_type ring_type);
217 static int ena_queue_start(struct ena_ring *ring);
218 static int ena_queue_start_all(struct rte_eth_dev *dev,
219 enum ena_ring_type ring_type);
220 static void ena_stats_restart(struct rte_eth_dev *dev);
221 static int ena_infos_get(struct rte_eth_dev *dev,
222 struct rte_eth_dev_info *dev_info);
223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
224 struct rte_eth_rss_reta_entry64 *reta_conf,
226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
227 struct rte_eth_rss_reta_entry64 *reta_conf,
229 static void ena_interrupt_handler_rte(void *cb_arg);
230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
231 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
233 static int ena_xstats_get_names(struct rte_eth_dev *dev,
234 struct rte_eth_xstat_name *xstats_names,
236 static int ena_xstats_get(struct rte_eth_dev *dev,
237 struct rte_eth_xstat *stats,
239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
243 static int ena_process_bool_devarg(const char *key,
246 static int ena_parse_devargs(struct ena_adapter *adapter,
247 struct rte_devargs *devargs);
248 static int ena_copy_eni_stats(struct ena_adapter *adapter);
250 static const struct eth_dev_ops ena_dev_ops = {
251 .dev_configure = ena_dev_configure,
252 .dev_infos_get = ena_infos_get,
253 .rx_queue_setup = ena_rx_queue_setup,
254 .tx_queue_setup = ena_tx_queue_setup,
255 .dev_start = ena_start,
256 .dev_stop = ena_stop,
257 .link_update = ena_link_update,
258 .stats_get = ena_stats_get,
259 .xstats_get_names = ena_xstats_get_names,
260 .xstats_get = ena_xstats_get,
261 .xstats_get_by_id = ena_xstats_get_by_id,
262 .mtu_set = ena_mtu_set,
263 .rx_queue_release = ena_rx_queue_release,
264 .tx_queue_release = ena_tx_queue_release,
265 .dev_close = ena_close,
266 .dev_reset = ena_dev_reset,
267 .reta_update = ena_rss_reta_update,
268 .reta_query = ena_rss_reta_query,
271 void ena_rss_key_fill(void *key, size_t size)
273 static bool key_generated;
274 static uint8_t default_key[ENA_HASH_KEY_SIZE];
277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
279 if (!key_generated) {
280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
281 default_key[i] = rte_rand() & 0xff;
282 key_generated = true;
285 rte_memcpy(key, default_key, size);
288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
289 struct ena_com_rx_ctx *ena_rx_ctx)
291 uint64_t ol_flags = 0;
292 uint32_t packet_type = 0;
294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
295 packet_type |= RTE_PTYPE_L4_TCP;
296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
297 packet_type |= RTE_PTYPE_L4_UDP;
299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
300 packet_type |= RTE_PTYPE_L3_IPV4;
301 if (unlikely(ena_rx_ctx->l3_csum_err))
302 ol_flags |= PKT_RX_IP_CKSUM_BAD;
304 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
305 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
306 packet_type |= RTE_PTYPE_L3_IPV6;
309 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
312 if (unlikely(ena_rx_ctx->l4_csum_err))
313 ol_flags |= PKT_RX_L4_CKSUM_BAD;
315 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
317 mbuf->ol_flags = ol_flags;
318 mbuf->packet_type = packet_type;
321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
322 struct ena_com_tx_ctx *ena_tx_ctx,
323 uint64_t queue_offloads,
324 bool disable_meta_caching)
326 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
328 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
329 (queue_offloads & QUEUE_OFFLOADS)) {
330 /* check if TSO is required */
331 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
332 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
333 ena_tx_ctx->tso_enable = true;
335 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
338 /* check if L3 checksum is needed */
339 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
340 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
341 ena_tx_ctx->l3_csum_enable = true;
343 if (mbuf->ol_flags & PKT_TX_IPV6) {
344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
346 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
348 /* set don't fragment (DF) flag */
349 if (mbuf->packet_type &
350 (RTE_PTYPE_L4_NONFRAG
351 | RTE_PTYPE_INNER_L4_NONFRAG))
352 ena_tx_ctx->df = true;
355 /* check if L4 checksum is needed */
356 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
357 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
358 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
359 ena_tx_ctx->l4_csum_enable = true;
360 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
362 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
363 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
364 ena_tx_ctx->l4_csum_enable = true;
366 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
367 ena_tx_ctx->l4_csum_enable = false;
370 ena_meta->mss = mbuf->tso_segsz;
371 ena_meta->l3_hdr_len = mbuf->l3_len;
372 ena_meta->l3_hdr_offset = mbuf->l2_len;
374 ena_tx_ctx->meta_valid = true;
375 } else if (disable_meta_caching) {
376 memset(ena_meta, 0, sizeof(*ena_meta));
377 ena_tx_ctx->meta_valid = true;
379 ena_tx_ctx->meta_valid = false;
383 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
385 struct ena_tx_buffer *tx_info = NULL;
387 if (likely(req_id < tx_ring->ring_size)) {
388 tx_info = &tx_ring->tx_buffer_info[req_id];
389 if (likely(tx_info->mbuf))
394 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
396 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
398 /* Trigger device reset */
399 ++tx_ring->tx_stats.bad_req_id;
400 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
401 tx_ring->adapter->trigger_reset = true;
405 static void ena_config_host_info(struct ena_com_dev *ena_dev)
407 struct ena_admin_host_info *host_info;
410 /* Allocate only the host info */
411 rc = ena_com_allocate_host_info(ena_dev);
413 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
417 host_info = ena_dev->host_attr.host_info;
419 host_info->os_type = ENA_ADMIN_OS_DPDK;
420 host_info->kernel_ver = RTE_VERSION;
421 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
422 sizeof(host_info->kernel_ver_str));
423 host_info->os_dist = RTE_VERSION;
424 strlcpy((char *)host_info->os_dist_str, rte_version(),
425 sizeof(host_info->os_dist_str));
426 host_info->driver_version =
427 (DRV_MODULE_VER_MAJOR) |
428 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
429 (DRV_MODULE_VER_SUBMINOR <<
430 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
431 host_info->num_cpus = rte_lcore_count();
433 host_info->driver_supported_features =
434 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
436 rc = ena_com_set_host_attributes(ena_dev);
438 if (rc == -ENA_COM_UNSUPPORTED)
439 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
441 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
449 ena_com_delete_host_info(ena_dev);
452 /* This function calculates the number of xstats based on the current config */
453 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
455 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
456 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
457 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
460 static void ena_config_debug_area(struct ena_adapter *adapter)
465 ss_count = ena_xstats_calc_num(adapter->rte_dev);
467 /* allocate 32 bytes for each string and 64bit for the value */
468 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
470 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
472 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
476 rc = ena_com_set_host_attributes(&adapter->ena_dev);
478 if (rc == -ENA_COM_UNSUPPORTED)
479 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
481 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
488 ena_com_delete_debug_area(&adapter->ena_dev);
491 static int ena_close(struct rte_eth_dev *dev)
493 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
494 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
495 struct ena_adapter *adapter = dev->data->dev_private;
498 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
501 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
503 adapter->state = ENA_ADAPTER_STATE_CLOSED;
505 ena_rx_queue_release_all(dev);
506 ena_tx_queue_release_all(dev);
508 rte_free(adapter->drv_stats);
509 adapter->drv_stats = NULL;
511 rte_intr_disable(intr_handle);
512 rte_intr_callback_unregister(intr_handle,
513 ena_interrupt_handler_rte,
517 * MAC is not allocated dynamically. Setting NULL should prevent from
518 * release of the resource in the rte_eth_dev_release_port().
520 dev->data->mac_addrs = NULL;
526 ena_dev_reset(struct rte_eth_dev *dev)
530 ena_destroy_device(dev);
531 rc = eth_ena_dev_init(dev);
533 PMD_INIT_LOG(CRIT, "Cannot initialize device");
538 static int ena_rss_reta_update(struct rte_eth_dev *dev,
539 struct rte_eth_rss_reta_entry64 *reta_conf,
542 struct ena_adapter *adapter = dev->data->dev_private;
543 struct ena_com_dev *ena_dev = &adapter->ena_dev;
549 if ((reta_size == 0) || (reta_conf == NULL))
552 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
554 "indirection table %d is bigger than supported (%d)\n",
555 reta_size, ENA_RX_RSS_TABLE_SIZE);
559 for (i = 0 ; i < reta_size ; i++) {
560 /* each reta_conf is for 64 entries.
561 * to support 128 we use 2 conf of 64
563 conf_idx = i / RTE_RETA_GROUP_SIZE;
564 idx = i % RTE_RETA_GROUP_SIZE;
565 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
567 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
569 rc = ena_com_indirect_table_fill_entry(ena_dev,
572 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
574 "Cannot fill indirect table\n");
580 rte_spinlock_lock(&adapter->admin_lock);
581 rc = ena_com_indirect_table_set(ena_dev);
582 rte_spinlock_unlock(&adapter->admin_lock);
583 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
584 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
588 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n",
589 __func__, reta_size, adapter->rte_dev->data->port_id);
594 /* Query redirection table. */
595 static int ena_rss_reta_query(struct rte_eth_dev *dev,
596 struct rte_eth_rss_reta_entry64 *reta_conf,
599 struct ena_adapter *adapter = dev->data->dev_private;
600 struct ena_com_dev *ena_dev = &adapter->ena_dev;
603 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
607 if (reta_size == 0 || reta_conf == NULL ||
608 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
611 rte_spinlock_lock(&adapter->admin_lock);
612 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
613 rte_spinlock_unlock(&adapter->admin_lock);
614 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
615 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
619 for (i = 0 ; i < reta_size ; i++) {
620 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
621 reta_idx = i % RTE_RETA_GROUP_SIZE;
622 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
623 reta_conf[reta_conf_idx].reta[reta_idx] =
624 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
630 static int ena_rss_init_default(struct ena_adapter *adapter)
632 struct ena_com_dev *ena_dev = &adapter->ena_dev;
633 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
637 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
639 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
643 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
644 val = i % nb_rx_queues;
645 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
646 ENA_IO_RXQ_IDX(val));
647 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
648 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
653 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
654 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
655 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
656 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
660 rc = ena_com_set_default_hash_ctrl(ena_dev);
661 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
662 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
666 rc = ena_com_indirect_table_set(ena_dev);
667 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
668 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
671 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
672 adapter->rte_dev->data->port_id);
677 ena_com_rss_destroy(ena_dev);
683 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
685 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
686 int nb_queues = dev->data->nb_rx_queues;
689 for (i = 0; i < nb_queues; i++)
690 ena_rx_queue_release(queues[i]);
693 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
695 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
696 int nb_queues = dev->data->nb_tx_queues;
699 for (i = 0; i < nb_queues; i++)
700 ena_tx_queue_release(queues[i]);
703 static void ena_rx_queue_release(void *queue)
705 struct ena_ring *ring = (struct ena_ring *)queue;
707 /* Free ring resources */
708 if (ring->rx_buffer_info)
709 rte_free(ring->rx_buffer_info);
710 ring->rx_buffer_info = NULL;
712 if (ring->rx_refill_buffer)
713 rte_free(ring->rx_refill_buffer);
714 ring->rx_refill_buffer = NULL;
716 if (ring->empty_rx_reqs)
717 rte_free(ring->empty_rx_reqs);
718 ring->empty_rx_reqs = NULL;
720 ring->configured = 0;
722 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
723 ring->port_id, ring->id);
726 static void ena_tx_queue_release(void *queue)
728 struct ena_ring *ring = (struct ena_ring *)queue;
730 /* Free ring resources */
731 if (ring->push_buf_intermediate_buf)
732 rte_free(ring->push_buf_intermediate_buf);
734 if (ring->tx_buffer_info)
735 rte_free(ring->tx_buffer_info);
737 if (ring->empty_tx_reqs)
738 rte_free(ring->empty_tx_reqs);
740 ring->empty_tx_reqs = NULL;
741 ring->tx_buffer_info = NULL;
742 ring->push_buf_intermediate_buf = NULL;
744 ring->configured = 0;
746 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
747 ring->port_id, ring->id);
750 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
754 for (i = 0; i < ring->ring_size; ++i) {
755 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
757 rte_mbuf_raw_free(rx_info->mbuf);
758 rx_info->mbuf = NULL;
763 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
767 for (i = 0; i < ring->ring_size; ++i) {
768 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
771 rte_pktmbuf_free(tx_buf->mbuf);
775 static int ena_link_update(struct rte_eth_dev *dev,
776 __rte_unused int wait_to_complete)
778 struct rte_eth_link *link = &dev->data->dev_link;
779 struct ena_adapter *adapter = dev->data->dev_private;
781 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
782 link->link_speed = ETH_SPEED_NUM_NONE;
783 link->link_duplex = ETH_LINK_FULL_DUPLEX;
788 static int ena_queue_start_all(struct rte_eth_dev *dev,
789 enum ena_ring_type ring_type)
791 struct ena_adapter *adapter = dev->data->dev_private;
792 struct ena_ring *queues = NULL;
797 if (ring_type == ENA_RING_TYPE_RX) {
798 queues = adapter->rx_ring;
799 nb_queues = dev->data->nb_rx_queues;
801 queues = adapter->tx_ring;
802 nb_queues = dev->data->nb_tx_queues;
804 for (i = 0; i < nb_queues; i++) {
805 if (queues[i].configured) {
806 if (ring_type == ENA_RING_TYPE_RX) {
808 dev->data->rx_queues[i] == &queues[i],
809 "Inconsistent state of rx queues\n");
812 dev->data->tx_queues[i] == &queues[i],
813 "Inconsistent state of tx queues\n");
816 rc = ena_queue_start(&queues[i]);
820 "failed to start queue %d type(%d)",
831 if (queues[i].configured)
832 ena_queue_stop(&queues[i]);
837 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
839 uint32_t max_frame_len = adapter->max_mtu;
841 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
842 DEV_RX_OFFLOAD_JUMBO_FRAME)
844 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
846 return max_frame_len;
849 static int ena_check_valid_conf(struct ena_adapter *adapter)
851 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
853 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
854 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
855 "max mtu: %d, min mtu: %d",
856 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
857 return ENA_COM_UNSUPPORTED;
864 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
865 bool use_large_llq_hdr)
867 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
868 struct ena_com_dev *ena_dev = ctx->ena_dev;
869 uint32_t max_tx_queue_size;
870 uint32_t max_rx_queue_size;
872 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
873 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
874 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
875 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
876 max_queue_ext->max_rx_sq_depth);
877 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
879 if (ena_dev->tx_mem_queue_type ==
880 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
881 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
884 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
885 max_queue_ext->max_tx_sq_depth);
888 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
889 max_queue_ext->max_per_packet_rx_descs);
890 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
891 max_queue_ext->max_per_packet_tx_descs);
893 struct ena_admin_queue_feature_desc *max_queues =
894 &ctx->get_feat_ctx->max_queues;
895 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
896 max_queues->max_sq_depth);
897 max_tx_queue_size = max_queues->max_cq_depth;
899 if (ena_dev->tx_mem_queue_type ==
900 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
901 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
904 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
905 max_queues->max_sq_depth);
908 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
909 max_queues->max_packet_rx_descs);
910 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
911 max_queues->max_packet_tx_descs);
914 /* Round down to the nearest power of 2 */
915 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
916 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
918 if (use_large_llq_hdr) {
919 if ((llq->entry_size_ctrl_supported &
920 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
921 (ena_dev->tx_mem_queue_type ==
922 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
923 max_tx_queue_size /= 2;
925 "Forcing large headers and decreasing maximum TX queue size to %d\n",
929 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
933 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
934 PMD_INIT_LOG(ERR, "Invalid queue size");
938 ctx->max_tx_queue_size = max_tx_queue_size;
939 ctx->max_rx_queue_size = max_rx_queue_size;
944 static void ena_stats_restart(struct rte_eth_dev *dev)
946 struct ena_adapter *adapter = dev->data->dev_private;
948 rte_atomic64_init(&adapter->drv_stats->ierrors);
949 rte_atomic64_init(&adapter->drv_stats->oerrors);
950 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
951 adapter->drv_stats->rx_drops = 0;
954 static int ena_stats_get(struct rte_eth_dev *dev,
955 struct rte_eth_stats *stats)
957 struct ena_admin_basic_stats ena_stats;
958 struct ena_adapter *adapter = dev->data->dev_private;
959 struct ena_com_dev *ena_dev = &adapter->ena_dev;
964 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
967 memset(&ena_stats, 0, sizeof(ena_stats));
969 rte_spinlock_lock(&adapter->admin_lock);
970 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
971 rte_spinlock_unlock(&adapter->admin_lock);
973 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
977 /* Set of basic statistics from ENA */
978 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
979 ena_stats.rx_pkts_low);
980 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
981 ena_stats.tx_pkts_low);
982 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
983 ena_stats.rx_bytes_low);
984 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
985 ena_stats.tx_bytes_low);
987 /* Driver related stats */
988 stats->imissed = adapter->drv_stats->rx_drops;
989 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
990 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
991 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
993 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
994 RTE_ETHDEV_QUEUE_STAT_CNTRS);
995 for (i = 0; i < max_rings_stats; ++i) {
996 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
998 stats->q_ibytes[i] = rx_stats->bytes;
999 stats->q_ipackets[i] = rx_stats->cnt;
1000 stats->q_errors[i] = rx_stats->bad_desc_num +
1001 rx_stats->bad_req_id;
1004 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1005 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1006 for (i = 0; i < max_rings_stats; ++i) {
1007 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1009 stats->q_obytes[i] = tx_stats->bytes;
1010 stats->q_opackets[i] = tx_stats->cnt;
1016 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1018 struct ena_adapter *adapter;
1019 struct ena_com_dev *ena_dev;
1022 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1023 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1024 adapter = dev->data->dev_private;
1026 ena_dev = &adapter->ena_dev;
1027 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1029 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1031 "Invalid MTU setting. new_mtu: %d "
1032 "max mtu: %d min mtu: %d\n",
1033 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1037 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1039 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1041 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1046 static int ena_start(struct rte_eth_dev *dev)
1048 struct ena_adapter *adapter = dev->data->dev_private;
1052 rc = ena_check_valid_conf(adapter);
1056 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1060 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1064 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1065 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1066 rc = ena_rss_init_default(adapter);
1071 ena_stats_restart(dev);
1073 adapter->timestamp_wd = rte_get_timer_cycles();
1074 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1076 ticks = rte_get_timer_hz();
1077 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1078 ena_timer_wd_callback, adapter);
1080 ++adapter->dev_stats.dev_start;
1081 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1086 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1088 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1092 static int ena_stop(struct rte_eth_dev *dev)
1094 struct ena_adapter *adapter = dev->data->dev_private;
1095 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1098 rte_timer_stop_sync(&adapter->timer_wd);
1099 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1100 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1102 if (adapter->trigger_reset) {
1103 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1105 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1108 ++adapter->dev_stats.dev_stop;
1109 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1110 dev->data->dev_started = 0;
1115 static int ena_create_io_queue(struct ena_ring *ring)
1117 struct ena_adapter *adapter;
1118 struct ena_com_dev *ena_dev;
1119 struct ena_com_create_io_ctx ctx =
1120 /* policy set to _HOST just to satisfy icc compiler */
1121 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1127 adapter = ring->adapter;
1128 ena_dev = &adapter->ena_dev;
1130 if (ring->type == ENA_RING_TYPE_TX) {
1131 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1132 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1133 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1134 for (i = 0; i < ring->ring_size; i++)
1135 ring->empty_tx_reqs[i] = i;
1137 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1138 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1139 for (i = 0; i < ring->ring_size; i++)
1140 ring->empty_rx_reqs[i] = i;
1142 ctx.queue_size = ring->ring_size;
1144 ctx.msix_vector = -1; /* interrupts not used */
1145 ctx.numa_node = ring->numa_socket_id;
1147 rc = ena_com_create_io_queue(ena_dev, &ctx);
1150 "failed to create io queue #%d (qid:%d) rc: %d\n",
1151 ring->id, ena_qid, rc);
1155 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1156 &ring->ena_com_io_sq,
1157 &ring->ena_com_io_cq);
1160 "Failed to get io queue handlers. queue num %d rc: %d\n",
1162 ena_com_destroy_io_queue(ena_dev, ena_qid);
1166 if (ring->type == ENA_RING_TYPE_TX)
1167 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1172 static void ena_queue_stop(struct ena_ring *ring)
1174 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1176 if (ring->type == ENA_RING_TYPE_RX) {
1177 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1178 ena_rx_queue_release_bufs(ring);
1180 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1181 ena_tx_queue_release_bufs(ring);
1185 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1186 enum ena_ring_type ring_type)
1188 struct ena_adapter *adapter = dev->data->dev_private;
1189 struct ena_ring *queues = NULL;
1190 uint16_t nb_queues, i;
1192 if (ring_type == ENA_RING_TYPE_RX) {
1193 queues = adapter->rx_ring;
1194 nb_queues = dev->data->nb_rx_queues;
1196 queues = adapter->tx_ring;
1197 nb_queues = dev->data->nb_tx_queues;
1200 for (i = 0; i < nb_queues; ++i)
1201 if (queues[i].configured)
1202 ena_queue_stop(&queues[i]);
1205 static int ena_queue_start(struct ena_ring *ring)
1209 ena_assert_msg(ring->configured == 1,
1210 "Trying to start unconfigured queue\n");
1212 rc = ena_create_io_queue(ring);
1214 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1218 ring->next_to_clean = 0;
1219 ring->next_to_use = 0;
1221 if (ring->type == ENA_RING_TYPE_TX) {
1222 ring->tx_stats.available_desc =
1223 ena_com_free_q_entries(ring->ena_com_io_sq);
1227 bufs_num = ring->ring_size - 1;
1228 rc = ena_populate_rx_queue(ring, bufs_num);
1229 if (rc != bufs_num) {
1230 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1231 ENA_IO_RXQ_IDX(ring->id));
1232 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1233 return ENA_COM_FAULT;
1235 /* Flush per-core RX buffers pools cache as they can be used on other
1238 rte_mempool_cache_flush(NULL, ring->mb_pool);
1243 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1246 unsigned int socket_id,
1247 const struct rte_eth_txconf *tx_conf)
1249 struct ena_ring *txq = NULL;
1250 struct ena_adapter *adapter = dev->data->dev_private;
1253 txq = &adapter->tx_ring[queue_idx];
1255 if (txq->configured) {
1257 "API violation. Queue %d is already configured\n",
1259 return ENA_COM_FAULT;
1262 if (!rte_is_power_of_2(nb_desc)) {
1264 "Unsupported size of TX queue: %d is not a power of 2.\n",
1269 if (nb_desc > adapter->max_tx_ring_size) {
1271 "Unsupported size of TX queue (max size: %d)\n",
1272 adapter->max_tx_ring_size);
1276 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1277 nb_desc = adapter->max_tx_ring_size;
1279 txq->port_id = dev->data->port_id;
1280 txq->next_to_clean = 0;
1281 txq->next_to_use = 0;
1282 txq->ring_size = nb_desc;
1283 txq->size_mask = nb_desc - 1;
1284 txq->numa_socket_id = socket_id;
1286 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1287 sizeof(struct ena_tx_buffer) *
1289 RTE_CACHE_LINE_SIZE);
1290 if (!txq->tx_buffer_info) {
1291 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1295 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1296 sizeof(u16) * txq->ring_size,
1297 RTE_CACHE_LINE_SIZE);
1298 if (!txq->empty_tx_reqs) {
1299 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1300 rte_free(txq->tx_buffer_info);
1304 txq->push_buf_intermediate_buf =
1305 rte_zmalloc("txq->push_buf_intermediate_buf",
1306 txq->tx_max_header_size,
1307 RTE_CACHE_LINE_SIZE);
1308 if (!txq->push_buf_intermediate_buf) {
1309 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1310 rte_free(txq->tx_buffer_info);
1311 rte_free(txq->empty_tx_reqs);
1315 for (i = 0; i < txq->ring_size; i++)
1316 txq->empty_tx_reqs[i] = i;
1318 if (tx_conf != NULL) {
1320 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1322 /* Store pointer to this queue in upper layer */
1323 txq->configured = 1;
1324 dev->data->tx_queues[queue_idx] = txq;
1329 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1332 unsigned int socket_id,
1333 __rte_unused const struct rte_eth_rxconf *rx_conf,
1334 struct rte_mempool *mp)
1336 struct ena_adapter *adapter = dev->data->dev_private;
1337 struct ena_ring *rxq = NULL;
1341 rxq = &adapter->rx_ring[queue_idx];
1342 if (rxq->configured) {
1344 "API violation. Queue %d is already configured\n",
1346 return ENA_COM_FAULT;
1349 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1350 nb_desc = adapter->max_rx_ring_size;
1352 if (!rte_is_power_of_2(nb_desc)) {
1354 "Unsupported size of RX queue: %d is not a power of 2.\n",
1359 if (nb_desc > adapter->max_rx_ring_size) {
1361 "Unsupported size of RX queue (max size: %d)\n",
1362 adapter->max_rx_ring_size);
1366 /* ENA isn't supporting buffers smaller than 1400 bytes */
1367 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1368 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1370 "Unsupported size of RX buffer: %zu (min size: %d)\n",
1371 buffer_size, ENA_RX_BUF_MIN_SIZE);
1375 rxq->port_id = dev->data->port_id;
1376 rxq->next_to_clean = 0;
1377 rxq->next_to_use = 0;
1378 rxq->ring_size = nb_desc;
1379 rxq->size_mask = nb_desc - 1;
1380 rxq->numa_socket_id = socket_id;
1383 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1384 sizeof(struct ena_rx_buffer) * nb_desc,
1385 RTE_CACHE_LINE_SIZE);
1386 if (!rxq->rx_buffer_info) {
1387 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1391 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1392 sizeof(struct rte_mbuf *) * nb_desc,
1393 RTE_CACHE_LINE_SIZE);
1395 if (!rxq->rx_refill_buffer) {
1396 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1397 rte_free(rxq->rx_buffer_info);
1398 rxq->rx_buffer_info = NULL;
1402 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1403 sizeof(uint16_t) * nb_desc,
1404 RTE_CACHE_LINE_SIZE);
1405 if (!rxq->empty_rx_reqs) {
1406 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1407 rte_free(rxq->rx_buffer_info);
1408 rxq->rx_buffer_info = NULL;
1409 rte_free(rxq->rx_refill_buffer);
1410 rxq->rx_refill_buffer = NULL;
1414 for (i = 0; i < nb_desc; i++)
1415 rxq->empty_rx_reqs[i] = i;
1417 /* Store pointer to this queue in upper layer */
1418 rxq->configured = 1;
1419 dev->data->rx_queues[queue_idx] = rxq;
1424 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1425 struct rte_mbuf *mbuf, uint16_t id)
1427 struct ena_com_buf ebuf;
1430 /* prepare physical address for DMA transaction */
1431 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1432 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1434 /* pass resource to device */
1435 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1436 if (unlikely(rc != 0))
1437 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1442 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1446 uint16_t next_to_use = rxq->next_to_use;
1447 uint16_t in_use, req_id;
1448 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1450 if (unlikely(!count))
1453 in_use = rxq->ring_size - 1 -
1454 ena_com_free_q_entries(rxq->ena_com_io_sq);
1455 ena_assert_msg(((in_use + count) < rxq->ring_size),
1456 "bad ring state\n");
1458 /* get resources for incoming packets */
1459 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1460 if (unlikely(rc < 0)) {
1461 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1462 ++rxq->rx_stats.mbuf_alloc_fail;
1463 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1467 for (i = 0; i < count; i++) {
1468 struct rte_mbuf *mbuf = mbufs[i];
1469 struct ena_rx_buffer *rx_info;
1471 if (likely((i + 4) < count))
1472 rte_prefetch0(mbufs[i + 4]);
1474 req_id = rxq->empty_rx_reqs[next_to_use];
1475 rx_info = &rxq->rx_buffer_info[req_id];
1477 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1478 if (unlikely(rc != 0))
1481 rx_info->mbuf = mbuf;
1482 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1485 if (unlikely(i < count)) {
1486 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1487 "buffers (from %d)\n", rxq->id, i, count);
1488 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1490 ++rxq->rx_stats.refill_partial;
1493 /* When we submitted free recources to device... */
1494 if (likely(i > 0)) {
1495 /* ...let HW know that it can fill buffers with data. */
1496 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1498 rxq->next_to_use = next_to_use;
1504 static int ena_device_init(struct ena_com_dev *ena_dev,
1505 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1508 uint32_t aenq_groups;
1510 bool readless_supported;
1512 /* Initialize mmio registers */
1513 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1515 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1519 /* The PCIe configuration space revision id indicate if mmio reg
1522 readless_supported =
1523 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1524 & ENA_MMIO_DISABLE_REG_READ);
1525 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1528 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1530 PMD_DRV_LOG(ERR, "cannot reset device\n");
1531 goto err_mmio_read_less;
1534 /* check FW version */
1535 rc = ena_com_validate_version(ena_dev);
1537 PMD_DRV_LOG(ERR, "device version is too low\n");
1538 goto err_mmio_read_less;
1541 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1543 /* ENA device administration layer init */
1544 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1547 "cannot initialize ena admin queue with device\n");
1548 goto err_mmio_read_less;
1551 /* To enable the msix interrupts the driver needs to know the number
1552 * of queues. So the driver uses polling mode to retrieve this
1555 ena_com_set_admin_polling_mode(ena_dev, true);
1557 ena_config_host_info(ena_dev);
1559 /* Get Device Attributes and features */
1560 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1563 "cannot get attribute for ena device rc= %d\n", rc);
1564 goto err_admin_init;
1567 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1568 BIT(ENA_ADMIN_NOTIFICATION) |
1569 BIT(ENA_ADMIN_KEEP_ALIVE) |
1570 BIT(ENA_ADMIN_FATAL_ERROR) |
1571 BIT(ENA_ADMIN_WARNING);
1573 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1574 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1576 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1577 goto err_admin_init;
1580 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1585 ena_com_admin_destroy(ena_dev);
1588 ena_com_mmio_reg_read_request_destroy(ena_dev);
1593 static void ena_interrupt_handler_rte(void *cb_arg)
1595 struct ena_adapter *adapter = cb_arg;
1596 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1598 ena_com_admin_q_comp_intr_handler(ena_dev);
1599 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1600 ena_com_aenq_intr_handler(ena_dev, adapter);
1603 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1605 if (!adapter->wd_state)
1608 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1611 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1612 adapter->keep_alive_timeout)) {
1613 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1614 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1615 adapter->trigger_reset = true;
1616 ++adapter->dev_stats.wd_expired;
1620 /* Check if admin queue is enabled */
1621 static void check_for_admin_com_state(struct ena_adapter *adapter)
1623 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1624 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1625 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1626 adapter->trigger_reset = true;
1630 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1633 struct ena_adapter *adapter = arg;
1634 struct rte_eth_dev *dev = adapter->rte_dev;
1636 check_for_missing_keep_alive(adapter);
1637 check_for_admin_com_state(adapter);
1639 if (unlikely(adapter->trigger_reset)) {
1640 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1641 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1647 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1648 struct ena_admin_feature_llq_desc *llq,
1649 bool use_large_llq_hdr)
1651 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1652 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1653 llq_config->llq_num_decs_before_header =
1654 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1656 if (use_large_llq_hdr &&
1657 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1658 llq_config->llq_ring_entry_size =
1659 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1660 llq_config->llq_ring_entry_size_value = 256;
1662 llq_config->llq_ring_entry_size =
1663 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1664 llq_config->llq_ring_entry_size_value = 128;
1669 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1670 struct ena_com_dev *ena_dev,
1671 struct ena_admin_feature_llq_desc *llq,
1672 struct ena_llq_configurations *llq_default_configurations)
1675 u32 llq_feature_mask;
1677 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1678 if (!(ena_dev->supported_features & llq_feature_mask)) {
1680 "LLQ is not supported. Fallback to host mode policy.\n");
1681 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1685 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1687 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1688 "Fallback to host mode policy.");
1689 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1693 /* Nothing to config, exit */
1694 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1697 if (!adapter->dev_mem_base) {
1698 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1699 "Fallback to host mode policy.\n.");
1700 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1704 ena_dev->mem_bar = adapter->dev_mem_base;
1709 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1710 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1712 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1714 /* Regular queues capabilities */
1715 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1716 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1717 &get_feat_ctx->max_queue_ext.max_queue_ext;
1718 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1719 max_queue_ext->max_rx_cq_num);
1720 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1721 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1723 struct ena_admin_queue_feature_desc *max_queues =
1724 &get_feat_ctx->max_queues;
1725 io_tx_sq_num = max_queues->max_sq_num;
1726 io_tx_cq_num = max_queues->max_cq_num;
1727 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1730 /* In case of LLQ use the llq number in the get feature cmd */
1731 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1732 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1734 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1735 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1736 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1738 if (unlikely(max_num_io_queues == 0)) {
1739 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1743 return max_num_io_queues;
1746 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1748 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1749 struct rte_pci_device *pci_dev;
1750 struct rte_intr_handle *intr_handle;
1751 struct ena_adapter *adapter = eth_dev->data->dev_private;
1752 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1753 struct ena_com_dev_get_features_ctx get_feat_ctx;
1754 struct ena_llq_configurations llq_config;
1755 const char *queue_type_str;
1756 uint32_t max_num_io_queues;
1758 static int adapters_found;
1759 bool disable_meta_caching;
1760 bool wd_state = false;
1762 eth_dev->dev_ops = &ena_dev_ops;
1763 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1764 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1765 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1767 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1770 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1772 memset(adapter, 0, sizeof(struct ena_adapter));
1773 ena_dev = &adapter->ena_dev;
1775 adapter->rte_eth_dev_data = eth_dev->data;
1776 adapter->rte_dev = eth_dev;
1778 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1779 adapter->pdev = pci_dev;
1781 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1782 pci_dev->addr.domain,
1784 pci_dev->addr.devid,
1785 pci_dev->addr.function);
1787 intr_handle = &pci_dev->intr_handle;
1789 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1790 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1792 if (!adapter->regs) {
1793 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1798 ena_dev->reg_bar = adapter->regs;
1799 ena_dev->dmadev = adapter->pdev;
1801 adapter->id_number = adapters_found;
1803 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1804 adapter->id_number);
1806 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1808 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1812 /* device specific initialization routine */
1813 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1815 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1818 adapter->wd_state = wd_state;
1820 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1821 adapter->use_large_llq_hdr);
1822 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1823 &get_feat_ctx.llq, &llq_config);
1825 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1829 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1830 queue_type_str = "Regular";
1832 queue_type_str = "Low latency";
1833 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1835 calc_queue_ctx.ena_dev = ena_dev;
1836 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1838 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1839 rc = ena_calc_io_queue_size(&calc_queue_ctx,
1840 adapter->use_large_llq_hdr);
1841 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1843 goto err_device_destroy;
1846 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1847 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1848 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1849 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1850 adapter->max_num_io_queues = max_num_io_queues;
1852 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1853 disable_meta_caching =
1854 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1855 BIT(ENA_ADMIN_DISABLE_META_CACHING));
1857 disable_meta_caching = false;
1860 /* prepare ring structures */
1861 ena_init_rings(adapter, disable_meta_caching);
1863 ena_config_debug_area(adapter);
1865 /* Set max MTU for this device */
1866 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1868 /* set device support for offloads */
1869 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1870 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1871 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1872 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1873 adapter->offloads.rx_csum_supported =
1874 (get_feat_ctx.offload.rx_supported &
1875 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1877 /* Copy MAC address and point DPDK to it */
1878 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1879 rte_ether_addr_copy((struct rte_ether_addr *)
1880 get_feat_ctx.dev_attr.mac_addr,
1881 (struct rte_ether_addr *)adapter->mac_addr);
1883 adapter->drv_stats = rte_zmalloc("adapter stats",
1884 sizeof(*adapter->drv_stats),
1885 RTE_CACHE_LINE_SIZE);
1886 if (!adapter->drv_stats) {
1887 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1889 goto err_delete_debug_area;
1892 rte_spinlock_init(&adapter->admin_lock);
1894 rte_intr_callback_register(intr_handle,
1895 ena_interrupt_handler_rte,
1897 rte_intr_enable(intr_handle);
1898 ena_com_set_admin_polling_mode(ena_dev, false);
1899 ena_com_admin_aenq_enable(ena_dev);
1901 if (adapters_found == 0)
1902 rte_timer_subsystem_init();
1903 rte_timer_init(&adapter->timer_wd);
1906 adapter->state = ENA_ADAPTER_STATE_INIT;
1910 err_delete_debug_area:
1911 ena_com_delete_debug_area(ena_dev);
1914 ena_com_delete_host_info(ena_dev);
1915 ena_com_admin_destroy(ena_dev);
1921 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1923 struct ena_adapter *adapter = eth_dev->data->dev_private;
1924 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1926 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1929 ena_com_set_admin_running_state(ena_dev, false);
1931 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1934 ena_com_delete_debug_area(ena_dev);
1935 ena_com_delete_host_info(ena_dev);
1937 ena_com_abort_admin_commands(ena_dev);
1938 ena_com_wait_for_abort_completion(ena_dev);
1939 ena_com_admin_destroy(ena_dev);
1940 ena_com_mmio_reg_read_request_destroy(ena_dev);
1942 adapter->state = ENA_ADAPTER_STATE_FREE;
1945 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1947 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1950 ena_destroy_device(eth_dev);
1955 static int ena_dev_configure(struct rte_eth_dev *dev)
1957 struct ena_adapter *adapter = dev->data->dev_private;
1959 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1961 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1962 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1966 static void ena_init_rings(struct ena_adapter *adapter,
1967 bool disable_meta_caching)
1971 for (i = 0; i < adapter->max_num_io_queues; i++) {
1972 struct ena_ring *ring = &adapter->tx_ring[i];
1974 ring->configured = 0;
1975 ring->type = ENA_RING_TYPE_TX;
1976 ring->adapter = adapter;
1978 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1979 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1980 ring->sgl_size = adapter->max_tx_sgl_size;
1981 ring->disable_meta_caching = disable_meta_caching;
1984 for (i = 0; i < adapter->max_num_io_queues; i++) {
1985 struct ena_ring *ring = &adapter->rx_ring[i];
1987 ring->configured = 0;
1988 ring->type = ENA_RING_TYPE_RX;
1989 ring->adapter = adapter;
1991 ring->sgl_size = adapter->max_rx_sgl_size;
1995 static int ena_infos_get(struct rte_eth_dev *dev,
1996 struct rte_eth_dev_info *dev_info)
1998 struct ena_adapter *adapter;
1999 struct ena_com_dev *ena_dev;
2000 uint64_t rx_feat = 0, tx_feat = 0;
2002 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2003 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2004 adapter = dev->data->dev_private;
2006 ena_dev = &adapter->ena_dev;
2007 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2009 dev_info->speed_capa =
2011 ETH_LINK_SPEED_2_5G |
2013 ETH_LINK_SPEED_10G |
2014 ETH_LINK_SPEED_25G |
2015 ETH_LINK_SPEED_40G |
2016 ETH_LINK_SPEED_50G |
2017 ETH_LINK_SPEED_100G;
2019 /* Set Tx & Rx features available for device */
2020 if (adapter->offloads.tso4_supported)
2021 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2023 if (adapter->offloads.tx_csum_supported)
2024 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2025 DEV_TX_OFFLOAD_UDP_CKSUM |
2026 DEV_TX_OFFLOAD_TCP_CKSUM;
2028 if (adapter->offloads.rx_csum_supported)
2029 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2030 DEV_RX_OFFLOAD_UDP_CKSUM |
2031 DEV_RX_OFFLOAD_TCP_CKSUM;
2033 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2035 /* Inform framework about available features */
2036 dev_info->rx_offload_capa = rx_feat;
2037 dev_info->rx_queue_offload_capa = rx_feat;
2038 dev_info->tx_offload_capa = tx_feat;
2039 dev_info->tx_queue_offload_capa = tx_feat;
2041 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2044 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2045 dev_info->max_rx_pktlen = adapter->max_mtu;
2046 dev_info->max_mac_addrs = 1;
2048 dev_info->max_rx_queues = adapter->max_num_io_queues;
2049 dev_info->max_tx_queues = adapter->max_num_io_queues;
2050 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2052 adapter->tx_supported_offloads = tx_feat;
2053 adapter->rx_supported_offloads = rx_feat;
2055 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2056 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2057 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2058 adapter->max_rx_sgl_size);
2059 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2060 adapter->max_rx_sgl_size);
2062 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2063 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2064 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2065 adapter->max_tx_sgl_size);
2066 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2067 adapter->max_tx_sgl_size);
2072 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2074 mbuf->data_len = len;
2075 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2080 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2081 struct ena_com_rx_buf_info *ena_bufs,
2083 uint16_t *next_to_clean,
2086 struct rte_mbuf *mbuf;
2087 struct rte_mbuf *mbuf_head;
2088 struct ena_rx_buffer *rx_info;
2090 uint16_t ntc, len, req_id, buf = 0;
2092 if (unlikely(descs == 0))
2095 ntc = *next_to_clean;
2097 len = ena_bufs[buf].len;
2098 req_id = ena_bufs[buf].req_id;
2100 rx_info = &rx_ring->rx_buffer_info[req_id];
2102 mbuf = rx_info->mbuf;
2103 RTE_ASSERT(mbuf != NULL);
2105 ena_init_rx_mbuf(mbuf, len);
2107 /* Fill the mbuf head with the data specific for 1st segment. */
2109 mbuf_head->nb_segs = descs;
2110 mbuf_head->port = rx_ring->port_id;
2111 mbuf_head->pkt_len = len;
2112 mbuf_head->data_off += offset;
2114 rx_info->mbuf = NULL;
2115 rx_ring->empty_rx_reqs[ntc] = req_id;
2116 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2120 len = ena_bufs[buf].len;
2121 req_id = ena_bufs[buf].req_id;
2123 rx_info = &rx_ring->rx_buffer_info[req_id];
2124 RTE_ASSERT(rx_info->mbuf != NULL);
2126 if (unlikely(len == 0)) {
2128 * Some devices can pass descriptor with the length 0.
2129 * To avoid confusion, the PMD is simply putting the
2130 * descriptor back, as it was never used. We'll avoid
2131 * mbuf allocation that way.
2133 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2134 rx_info->mbuf, req_id);
2135 if (unlikely(rc != 0)) {
2136 /* Free the mbuf in case of an error. */
2137 rte_mbuf_raw_free(rx_info->mbuf);
2140 * If there was no error, just exit the loop as
2141 * 0 length descriptor is always the last one.
2146 /* Create an mbuf chain. */
2147 mbuf->next = rx_info->mbuf;
2150 ena_init_rx_mbuf(mbuf, len);
2151 mbuf_head->pkt_len += len;
2155 * Mark the descriptor as depleted and perform necessary
2157 * This code will execute in two cases:
2158 * 1. Descriptor len was greater than 0 - normal situation.
2159 * 2. Descriptor len was 0 and we failed to add the descriptor
2160 * to the device. In that situation, we should try to add
2161 * the mbuf again in the populate routine and mark the
2162 * descriptor as used up by the device.
2164 rx_info->mbuf = NULL;
2165 rx_ring->empty_rx_reqs[ntc] = req_id;
2166 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2169 *next_to_clean = ntc;
2174 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2177 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2178 unsigned int free_queue_entries;
2179 unsigned int refill_threshold;
2180 uint16_t next_to_clean = rx_ring->next_to_clean;
2181 uint16_t descs_in_use;
2182 struct rte_mbuf *mbuf;
2184 struct ena_com_rx_ctx ena_rx_ctx;
2187 /* Check adapter state */
2188 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2190 "Trying to receive pkts while device is NOT running\n");
2194 descs_in_use = rx_ring->ring_size -
2195 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2196 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2198 for (completed = 0; completed < nb_pkts; completed++) {
2199 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2200 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2201 ena_rx_ctx.descs = 0;
2202 ena_rx_ctx.pkt_offset = 0;
2203 /* receive packet context */
2204 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2205 rx_ring->ena_com_io_sq,
2208 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2209 if (rc == ENA_COM_NO_SPACE) {
2210 ++rx_ring->rx_stats.bad_desc_num;
2211 rx_ring->adapter->reset_reason =
2212 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2214 ++rx_ring->rx_stats.bad_req_id;
2215 rx_ring->adapter->reset_reason =
2216 ENA_REGS_RESET_INV_RX_REQ_ID;
2218 rx_ring->adapter->trigger_reset = true;
2222 mbuf = ena_rx_mbuf(rx_ring,
2223 ena_rx_ctx.ena_bufs,
2226 ena_rx_ctx.pkt_offset);
2227 if (unlikely(mbuf == NULL)) {
2228 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2229 rx_ring->empty_rx_reqs[next_to_clean] =
2230 rx_ring->ena_bufs[i].req_id;
2231 next_to_clean = ENA_IDX_NEXT_MASKED(
2232 next_to_clean, rx_ring->size_mask);
2237 /* fill mbuf attributes if any */
2238 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2240 if (unlikely(mbuf->ol_flags &
2241 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2242 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2243 ++rx_ring->rx_stats.bad_csum;
2246 mbuf->hash.rss = ena_rx_ctx.hash;
2248 rx_pkts[completed] = mbuf;
2249 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2252 rx_ring->rx_stats.cnt += completed;
2253 rx_ring->next_to_clean = next_to_clean;
2255 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2257 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2258 (unsigned int)ENA_REFILL_THRESH_PACKET);
2260 /* Burst refill to save doorbells, memory barriers, const interval */
2261 if (free_queue_entries > refill_threshold) {
2262 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2263 ena_populate_rx_queue(rx_ring, free_queue_entries);
2270 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2276 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2277 struct rte_ipv4_hdr *ip_hdr;
2279 uint16_t frag_field;
2281 for (i = 0; i != nb_pkts; i++) {
2283 ol_flags = m->ol_flags;
2285 if (!(ol_flags & PKT_TX_IPV4))
2288 /* If there was not L2 header length specified, assume it is
2289 * length of the ethernet header.
2291 if (unlikely(m->l2_len == 0))
2292 m->l2_len = sizeof(struct rte_ether_hdr);
2294 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2296 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2298 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2299 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2301 /* If IPv4 header has DF flag enabled and TSO support is
2302 * disabled, partial chcecksum should not be calculated.
2304 if (!tx_ring->adapter->offloads.tso4_supported)
2308 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2309 (ol_flags & PKT_TX_L4_MASK) ==
2310 PKT_TX_SCTP_CKSUM) {
2311 rte_errno = ENOTSUP;
2315 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2316 ret = rte_validate_tx_offload(m);
2323 /* In case we are supposed to TSO and have DF not set (DF=0)
2324 * hardware must be provided with partial checksum, otherwise
2325 * it will take care of necessary calculations.
2328 ret = rte_net_intel_cksum_flags_prepare(m,
2329 ol_flags & ~PKT_TX_TCP_SEG);
2339 static void ena_update_hints(struct ena_adapter *adapter,
2340 struct ena_admin_ena_hw_hints *hints)
2342 if (hints->admin_completion_tx_timeout)
2343 adapter->ena_dev.admin_queue.completion_timeout =
2344 hints->admin_completion_tx_timeout * 1000;
2346 if (hints->mmio_read_timeout)
2347 /* convert to usec */
2348 adapter->ena_dev.mmio_read.reg_read_to =
2349 hints->mmio_read_timeout * 1000;
2351 if (hints->driver_watchdog_timeout) {
2352 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2353 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2355 // Convert msecs to ticks
2356 adapter->keep_alive_timeout =
2357 (hints->driver_watchdog_timeout *
2358 rte_get_timer_hz()) / 1000;
2362 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2363 struct rte_mbuf *mbuf)
2365 struct ena_com_dev *ena_dev;
2366 int num_segments, header_len, rc;
2368 ena_dev = &tx_ring->adapter->ena_dev;
2369 num_segments = mbuf->nb_segs;
2370 header_len = mbuf->data_len;
2372 if (likely(num_segments < tx_ring->sgl_size))
2375 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2376 (num_segments == tx_ring->sgl_size) &&
2377 (header_len < tx_ring->tx_max_header_size))
2380 /* Checking for space for 2 additional metadata descriptors due to
2381 * possible header split and metadata descriptor. Linearization will
2382 * be needed so we reduce the segments number from num_segments to 1
2384 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2385 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2386 return ENA_COM_NO_MEM;
2388 ++tx_ring->tx_stats.linearize;
2389 rc = rte_pktmbuf_linearize(mbuf);
2391 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2392 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2393 ++tx_ring->tx_stats.linearize_failed;
2400 /* Checking for space for 2 additional metadata descriptors due to
2401 * possible header split and metadata descriptor
2403 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2404 num_segments + 2)) {
2405 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2406 return ENA_COM_NO_MEM;
2412 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2413 struct ena_tx_buffer *tx_info,
2414 struct rte_mbuf *mbuf,
2416 uint16_t *header_len)
2418 struct ena_com_buf *ena_buf;
2419 uint16_t delta, seg_len, push_len;
2422 seg_len = mbuf->data_len;
2424 tx_info->mbuf = mbuf;
2425 ena_buf = tx_info->bufs;
2427 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2429 * Tx header might be (and will be in most cases) smaller than
2430 * tx_max_header_size. But it's not an issue to send more data
2431 * to the device, than actually needed if the mbuf size is
2432 * greater than tx_max_header_size.
2434 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2435 *header_len = push_len;
2437 if (likely(push_len <= seg_len)) {
2438 /* If the push header is in the single segment, then
2439 * just point it to the 1st mbuf data.
2441 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2443 /* If the push header lays in the several segments, copy
2444 * it to the intermediate buffer.
2446 rte_pktmbuf_read(mbuf, 0, push_len,
2447 tx_ring->push_buf_intermediate_buf);
2448 *push_header = tx_ring->push_buf_intermediate_buf;
2449 delta = push_len - seg_len;
2452 *push_header = NULL;
2457 /* Process first segment taking into consideration pushed header */
2458 if (seg_len > push_len) {
2459 ena_buf->paddr = mbuf->buf_iova +
2462 ena_buf->len = seg_len - push_len;
2464 tx_info->num_of_bufs++;
2467 while ((mbuf = mbuf->next) != NULL) {
2468 seg_len = mbuf->data_len;
2470 /* Skip mbufs if whole data is pushed as a header */
2471 if (unlikely(delta > seg_len)) {
2476 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2477 ena_buf->len = seg_len - delta;
2479 tx_info->num_of_bufs++;
2485 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2487 struct ena_tx_buffer *tx_info;
2488 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2489 uint16_t next_to_use;
2490 uint16_t header_len;
2496 rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2500 next_to_use = tx_ring->next_to_use;
2502 req_id = tx_ring->empty_tx_reqs[next_to_use];
2503 tx_info = &tx_ring->tx_buffer_info[req_id];
2504 tx_info->num_of_bufs = 0;
2506 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2508 ena_tx_ctx.ena_bufs = tx_info->bufs;
2509 ena_tx_ctx.push_header = push_header;
2510 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2511 ena_tx_ctx.req_id = req_id;
2512 ena_tx_ctx.header_len = header_len;
2514 /* Set Tx offloads flags, if applicable */
2515 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2516 tx_ring->disable_meta_caching);
2518 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2521 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2523 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2524 tx_ring->tx_stats.doorbells++;
2527 /* prepare the packet's descriptors to dma engine */
2528 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2531 ++tx_ring->tx_stats.prepare_ctx_err;
2535 tx_info->tx_descs = nb_hw_desc;
2537 tx_ring->tx_stats.cnt++;
2538 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2540 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2541 tx_ring->size_mask);
2546 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2548 unsigned int cleanup_budget;
2549 unsigned int total_tx_descs = 0;
2550 uint16_t next_to_clean = tx_ring->next_to_clean;
2552 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2553 (unsigned int)ENA_REFILL_THRESH_PACKET);
2555 while (likely(total_tx_descs < cleanup_budget)) {
2556 struct rte_mbuf *mbuf;
2557 struct ena_tx_buffer *tx_info;
2560 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2563 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2566 /* Get Tx info & store how many descs were processed */
2567 tx_info = &tx_ring->tx_buffer_info[req_id];
2569 mbuf = tx_info->mbuf;
2570 rte_pktmbuf_free(mbuf);
2572 tx_info->mbuf = NULL;
2573 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2575 total_tx_descs += tx_info->tx_descs;
2577 /* Put back descriptor to the ring for reuse */
2578 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2579 tx_ring->size_mask);
2582 if (likely(total_tx_descs > 0)) {
2583 /* acknowledge completion of sent packets */
2584 tx_ring->next_to_clean = next_to_clean;
2585 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2586 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2590 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2593 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2594 uint16_t sent_idx = 0;
2596 /* Check adapter state */
2597 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2599 "Trying to xmit pkts while device is NOT running\n");
2603 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2604 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2607 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2608 tx_ring->size_mask)]);
2611 tx_ring->tx_stats.available_desc =
2612 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2614 /* If there are ready packets to be xmitted... */
2616 /* ...let HW do its best :-) */
2617 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2618 tx_ring->tx_stats.doorbells++;
2621 ena_tx_cleanup(tx_ring);
2623 tx_ring->tx_stats.available_desc =
2624 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2625 tx_ring->tx_stats.tx_poll++;
2630 int ena_copy_eni_stats(struct ena_adapter *adapter)
2632 struct ena_admin_eni_stats admin_eni_stats;
2635 rte_spinlock_lock(&adapter->admin_lock);
2636 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2637 rte_spinlock_unlock(&adapter->admin_lock);
2639 if (rc == ENA_COM_UNSUPPORTED) {
2641 "Retrieving ENI metrics is not supported.\n");
2643 PMD_DRV_LOG(WARNING,
2644 "Failed to get ENI metrics: %d\n", rc);
2649 rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2650 sizeof(struct ena_stats_eni));
2656 * DPDK callback to retrieve names of extended device statistics
2659 * Pointer to Ethernet device structure.
2660 * @param[out] xstats_names
2661 * Buffer to insert names into.
2666 * Number of xstats names.
2668 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2669 struct rte_eth_xstat_name *xstats_names,
2672 unsigned int xstats_count = ena_xstats_calc_num(dev);
2673 unsigned int stat, i, count = 0;
2675 if (n < xstats_count || !xstats_names)
2676 return xstats_count;
2678 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2679 strcpy(xstats_names[count].name,
2680 ena_stats_global_strings[stat].name);
2682 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2683 strcpy(xstats_names[count].name,
2684 ena_stats_eni_strings[stat].name);
2686 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2687 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2688 snprintf(xstats_names[count].name,
2689 sizeof(xstats_names[count].name),
2691 ena_stats_rx_strings[stat].name);
2693 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2694 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2695 snprintf(xstats_names[count].name,
2696 sizeof(xstats_names[count].name),
2698 ena_stats_tx_strings[stat].name);
2700 return xstats_count;
2704 * DPDK callback to get extended device statistics.
2707 * Pointer to Ethernet device structure.
2709 * Stats table output buffer.
2711 * The size of the stats table.
2714 * Number of xstats on success, negative on failure.
2716 static int ena_xstats_get(struct rte_eth_dev *dev,
2717 struct rte_eth_xstat *xstats,
2720 struct ena_adapter *adapter = dev->data->dev_private;
2721 unsigned int xstats_count = ena_xstats_calc_num(dev);
2722 unsigned int stat, i, count = 0;
2726 if (n < xstats_count)
2727 return xstats_count;
2732 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2733 stat_offset = ena_stats_global_strings[stat].stat_offset;
2734 stats_begin = &adapter->dev_stats;
2736 xstats[count].id = count;
2737 xstats[count].value = *((uint64_t *)
2738 ((char *)stats_begin + stat_offset));
2741 /* Even if the function below fails, we should copy previous (or initial
2742 * values) to keep structure of rte_eth_xstat consistent.
2744 ena_copy_eni_stats(adapter);
2745 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2746 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2747 stats_begin = &adapter->eni_stats;
2749 xstats[count].id = count;
2750 xstats[count].value = *((uint64_t *)
2751 ((char *)stats_begin + stat_offset));
2754 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2755 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2756 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2757 stats_begin = &adapter->rx_ring[i].rx_stats;
2759 xstats[count].id = count;
2760 xstats[count].value = *((uint64_t *)
2761 ((char *)stats_begin + stat_offset));
2765 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2766 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2767 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2768 stats_begin = &adapter->tx_ring[i].rx_stats;
2770 xstats[count].id = count;
2771 xstats[count].value = *((uint64_t *)
2772 ((char *)stats_begin + stat_offset));
2779 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2780 const uint64_t *ids,
2784 struct ena_adapter *adapter = dev->data->dev_private;
2786 uint64_t rx_entries, tx_entries;
2790 bool was_eni_copied = false;
2792 for (i = 0; i < n; ++i) {
2794 /* Check if id belongs to global statistics */
2795 if (id < ENA_STATS_ARRAY_GLOBAL) {
2796 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2801 /* Check if id belongs to ENI statistics */
2802 id -= ENA_STATS_ARRAY_GLOBAL;
2803 if (id < ENA_STATS_ARRAY_ENI) {
2804 /* Avoid reading ENI stats multiple times in a single
2805 * function call, as it requires communication with the
2808 if (!was_eni_copied) {
2809 was_eni_copied = true;
2810 ena_copy_eni_stats(adapter);
2812 values[i] = *((uint64_t *)&adapter->eni_stats + id);
2817 /* Check if id belongs to rx queue statistics */
2818 id -= ENA_STATS_ARRAY_ENI;
2819 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2820 if (id < rx_entries) {
2821 qid = id % dev->data->nb_rx_queues;
2822 id /= dev->data->nb_rx_queues;
2823 values[i] = *((uint64_t *)
2824 &adapter->rx_ring[qid].rx_stats + id);
2828 /* Check if id belongs to rx queue statistics */
2830 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2831 if (id < tx_entries) {
2832 qid = id % dev->data->nb_tx_queues;
2833 id /= dev->data->nb_tx_queues;
2834 values[i] = *((uint64_t *)
2835 &adapter->tx_ring[qid].tx_stats + id);
2844 static int ena_process_bool_devarg(const char *key,
2848 struct ena_adapter *adapter = opaque;
2851 /* Parse the value. */
2852 if (strcmp(value, "1") == 0) {
2854 } else if (strcmp(value, "0") == 0) {
2858 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2863 /* Now, assign it to the proper adapter field. */
2864 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2865 adapter->use_large_llq_hdr = bool_value;
2870 static int ena_parse_devargs(struct ena_adapter *adapter,
2871 struct rte_devargs *devargs)
2873 static const char * const allowed_args[] = {
2874 ENA_DEVARG_LARGE_LLQ_HDR,
2876 struct rte_kvargs *kvlist;
2879 if (devargs == NULL)
2882 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2883 if (kvlist == NULL) {
2884 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2889 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2890 ena_process_bool_devarg, adapter);
2892 rte_kvargs_free(kvlist);
2897 /*********************************************************************
2899 *********************************************************************/
2900 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2901 struct rte_pci_device *pci_dev)
2903 return rte_eth_dev_pci_generic_probe(pci_dev,
2904 sizeof(struct ena_adapter), eth_ena_dev_init);
2907 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2909 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2912 static struct rte_pci_driver rte_ena_pmd = {
2913 .id_table = pci_id_ena_map,
2914 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2915 RTE_PCI_DRV_WC_ACTIVATE,
2916 .probe = eth_ena_pci_probe,
2917 .remove = eth_ena_pci_remove,
2920 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2921 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2922 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2923 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2924 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE);
2925 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE);
2926 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2927 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE);
2929 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2930 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE);
2932 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2933 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE);
2935 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2936 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE);
2939 /******************************************************************************
2940 ******************************** AENQ Handlers *******************************
2941 *****************************************************************************/
2942 static void ena_update_on_link_change(void *adapter_data,
2943 struct ena_admin_aenq_entry *aenq_e)
2945 struct rte_eth_dev *eth_dev;
2946 struct ena_adapter *adapter;
2947 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2950 adapter = adapter_data;
2951 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2952 eth_dev = adapter->rte_dev;
2954 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2955 adapter->link_status = status;
2957 ena_link_update(eth_dev, 0);
2958 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2961 static void ena_notification(void *data,
2962 struct ena_admin_aenq_entry *aenq_e)
2964 struct ena_adapter *adapter = data;
2965 struct ena_admin_ena_hw_hints *hints;
2967 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2968 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2969 aenq_e->aenq_common_desc.group,
2970 ENA_ADMIN_NOTIFICATION);
2972 switch (aenq_e->aenq_common_desc.syndrom) {
2973 case ENA_ADMIN_UPDATE_HINTS:
2974 hints = (struct ena_admin_ena_hw_hints *)
2975 (&aenq_e->inline_data_w4);
2976 ena_update_hints(adapter, hints);
2979 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2980 aenq_e->aenq_common_desc.syndrom);
2984 static void ena_keep_alive(void *adapter_data,
2985 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2987 struct ena_adapter *adapter = adapter_data;
2988 struct ena_admin_aenq_keep_alive_desc *desc;
2992 adapter->timestamp_wd = rte_get_timer_cycles();
2994 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2995 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2996 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2998 adapter->drv_stats->rx_drops = rx_drops;
2999 adapter->dev_stats.tx_drops = tx_drops;
3003 * This handler will called for unknown event group or unimplemented handlers
3005 static void unimplemented_aenq_handler(__rte_unused void *data,
3006 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3008 PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3009 "unimplemented handler\n");
3012 static struct ena_aenq_handlers aenq_handlers = {
3014 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3015 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3016 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3018 .unimplemented_handler = unimplemented_aenq_handler