1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_ethdev_pci.h>
11 #include <rte_atomic.h>
13 #include <rte_errno.h>
14 #include <rte_version.h>
16 #include <rte_kvargs.h>
18 #include "ena_ethdev.h"
20 #include "ena_platform.h"
22 #include "ena_eth_com.h"
24 #include <ena_common_defs.h>
25 #include <ena_regs_defs.h>
26 #include <ena_admin_defs.h>
27 #include <ena_eth_io_defs.h>
29 #define DRV_MODULE_VER_MAJOR 2
30 #define DRV_MODULE_VER_MINOR 1
31 #define DRV_MODULE_VER_SUBMINOR 0
33 #define ENA_IO_TXQ_IDX(q) (2 * (q))
34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
35 /*reverse version of ENA_IO_RXQ_IDX*/
36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
41 #define GET_L4_HDR_LEN(mbuf) \
42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
47 #define ENA_HASH_KEY_SIZE 40
48 #define ETH_GSTRING_LEN 32
50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
52 #define ENA_MIN_RING_DESC 128
54 enum ethtool_stringset {
60 char name[ETH_GSTRING_LEN];
64 #define ENA_STAT_ENTRY(stat, stat_type) { \
66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
69 #define ENA_STAT_RX_ENTRY(stat) \
70 ENA_STAT_ENTRY(stat, rx)
72 #define ENA_STAT_TX_ENTRY(stat) \
73 ENA_STAT_ENTRY(stat, tx)
75 #define ENA_STAT_ENI_ENTRY(stat) \
76 ENA_STAT_ENTRY(stat, eni)
78 #define ENA_STAT_GLOBAL_ENTRY(stat) \
79 ENA_STAT_ENTRY(stat, dev)
81 /* Device arguments */
82 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
85 * Each rte_memzone should have unique name.
86 * To satisfy it, count number of allocation and add it to name.
88 rte_atomic32_t ena_alloc_cnt;
90 static const struct ena_stats ena_stats_global_strings[] = {
91 ENA_STAT_GLOBAL_ENTRY(wd_expired),
92 ENA_STAT_GLOBAL_ENTRY(dev_start),
93 ENA_STAT_GLOBAL_ENTRY(dev_stop),
94 ENA_STAT_GLOBAL_ENTRY(tx_drops),
97 static const struct ena_stats ena_stats_eni_strings[] = {
98 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
99 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
100 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
101 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
102 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
105 static const struct ena_stats ena_stats_tx_strings[] = {
106 ENA_STAT_TX_ENTRY(cnt),
107 ENA_STAT_TX_ENTRY(bytes),
108 ENA_STAT_TX_ENTRY(prepare_ctx_err),
109 ENA_STAT_TX_ENTRY(linearize),
110 ENA_STAT_TX_ENTRY(linearize_failed),
111 ENA_STAT_TX_ENTRY(tx_poll),
112 ENA_STAT_TX_ENTRY(doorbells),
113 ENA_STAT_TX_ENTRY(bad_req_id),
114 ENA_STAT_TX_ENTRY(available_desc),
117 static const struct ena_stats ena_stats_rx_strings[] = {
118 ENA_STAT_RX_ENTRY(cnt),
119 ENA_STAT_RX_ENTRY(bytes),
120 ENA_STAT_RX_ENTRY(refill_partial),
121 ENA_STAT_RX_ENTRY(bad_csum),
122 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
123 ENA_STAT_RX_ENTRY(bad_desc_num),
124 ENA_STAT_RX_ENTRY(bad_req_id),
127 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
128 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings)
129 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
130 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
132 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
133 DEV_TX_OFFLOAD_UDP_CKSUM |\
134 DEV_TX_OFFLOAD_IPV4_CKSUM |\
135 DEV_TX_OFFLOAD_TCP_TSO)
136 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
140 /** Vendor ID used by Amazon devices */
141 #define PCI_VENDOR_ID_AMAZON 0x1D0F
142 /** Amazon devices */
143 #define PCI_DEVICE_ID_ENA_VF 0xEC20
144 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
146 #define ENA_TX_OFFLOAD_MASK (\
153 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
154 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
156 static const struct rte_pci_id pci_id_ena_map[] = {
157 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
158 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
162 static struct ena_aenq_handlers aenq_handlers;
164 static int ena_device_init(struct ena_com_dev *ena_dev,
165 struct ena_com_dev_get_features_ctx *get_feat_ctx,
167 static int ena_dev_configure(struct rte_eth_dev *dev);
168 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
169 struct ena_tx_buffer *tx_info,
170 struct rte_mbuf *mbuf,
172 uint16_t *header_len);
173 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
174 static void ena_tx_cleanup(struct ena_ring *tx_ring);
175 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
177 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
179 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
180 uint16_t nb_desc, unsigned int socket_id,
181 const struct rte_eth_txconf *tx_conf);
182 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_rxconf *rx_conf,
185 struct rte_mempool *mp);
186 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
187 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
188 struct ena_com_rx_buf_info *ena_bufs,
190 uint16_t *next_to_clean,
192 static uint16_t eth_ena_recv_pkts(void *rx_queue,
193 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
194 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
195 struct rte_mbuf *mbuf, uint16_t id);
196 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
197 static void ena_init_rings(struct ena_adapter *adapter,
198 bool disable_meta_caching);
199 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
200 static int ena_start(struct rte_eth_dev *dev);
201 static int ena_stop(struct rte_eth_dev *dev);
202 static int ena_close(struct rte_eth_dev *dev);
203 static int ena_dev_reset(struct rte_eth_dev *dev);
204 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
205 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
206 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
207 static void ena_rx_queue_release(void *queue);
208 static void ena_tx_queue_release(void *queue);
209 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
210 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
211 static int ena_link_update(struct rte_eth_dev *dev,
212 int wait_to_complete);
213 static int ena_create_io_queue(struct ena_ring *ring);
214 static void ena_queue_stop(struct ena_ring *ring);
215 static void ena_queue_stop_all(struct rte_eth_dev *dev,
216 enum ena_ring_type ring_type);
217 static int ena_queue_start(struct ena_ring *ring);
218 static int ena_queue_start_all(struct rte_eth_dev *dev,
219 enum ena_ring_type ring_type);
220 static void ena_stats_restart(struct rte_eth_dev *dev);
221 static int ena_infos_get(struct rte_eth_dev *dev,
222 struct rte_eth_dev_info *dev_info);
223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
224 struct rte_eth_rss_reta_entry64 *reta_conf,
226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
227 struct rte_eth_rss_reta_entry64 *reta_conf,
229 static void ena_interrupt_handler_rte(void *cb_arg);
230 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
231 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
232 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
233 static int ena_xstats_get_names(struct rte_eth_dev *dev,
234 struct rte_eth_xstat_name *xstats_names,
236 static int ena_xstats_get(struct rte_eth_dev *dev,
237 struct rte_eth_xstat *stats,
239 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
243 static int ena_process_bool_devarg(const char *key,
246 static int ena_parse_devargs(struct ena_adapter *adapter,
247 struct rte_devargs *devargs);
248 static int ena_copy_eni_stats(struct ena_adapter *adapter);
250 static const struct eth_dev_ops ena_dev_ops = {
251 .dev_configure = ena_dev_configure,
252 .dev_infos_get = ena_infos_get,
253 .rx_queue_setup = ena_rx_queue_setup,
254 .tx_queue_setup = ena_tx_queue_setup,
255 .dev_start = ena_start,
256 .dev_stop = ena_stop,
257 .link_update = ena_link_update,
258 .stats_get = ena_stats_get,
259 .xstats_get_names = ena_xstats_get_names,
260 .xstats_get = ena_xstats_get,
261 .xstats_get_by_id = ena_xstats_get_by_id,
262 .mtu_set = ena_mtu_set,
263 .rx_queue_release = ena_rx_queue_release,
264 .tx_queue_release = ena_tx_queue_release,
265 .dev_close = ena_close,
266 .dev_reset = ena_dev_reset,
267 .reta_update = ena_rss_reta_update,
268 .reta_query = ena_rss_reta_query,
271 void ena_rss_key_fill(void *key, size_t size)
273 static bool key_generated;
274 static uint8_t default_key[ENA_HASH_KEY_SIZE];
277 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
279 if (!key_generated) {
280 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
281 default_key[i] = rte_rand() & 0xff;
282 key_generated = true;
285 rte_memcpy(key, default_key, size);
288 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
289 struct ena_com_rx_ctx *ena_rx_ctx)
291 uint64_t ol_flags = 0;
292 uint32_t packet_type = 0;
294 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
295 packet_type |= RTE_PTYPE_L4_TCP;
296 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
297 packet_type |= RTE_PTYPE_L4_UDP;
299 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
300 packet_type |= RTE_PTYPE_L3_IPV4;
301 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
302 packet_type |= RTE_PTYPE_L3_IPV6;
304 if (!ena_rx_ctx->l4_csum_checked)
305 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
307 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
308 ol_flags |= PKT_RX_L4_CKSUM_BAD;
310 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
312 if (unlikely(ena_rx_ctx->l3_csum_err))
313 ol_flags |= PKT_RX_IP_CKSUM_BAD;
315 mbuf->ol_flags = ol_flags;
316 mbuf->packet_type = packet_type;
319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
320 struct ena_com_tx_ctx *ena_tx_ctx,
321 uint64_t queue_offloads,
322 bool disable_meta_caching)
324 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
326 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
327 (queue_offloads & QUEUE_OFFLOADS)) {
328 /* check if TSO is required */
329 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
330 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
331 ena_tx_ctx->tso_enable = true;
333 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
336 /* check if L3 checksum is needed */
337 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
338 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
339 ena_tx_ctx->l3_csum_enable = true;
341 if (mbuf->ol_flags & PKT_TX_IPV6) {
342 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
346 /* set don't fragment (DF) flag */
347 if (mbuf->packet_type &
348 (RTE_PTYPE_L4_NONFRAG
349 | RTE_PTYPE_INNER_L4_NONFRAG))
350 ena_tx_ctx->df = true;
353 /* check if L4 checksum is needed */
354 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
355 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
357 ena_tx_ctx->l4_csum_enable = true;
358 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
360 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
361 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
362 ena_tx_ctx->l4_csum_enable = true;
364 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
365 ena_tx_ctx->l4_csum_enable = false;
368 ena_meta->mss = mbuf->tso_segsz;
369 ena_meta->l3_hdr_len = mbuf->l3_len;
370 ena_meta->l3_hdr_offset = mbuf->l2_len;
372 ena_tx_ctx->meta_valid = true;
373 } else if (disable_meta_caching) {
374 memset(ena_meta, 0, sizeof(*ena_meta));
375 ena_tx_ctx->meta_valid = true;
377 ena_tx_ctx->meta_valid = false;
381 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
383 if (likely(req_id < rx_ring->ring_size))
386 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
388 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
389 rx_ring->adapter->trigger_reset = true;
390 ++rx_ring->rx_stats.bad_req_id;
395 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
397 struct ena_tx_buffer *tx_info = NULL;
399 if (likely(req_id < tx_ring->ring_size)) {
400 tx_info = &tx_ring->tx_buffer_info[req_id];
401 if (likely(tx_info->mbuf))
406 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
408 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
410 /* Trigger device reset */
411 ++tx_ring->tx_stats.bad_req_id;
412 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
413 tx_ring->adapter->trigger_reset = true;
417 static void ena_config_host_info(struct ena_com_dev *ena_dev)
419 struct ena_admin_host_info *host_info;
422 /* Allocate only the host info */
423 rc = ena_com_allocate_host_info(ena_dev);
425 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
429 host_info = ena_dev->host_attr.host_info;
431 host_info->os_type = ENA_ADMIN_OS_DPDK;
432 host_info->kernel_ver = RTE_VERSION;
433 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
434 sizeof(host_info->kernel_ver_str));
435 host_info->os_dist = RTE_VERSION;
436 strlcpy((char *)host_info->os_dist_str, rte_version(),
437 sizeof(host_info->os_dist_str));
438 host_info->driver_version =
439 (DRV_MODULE_VER_MAJOR) |
440 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
441 (DRV_MODULE_VER_SUBMINOR <<
442 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
443 host_info->num_cpus = rte_lcore_count();
445 host_info->driver_supported_features =
446 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
448 rc = ena_com_set_host_attributes(ena_dev);
450 if (rc == -ENA_COM_UNSUPPORTED)
451 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
453 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
461 ena_com_delete_host_info(ena_dev);
464 /* This function calculates the number of xstats based on the current config */
465 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
467 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
468 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
469 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
472 static void ena_config_debug_area(struct ena_adapter *adapter)
477 ss_count = ena_xstats_calc_num(adapter->rte_dev);
479 /* allocate 32 bytes for each string and 64bit for the value */
480 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
482 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
484 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
488 rc = ena_com_set_host_attributes(&adapter->ena_dev);
490 if (rc == -ENA_COM_UNSUPPORTED)
491 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
493 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
500 ena_com_delete_debug_area(&adapter->ena_dev);
503 static int ena_close(struct rte_eth_dev *dev)
505 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
506 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
507 struct ena_adapter *adapter = dev->data->dev_private;
510 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
513 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
515 adapter->state = ENA_ADAPTER_STATE_CLOSED;
517 ena_rx_queue_release_all(dev);
518 ena_tx_queue_release_all(dev);
520 rte_free(adapter->drv_stats);
521 adapter->drv_stats = NULL;
523 rte_intr_disable(intr_handle);
524 rte_intr_callback_unregister(intr_handle,
525 ena_interrupt_handler_rte,
529 * MAC is not allocated dynamically. Setting NULL should prevent from
530 * release of the resource in the rte_eth_dev_release_port().
532 dev->data->mac_addrs = NULL;
538 ena_dev_reset(struct rte_eth_dev *dev)
542 ena_destroy_device(dev);
543 rc = eth_ena_dev_init(dev);
545 PMD_INIT_LOG(CRIT, "Cannot initialize device");
550 static int ena_rss_reta_update(struct rte_eth_dev *dev,
551 struct rte_eth_rss_reta_entry64 *reta_conf,
554 struct ena_adapter *adapter = dev->data->dev_private;
555 struct ena_com_dev *ena_dev = &adapter->ena_dev;
561 if ((reta_size == 0) || (reta_conf == NULL))
564 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
566 "indirection table %d is bigger than supported (%d)\n",
567 reta_size, ENA_RX_RSS_TABLE_SIZE);
571 for (i = 0 ; i < reta_size ; i++) {
572 /* each reta_conf is for 64 entries.
573 * to support 128 we use 2 conf of 64
575 conf_idx = i / RTE_RETA_GROUP_SIZE;
576 idx = i % RTE_RETA_GROUP_SIZE;
577 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
579 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
581 rc = ena_com_indirect_table_fill_entry(ena_dev,
584 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
586 "Cannot fill indirect table\n");
592 rte_spinlock_lock(&adapter->admin_lock);
593 rc = ena_com_indirect_table_set(ena_dev);
594 rte_spinlock_unlock(&adapter->admin_lock);
595 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
596 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
600 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n",
601 __func__, reta_size, adapter->rte_dev->data->port_id);
606 /* Query redirection table. */
607 static int ena_rss_reta_query(struct rte_eth_dev *dev,
608 struct rte_eth_rss_reta_entry64 *reta_conf,
611 struct ena_adapter *adapter = dev->data->dev_private;
612 struct ena_com_dev *ena_dev = &adapter->ena_dev;
615 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
619 if (reta_size == 0 || reta_conf == NULL ||
620 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
623 rte_spinlock_lock(&adapter->admin_lock);
624 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
625 rte_spinlock_unlock(&adapter->admin_lock);
626 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
627 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
631 for (i = 0 ; i < reta_size ; i++) {
632 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
633 reta_idx = i % RTE_RETA_GROUP_SIZE;
634 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
635 reta_conf[reta_conf_idx].reta[reta_idx] =
636 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
642 static int ena_rss_init_default(struct ena_adapter *adapter)
644 struct ena_com_dev *ena_dev = &adapter->ena_dev;
645 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
649 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
651 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
655 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
656 val = i % nb_rx_queues;
657 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
658 ENA_IO_RXQ_IDX(val));
659 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
660 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
665 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
666 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
667 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
668 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
672 rc = ena_com_set_default_hash_ctrl(ena_dev);
673 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
674 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
678 rc = ena_com_indirect_table_set(ena_dev);
679 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
680 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
683 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
684 adapter->rte_dev->data->port_id);
689 ena_com_rss_destroy(ena_dev);
695 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
697 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
698 int nb_queues = dev->data->nb_rx_queues;
701 for (i = 0; i < nb_queues; i++)
702 ena_rx_queue_release(queues[i]);
705 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
707 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
708 int nb_queues = dev->data->nb_tx_queues;
711 for (i = 0; i < nb_queues; i++)
712 ena_tx_queue_release(queues[i]);
715 static void ena_rx_queue_release(void *queue)
717 struct ena_ring *ring = (struct ena_ring *)queue;
719 /* Free ring resources */
720 if (ring->rx_buffer_info)
721 rte_free(ring->rx_buffer_info);
722 ring->rx_buffer_info = NULL;
724 if (ring->rx_refill_buffer)
725 rte_free(ring->rx_refill_buffer);
726 ring->rx_refill_buffer = NULL;
728 if (ring->empty_rx_reqs)
729 rte_free(ring->empty_rx_reqs);
730 ring->empty_rx_reqs = NULL;
732 ring->configured = 0;
734 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
735 ring->port_id, ring->id);
738 static void ena_tx_queue_release(void *queue)
740 struct ena_ring *ring = (struct ena_ring *)queue;
742 /* Free ring resources */
743 if (ring->push_buf_intermediate_buf)
744 rte_free(ring->push_buf_intermediate_buf);
746 if (ring->tx_buffer_info)
747 rte_free(ring->tx_buffer_info);
749 if (ring->empty_tx_reqs)
750 rte_free(ring->empty_tx_reqs);
752 ring->empty_tx_reqs = NULL;
753 ring->tx_buffer_info = NULL;
754 ring->push_buf_intermediate_buf = NULL;
756 ring->configured = 0;
758 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
759 ring->port_id, ring->id);
762 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
766 for (i = 0; i < ring->ring_size; ++i) {
767 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
769 rte_mbuf_raw_free(rx_info->mbuf);
770 rx_info->mbuf = NULL;
775 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
779 for (i = 0; i < ring->ring_size; ++i) {
780 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
783 rte_pktmbuf_free(tx_buf->mbuf);
787 static int ena_link_update(struct rte_eth_dev *dev,
788 __rte_unused int wait_to_complete)
790 struct rte_eth_link *link = &dev->data->dev_link;
791 struct ena_adapter *adapter = dev->data->dev_private;
793 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
794 link->link_speed = ETH_SPEED_NUM_NONE;
795 link->link_duplex = ETH_LINK_FULL_DUPLEX;
800 static int ena_queue_start_all(struct rte_eth_dev *dev,
801 enum ena_ring_type ring_type)
803 struct ena_adapter *adapter = dev->data->dev_private;
804 struct ena_ring *queues = NULL;
809 if (ring_type == ENA_RING_TYPE_RX) {
810 queues = adapter->rx_ring;
811 nb_queues = dev->data->nb_rx_queues;
813 queues = adapter->tx_ring;
814 nb_queues = dev->data->nb_tx_queues;
816 for (i = 0; i < nb_queues; i++) {
817 if (queues[i].configured) {
818 if (ring_type == ENA_RING_TYPE_RX) {
820 dev->data->rx_queues[i] == &queues[i],
821 "Inconsistent state of rx queues\n");
824 dev->data->tx_queues[i] == &queues[i],
825 "Inconsistent state of tx queues\n");
828 rc = ena_queue_start(&queues[i]);
832 "failed to start queue %d type(%d)",
843 if (queues[i].configured)
844 ena_queue_stop(&queues[i]);
849 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
851 uint32_t max_frame_len = adapter->max_mtu;
853 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
854 DEV_RX_OFFLOAD_JUMBO_FRAME)
856 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
858 return max_frame_len;
861 static int ena_check_valid_conf(struct ena_adapter *adapter)
863 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
865 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
866 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
867 "max mtu: %d, min mtu: %d",
868 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
869 return ENA_COM_UNSUPPORTED;
876 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
877 bool use_large_llq_hdr)
879 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
880 struct ena_com_dev *ena_dev = ctx->ena_dev;
881 uint32_t max_tx_queue_size;
882 uint32_t max_rx_queue_size;
884 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
885 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
886 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
887 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
888 max_queue_ext->max_rx_sq_depth);
889 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
891 if (ena_dev->tx_mem_queue_type ==
892 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
893 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
896 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
897 max_queue_ext->max_tx_sq_depth);
900 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
901 max_queue_ext->max_per_packet_rx_descs);
902 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
903 max_queue_ext->max_per_packet_tx_descs);
905 struct ena_admin_queue_feature_desc *max_queues =
906 &ctx->get_feat_ctx->max_queues;
907 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
908 max_queues->max_sq_depth);
909 max_tx_queue_size = max_queues->max_cq_depth;
911 if (ena_dev->tx_mem_queue_type ==
912 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
913 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
916 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
917 max_queues->max_sq_depth);
920 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
921 max_queues->max_packet_rx_descs);
922 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
923 max_queues->max_packet_tx_descs);
926 /* Round down to the nearest power of 2 */
927 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
928 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
930 if (use_large_llq_hdr) {
931 if ((llq->entry_size_ctrl_supported &
932 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
933 (ena_dev->tx_mem_queue_type ==
934 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
935 max_tx_queue_size /= 2;
937 "Forcing large headers and decreasing maximum TX queue size to %d\n",
941 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
945 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
946 PMD_INIT_LOG(ERR, "Invalid queue size");
950 ctx->max_tx_queue_size = max_tx_queue_size;
951 ctx->max_rx_queue_size = max_rx_queue_size;
956 static void ena_stats_restart(struct rte_eth_dev *dev)
958 struct ena_adapter *adapter = dev->data->dev_private;
960 rte_atomic64_init(&adapter->drv_stats->ierrors);
961 rte_atomic64_init(&adapter->drv_stats->oerrors);
962 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
963 adapter->drv_stats->rx_drops = 0;
966 static int ena_stats_get(struct rte_eth_dev *dev,
967 struct rte_eth_stats *stats)
969 struct ena_admin_basic_stats ena_stats;
970 struct ena_adapter *adapter = dev->data->dev_private;
971 struct ena_com_dev *ena_dev = &adapter->ena_dev;
976 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
979 memset(&ena_stats, 0, sizeof(ena_stats));
981 rte_spinlock_lock(&adapter->admin_lock);
982 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
983 rte_spinlock_unlock(&adapter->admin_lock);
985 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
989 /* Set of basic statistics from ENA */
990 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
991 ena_stats.rx_pkts_low);
992 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
993 ena_stats.tx_pkts_low);
994 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
995 ena_stats.rx_bytes_low);
996 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
997 ena_stats.tx_bytes_low);
999 /* Driver related stats */
1000 stats->imissed = adapter->drv_stats->rx_drops;
1001 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1002 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1003 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1005 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1006 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1007 for (i = 0; i < max_rings_stats; ++i) {
1008 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1010 stats->q_ibytes[i] = rx_stats->bytes;
1011 stats->q_ipackets[i] = rx_stats->cnt;
1012 stats->q_errors[i] = rx_stats->bad_desc_num +
1013 rx_stats->bad_req_id;
1016 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1017 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1018 for (i = 0; i < max_rings_stats; ++i) {
1019 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1021 stats->q_obytes[i] = tx_stats->bytes;
1022 stats->q_opackets[i] = tx_stats->cnt;
1028 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1030 struct ena_adapter *adapter;
1031 struct ena_com_dev *ena_dev;
1034 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1035 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1036 adapter = dev->data->dev_private;
1038 ena_dev = &adapter->ena_dev;
1039 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1041 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1043 "Invalid MTU setting. new_mtu: %d "
1044 "max mtu: %d min mtu: %d\n",
1045 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1049 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1051 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1053 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1058 static int ena_start(struct rte_eth_dev *dev)
1060 struct ena_adapter *adapter = dev->data->dev_private;
1064 rc = ena_check_valid_conf(adapter);
1068 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1072 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1076 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1077 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1078 rc = ena_rss_init_default(adapter);
1083 ena_stats_restart(dev);
1085 adapter->timestamp_wd = rte_get_timer_cycles();
1086 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1088 ticks = rte_get_timer_hz();
1089 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1090 ena_timer_wd_callback, adapter);
1092 ++adapter->dev_stats.dev_start;
1093 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1098 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1100 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1104 static int ena_stop(struct rte_eth_dev *dev)
1106 struct ena_adapter *adapter = dev->data->dev_private;
1107 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1110 rte_timer_stop_sync(&adapter->timer_wd);
1111 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1112 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1114 if (adapter->trigger_reset) {
1115 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1117 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1120 ++adapter->dev_stats.dev_stop;
1121 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1122 dev->data->dev_started = 0;
1127 static int ena_create_io_queue(struct ena_ring *ring)
1129 struct ena_adapter *adapter;
1130 struct ena_com_dev *ena_dev;
1131 struct ena_com_create_io_ctx ctx =
1132 /* policy set to _HOST just to satisfy icc compiler */
1133 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1139 adapter = ring->adapter;
1140 ena_dev = &adapter->ena_dev;
1142 if (ring->type == ENA_RING_TYPE_TX) {
1143 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1144 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1145 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1146 for (i = 0; i < ring->ring_size; i++)
1147 ring->empty_tx_reqs[i] = i;
1149 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1150 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1151 for (i = 0; i < ring->ring_size; i++)
1152 ring->empty_rx_reqs[i] = i;
1154 ctx.queue_size = ring->ring_size;
1156 ctx.msix_vector = -1; /* interrupts not used */
1157 ctx.numa_node = ring->numa_socket_id;
1159 rc = ena_com_create_io_queue(ena_dev, &ctx);
1162 "failed to create io queue #%d (qid:%d) rc: %d\n",
1163 ring->id, ena_qid, rc);
1167 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1168 &ring->ena_com_io_sq,
1169 &ring->ena_com_io_cq);
1172 "Failed to get io queue handlers. queue num %d rc: %d\n",
1174 ena_com_destroy_io_queue(ena_dev, ena_qid);
1178 if (ring->type == ENA_RING_TYPE_TX)
1179 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1184 static void ena_queue_stop(struct ena_ring *ring)
1186 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1188 if (ring->type == ENA_RING_TYPE_RX) {
1189 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1190 ena_rx_queue_release_bufs(ring);
1192 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1193 ena_tx_queue_release_bufs(ring);
1197 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1198 enum ena_ring_type ring_type)
1200 struct ena_adapter *adapter = dev->data->dev_private;
1201 struct ena_ring *queues = NULL;
1202 uint16_t nb_queues, i;
1204 if (ring_type == ENA_RING_TYPE_RX) {
1205 queues = adapter->rx_ring;
1206 nb_queues = dev->data->nb_rx_queues;
1208 queues = adapter->tx_ring;
1209 nb_queues = dev->data->nb_tx_queues;
1212 for (i = 0; i < nb_queues; ++i)
1213 if (queues[i].configured)
1214 ena_queue_stop(&queues[i]);
1217 static int ena_queue_start(struct ena_ring *ring)
1221 ena_assert_msg(ring->configured == 1,
1222 "Trying to start unconfigured queue\n");
1224 rc = ena_create_io_queue(ring);
1226 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1230 ring->next_to_clean = 0;
1231 ring->next_to_use = 0;
1233 if (ring->type == ENA_RING_TYPE_TX) {
1234 ring->tx_stats.available_desc =
1235 ena_com_free_q_entries(ring->ena_com_io_sq);
1239 bufs_num = ring->ring_size - 1;
1240 rc = ena_populate_rx_queue(ring, bufs_num);
1241 if (rc != bufs_num) {
1242 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1243 ENA_IO_RXQ_IDX(ring->id));
1244 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1245 return ENA_COM_FAULT;
1251 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1254 unsigned int socket_id,
1255 const struct rte_eth_txconf *tx_conf)
1257 struct ena_ring *txq = NULL;
1258 struct ena_adapter *adapter = dev->data->dev_private;
1261 txq = &adapter->tx_ring[queue_idx];
1263 if (txq->configured) {
1265 "API violation. Queue %d is already configured\n",
1267 return ENA_COM_FAULT;
1270 if (!rte_is_power_of_2(nb_desc)) {
1272 "Unsupported size of TX queue: %d is not a power of 2.\n",
1277 if (nb_desc > adapter->max_tx_ring_size) {
1279 "Unsupported size of TX queue (max size: %d)\n",
1280 adapter->max_tx_ring_size);
1284 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1285 nb_desc = adapter->max_tx_ring_size;
1287 txq->port_id = dev->data->port_id;
1288 txq->next_to_clean = 0;
1289 txq->next_to_use = 0;
1290 txq->ring_size = nb_desc;
1291 txq->size_mask = nb_desc - 1;
1292 txq->numa_socket_id = socket_id;
1294 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1295 sizeof(struct ena_tx_buffer) *
1297 RTE_CACHE_LINE_SIZE);
1298 if (!txq->tx_buffer_info) {
1299 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1303 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1304 sizeof(u16) * txq->ring_size,
1305 RTE_CACHE_LINE_SIZE);
1306 if (!txq->empty_tx_reqs) {
1307 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1308 rte_free(txq->tx_buffer_info);
1312 txq->push_buf_intermediate_buf =
1313 rte_zmalloc("txq->push_buf_intermediate_buf",
1314 txq->tx_max_header_size,
1315 RTE_CACHE_LINE_SIZE);
1316 if (!txq->push_buf_intermediate_buf) {
1317 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1318 rte_free(txq->tx_buffer_info);
1319 rte_free(txq->empty_tx_reqs);
1323 for (i = 0; i < txq->ring_size; i++)
1324 txq->empty_tx_reqs[i] = i;
1326 if (tx_conf != NULL) {
1328 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1330 /* Store pointer to this queue in upper layer */
1331 txq->configured = 1;
1332 dev->data->tx_queues[queue_idx] = txq;
1337 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1340 unsigned int socket_id,
1341 __rte_unused const struct rte_eth_rxconf *rx_conf,
1342 struct rte_mempool *mp)
1344 struct ena_adapter *adapter = dev->data->dev_private;
1345 struct ena_ring *rxq = NULL;
1349 rxq = &adapter->rx_ring[queue_idx];
1350 if (rxq->configured) {
1352 "API violation. Queue %d is already configured\n",
1354 return ENA_COM_FAULT;
1357 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1358 nb_desc = adapter->max_rx_ring_size;
1360 if (!rte_is_power_of_2(nb_desc)) {
1362 "Unsupported size of RX queue: %d is not a power of 2.\n",
1367 if (nb_desc > adapter->max_rx_ring_size) {
1369 "Unsupported size of RX queue (max size: %d)\n",
1370 adapter->max_rx_ring_size);
1374 /* ENA isn't supporting buffers smaller than 1400 bytes */
1375 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1376 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1378 "Unsupported size of RX buffer: %zu (min size: %d)\n",
1379 buffer_size, ENA_RX_BUF_MIN_SIZE);
1383 rxq->port_id = dev->data->port_id;
1384 rxq->next_to_clean = 0;
1385 rxq->next_to_use = 0;
1386 rxq->ring_size = nb_desc;
1387 rxq->size_mask = nb_desc - 1;
1388 rxq->numa_socket_id = socket_id;
1391 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1392 sizeof(struct ena_rx_buffer) * nb_desc,
1393 RTE_CACHE_LINE_SIZE);
1394 if (!rxq->rx_buffer_info) {
1395 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1399 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1400 sizeof(struct rte_mbuf *) * nb_desc,
1401 RTE_CACHE_LINE_SIZE);
1403 if (!rxq->rx_refill_buffer) {
1404 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1405 rte_free(rxq->rx_buffer_info);
1406 rxq->rx_buffer_info = NULL;
1410 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1411 sizeof(uint16_t) * nb_desc,
1412 RTE_CACHE_LINE_SIZE);
1413 if (!rxq->empty_rx_reqs) {
1414 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1415 rte_free(rxq->rx_buffer_info);
1416 rxq->rx_buffer_info = NULL;
1417 rte_free(rxq->rx_refill_buffer);
1418 rxq->rx_refill_buffer = NULL;
1422 for (i = 0; i < nb_desc; i++)
1423 rxq->empty_rx_reqs[i] = i;
1425 /* Store pointer to this queue in upper layer */
1426 rxq->configured = 1;
1427 dev->data->rx_queues[queue_idx] = rxq;
1432 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1433 struct rte_mbuf *mbuf, uint16_t id)
1435 struct ena_com_buf ebuf;
1438 /* prepare physical address for DMA transaction */
1439 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1440 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1442 /* pass resource to device */
1443 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1444 if (unlikely(rc != 0))
1445 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1450 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1454 uint16_t next_to_use = rxq->next_to_use;
1455 uint16_t in_use, req_id;
1456 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1458 if (unlikely(!count))
1461 in_use = rxq->ring_size - 1 -
1462 ena_com_free_q_entries(rxq->ena_com_io_sq);
1463 ena_assert_msg(((in_use + count) < rxq->ring_size),
1464 "bad ring state\n");
1466 /* get resources for incoming packets */
1467 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1468 if (unlikely(rc < 0)) {
1469 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1470 ++rxq->rx_stats.mbuf_alloc_fail;
1471 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1475 for (i = 0; i < count; i++) {
1476 struct rte_mbuf *mbuf = mbufs[i];
1477 struct ena_rx_buffer *rx_info;
1479 if (likely((i + 4) < count))
1480 rte_prefetch0(mbufs[i + 4]);
1482 req_id = rxq->empty_rx_reqs[next_to_use];
1483 rc = validate_rx_req_id(rxq, req_id);
1487 rx_info = &rxq->rx_buffer_info[req_id];
1489 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1490 if (unlikely(rc != 0))
1493 rx_info->mbuf = mbuf;
1494 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1497 if (unlikely(i < count)) {
1498 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1499 "buffers (from %d)\n", rxq->id, i, count);
1500 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1502 ++rxq->rx_stats.refill_partial;
1505 /* When we submitted free recources to device... */
1506 if (likely(i > 0)) {
1507 /* ...let HW know that it can fill buffers with data. */
1508 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1510 rxq->next_to_use = next_to_use;
1516 static int ena_device_init(struct ena_com_dev *ena_dev,
1517 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1520 uint32_t aenq_groups;
1522 bool readless_supported;
1524 /* Initialize mmio registers */
1525 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1527 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1531 /* The PCIe configuration space revision id indicate if mmio reg
1534 readless_supported =
1535 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1536 & ENA_MMIO_DISABLE_REG_READ);
1537 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1540 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1542 PMD_DRV_LOG(ERR, "cannot reset device\n");
1543 goto err_mmio_read_less;
1546 /* check FW version */
1547 rc = ena_com_validate_version(ena_dev);
1549 PMD_DRV_LOG(ERR, "device version is too low\n");
1550 goto err_mmio_read_less;
1553 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1555 /* ENA device administration layer init */
1556 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1559 "cannot initialize ena admin queue with device\n");
1560 goto err_mmio_read_less;
1563 /* To enable the msix interrupts the driver needs to know the number
1564 * of queues. So the driver uses polling mode to retrieve this
1567 ena_com_set_admin_polling_mode(ena_dev, true);
1569 ena_config_host_info(ena_dev);
1571 /* Get Device Attributes and features */
1572 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1575 "cannot get attribute for ena device rc= %d\n", rc);
1576 goto err_admin_init;
1579 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1580 BIT(ENA_ADMIN_NOTIFICATION) |
1581 BIT(ENA_ADMIN_KEEP_ALIVE) |
1582 BIT(ENA_ADMIN_FATAL_ERROR) |
1583 BIT(ENA_ADMIN_WARNING);
1585 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1586 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1588 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1589 goto err_admin_init;
1592 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1597 ena_com_admin_destroy(ena_dev);
1600 ena_com_mmio_reg_read_request_destroy(ena_dev);
1605 static void ena_interrupt_handler_rte(void *cb_arg)
1607 struct ena_adapter *adapter = cb_arg;
1608 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1610 ena_com_admin_q_comp_intr_handler(ena_dev);
1611 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1612 ena_com_aenq_intr_handler(ena_dev, adapter);
1615 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1617 if (!adapter->wd_state)
1620 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1623 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1624 adapter->keep_alive_timeout)) {
1625 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1626 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1627 adapter->trigger_reset = true;
1628 ++adapter->dev_stats.wd_expired;
1632 /* Check if admin queue is enabled */
1633 static void check_for_admin_com_state(struct ena_adapter *adapter)
1635 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1636 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1637 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1638 adapter->trigger_reset = true;
1642 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1645 struct ena_adapter *adapter = arg;
1646 struct rte_eth_dev *dev = adapter->rte_dev;
1648 check_for_missing_keep_alive(adapter);
1649 check_for_admin_com_state(adapter);
1651 if (unlikely(adapter->trigger_reset)) {
1652 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1653 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1659 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1660 struct ena_admin_feature_llq_desc *llq,
1661 bool use_large_llq_hdr)
1663 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1664 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1665 llq_config->llq_num_decs_before_header =
1666 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1668 if (use_large_llq_hdr &&
1669 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1670 llq_config->llq_ring_entry_size =
1671 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1672 llq_config->llq_ring_entry_size_value = 256;
1674 llq_config->llq_ring_entry_size =
1675 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1676 llq_config->llq_ring_entry_size_value = 128;
1681 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1682 struct ena_com_dev *ena_dev,
1683 struct ena_admin_feature_llq_desc *llq,
1684 struct ena_llq_configurations *llq_default_configurations)
1687 u32 llq_feature_mask;
1689 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1690 if (!(ena_dev->supported_features & llq_feature_mask)) {
1692 "LLQ is not supported. Fallback to host mode policy.\n");
1693 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1697 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1699 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1700 "Fallback to host mode policy.");
1701 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1705 /* Nothing to config, exit */
1706 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1709 if (!adapter->dev_mem_base) {
1710 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1711 "Fallback to host mode policy.\n.");
1712 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1716 ena_dev->mem_bar = adapter->dev_mem_base;
1721 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1722 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1724 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1726 /* Regular queues capabilities */
1727 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1728 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1729 &get_feat_ctx->max_queue_ext.max_queue_ext;
1730 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1731 max_queue_ext->max_rx_cq_num);
1732 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1733 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1735 struct ena_admin_queue_feature_desc *max_queues =
1736 &get_feat_ctx->max_queues;
1737 io_tx_sq_num = max_queues->max_sq_num;
1738 io_tx_cq_num = max_queues->max_cq_num;
1739 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1742 /* In case of LLQ use the llq number in the get feature cmd */
1743 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1744 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1746 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1747 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1748 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1750 if (unlikely(max_num_io_queues == 0)) {
1751 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1755 return max_num_io_queues;
1758 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1760 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1761 struct rte_pci_device *pci_dev;
1762 struct rte_intr_handle *intr_handle;
1763 struct ena_adapter *adapter = eth_dev->data->dev_private;
1764 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1765 struct ena_com_dev_get_features_ctx get_feat_ctx;
1766 struct ena_llq_configurations llq_config;
1767 const char *queue_type_str;
1768 uint32_t max_num_io_queues;
1770 static int adapters_found;
1771 bool disable_meta_caching;
1772 bool wd_state = false;
1774 eth_dev->dev_ops = &ena_dev_ops;
1775 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1776 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1777 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1779 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1782 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1784 memset(adapter, 0, sizeof(struct ena_adapter));
1785 ena_dev = &adapter->ena_dev;
1787 adapter->rte_eth_dev_data = eth_dev->data;
1788 adapter->rte_dev = eth_dev;
1790 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1791 adapter->pdev = pci_dev;
1793 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1794 pci_dev->addr.domain,
1796 pci_dev->addr.devid,
1797 pci_dev->addr.function);
1799 intr_handle = &pci_dev->intr_handle;
1801 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1802 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1804 if (!adapter->regs) {
1805 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1810 ena_dev->reg_bar = adapter->regs;
1811 ena_dev->dmadev = adapter->pdev;
1813 adapter->id_number = adapters_found;
1815 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1816 adapter->id_number);
1818 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1820 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1824 /* device specific initialization routine */
1825 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1827 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1830 adapter->wd_state = wd_state;
1832 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1833 adapter->use_large_llq_hdr);
1834 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1835 &get_feat_ctx.llq, &llq_config);
1837 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1841 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1842 queue_type_str = "Regular";
1844 queue_type_str = "Low latency";
1845 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1847 calc_queue_ctx.ena_dev = ena_dev;
1848 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1850 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1851 rc = ena_calc_io_queue_size(&calc_queue_ctx,
1852 adapter->use_large_llq_hdr);
1853 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1855 goto err_device_destroy;
1858 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1859 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1860 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1861 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1862 adapter->max_num_io_queues = max_num_io_queues;
1864 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1865 disable_meta_caching =
1866 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1867 BIT(ENA_ADMIN_DISABLE_META_CACHING));
1869 disable_meta_caching = false;
1872 /* prepare ring structures */
1873 ena_init_rings(adapter, disable_meta_caching);
1875 ena_config_debug_area(adapter);
1877 /* Set max MTU for this device */
1878 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1880 /* set device support for offloads */
1881 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1882 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1883 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1884 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1885 adapter->offloads.rx_csum_supported =
1886 (get_feat_ctx.offload.rx_supported &
1887 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1889 /* Copy MAC address and point DPDK to it */
1890 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1891 rte_ether_addr_copy((struct rte_ether_addr *)
1892 get_feat_ctx.dev_attr.mac_addr,
1893 (struct rte_ether_addr *)adapter->mac_addr);
1895 adapter->drv_stats = rte_zmalloc("adapter stats",
1896 sizeof(*adapter->drv_stats),
1897 RTE_CACHE_LINE_SIZE);
1898 if (!adapter->drv_stats) {
1899 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1901 goto err_delete_debug_area;
1904 rte_spinlock_init(&adapter->admin_lock);
1906 rte_intr_callback_register(intr_handle,
1907 ena_interrupt_handler_rte,
1909 rte_intr_enable(intr_handle);
1910 ena_com_set_admin_polling_mode(ena_dev, false);
1911 ena_com_admin_aenq_enable(ena_dev);
1913 if (adapters_found == 0)
1914 rte_timer_subsystem_init();
1915 rte_timer_init(&adapter->timer_wd);
1918 adapter->state = ENA_ADAPTER_STATE_INIT;
1922 err_delete_debug_area:
1923 ena_com_delete_debug_area(ena_dev);
1926 ena_com_delete_host_info(ena_dev);
1927 ena_com_admin_destroy(ena_dev);
1933 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1935 struct ena_adapter *adapter = eth_dev->data->dev_private;
1936 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1938 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1941 ena_com_set_admin_running_state(ena_dev, false);
1943 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1946 ena_com_delete_debug_area(ena_dev);
1947 ena_com_delete_host_info(ena_dev);
1949 ena_com_abort_admin_commands(ena_dev);
1950 ena_com_wait_for_abort_completion(ena_dev);
1951 ena_com_admin_destroy(ena_dev);
1952 ena_com_mmio_reg_read_request_destroy(ena_dev);
1954 adapter->state = ENA_ADAPTER_STATE_FREE;
1957 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1959 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1962 ena_destroy_device(eth_dev);
1967 static int ena_dev_configure(struct rte_eth_dev *dev)
1969 struct ena_adapter *adapter = dev->data->dev_private;
1971 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1973 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1974 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1978 static void ena_init_rings(struct ena_adapter *adapter,
1979 bool disable_meta_caching)
1983 for (i = 0; i < adapter->max_num_io_queues; i++) {
1984 struct ena_ring *ring = &adapter->tx_ring[i];
1986 ring->configured = 0;
1987 ring->type = ENA_RING_TYPE_TX;
1988 ring->adapter = adapter;
1990 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1991 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1992 ring->sgl_size = adapter->max_tx_sgl_size;
1993 ring->disable_meta_caching = disable_meta_caching;
1996 for (i = 0; i < adapter->max_num_io_queues; i++) {
1997 struct ena_ring *ring = &adapter->rx_ring[i];
1999 ring->configured = 0;
2000 ring->type = ENA_RING_TYPE_RX;
2001 ring->adapter = adapter;
2003 ring->sgl_size = adapter->max_rx_sgl_size;
2007 static int ena_infos_get(struct rte_eth_dev *dev,
2008 struct rte_eth_dev_info *dev_info)
2010 struct ena_adapter *adapter;
2011 struct ena_com_dev *ena_dev;
2012 uint64_t rx_feat = 0, tx_feat = 0;
2014 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2015 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2016 adapter = dev->data->dev_private;
2018 ena_dev = &adapter->ena_dev;
2019 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2021 dev_info->speed_capa =
2023 ETH_LINK_SPEED_2_5G |
2025 ETH_LINK_SPEED_10G |
2026 ETH_LINK_SPEED_25G |
2027 ETH_LINK_SPEED_40G |
2028 ETH_LINK_SPEED_50G |
2029 ETH_LINK_SPEED_100G;
2031 /* Set Tx & Rx features available for device */
2032 if (adapter->offloads.tso4_supported)
2033 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2035 if (adapter->offloads.tx_csum_supported)
2036 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2037 DEV_TX_OFFLOAD_UDP_CKSUM |
2038 DEV_TX_OFFLOAD_TCP_CKSUM;
2040 if (adapter->offloads.rx_csum_supported)
2041 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2042 DEV_RX_OFFLOAD_UDP_CKSUM |
2043 DEV_RX_OFFLOAD_TCP_CKSUM;
2045 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2047 /* Inform framework about available features */
2048 dev_info->rx_offload_capa = rx_feat;
2049 dev_info->rx_queue_offload_capa = rx_feat;
2050 dev_info->tx_offload_capa = tx_feat;
2051 dev_info->tx_queue_offload_capa = tx_feat;
2053 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2056 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2057 dev_info->max_rx_pktlen = adapter->max_mtu;
2058 dev_info->max_mac_addrs = 1;
2060 dev_info->max_rx_queues = adapter->max_num_io_queues;
2061 dev_info->max_tx_queues = adapter->max_num_io_queues;
2062 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2064 adapter->tx_supported_offloads = tx_feat;
2065 adapter->rx_supported_offloads = rx_feat;
2067 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2068 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2069 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2070 adapter->max_rx_sgl_size);
2071 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2072 adapter->max_rx_sgl_size);
2074 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2075 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2076 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2077 adapter->max_tx_sgl_size);
2078 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2079 adapter->max_tx_sgl_size);
2084 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2086 mbuf->data_len = len;
2087 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2092 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2093 struct ena_com_rx_buf_info *ena_bufs,
2095 uint16_t *next_to_clean,
2098 struct rte_mbuf *mbuf;
2099 struct rte_mbuf *mbuf_head;
2100 struct ena_rx_buffer *rx_info;
2102 uint16_t ntc, len, req_id, buf = 0;
2104 if (unlikely(descs == 0))
2107 ntc = *next_to_clean;
2109 len = ena_bufs[buf].len;
2110 req_id = ena_bufs[buf].req_id;
2111 if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2114 rx_info = &rx_ring->rx_buffer_info[req_id];
2116 mbuf = rx_info->mbuf;
2117 RTE_ASSERT(mbuf != NULL);
2119 ena_init_rx_mbuf(mbuf, len);
2121 /* Fill the mbuf head with the data specific for 1st segment. */
2123 mbuf_head->nb_segs = descs;
2124 mbuf_head->port = rx_ring->port_id;
2125 mbuf_head->pkt_len = len;
2126 mbuf_head->data_off += offset;
2128 rx_info->mbuf = NULL;
2129 rx_ring->empty_rx_reqs[ntc] = req_id;
2130 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2134 len = ena_bufs[buf].len;
2135 req_id = ena_bufs[buf].req_id;
2136 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2137 rte_mbuf_raw_free(mbuf_head);
2141 rx_info = &rx_ring->rx_buffer_info[req_id];
2142 RTE_ASSERT(rx_info->mbuf != NULL);
2144 if (unlikely(len == 0)) {
2146 * Some devices can pass descriptor with the length 0.
2147 * To avoid confusion, the PMD is simply putting the
2148 * descriptor back, as it was never used. We'll avoid
2149 * mbuf allocation that way.
2151 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2152 rx_info->mbuf, req_id);
2153 if (unlikely(rc != 0)) {
2154 /* Free the mbuf in case of an error. */
2155 rte_mbuf_raw_free(rx_info->mbuf);
2158 * If there was no error, just exit the loop as
2159 * 0 length descriptor is always the last one.
2164 /* Create an mbuf chain. */
2165 mbuf->next = rx_info->mbuf;
2168 ena_init_rx_mbuf(mbuf, len);
2169 mbuf_head->pkt_len += len;
2173 * Mark the descriptor as depleted and perform necessary
2175 * This code will execute in two cases:
2176 * 1. Descriptor len was greater than 0 - normal situation.
2177 * 2. Descriptor len was 0 and we failed to add the descriptor
2178 * to the device. In that situation, we should try to add
2179 * the mbuf again in the populate routine and mark the
2180 * descriptor as used up by the device.
2182 rx_info->mbuf = NULL;
2183 rx_ring->empty_rx_reqs[ntc] = req_id;
2184 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2187 *next_to_clean = ntc;
2192 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2195 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2196 unsigned int free_queue_entries;
2197 unsigned int refill_threshold;
2198 uint16_t next_to_clean = rx_ring->next_to_clean;
2199 uint16_t descs_in_use;
2200 struct rte_mbuf *mbuf;
2202 struct ena_com_rx_ctx ena_rx_ctx;
2205 /* Check adapter state */
2206 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2208 "Trying to receive pkts while device is NOT running\n");
2212 descs_in_use = rx_ring->ring_size -
2213 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2214 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2216 for (completed = 0; completed < nb_pkts; completed++) {
2217 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2218 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2219 ena_rx_ctx.descs = 0;
2220 ena_rx_ctx.pkt_offset = 0;
2221 /* receive packet context */
2222 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2223 rx_ring->ena_com_io_sq,
2226 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2227 rx_ring->adapter->reset_reason =
2228 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2229 rx_ring->adapter->trigger_reset = true;
2230 ++rx_ring->rx_stats.bad_desc_num;
2234 mbuf = ena_rx_mbuf(rx_ring,
2235 ena_rx_ctx.ena_bufs,
2238 ena_rx_ctx.pkt_offset);
2239 if (unlikely(mbuf == NULL)) {
2240 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2241 rx_ring->empty_rx_reqs[next_to_clean] =
2242 rx_ring->ena_bufs[i].req_id;
2243 next_to_clean = ENA_IDX_NEXT_MASKED(
2244 next_to_clean, rx_ring->size_mask);
2249 /* fill mbuf attributes if any */
2250 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2252 if (unlikely(mbuf->ol_flags &
2253 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2254 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2255 ++rx_ring->rx_stats.bad_csum;
2258 mbuf->hash.rss = ena_rx_ctx.hash;
2260 rx_pkts[completed] = mbuf;
2261 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2264 rx_ring->rx_stats.cnt += completed;
2265 rx_ring->next_to_clean = next_to_clean;
2267 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2269 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2270 (unsigned int)ENA_REFILL_THRESH_PACKET);
2272 /* Burst refill to save doorbells, memory barriers, const interval */
2273 if (free_queue_entries > refill_threshold) {
2274 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2275 ena_populate_rx_queue(rx_ring, free_queue_entries);
2282 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2288 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2289 struct rte_ipv4_hdr *ip_hdr;
2291 uint16_t frag_field;
2293 for (i = 0; i != nb_pkts; i++) {
2295 ol_flags = m->ol_flags;
2297 if (!(ol_flags & PKT_TX_IPV4))
2300 /* If there was not L2 header length specified, assume it is
2301 * length of the ethernet header.
2303 if (unlikely(m->l2_len == 0))
2304 m->l2_len = sizeof(struct rte_ether_hdr);
2306 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2308 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2310 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2311 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2313 /* If IPv4 header has DF flag enabled and TSO support is
2314 * disabled, partial chcecksum should not be calculated.
2316 if (!tx_ring->adapter->offloads.tso4_supported)
2320 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2321 (ol_flags & PKT_TX_L4_MASK) ==
2322 PKT_TX_SCTP_CKSUM) {
2323 rte_errno = ENOTSUP;
2327 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2328 ret = rte_validate_tx_offload(m);
2335 /* In case we are supposed to TSO and have DF not set (DF=0)
2336 * hardware must be provided with partial checksum, otherwise
2337 * it will take care of necessary calculations.
2340 ret = rte_net_intel_cksum_flags_prepare(m,
2341 ol_flags & ~PKT_TX_TCP_SEG);
2351 static void ena_update_hints(struct ena_adapter *adapter,
2352 struct ena_admin_ena_hw_hints *hints)
2354 if (hints->admin_completion_tx_timeout)
2355 adapter->ena_dev.admin_queue.completion_timeout =
2356 hints->admin_completion_tx_timeout * 1000;
2358 if (hints->mmio_read_timeout)
2359 /* convert to usec */
2360 adapter->ena_dev.mmio_read.reg_read_to =
2361 hints->mmio_read_timeout * 1000;
2363 if (hints->driver_watchdog_timeout) {
2364 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2365 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2367 // Convert msecs to ticks
2368 adapter->keep_alive_timeout =
2369 (hints->driver_watchdog_timeout *
2370 rte_get_timer_hz()) / 1000;
2374 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2375 struct rte_mbuf *mbuf)
2377 struct ena_com_dev *ena_dev;
2378 int num_segments, header_len, rc;
2380 ena_dev = &tx_ring->adapter->ena_dev;
2381 num_segments = mbuf->nb_segs;
2382 header_len = mbuf->data_len;
2384 if (likely(num_segments < tx_ring->sgl_size))
2387 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2388 (num_segments == tx_ring->sgl_size) &&
2389 (header_len < tx_ring->tx_max_header_size))
2392 ++tx_ring->tx_stats.linearize;
2393 rc = rte_pktmbuf_linearize(mbuf);
2395 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2396 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2397 ++tx_ring->tx_stats.linearize_failed;
2404 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2405 struct ena_tx_buffer *tx_info,
2406 struct rte_mbuf *mbuf,
2408 uint16_t *header_len)
2410 struct ena_com_buf *ena_buf;
2411 uint16_t delta, seg_len, push_len;
2414 seg_len = mbuf->data_len;
2416 tx_info->mbuf = mbuf;
2417 ena_buf = tx_info->bufs;
2419 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2421 * Tx header might be (and will be in most cases) smaller than
2422 * tx_max_header_size. But it's not an issue to send more data
2423 * to the device, than actually needed if the mbuf size is
2424 * greater than tx_max_header_size.
2426 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2427 *header_len = push_len;
2429 if (likely(push_len <= seg_len)) {
2430 /* If the push header is in the single segment, then
2431 * just point it to the 1st mbuf data.
2433 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2435 /* If the push header lays in the several segments, copy
2436 * it to the intermediate buffer.
2438 rte_pktmbuf_read(mbuf, 0, push_len,
2439 tx_ring->push_buf_intermediate_buf);
2440 *push_header = tx_ring->push_buf_intermediate_buf;
2441 delta = push_len - seg_len;
2444 *push_header = NULL;
2449 /* Process first segment taking into consideration pushed header */
2450 if (seg_len > push_len) {
2451 ena_buf->paddr = mbuf->buf_iova +
2454 ena_buf->len = seg_len - push_len;
2456 tx_info->num_of_bufs++;
2459 while ((mbuf = mbuf->next) != NULL) {
2460 seg_len = mbuf->data_len;
2462 /* Skip mbufs if whole data is pushed as a header */
2463 if (unlikely(delta > seg_len)) {
2468 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2469 ena_buf->len = seg_len - delta;
2471 tx_info->num_of_bufs++;
2477 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2479 struct ena_tx_buffer *tx_info;
2480 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2481 uint16_t next_to_use;
2482 uint16_t header_len;
2488 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2492 next_to_use = tx_ring->next_to_use;
2494 req_id = tx_ring->empty_tx_reqs[next_to_use];
2495 tx_info = &tx_ring->tx_buffer_info[req_id];
2496 tx_info->num_of_bufs = 0;
2498 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2500 ena_tx_ctx.ena_bufs = tx_info->bufs;
2501 ena_tx_ctx.push_header = push_header;
2502 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2503 ena_tx_ctx.req_id = req_id;
2504 ena_tx_ctx.header_len = header_len;
2506 /* Set Tx offloads flags, if applicable */
2507 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2508 tx_ring->disable_meta_caching);
2510 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2513 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2515 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2518 /* prepare the packet's descriptors to dma engine */
2519 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2522 ++tx_ring->tx_stats.prepare_ctx_err;
2526 tx_info->tx_descs = nb_hw_desc;
2528 tx_ring->tx_stats.cnt++;
2529 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2531 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2532 tx_ring->size_mask);
2537 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2539 unsigned int cleanup_budget;
2540 unsigned int total_tx_descs = 0;
2541 uint16_t next_to_clean = tx_ring->next_to_clean;
2543 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2544 (unsigned int)ENA_REFILL_THRESH_PACKET);
2546 while (likely(total_tx_descs < cleanup_budget)) {
2547 struct rte_mbuf *mbuf;
2548 struct ena_tx_buffer *tx_info;
2551 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2554 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2557 /* Get Tx info & store how many descs were processed */
2558 tx_info = &tx_ring->tx_buffer_info[req_id];
2560 mbuf = tx_info->mbuf;
2561 rte_pktmbuf_free(mbuf);
2563 tx_info->mbuf = NULL;
2564 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2566 total_tx_descs += tx_info->tx_descs;
2568 /* Put back descriptor to the ring for reuse */
2569 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2570 tx_ring->size_mask);
2573 if (likely(total_tx_descs > 0)) {
2574 /* acknowledge completion of sent packets */
2575 tx_ring->next_to_clean = next_to_clean;
2576 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2577 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2581 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2584 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2585 uint16_t sent_idx = 0;
2587 /* Check adapter state */
2588 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2590 "Trying to xmit pkts while device is NOT running\n");
2594 nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2597 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2598 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2601 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2602 tx_ring->size_mask)]);
2605 tx_ring->tx_stats.available_desc =
2606 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2608 /* If there are ready packets to be xmitted... */
2610 /* ...let HW do its best :-) */
2611 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2612 tx_ring->tx_stats.doorbells++;
2615 ena_tx_cleanup(tx_ring);
2617 tx_ring->tx_stats.available_desc =
2618 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2619 tx_ring->tx_stats.tx_poll++;
2624 int ena_copy_eni_stats(struct ena_adapter *adapter)
2626 struct ena_admin_eni_stats admin_eni_stats;
2629 rte_spinlock_lock(&adapter->admin_lock);
2630 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2631 rte_spinlock_unlock(&adapter->admin_lock);
2633 if (rc == ENA_COM_UNSUPPORTED) {
2635 "Retrieving ENI metrics is not supported.\n");
2637 PMD_DRV_LOG(WARNING,
2638 "Failed to get ENI metrics: %d\n", rc);
2643 rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2644 sizeof(struct ena_stats_eni));
2650 * DPDK callback to retrieve names of extended device statistics
2653 * Pointer to Ethernet device structure.
2654 * @param[out] xstats_names
2655 * Buffer to insert names into.
2660 * Number of xstats names.
2662 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2663 struct rte_eth_xstat_name *xstats_names,
2666 unsigned int xstats_count = ena_xstats_calc_num(dev);
2667 unsigned int stat, i, count = 0;
2669 if (n < xstats_count || !xstats_names)
2670 return xstats_count;
2672 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2673 strcpy(xstats_names[count].name,
2674 ena_stats_global_strings[stat].name);
2676 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2677 strcpy(xstats_names[count].name,
2678 ena_stats_eni_strings[stat].name);
2680 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2681 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2682 snprintf(xstats_names[count].name,
2683 sizeof(xstats_names[count].name),
2685 ena_stats_rx_strings[stat].name);
2687 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2688 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2689 snprintf(xstats_names[count].name,
2690 sizeof(xstats_names[count].name),
2692 ena_stats_tx_strings[stat].name);
2694 return xstats_count;
2698 * DPDK callback to get extended device statistics.
2701 * Pointer to Ethernet device structure.
2703 * Stats table output buffer.
2705 * The size of the stats table.
2708 * Number of xstats on success, negative on failure.
2710 static int ena_xstats_get(struct rte_eth_dev *dev,
2711 struct rte_eth_xstat *xstats,
2714 struct ena_adapter *adapter = dev->data->dev_private;
2715 unsigned int xstats_count = ena_xstats_calc_num(dev);
2716 unsigned int stat, i, count = 0;
2720 if (n < xstats_count)
2721 return xstats_count;
2726 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2727 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2728 stats_begin = &adapter->dev_stats;
2730 xstats[count].id = count;
2731 xstats[count].value = *((uint64_t *)
2732 ((char *)stats_begin + stat_offset));
2735 /* Even if the function below fails, we should copy previous (or initial
2736 * values) to keep structure of rte_eth_xstat consistent.
2738 ena_copy_eni_stats(adapter);
2739 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2740 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2741 stats_begin = &adapter->eni_stats;
2743 xstats[count].id = count;
2744 xstats[count].value = *((uint64_t *)
2745 ((char *)stats_begin + stat_offset));
2748 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2749 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2750 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2751 stats_begin = &adapter->rx_ring[i].rx_stats;
2753 xstats[count].id = count;
2754 xstats[count].value = *((uint64_t *)
2755 ((char *)stats_begin + stat_offset));
2759 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2760 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2761 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2762 stats_begin = &adapter->tx_ring[i].rx_stats;
2764 xstats[count].id = count;
2765 xstats[count].value = *((uint64_t *)
2766 ((char *)stats_begin + stat_offset));
2773 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2774 const uint64_t *ids,
2778 struct ena_adapter *adapter = dev->data->dev_private;
2780 uint64_t rx_entries, tx_entries;
2784 bool was_eni_copied = false;
2786 for (i = 0; i < n; ++i) {
2788 /* Check if id belongs to global statistics */
2789 if (id < ENA_STATS_ARRAY_GLOBAL) {
2790 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2795 /* Check if id belongs to ENI statistics */
2796 id -= ENA_STATS_ARRAY_GLOBAL;
2797 if (id < ENA_STATS_ARRAY_ENI) {
2798 /* Avoid reading ENI stats multiple times in a single
2799 * function call, as it requires communication with the
2802 if (!was_eni_copied) {
2803 was_eni_copied = true;
2804 ena_copy_eni_stats(adapter);
2806 values[i] = *((uint64_t *)&adapter->eni_stats + id);
2811 /* Check if id belongs to rx queue statistics */
2812 id -= ENA_STATS_ARRAY_ENI;
2813 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2814 if (id < rx_entries) {
2815 qid = id % dev->data->nb_rx_queues;
2816 id /= dev->data->nb_rx_queues;
2817 values[i] = *((uint64_t *)
2818 &adapter->rx_ring[qid].rx_stats + id);
2822 /* Check if id belongs to rx queue statistics */
2824 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2825 if (id < tx_entries) {
2826 qid = id % dev->data->nb_tx_queues;
2827 id /= dev->data->nb_tx_queues;
2828 values[i] = *((uint64_t *)
2829 &adapter->tx_ring[qid].tx_stats + id);
2838 static int ena_process_bool_devarg(const char *key,
2842 struct ena_adapter *adapter = opaque;
2845 /* Parse the value. */
2846 if (strcmp(value, "1") == 0) {
2848 } else if (strcmp(value, "0") == 0) {
2852 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2857 /* Now, assign it to the proper adapter field. */
2858 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2859 adapter->use_large_llq_hdr = bool_value;
2864 static int ena_parse_devargs(struct ena_adapter *adapter,
2865 struct rte_devargs *devargs)
2867 static const char * const allowed_args[] = {
2868 ENA_DEVARG_LARGE_LLQ_HDR,
2870 struct rte_kvargs *kvlist;
2873 if (devargs == NULL)
2876 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2877 if (kvlist == NULL) {
2878 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2883 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2884 ena_process_bool_devarg, adapter);
2886 rte_kvargs_free(kvlist);
2891 /*********************************************************************
2893 *********************************************************************/
2894 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2895 struct rte_pci_device *pci_dev)
2897 return rte_eth_dev_pci_generic_probe(pci_dev,
2898 sizeof(struct ena_adapter), eth_ena_dev_init);
2901 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2903 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2906 static struct rte_pci_driver rte_ena_pmd = {
2907 .id_table = pci_id_ena_map,
2908 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2909 RTE_PCI_DRV_WC_ACTIVATE,
2910 .probe = eth_ena_pci_probe,
2911 .remove = eth_ena_pci_remove,
2914 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2915 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2916 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2917 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2918 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE);
2919 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE);
2920 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2921 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE);
2923 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2924 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE);
2926 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2927 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE);
2929 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2930 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE);
2933 /******************************************************************************
2934 ******************************** AENQ Handlers *******************************
2935 *****************************************************************************/
2936 static void ena_update_on_link_change(void *adapter_data,
2937 struct ena_admin_aenq_entry *aenq_e)
2939 struct rte_eth_dev *eth_dev;
2940 struct ena_adapter *adapter;
2941 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2944 adapter = adapter_data;
2945 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2946 eth_dev = adapter->rte_dev;
2948 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2949 adapter->link_status = status;
2951 ena_link_update(eth_dev, 0);
2952 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2955 static void ena_notification(void *data,
2956 struct ena_admin_aenq_entry *aenq_e)
2958 struct ena_adapter *adapter = data;
2959 struct ena_admin_ena_hw_hints *hints;
2961 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2962 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2963 aenq_e->aenq_common_desc.group,
2964 ENA_ADMIN_NOTIFICATION);
2966 switch (aenq_e->aenq_common_desc.syndrom) {
2967 case ENA_ADMIN_UPDATE_HINTS:
2968 hints = (struct ena_admin_ena_hw_hints *)
2969 (&aenq_e->inline_data_w4);
2970 ena_update_hints(adapter, hints);
2973 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2974 aenq_e->aenq_common_desc.syndrom);
2978 static void ena_keep_alive(void *adapter_data,
2979 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2981 struct ena_adapter *adapter = adapter_data;
2982 struct ena_admin_aenq_keep_alive_desc *desc;
2986 adapter->timestamp_wd = rte_get_timer_cycles();
2988 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2989 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2990 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2992 adapter->drv_stats->rx_drops = rx_drops;
2993 adapter->dev_stats.tx_drops = tx_drops;
2997 * This handler will called for unknown event group or unimplemented handlers
2999 static void unimplemented_aenq_handler(__rte_unused void *data,
3000 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3002 PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3003 "unimplemented handler\n");
3006 static struct ena_aenq_handlers aenq_handlers = {
3008 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3009 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3010 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3012 .unimplemented_handler = unimplemented_aenq_handler