1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_ethdev_pci.h>
11 #include <rte_atomic.h>
13 #include <rte_errno.h>
14 #include <rte_version.h>
16 #include <rte_kvargs.h>
18 #include "ena_ethdev.h"
20 #include "ena_platform.h"
22 #include "ena_eth_com.h"
24 #include <ena_common_defs.h>
25 #include <ena_regs_defs.h>
26 #include <ena_admin_defs.h>
27 #include <ena_eth_io_defs.h>
29 #define DRV_MODULE_VER_MAJOR 2
30 #define DRV_MODULE_VER_MINOR 1
31 #define DRV_MODULE_VER_SUBMINOR 0
33 #define ENA_IO_TXQ_IDX(q) (2 * (q))
34 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
35 /*reverse version of ENA_IO_RXQ_IDX*/
36 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
41 #define GET_L4_HDR_LEN(mbuf) \
42 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
43 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
45 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
46 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
47 #define ENA_HASH_KEY_SIZE 40
48 #define ETH_GSTRING_LEN 32
50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
52 #define ENA_MIN_RING_DESC 128
54 enum ethtool_stringset {
60 char name[ETH_GSTRING_LEN];
64 #define ENA_STAT_ENTRY(stat, stat_type) { \
66 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
69 #define ENA_STAT_RX_ENTRY(stat) \
70 ENA_STAT_ENTRY(stat, rx)
72 #define ENA_STAT_TX_ENTRY(stat) \
73 ENA_STAT_ENTRY(stat, tx)
75 #define ENA_STAT_GLOBAL_ENTRY(stat) \
76 ENA_STAT_ENTRY(stat, dev)
78 /* Device arguments */
79 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
82 * Each rte_memzone should have unique name.
83 * To satisfy it, count number of allocation and add it to name.
85 rte_atomic32_t ena_alloc_cnt;
87 static const struct ena_stats ena_stats_global_strings[] = {
88 ENA_STAT_GLOBAL_ENTRY(wd_expired),
89 ENA_STAT_GLOBAL_ENTRY(dev_start),
90 ENA_STAT_GLOBAL_ENTRY(dev_stop),
91 ENA_STAT_GLOBAL_ENTRY(tx_drops),
94 static const struct ena_stats ena_stats_tx_strings[] = {
95 ENA_STAT_TX_ENTRY(cnt),
96 ENA_STAT_TX_ENTRY(bytes),
97 ENA_STAT_TX_ENTRY(prepare_ctx_err),
98 ENA_STAT_TX_ENTRY(linearize),
99 ENA_STAT_TX_ENTRY(linearize_failed),
100 ENA_STAT_TX_ENTRY(tx_poll),
101 ENA_STAT_TX_ENTRY(doorbells),
102 ENA_STAT_TX_ENTRY(bad_req_id),
103 ENA_STAT_TX_ENTRY(available_desc),
106 static const struct ena_stats ena_stats_rx_strings[] = {
107 ENA_STAT_RX_ENTRY(cnt),
108 ENA_STAT_RX_ENTRY(bytes),
109 ENA_STAT_RX_ENTRY(refill_partial),
110 ENA_STAT_RX_ENTRY(bad_csum),
111 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
112 ENA_STAT_RX_ENTRY(bad_desc_num),
113 ENA_STAT_RX_ENTRY(bad_req_id),
116 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
117 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
118 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
120 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
121 DEV_TX_OFFLOAD_UDP_CKSUM |\
122 DEV_TX_OFFLOAD_IPV4_CKSUM |\
123 DEV_TX_OFFLOAD_TCP_TSO)
124 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
128 /** Vendor ID used by Amazon devices */
129 #define PCI_VENDOR_ID_AMAZON 0x1D0F
130 /** Amazon devices */
131 #define PCI_DEVICE_ID_ENA_VF 0xEC20
132 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
134 #define ENA_TX_OFFLOAD_MASK (\
141 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
142 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
144 static const struct rte_pci_id pci_id_ena_map[] = {
145 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
146 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
150 static struct ena_aenq_handlers aenq_handlers;
152 static int ena_device_init(struct ena_com_dev *ena_dev,
153 struct ena_com_dev_get_features_ctx *get_feat_ctx,
155 static int ena_dev_configure(struct rte_eth_dev *dev);
156 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
157 struct ena_tx_buffer *tx_info,
158 struct rte_mbuf *mbuf,
160 uint16_t *header_len);
161 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
162 static void ena_tx_cleanup(struct ena_ring *tx_ring);
163 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
165 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
167 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
168 uint16_t nb_desc, unsigned int socket_id,
169 const struct rte_eth_txconf *tx_conf);
170 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
171 uint16_t nb_desc, unsigned int socket_id,
172 const struct rte_eth_rxconf *rx_conf,
173 struct rte_mempool *mp);
174 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
175 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
176 struct ena_com_rx_buf_info *ena_bufs,
178 uint16_t *next_to_clean,
180 static uint16_t eth_ena_recv_pkts(void *rx_queue,
181 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
182 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
183 struct rte_mbuf *mbuf, uint16_t id);
184 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
185 static void ena_init_rings(struct ena_adapter *adapter,
186 bool disable_meta_caching);
187 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
188 static int ena_start(struct rte_eth_dev *dev);
189 static void ena_stop(struct rte_eth_dev *dev);
190 static void ena_close(struct rte_eth_dev *dev);
191 static int ena_dev_reset(struct rte_eth_dev *dev);
192 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
193 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
194 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
195 static void ena_rx_queue_release(void *queue);
196 static void ena_tx_queue_release(void *queue);
197 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
198 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
199 static int ena_link_update(struct rte_eth_dev *dev,
200 int wait_to_complete);
201 static int ena_create_io_queue(struct ena_ring *ring);
202 static void ena_queue_stop(struct ena_ring *ring);
203 static void ena_queue_stop_all(struct rte_eth_dev *dev,
204 enum ena_ring_type ring_type);
205 static int ena_queue_start(struct ena_ring *ring);
206 static int ena_queue_start_all(struct rte_eth_dev *dev,
207 enum ena_ring_type ring_type);
208 static void ena_stats_restart(struct rte_eth_dev *dev);
209 static int ena_infos_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ena_rss_reta_update(struct rte_eth_dev *dev,
212 struct rte_eth_rss_reta_entry64 *reta_conf,
214 static int ena_rss_reta_query(struct rte_eth_dev *dev,
215 struct rte_eth_rss_reta_entry64 *reta_conf,
217 static void ena_interrupt_handler_rte(void *cb_arg);
218 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
219 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
220 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
221 static int ena_xstats_get_names(struct rte_eth_dev *dev,
222 struct rte_eth_xstat_name *xstats_names,
224 static int ena_xstats_get(struct rte_eth_dev *dev,
225 struct rte_eth_xstat *stats,
227 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
231 static int ena_process_bool_devarg(const char *key,
234 static int ena_parse_devargs(struct ena_adapter *adapter,
235 struct rte_devargs *devargs);
237 static const struct eth_dev_ops ena_dev_ops = {
238 .dev_configure = ena_dev_configure,
239 .dev_infos_get = ena_infos_get,
240 .rx_queue_setup = ena_rx_queue_setup,
241 .tx_queue_setup = ena_tx_queue_setup,
242 .dev_start = ena_start,
243 .dev_stop = ena_stop,
244 .link_update = ena_link_update,
245 .stats_get = ena_stats_get,
246 .xstats_get_names = ena_xstats_get_names,
247 .xstats_get = ena_xstats_get,
248 .xstats_get_by_id = ena_xstats_get_by_id,
249 .mtu_set = ena_mtu_set,
250 .rx_queue_release = ena_rx_queue_release,
251 .tx_queue_release = ena_tx_queue_release,
252 .dev_close = ena_close,
253 .dev_reset = ena_dev_reset,
254 .reta_update = ena_rss_reta_update,
255 .reta_query = ena_rss_reta_query,
258 void ena_rss_key_fill(void *key, size_t size)
260 static bool key_generated;
261 static uint8_t default_key[ENA_HASH_KEY_SIZE];
264 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
266 if (!key_generated) {
267 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
268 default_key[i] = rte_rand() & 0xff;
269 key_generated = true;
272 rte_memcpy(key, default_key, size);
275 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
276 struct ena_com_rx_ctx *ena_rx_ctx)
278 uint64_t ol_flags = 0;
279 uint32_t packet_type = 0;
281 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
282 packet_type |= RTE_PTYPE_L4_TCP;
283 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
284 packet_type |= RTE_PTYPE_L4_UDP;
286 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
287 packet_type |= RTE_PTYPE_L3_IPV4;
288 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
289 packet_type |= RTE_PTYPE_L3_IPV6;
291 if (!ena_rx_ctx->l4_csum_checked)
292 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
294 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
295 ol_flags |= PKT_RX_L4_CKSUM_BAD;
297 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
299 if (unlikely(ena_rx_ctx->l3_csum_err))
300 ol_flags |= PKT_RX_IP_CKSUM_BAD;
302 mbuf->ol_flags = ol_flags;
303 mbuf->packet_type = packet_type;
306 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
307 struct ena_com_tx_ctx *ena_tx_ctx,
308 uint64_t queue_offloads,
309 bool disable_meta_caching)
311 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
313 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
314 (queue_offloads & QUEUE_OFFLOADS)) {
315 /* check if TSO is required */
316 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
317 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
318 ena_tx_ctx->tso_enable = true;
320 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
323 /* check if L3 checksum is needed */
324 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
325 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
326 ena_tx_ctx->l3_csum_enable = true;
328 if (mbuf->ol_flags & PKT_TX_IPV6) {
329 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
331 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
333 /* set don't fragment (DF) flag */
334 if (mbuf->packet_type &
335 (RTE_PTYPE_L4_NONFRAG
336 | RTE_PTYPE_INNER_L4_NONFRAG))
337 ena_tx_ctx->df = true;
340 /* check if L4 checksum is needed */
341 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
342 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
343 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
344 ena_tx_ctx->l4_csum_enable = true;
345 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
347 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
348 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
349 ena_tx_ctx->l4_csum_enable = true;
351 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
352 ena_tx_ctx->l4_csum_enable = false;
355 ena_meta->mss = mbuf->tso_segsz;
356 ena_meta->l3_hdr_len = mbuf->l3_len;
357 ena_meta->l3_hdr_offset = mbuf->l2_len;
359 ena_tx_ctx->meta_valid = true;
360 } else if (disable_meta_caching) {
361 memset(ena_meta, 0, sizeof(*ena_meta));
362 ena_tx_ctx->meta_valid = true;
364 ena_tx_ctx->meta_valid = false;
368 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
370 if (likely(req_id < rx_ring->ring_size))
373 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
375 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
376 rx_ring->adapter->trigger_reset = true;
377 ++rx_ring->rx_stats.bad_req_id;
382 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
384 struct ena_tx_buffer *tx_info = NULL;
386 if (likely(req_id < tx_ring->ring_size)) {
387 tx_info = &tx_ring->tx_buffer_info[req_id];
388 if (likely(tx_info->mbuf))
393 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
395 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
397 /* Trigger device reset */
398 ++tx_ring->tx_stats.bad_req_id;
399 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
400 tx_ring->adapter->trigger_reset = true;
404 static void ena_config_host_info(struct ena_com_dev *ena_dev)
406 struct ena_admin_host_info *host_info;
409 /* Allocate only the host info */
410 rc = ena_com_allocate_host_info(ena_dev);
412 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
416 host_info = ena_dev->host_attr.host_info;
418 host_info->os_type = ENA_ADMIN_OS_DPDK;
419 host_info->kernel_ver = RTE_VERSION;
420 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
421 sizeof(host_info->kernel_ver_str));
422 host_info->os_dist = RTE_VERSION;
423 strlcpy((char *)host_info->os_dist_str, rte_version(),
424 sizeof(host_info->os_dist_str));
425 host_info->driver_version =
426 (DRV_MODULE_VER_MAJOR) |
427 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
428 (DRV_MODULE_VER_SUBMINOR <<
429 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
430 host_info->num_cpus = rte_lcore_count();
432 host_info->driver_supported_features =
433 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
435 rc = ena_com_set_host_attributes(ena_dev);
437 if (rc == -ENA_COM_UNSUPPORTED)
438 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
440 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
448 ena_com_delete_host_info(ena_dev);
451 /* This function calculates the number of xstats based on the current config */
452 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
454 return ENA_STATS_ARRAY_GLOBAL +
455 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
456 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
459 static void ena_config_debug_area(struct ena_adapter *adapter)
464 ss_count = ena_xstats_calc_num(adapter->rte_dev);
466 /* allocate 32 bytes for each string and 64bit for the value */
467 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
469 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
471 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
475 rc = ena_com_set_host_attributes(&adapter->ena_dev);
477 if (rc == -ENA_COM_UNSUPPORTED)
478 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
480 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
487 ena_com_delete_debug_area(&adapter->ena_dev);
490 static void ena_close(struct rte_eth_dev *dev)
492 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
493 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
494 struct ena_adapter *adapter = dev->data->dev_private;
496 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
498 adapter->state = ENA_ADAPTER_STATE_CLOSED;
500 ena_rx_queue_release_all(dev);
501 ena_tx_queue_release_all(dev);
503 rte_free(adapter->drv_stats);
504 adapter->drv_stats = NULL;
506 rte_intr_disable(intr_handle);
507 rte_intr_callback_unregister(intr_handle,
508 ena_interrupt_handler_rte,
512 * MAC is not allocated dynamically. Setting NULL should prevent from
513 * release of the resource in the rte_eth_dev_release_port().
515 dev->data->mac_addrs = NULL;
519 ena_dev_reset(struct rte_eth_dev *dev)
523 ena_destroy_device(dev);
524 rc = eth_ena_dev_init(dev);
526 PMD_INIT_LOG(CRIT, "Cannot initialize device");
531 static int ena_rss_reta_update(struct rte_eth_dev *dev,
532 struct rte_eth_rss_reta_entry64 *reta_conf,
535 struct ena_adapter *adapter = dev->data->dev_private;
536 struct ena_com_dev *ena_dev = &adapter->ena_dev;
542 if ((reta_size == 0) || (reta_conf == NULL))
545 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
547 "indirection table %d is bigger than supported (%d)\n",
548 reta_size, ENA_RX_RSS_TABLE_SIZE);
552 for (i = 0 ; i < reta_size ; i++) {
553 /* each reta_conf is for 64 entries.
554 * to support 128 we use 2 conf of 64
556 conf_idx = i / RTE_RETA_GROUP_SIZE;
557 idx = i % RTE_RETA_GROUP_SIZE;
558 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
560 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
562 rc = ena_com_indirect_table_fill_entry(ena_dev,
565 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
567 "Cannot fill indirect table\n");
573 rc = ena_com_indirect_table_set(ena_dev);
574 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
575 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
579 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n",
580 __func__, reta_size, adapter->rte_dev->data->port_id);
585 /* Query redirection table. */
586 static int ena_rss_reta_query(struct rte_eth_dev *dev,
587 struct rte_eth_rss_reta_entry64 *reta_conf,
590 struct ena_adapter *adapter = dev->data->dev_private;
591 struct ena_com_dev *ena_dev = &adapter->ena_dev;
594 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
598 if (reta_size == 0 || reta_conf == NULL ||
599 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
602 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
603 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
604 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
608 for (i = 0 ; i < reta_size ; i++) {
609 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
610 reta_idx = i % RTE_RETA_GROUP_SIZE;
611 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
612 reta_conf[reta_conf_idx].reta[reta_idx] =
613 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
619 static int ena_rss_init_default(struct ena_adapter *adapter)
621 struct ena_com_dev *ena_dev = &adapter->ena_dev;
622 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
626 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
628 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
632 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
633 val = i % nb_rx_queues;
634 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
635 ENA_IO_RXQ_IDX(val));
636 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
637 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
642 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
643 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
644 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
645 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
649 rc = ena_com_set_default_hash_ctrl(ena_dev);
650 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
651 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
655 rc = ena_com_indirect_table_set(ena_dev);
656 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
657 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
660 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
661 adapter->rte_dev->data->port_id);
666 ena_com_rss_destroy(ena_dev);
672 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
674 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
675 int nb_queues = dev->data->nb_rx_queues;
678 for (i = 0; i < nb_queues; i++)
679 ena_rx_queue_release(queues[i]);
682 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
684 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
685 int nb_queues = dev->data->nb_tx_queues;
688 for (i = 0; i < nb_queues; i++)
689 ena_tx_queue_release(queues[i]);
692 static void ena_rx_queue_release(void *queue)
694 struct ena_ring *ring = (struct ena_ring *)queue;
696 /* Free ring resources */
697 if (ring->rx_buffer_info)
698 rte_free(ring->rx_buffer_info);
699 ring->rx_buffer_info = NULL;
701 if (ring->rx_refill_buffer)
702 rte_free(ring->rx_refill_buffer);
703 ring->rx_refill_buffer = NULL;
705 if (ring->empty_rx_reqs)
706 rte_free(ring->empty_rx_reqs);
707 ring->empty_rx_reqs = NULL;
709 ring->configured = 0;
711 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
712 ring->port_id, ring->id);
715 static void ena_tx_queue_release(void *queue)
717 struct ena_ring *ring = (struct ena_ring *)queue;
719 /* Free ring resources */
720 if (ring->push_buf_intermediate_buf)
721 rte_free(ring->push_buf_intermediate_buf);
723 if (ring->tx_buffer_info)
724 rte_free(ring->tx_buffer_info);
726 if (ring->empty_tx_reqs)
727 rte_free(ring->empty_tx_reqs);
729 ring->empty_tx_reqs = NULL;
730 ring->tx_buffer_info = NULL;
731 ring->push_buf_intermediate_buf = NULL;
733 ring->configured = 0;
735 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
736 ring->port_id, ring->id);
739 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
743 for (i = 0; i < ring->ring_size; ++i) {
744 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
746 rte_mbuf_raw_free(rx_info->mbuf);
747 rx_info->mbuf = NULL;
752 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
756 for (i = 0; i < ring->ring_size; ++i) {
757 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
760 rte_pktmbuf_free(tx_buf->mbuf);
764 static int ena_link_update(struct rte_eth_dev *dev,
765 __rte_unused int wait_to_complete)
767 struct rte_eth_link *link = &dev->data->dev_link;
768 struct ena_adapter *adapter = dev->data->dev_private;
770 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
771 link->link_speed = ETH_SPEED_NUM_NONE;
772 link->link_duplex = ETH_LINK_FULL_DUPLEX;
777 static int ena_queue_start_all(struct rte_eth_dev *dev,
778 enum ena_ring_type ring_type)
780 struct ena_adapter *adapter = dev->data->dev_private;
781 struct ena_ring *queues = NULL;
786 if (ring_type == ENA_RING_TYPE_RX) {
787 queues = adapter->rx_ring;
788 nb_queues = dev->data->nb_rx_queues;
790 queues = adapter->tx_ring;
791 nb_queues = dev->data->nb_tx_queues;
793 for (i = 0; i < nb_queues; i++) {
794 if (queues[i].configured) {
795 if (ring_type == ENA_RING_TYPE_RX) {
797 dev->data->rx_queues[i] == &queues[i],
798 "Inconsistent state of rx queues\n");
801 dev->data->tx_queues[i] == &queues[i],
802 "Inconsistent state of tx queues\n");
805 rc = ena_queue_start(&queues[i]);
809 "failed to start queue %d type(%d)",
820 if (queues[i].configured)
821 ena_queue_stop(&queues[i]);
826 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
828 uint32_t max_frame_len = adapter->max_mtu;
830 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
831 DEV_RX_OFFLOAD_JUMBO_FRAME)
833 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
835 return max_frame_len;
838 static int ena_check_valid_conf(struct ena_adapter *adapter)
840 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
842 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
843 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
844 "max mtu: %d, min mtu: %d",
845 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
846 return ENA_COM_UNSUPPORTED;
853 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
854 bool use_large_llq_hdr)
856 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
857 struct ena_com_dev *ena_dev = ctx->ena_dev;
858 uint32_t max_tx_queue_size;
859 uint32_t max_rx_queue_size;
861 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
862 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
863 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
864 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
865 max_queue_ext->max_rx_sq_depth);
866 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
868 if (ena_dev->tx_mem_queue_type ==
869 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
870 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
873 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
874 max_queue_ext->max_tx_sq_depth);
877 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
878 max_queue_ext->max_per_packet_rx_descs);
879 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
880 max_queue_ext->max_per_packet_tx_descs);
882 struct ena_admin_queue_feature_desc *max_queues =
883 &ctx->get_feat_ctx->max_queues;
884 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
885 max_queues->max_sq_depth);
886 max_tx_queue_size = max_queues->max_cq_depth;
888 if (ena_dev->tx_mem_queue_type ==
889 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
890 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
893 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
894 max_queues->max_sq_depth);
897 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
898 max_queues->max_packet_rx_descs);
899 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
900 max_queues->max_packet_tx_descs);
903 /* Round down to the nearest power of 2 */
904 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
905 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
907 if (use_large_llq_hdr) {
908 if ((llq->entry_size_ctrl_supported &
909 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
910 (ena_dev->tx_mem_queue_type ==
911 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
912 max_tx_queue_size /= 2;
914 "Forcing large headers and decreasing maximum TX queue size to %d\n",
918 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
922 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
923 PMD_INIT_LOG(ERR, "Invalid queue size");
927 ctx->max_tx_queue_size = max_tx_queue_size;
928 ctx->max_rx_queue_size = max_rx_queue_size;
933 static void ena_stats_restart(struct rte_eth_dev *dev)
935 struct ena_adapter *adapter = dev->data->dev_private;
937 rte_atomic64_init(&adapter->drv_stats->ierrors);
938 rte_atomic64_init(&adapter->drv_stats->oerrors);
939 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
940 adapter->drv_stats->rx_drops = 0;
943 static int ena_stats_get(struct rte_eth_dev *dev,
944 struct rte_eth_stats *stats)
946 struct ena_admin_basic_stats ena_stats;
947 struct ena_adapter *adapter = dev->data->dev_private;
948 struct ena_com_dev *ena_dev = &adapter->ena_dev;
953 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
956 memset(&ena_stats, 0, sizeof(ena_stats));
957 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
959 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
963 /* Set of basic statistics from ENA */
964 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
965 ena_stats.rx_pkts_low);
966 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
967 ena_stats.tx_pkts_low);
968 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
969 ena_stats.rx_bytes_low);
970 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
971 ena_stats.tx_bytes_low);
973 /* Driver related stats */
974 stats->imissed = adapter->drv_stats->rx_drops;
975 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
976 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
977 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
979 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
980 RTE_ETHDEV_QUEUE_STAT_CNTRS);
981 for (i = 0; i < max_rings_stats; ++i) {
982 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
984 stats->q_ibytes[i] = rx_stats->bytes;
985 stats->q_ipackets[i] = rx_stats->cnt;
986 stats->q_errors[i] = rx_stats->bad_desc_num +
987 rx_stats->bad_req_id;
990 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
991 RTE_ETHDEV_QUEUE_STAT_CNTRS);
992 for (i = 0; i < max_rings_stats; ++i) {
993 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
995 stats->q_obytes[i] = tx_stats->bytes;
996 stats->q_opackets[i] = tx_stats->cnt;
1002 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1004 struct ena_adapter *adapter;
1005 struct ena_com_dev *ena_dev;
1008 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1009 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1010 adapter = dev->data->dev_private;
1012 ena_dev = &adapter->ena_dev;
1013 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1015 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1017 "Invalid MTU setting. new_mtu: %d "
1018 "max mtu: %d min mtu: %d\n",
1019 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1023 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1025 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1027 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1032 static int ena_start(struct rte_eth_dev *dev)
1034 struct ena_adapter *adapter = dev->data->dev_private;
1038 rc = ena_check_valid_conf(adapter);
1042 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1046 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1050 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1051 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1052 rc = ena_rss_init_default(adapter);
1057 ena_stats_restart(dev);
1059 adapter->timestamp_wd = rte_get_timer_cycles();
1060 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1062 ticks = rte_get_timer_hz();
1063 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1064 ena_timer_wd_callback, adapter);
1066 ++adapter->dev_stats.dev_start;
1067 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1072 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1074 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1078 static void ena_stop(struct rte_eth_dev *dev)
1080 struct ena_adapter *adapter = dev->data->dev_private;
1081 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1084 rte_timer_stop_sync(&adapter->timer_wd);
1085 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1086 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1088 if (adapter->trigger_reset) {
1089 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1091 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1094 ++adapter->dev_stats.dev_stop;
1095 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1098 static int ena_create_io_queue(struct ena_ring *ring)
1100 struct ena_adapter *adapter;
1101 struct ena_com_dev *ena_dev;
1102 struct ena_com_create_io_ctx ctx =
1103 /* policy set to _HOST just to satisfy icc compiler */
1104 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1110 adapter = ring->adapter;
1111 ena_dev = &adapter->ena_dev;
1113 if (ring->type == ENA_RING_TYPE_TX) {
1114 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1115 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1116 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1117 for (i = 0; i < ring->ring_size; i++)
1118 ring->empty_tx_reqs[i] = i;
1120 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1121 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1122 for (i = 0; i < ring->ring_size; i++)
1123 ring->empty_rx_reqs[i] = i;
1125 ctx.queue_size = ring->ring_size;
1127 ctx.msix_vector = -1; /* interrupts not used */
1128 ctx.numa_node = ring->numa_socket_id;
1130 rc = ena_com_create_io_queue(ena_dev, &ctx);
1133 "failed to create io queue #%d (qid:%d) rc: %d\n",
1134 ring->id, ena_qid, rc);
1138 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1139 &ring->ena_com_io_sq,
1140 &ring->ena_com_io_cq);
1143 "Failed to get io queue handlers. queue num %d rc: %d\n",
1145 ena_com_destroy_io_queue(ena_dev, ena_qid);
1149 if (ring->type == ENA_RING_TYPE_TX)
1150 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1155 static void ena_queue_stop(struct ena_ring *ring)
1157 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1159 if (ring->type == ENA_RING_TYPE_RX) {
1160 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1161 ena_rx_queue_release_bufs(ring);
1163 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1164 ena_tx_queue_release_bufs(ring);
1168 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1169 enum ena_ring_type ring_type)
1171 struct ena_adapter *adapter = dev->data->dev_private;
1172 struct ena_ring *queues = NULL;
1173 uint16_t nb_queues, i;
1175 if (ring_type == ENA_RING_TYPE_RX) {
1176 queues = adapter->rx_ring;
1177 nb_queues = dev->data->nb_rx_queues;
1179 queues = adapter->tx_ring;
1180 nb_queues = dev->data->nb_tx_queues;
1183 for (i = 0; i < nb_queues; ++i)
1184 if (queues[i].configured)
1185 ena_queue_stop(&queues[i]);
1188 static int ena_queue_start(struct ena_ring *ring)
1192 ena_assert_msg(ring->configured == 1,
1193 "Trying to start unconfigured queue\n");
1195 rc = ena_create_io_queue(ring);
1197 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1201 ring->next_to_clean = 0;
1202 ring->next_to_use = 0;
1204 if (ring->type == ENA_RING_TYPE_TX) {
1205 ring->tx_stats.available_desc =
1206 ena_com_free_q_entries(ring->ena_com_io_sq);
1210 bufs_num = ring->ring_size - 1;
1211 rc = ena_populate_rx_queue(ring, bufs_num);
1212 if (rc != bufs_num) {
1213 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1214 ENA_IO_RXQ_IDX(ring->id));
1215 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1216 return ENA_COM_FAULT;
1222 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1225 unsigned int socket_id,
1226 const struct rte_eth_txconf *tx_conf)
1228 struct ena_ring *txq = NULL;
1229 struct ena_adapter *adapter = dev->data->dev_private;
1232 txq = &adapter->tx_ring[queue_idx];
1234 if (txq->configured) {
1236 "API violation. Queue %d is already configured\n",
1238 return ENA_COM_FAULT;
1241 if (!rte_is_power_of_2(nb_desc)) {
1243 "Unsupported size of TX queue: %d is not a power of 2.\n",
1248 if (nb_desc > adapter->max_tx_ring_size) {
1250 "Unsupported size of TX queue (max size: %d)\n",
1251 adapter->max_tx_ring_size);
1255 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1256 nb_desc = adapter->max_tx_ring_size;
1258 txq->port_id = dev->data->port_id;
1259 txq->next_to_clean = 0;
1260 txq->next_to_use = 0;
1261 txq->ring_size = nb_desc;
1262 txq->size_mask = nb_desc - 1;
1263 txq->numa_socket_id = socket_id;
1265 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1266 sizeof(struct ena_tx_buffer) *
1268 RTE_CACHE_LINE_SIZE);
1269 if (!txq->tx_buffer_info) {
1270 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1274 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1275 sizeof(u16) * txq->ring_size,
1276 RTE_CACHE_LINE_SIZE);
1277 if (!txq->empty_tx_reqs) {
1278 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1279 rte_free(txq->tx_buffer_info);
1283 txq->push_buf_intermediate_buf =
1284 rte_zmalloc("txq->push_buf_intermediate_buf",
1285 txq->tx_max_header_size,
1286 RTE_CACHE_LINE_SIZE);
1287 if (!txq->push_buf_intermediate_buf) {
1288 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1289 rte_free(txq->tx_buffer_info);
1290 rte_free(txq->empty_tx_reqs);
1294 for (i = 0; i < txq->ring_size; i++)
1295 txq->empty_tx_reqs[i] = i;
1297 if (tx_conf != NULL) {
1299 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1301 /* Store pointer to this queue in upper layer */
1302 txq->configured = 1;
1303 dev->data->tx_queues[queue_idx] = txq;
1308 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1311 unsigned int socket_id,
1312 __rte_unused const struct rte_eth_rxconf *rx_conf,
1313 struct rte_mempool *mp)
1315 struct ena_adapter *adapter = dev->data->dev_private;
1316 struct ena_ring *rxq = NULL;
1320 rxq = &adapter->rx_ring[queue_idx];
1321 if (rxq->configured) {
1323 "API violation. Queue %d is already configured\n",
1325 return ENA_COM_FAULT;
1328 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1329 nb_desc = adapter->max_rx_ring_size;
1331 if (!rte_is_power_of_2(nb_desc)) {
1333 "Unsupported size of RX queue: %d is not a power of 2.\n",
1338 if (nb_desc > adapter->max_rx_ring_size) {
1340 "Unsupported size of RX queue (max size: %d)\n",
1341 adapter->max_rx_ring_size);
1345 /* ENA isn't supporting buffers smaller than 1400 bytes */
1346 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1347 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1349 "Unsupported size of RX buffer: %zu (min size: %d)\n",
1350 buffer_size, ENA_RX_BUF_MIN_SIZE);
1354 rxq->port_id = dev->data->port_id;
1355 rxq->next_to_clean = 0;
1356 rxq->next_to_use = 0;
1357 rxq->ring_size = nb_desc;
1358 rxq->size_mask = nb_desc - 1;
1359 rxq->numa_socket_id = socket_id;
1362 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1363 sizeof(struct ena_rx_buffer) * nb_desc,
1364 RTE_CACHE_LINE_SIZE);
1365 if (!rxq->rx_buffer_info) {
1366 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1370 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1371 sizeof(struct rte_mbuf *) * nb_desc,
1372 RTE_CACHE_LINE_SIZE);
1374 if (!rxq->rx_refill_buffer) {
1375 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1376 rte_free(rxq->rx_buffer_info);
1377 rxq->rx_buffer_info = NULL;
1381 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1382 sizeof(uint16_t) * nb_desc,
1383 RTE_CACHE_LINE_SIZE);
1384 if (!rxq->empty_rx_reqs) {
1385 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1386 rte_free(rxq->rx_buffer_info);
1387 rxq->rx_buffer_info = NULL;
1388 rte_free(rxq->rx_refill_buffer);
1389 rxq->rx_refill_buffer = NULL;
1393 for (i = 0; i < nb_desc; i++)
1394 rxq->empty_rx_reqs[i] = i;
1396 /* Store pointer to this queue in upper layer */
1397 rxq->configured = 1;
1398 dev->data->rx_queues[queue_idx] = rxq;
1403 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1404 struct rte_mbuf *mbuf, uint16_t id)
1406 struct ena_com_buf ebuf;
1409 /* prepare physical address for DMA transaction */
1410 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1411 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1413 /* pass resource to device */
1414 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1415 if (unlikely(rc != 0))
1416 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1421 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1425 uint16_t next_to_use = rxq->next_to_use;
1426 uint16_t in_use, req_id;
1427 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1429 if (unlikely(!count))
1432 in_use = rxq->ring_size - 1 -
1433 ena_com_free_q_entries(rxq->ena_com_io_sq);
1434 ena_assert_msg(((in_use + count) < rxq->ring_size),
1435 "bad ring state\n");
1437 /* get resources for incoming packets */
1438 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1439 if (unlikely(rc < 0)) {
1440 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1441 ++rxq->rx_stats.mbuf_alloc_fail;
1442 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1446 for (i = 0; i < count; i++) {
1447 struct rte_mbuf *mbuf = mbufs[i];
1448 struct ena_rx_buffer *rx_info;
1450 if (likely((i + 4) < count))
1451 rte_prefetch0(mbufs[i + 4]);
1453 req_id = rxq->empty_rx_reqs[next_to_use];
1454 rc = validate_rx_req_id(rxq, req_id);
1458 rx_info = &rxq->rx_buffer_info[req_id];
1460 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1461 if (unlikely(rc != 0))
1464 rx_info->mbuf = mbuf;
1465 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1468 if (unlikely(i < count)) {
1469 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1470 "buffers (from %d)\n", rxq->id, i, count);
1471 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1473 ++rxq->rx_stats.refill_partial;
1476 /* When we submitted free recources to device... */
1477 if (likely(i > 0)) {
1478 /* ...let HW know that it can fill buffers with data. */
1479 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1481 rxq->next_to_use = next_to_use;
1487 static int ena_device_init(struct ena_com_dev *ena_dev,
1488 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1491 uint32_t aenq_groups;
1493 bool readless_supported;
1495 /* Initialize mmio registers */
1496 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1498 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1502 /* The PCIe configuration space revision id indicate if mmio reg
1505 readless_supported =
1506 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1507 & ENA_MMIO_DISABLE_REG_READ);
1508 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1511 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1513 PMD_DRV_LOG(ERR, "cannot reset device\n");
1514 goto err_mmio_read_less;
1517 /* check FW version */
1518 rc = ena_com_validate_version(ena_dev);
1520 PMD_DRV_LOG(ERR, "device version is too low\n");
1521 goto err_mmio_read_less;
1524 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1526 /* ENA device administration layer init */
1527 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1530 "cannot initialize ena admin queue with device\n");
1531 goto err_mmio_read_less;
1534 /* To enable the msix interrupts the driver needs to know the number
1535 * of queues. So the driver uses polling mode to retrieve this
1538 ena_com_set_admin_polling_mode(ena_dev, true);
1540 ena_config_host_info(ena_dev);
1542 /* Get Device Attributes and features */
1543 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1546 "cannot get attribute for ena device rc= %d\n", rc);
1547 goto err_admin_init;
1550 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1551 BIT(ENA_ADMIN_NOTIFICATION) |
1552 BIT(ENA_ADMIN_KEEP_ALIVE) |
1553 BIT(ENA_ADMIN_FATAL_ERROR) |
1554 BIT(ENA_ADMIN_WARNING);
1556 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1557 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1559 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1560 goto err_admin_init;
1563 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1568 ena_com_admin_destroy(ena_dev);
1571 ena_com_mmio_reg_read_request_destroy(ena_dev);
1576 static void ena_interrupt_handler_rte(void *cb_arg)
1578 struct ena_adapter *adapter = cb_arg;
1579 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1581 ena_com_admin_q_comp_intr_handler(ena_dev);
1582 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1583 ena_com_aenq_intr_handler(ena_dev, adapter);
1586 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1588 if (!adapter->wd_state)
1591 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1594 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1595 adapter->keep_alive_timeout)) {
1596 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1597 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1598 adapter->trigger_reset = true;
1599 ++adapter->dev_stats.wd_expired;
1603 /* Check if admin queue is enabled */
1604 static void check_for_admin_com_state(struct ena_adapter *adapter)
1606 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1607 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1608 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1609 adapter->trigger_reset = true;
1613 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1616 struct ena_adapter *adapter = arg;
1617 struct rte_eth_dev *dev = adapter->rte_dev;
1619 check_for_missing_keep_alive(adapter);
1620 check_for_admin_com_state(adapter);
1622 if (unlikely(adapter->trigger_reset)) {
1623 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1624 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1630 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1631 struct ena_admin_feature_llq_desc *llq,
1632 bool use_large_llq_hdr)
1634 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1635 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1636 llq_config->llq_num_decs_before_header =
1637 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1639 if (use_large_llq_hdr &&
1640 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1641 llq_config->llq_ring_entry_size =
1642 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1643 llq_config->llq_ring_entry_size_value = 256;
1645 llq_config->llq_ring_entry_size =
1646 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1647 llq_config->llq_ring_entry_size_value = 128;
1652 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1653 struct ena_com_dev *ena_dev,
1654 struct ena_admin_feature_llq_desc *llq,
1655 struct ena_llq_configurations *llq_default_configurations)
1658 u32 llq_feature_mask;
1660 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1661 if (!(ena_dev->supported_features & llq_feature_mask)) {
1663 "LLQ is not supported. Fallback to host mode policy.\n");
1664 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1668 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1670 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1671 "Fallback to host mode policy.");
1672 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1676 /* Nothing to config, exit */
1677 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1680 if (!adapter->dev_mem_base) {
1681 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1682 "Fallback to host mode policy.\n.");
1683 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1687 ena_dev->mem_bar = adapter->dev_mem_base;
1692 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1693 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1695 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1697 /* Regular queues capabilities */
1698 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1699 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1700 &get_feat_ctx->max_queue_ext.max_queue_ext;
1701 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1702 max_queue_ext->max_rx_cq_num);
1703 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1704 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1706 struct ena_admin_queue_feature_desc *max_queues =
1707 &get_feat_ctx->max_queues;
1708 io_tx_sq_num = max_queues->max_sq_num;
1709 io_tx_cq_num = max_queues->max_cq_num;
1710 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1713 /* In case of LLQ use the llq number in the get feature cmd */
1714 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1715 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1717 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1718 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1719 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1721 if (unlikely(max_num_io_queues == 0)) {
1722 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1726 return max_num_io_queues;
1729 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1731 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1732 struct rte_pci_device *pci_dev;
1733 struct rte_intr_handle *intr_handle;
1734 struct ena_adapter *adapter = eth_dev->data->dev_private;
1735 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1736 struct ena_com_dev_get_features_ctx get_feat_ctx;
1737 struct ena_llq_configurations llq_config;
1738 const char *queue_type_str;
1739 uint32_t max_num_io_queues;
1741 static int adapters_found;
1742 bool disable_meta_caching;
1743 bool wd_state = false;
1745 eth_dev->dev_ops = &ena_dev_ops;
1746 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1747 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1748 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1750 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1753 memset(adapter, 0, sizeof(struct ena_adapter));
1754 ena_dev = &adapter->ena_dev;
1756 adapter->rte_eth_dev_data = eth_dev->data;
1757 adapter->rte_dev = eth_dev;
1759 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1760 adapter->pdev = pci_dev;
1762 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1763 pci_dev->addr.domain,
1765 pci_dev->addr.devid,
1766 pci_dev->addr.function);
1768 intr_handle = &pci_dev->intr_handle;
1770 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1771 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1773 if (!adapter->regs) {
1774 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1779 ena_dev->reg_bar = adapter->regs;
1780 ena_dev->dmadev = adapter->pdev;
1782 adapter->id_number = adapters_found;
1784 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1785 adapter->id_number);
1787 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1789 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1793 /* device specific initialization routine */
1794 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1796 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1799 adapter->wd_state = wd_state;
1801 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1802 adapter->use_large_llq_hdr);
1803 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1804 &get_feat_ctx.llq, &llq_config);
1806 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1810 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1811 queue_type_str = "Regular";
1813 queue_type_str = "Low latency";
1814 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1816 calc_queue_ctx.ena_dev = ena_dev;
1817 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1819 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1820 rc = ena_calc_io_queue_size(&calc_queue_ctx,
1821 adapter->use_large_llq_hdr);
1822 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1824 goto err_device_destroy;
1827 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1828 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1829 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1830 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1831 adapter->max_num_io_queues = max_num_io_queues;
1833 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1834 disable_meta_caching =
1835 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1836 BIT(ENA_ADMIN_DISABLE_META_CACHING));
1838 disable_meta_caching = false;
1841 /* prepare ring structures */
1842 ena_init_rings(adapter, disable_meta_caching);
1844 ena_config_debug_area(adapter);
1846 /* Set max MTU for this device */
1847 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1849 /* set device support for offloads */
1850 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1851 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1852 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1853 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1854 adapter->offloads.rx_csum_supported =
1855 (get_feat_ctx.offload.rx_supported &
1856 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1858 /* Copy MAC address and point DPDK to it */
1859 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1860 rte_ether_addr_copy((struct rte_ether_addr *)
1861 get_feat_ctx.dev_attr.mac_addr,
1862 (struct rte_ether_addr *)adapter->mac_addr);
1865 * Pass the information to the rte_eth_dev_close() that it should also
1866 * release the private port resources.
1868 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1870 adapter->drv_stats = rte_zmalloc("adapter stats",
1871 sizeof(*adapter->drv_stats),
1872 RTE_CACHE_LINE_SIZE);
1873 if (!adapter->drv_stats) {
1874 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1876 goto err_delete_debug_area;
1879 rte_intr_callback_register(intr_handle,
1880 ena_interrupt_handler_rte,
1882 rte_intr_enable(intr_handle);
1883 ena_com_set_admin_polling_mode(ena_dev, false);
1884 ena_com_admin_aenq_enable(ena_dev);
1886 if (adapters_found == 0)
1887 rte_timer_subsystem_init();
1888 rte_timer_init(&adapter->timer_wd);
1891 adapter->state = ENA_ADAPTER_STATE_INIT;
1895 err_delete_debug_area:
1896 ena_com_delete_debug_area(ena_dev);
1899 ena_com_delete_host_info(ena_dev);
1900 ena_com_admin_destroy(ena_dev);
1906 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1908 struct ena_adapter *adapter = eth_dev->data->dev_private;
1909 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1911 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1914 ena_com_set_admin_running_state(ena_dev, false);
1916 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1919 ena_com_delete_debug_area(ena_dev);
1920 ena_com_delete_host_info(ena_dev);
1922 ena_com_abort_admin_commands(ena_dev);
1923 ena_com_wait_for_abort_completion(ena_dev);
1924 ena_com_admin_destroy(ena_dev);
1925 ena_com_mmio_reg_read_request_destroy(ena_dev);
1927 adapter->state = ENA_ADAPTER_STATE_FREE;
1930 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1932 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1935 ena_destroy_device(eth_dev);
1937 eth_dev->dev_ops = NULL;
1938 eth_dev->rx_pkt_burst = NULL;
1939 eth_dev->tx_pkt_burst = NULL;
1940 eth_dev->tx_pkt_prepare = NULL;
1945 static int ena_dev_configure(struct rte_eth_dev *dev)
1947 struct ena_adapter *adapter = dev->data->dev_private;
1949 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1951 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1952 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1956 static void ena_init_rings(struct ena_adapter *adapter,
1957 bool disable_meta_caching)
1961 for (i = 0; i < adapter->max_num_io_queues; i++) {
1962 struct ena_ring *ring = &adapter->tx_ring[i];
1964 ring->configured = 0;
1965 ring->type = ENA_RING_TYPE_TX;
1966 ring->adapter = adapter;
1968 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1969 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1970 ring->sgl_size = adapter->max_tx_sgl_size;
1971 ring->disable_meta_caching = disable_meta_caching;
1974 for (i = 0; i < adapter->max_num_io_queues; i++) {
1975 struct ena_ring *ring = &adapter->rx_ring[i];
1977 ring->configured = 0;
1978 ring->type = ENA_RING_TYPE_RX;
1979 ring->adapter = adapter;
1981 ring->sgl_size = adapter->max_rx_sgl_size;
1985 static int ena_infos_get(struct rte_eth_dev *dev,
1986 struct rte_eth_dev_info *dev_info)
1988 struct ena_adapter *adapter;
1989 struct ena_com_dev *ena_dev;
1990 uint64_t rx_feat = 0, tx_feat = 0;
1992 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1993 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1994 adapter = dev->data->dev_private;
1996 ena_dev = &adapter->ena_dev;
1997 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1999 dev_info->speed_capa =
2001 ETH_LINK_SPEED_2_5G |
2003 ETH_LINK_SPEED_10G |
2004 ETH_LINK_SPEED_25G |
2005 ETH_LINK_SPEED_40G |
2006 ETH_LINK_SPEED_50G |
2007 ETH_LINK_SPEED_100G;
2009 /* Set Tx & Rx features available for device */
2010 if (adapter->offloads.tso4_supported)
2011 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2013 if (adapter->offloads.tx_csum_supported)
2014 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2015 DEV_TX_OFFLOAD_UDP_CKSUM |
2016 DEV_TX_OFFLOAD_TCP_CKSUM;
2018 if (adapter->offloads.rx_csum_supported)
2019 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2020 DEV_RX_OFFLOAD_UDP_CKSUM |
2021 DEV_RX_OFFLOAD_TCP_CKSUM;
2023 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2025 /* Inform framework about available features */
2026 dev_info->rx_offload_capa = rx_feat;
2027 dev_info->rx_queue_offload_capa = rx_feat;
2028 dev_info->tx_offload_capa = tx_feat;
2029 dev_info->tx_queue_offload_capa = tx_feat;
2031 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2034 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2035 dev_info->max_rx_pktlen = adapter->max_mtu;
2036 dev_info->max_mac_addrs = 1;
2038 dev_info->max_rx_queues = adapter->max_num_io_queues;
2039 dev_info->max_tx_queues = adapter->max_num_io_queues;
2040 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2042 adapter->tx_supported_offloads = tx_feat;
2043 adapter->rx_supported_offloads = rx_feat;
2045 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2046 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2047 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2048 adapter->max_rx_sgl_size);
2049 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2050 adapter->max_rx_sgl_size);
2052 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2053 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2054 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2055 adapter->max_tx_sgl_size);
2056 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2057 adapter->max_tx_sgl_size);
2062 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2064 mbuf->data_len = len;
2065 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2070 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2071 struct ena_com_rx_buf_info *ena_bufs,
2073 uint16_t *next_to_clean,
2076 struct rte_mbuf *mbuf;
2077 struct rte_mbuf *mbuf_head;
2078 struct ena_rx_buffer *rx_info;
2080 uint16_t ntc, len, req_id, buf = 0;
2082 if (unlikely(descs == 0))
2085 ntc = *next_to_clean;
2087 len = ena_bufs[buf].len;
2088 req_id = ena_bufs[buf].req_id;
2089 if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2092 rx_info = &rx_ring->rx_buffer_info[req_id];
2094 mbuf = rx_info->mbuf;
2095 RTE_ASSERT(mbuf != NULL);
2097 ena_init_rx_mbuf(mbuf, len);
2099 /* Fill the mbuf head with the data specific for 1st segment. */
2101 mbuf_head->nb_segs = descs;
2102 mbuf_head->port = rx_ring->port_id;
2103 mbuf_head->pkt_len = len;
2104 mbuf_head->data_off += offset;
2106 rx_info->mbuf = NULL;
2107 rx_ring->empty_rx_reqs[ntc] = req_id;
2108 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2112 len = ena_bufs[buf].len;
2113 req_id = ena_bufs[buf].req_id;
2114 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2115 rte_mbuf_raw_free(mbuf_head);
2119 rx_info = &rx_ring->rx_buffer_info[req_id];
2120 RTE_ASSERT(rx_info->mbuf != NULL);
2122 if (unlikely(len == 0)) {
2124 * Some devices can pass descriptor with the length 0.
2125 * To avoid confusion, the PMD is simply putting the
2126 * descriptor back, as it was never used. We'll avoid
2127 * mbuf allocation that way.
2129 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2130 rx_info->mbuf, req_id);
2131 if (unlikely(rc != 0)) {
2132 /* Free the mbuf in case of an error. */
2133 rte_mbuf_raw_free(rx_info->mbuf);
2136 * If there was no error, just exit the loop as
2137 * 0 length descriptor is always the last one.
2142 /* Create an mbuf chain. */
2143 mbuf->next = rx_info->mbuf;
2146 ena_init_rx_mbuf(mbuf, len);
2147 mbuf_head->pkt_len += len;
2151 * Mark the descriptor as depleted and perform necessary
2153 * This code will execute in two cases:
2154 * 1. Descriptor len was greater than 0 - normal situation.
2155 * 2. Descriptor len was 0 and we failed to add the descriptor
2156 * to the device. In that situation, we should try to add
2157 * the mbuf again in the populate routine and mark the
2158 * descriptor as used up by the device.
2160 rx_info->mbuf = NULL;
2161 rx_ring->empty_rx_reqs[ntc] = req_id;
2162 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2165 *next_to_clean = ntc;
2170 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2173 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2174 unsigned int free_queue_entries;
2175 unsigned int refill_threshold;
2176 uint16_t next_to_clean = rx_ring->next_to_clean;
2177 uint16_t descs_in_use;
2178 struct rte_mbuf *mbuf;
2180 struct ena_com_rx_ctx ena_rx_ctx;
2183 /* Check adapter state */
2184 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2186 "Trying to receive pkts while device is NOT running\n");
2190 descs_in_use = rx_ring->ring_size -
2191 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2192 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2194 for (completed = 0; completed < nb_pkts; completed++) {
2195 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2196 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2197 ena_rx_ctx.descs = 0;
2198 ena_rx_ctx.pkt_offset = 0;
2199 /* receive packet context */
2200 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2201 rx_ring->ena_com_io_sq,
2204 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2205 rx_ring->adapter->reset_reason =
2206 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2207 rx_ring->adapter->trigger_reset = true;
2208 ++rx_ring->rx_stats.bad_desc_num;
2212 mbuf = ena_rx_mbuf(rx_ring,
2213 ena_rx_ctx.ena_bufs,
2216 ena_rx_ctx.pkt_offset);
2217 if (unlikely(mbuf == NULL)) {
2218 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2219 rx_ring->empty_rx_reqs[next_to_clean] =
2220 rx_ring->ena_bufs[i].req_id;
2221 next_to_clean = ENA_IDX_NEXT_MASKED(
2222 next_to_clean, rx_ring->size_mask);
2227 /* fill mbuf attributes if any */
2228 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2230 if (unlikely(mbuf->ol_flags &
2231 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2232 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2233 ++rx_ring->rx_stats.bad_csum;
2236 mbuf->hash.rss = ena_rx_ctx.hash;
2238 rx_pkts[completed] = mbuf;
2239 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2242 rx_ring->rx_stats.cnt += completed;
2243 rx_ring->next_to_clean = next_to_clean;
2245 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2247 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2248 (unsigned int)ENA_REFILL_THRESH_PACKET);
2250 /* Burst refill to save doorbells, memory barriers, const interval */
2251 if (free_queue_entries > refill_threshold) {
2252 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2253 ena_populate_rx_queue(rx_ring, free_queue_entries);
2260 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2266 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2267 struct rte_ipv4_hdr *ip_hdr;
2269 uint16_t frag_field;
2271 for (i = 0; i != nb_pkts; i++) {
2273 ol_flags = m->ol_flags;
2275 if (!(ol_flags & PKT_TX_IPV4))
2278 /* If there was not L2 header length specified, assume it is
2279 * length of the ethernet header.
2281 if (unlikely(m->l2_len == 0))
2282 m->l2_len = sizeof(struct rte_ether_hdr);
2284 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2286 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2288 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2289 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2291 /* If IPv4 header has DF flag enabled and TSO support is
2292 * disabled, partial chcecksum should not be calculated.
2294 if (!tx_ring->adapter->offloads.tso4_supported)
2298 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2299 (ol_flags & PKT_TX_L4_MASK) ==
2300 PKT_TX_SCTP_CKSUM) {
2301 rte_errno = ENOTSUP;
2305 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2306 ret = rte_validate_tx_offload(m);
2313 /* In case we are supposed to TSO and have DF not set (DF=0)
2314 * hardware must be provided with partial checksum, otherwise
2315 * it will take care of necessary calculations.
2318 ret = rte_net_intel_cksum_flags_prepare(m,
2319 ol_flags & ~PKT_TX_TCP_SEG);
2329 static void ena_update_hints(struct ena_adapter *adapter,
2330 struct ena_admin_ena_hw_hints *hints)
2332 if (hints->admin_completion_tx_timeout)
2333 adapter->ena_dev.admin_queue.completion_timeout =
2334 hints->admin_completion_tx_timeout * 1000;
2336 if (hints->mmio_read_timeout)
2337 /* convert to usec */
2338 adapter->ena_dev.mmio_read.reg_read_to =
2339 hints->mmio_read_timeout * 1000;
2341 if (hints->driver_watchdog_timeout) {
2342 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2343 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2345 // Convert msecs to ticks
2346 adapter->keep_alive_timeout =
2347 (hints->driver_watchdog_timeout *
2348 rte_get_timer_hz()) / 1000;
2352 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2353 struct rte_mbuf *mbuf)
2355 struct ena_com_dev *ena_dev;
2356 int num_segments, header_len, rc;
2358 ena_dev = &tx_ring->adapter->ena_dev;
2359 num_segments = mbuf->nb_segs;
2360 header_len = mbuf->data_len;
2362 if (likely(num_segments < tx_ring->sgl_size))
2365 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2366 (num_segments == tx_ring->sgl_size) &&
2367 (header_len < tx_ring->tx_max_header_size))
2370 ++tx_ring->tx_stats.linearize;
2371 rc = rte_pktmbuf_linearize(mbuf);
2373 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2374 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2375 ++tx_ring->tx_stats.linearize_failed;
2382 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2383 struct ena_tx_buffer *tx_info,
2384 struct rte_mbuf *mbuf,
2386 uint16_t *header_len)
2388 struct ena_com_buf *ena_buf;
2389 uint16_t delta, seg_len, push_len;
2392 seg_len = mbuf->data_len;
2394 tx_info->mbuf = mbuf;
2395 ena_buf = tx_info->bufs;
2397 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2399 * Tx header might be (and will be in most cases) smaller than
2400 * tx_max_header_size. But it's not an issue to send more data
2401 * to the device, than actually needed if the mbuf size is
2402 * greater than tx_max_header_size.
2404 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2405 *header_len = push_len;
2407 if (likely(push_len <= seg_len)) {
2408 /* If the push header is in the single segment, then
2409 * just point it to the 1st mbuf data.
2411 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2413 /* If the push header lays in the several segments, copy
2414 * it to the intermediate buffer.
2416 rte_pktmbuf_read(mbuf, 0, push_len,
2417 tx_ring->push_buf_intermediate_buf);
2418 *push_header = tx_ring->push_buf_intermediate_buf;
2419 delta = push_len - seg_len;
2422 *push_header = NULL;
2427 /* Process first segment taking into consideration pushed header */
2428 if (seg_len > push_len) {
2429 ena_buf->paddr = mbuf->buf_iova +
2432 ena_buf->len = seg_len - push_len;
2434 tx_info->num_of_bufs++;
2437 while ((mbuf = mbuf->next) != NULL) {
2438 seg_len = mbuf->data_len;
2440 /* Skip mbufs if whole data is pushed as a header */
2441 if (unlikely(delta > seg_len)) {
2446 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2447 ena_buf->len = seg_len - delta;
2449 tx_info->num_of_bufs++;
2455 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2457 struct ena_tx_buffer *tx_info;
2458 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2459 uint16_t next_to_use;
2460 uint16_t header_len;
2466 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2470 next_to_use = tx_ring->next_to_use;
2472 req_id = tx_ring->empty_tx_reqs[next_to_use];
2473 tx_info = &tx_ring->tx_buffer_info[req_id];
2474 tx_info->num_of_bufs = 0;
2476 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2478 ena_tx_ctx.ena_bufs = tx_info->bufs;
2479 ena_tx_ctx.push_header = push_header;
2480 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2481 ena_tx_ctx.req_id = req_id;
2482 ena_tx_ctx.header_len = header_len;
2484 /* Set Tx offloads flags, if applicable */
2485 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2486 tx_ring->disable_meta_caching);
2488 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2491 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2493 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2496 /* prepare the packet's descriptors to dma engine */
2497 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2500 ++tx_ring->tx_stats.prepare_ctx_err;
2504 tx_info->tx_descs = nb_hw_desc;
2506 tx_ring->tx_stats.cnt++;
2507 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2509 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2510 tx_ring->size_mask);
2515 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2517 unsigned int cleanup_budget;
2518 unsigned int total_tx_descs = 0;
2519 uint16_t next_to_clean = tx_ring->next_to_clean;
2521 cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2522 (unsigned int)ENA_REFILL_THRESH_PACKET);
2524 while (likely(total_tx_descs < cleanup_budget)) {
2525 struct rte_mbuf *mbuf;
2526 struct ena_tx_buffer *tx_info;
2529 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2532 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2535 /* Get Tx info & store how many descs were processed */
2536 tx_info = &tx_ring->tx_buffer_info[req_id];
2538 mbuf = tx_info->mbuf;
2539 rte_pktmbuf_free(mbuf);
2541 tx_info->mbuf = NULL;
2542 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2544 total_tx_descs += tx_info->tx_descs;
2546 /* Put back descriptor to the ring for reuse */
2547 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2548 tx_ring->size_mask);
2551 if (likely(total_tx_descs > 0)) {
2552 /* acknowledge completion of sent packets */
2553 tx_ring->next_to_clean = next_to_clean;
2554 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2555 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2559 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2562 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2563 uint16_t sent_idx = 0;
2565 /* Check adapter state */
2566 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2568 "Trying to xmit pkts while device is NOT running\n");
2572 nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2575 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2576 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2579 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2580 tx_ring->size_mask)]);
2583 tx_ring->tx_stats.available_desc =
2584 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2586 /* If there are ready packets to be xmitted... */
2588 /* ...let HW do its best :-) */
2589 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2590 tx_ring->tx_stats.doorbells++;
2593 ena_tx_cleanup(tx_ring);
2595 tx_ring->tx_stats.available_desc =
2596 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2597 tx_ring->tx_stats.tx_poll++;
2603 * DPDK callback to retrieve names of extended device statistics
2606 * Pointer to Ethernet device structure.
2607 * @param[out] xstats_names
2608 * Buffer to insert names into.
2613 * Number of xstats names.
2615 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2616 struct rte_eth_xstat_name *xstats_names,
2619 unsigned int xstats_count = ena_xstats_calc_num(dev);
2620 unsigned int stat, i, count = 0;
2622 if (n < xstats_count || !xstats_names)
2623 return xstats_count;
2625 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2626 strcpy(xstats_names[count].name,
2627 ena_stats_global_strings[stat].name);
2629 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2630 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2631 snprintf(xstats_names[count].name,
2632 sizeof(xstats_names[count].name),
2634 ena_stats_rx_strings[stat].name);
2636 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2637 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2638 snprintf(xstats_names[count].name,
2639 sizeof(xstats_names[count].name),
2641 ena_stats_tx_strings[stat].name);
2643 return xstats_count;
2647 * DPDK callback to get extended device statistics.
2650 * Pointer to Ethernet device structure.
2652 * Stats table output buffer.
2654 * The size of the stats table.
2657 * Number of xstats on success, negative on failure.
2659 static int ena_xstats_get(struct rte_eth_dev *dev,
2660 struct rte_eth_xstat *xstats,
2663 struct ena_adapter *adapter = dev->data->dev_private;
2664 unsigned int xstats_count = ena_xstats_calc_num(dev);
2665 unsigned int stat, i, count = 0;
2669 if (n < xstats_count)
2670 return xstats_count;
2675 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2676 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2677 stats_begin = &adapter->dev_stats;
2679 xstats[count].id = count;
2680 xstats[count].value = *((uint64_t *)
2681 ((char *)stats_begin + stat_offset));
2684 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2685 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2686 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2687 stats_begin = &adapter->rx_ring[i].rx_stats;
2689 xstats[count].id = count;
2690 xstats[count].value = *((uint64_t *)
2691 ((char *)stats_begin + stat_offset));
2695 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2696 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2697 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2698 stats_begin = &adapter->tx_ring[i].rx_stats;
2700 xstats[count].id = count;
2701 xstats[count].value = *((uint64_t *)
2702 ((char *)stats_begin + stat_offset));
2709 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2710 const uint64_t *ids,
2714 struct ena_adapter *adapter = dev->data->dev_private;
2716 uint64_t rx_entries, tx_entries;
2720 for (i = 0; i < n; ++i) {
2722 /* Check if id belongs to global statistics */
2723 if (id < ENA_STATS_ARRAY_GLOBAL) {
2724 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2729 /* Check if id belongs to rx queue statistics */
2730 id -= ENA_STATS_ARRAY_GLOBAL;
2731 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2732 if (id < rx_entries) {
2733 qid = id % dev->data->nb_rx_queues;
2734 id /= dev->data->nb_rx_queues;
2735 values[i] = *((uint64_t *)
2736 &adapter->rx_ring[qid].rx_stats + id);
2740 /* Check if id belongs to rx queue statistics */
2742 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2743 if (id < tx_entries) {
2744 qid = id % dev->data->nb_tx_queues;
2745 id /= dev->data->nb_tx_queues;
2746 values[i] = *((uint64_t *)
2747 &adapter->tx_ring[qid].tx_stats + id);
2756 static int ena_process_bool_devarg(const char *key,
2760 struct ena_adapter *adapter = opaque;
2763 /* Parse the value. */
2764 if (strcmp(value, "1") == 0) {
2766 } else if (strcmp(value, "0") == 0) {
2770 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2775 /* Now, assign it to the proper adapter field. */
2776 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2777 adapter->use_large_llq_hdr = bool_value;
2782 static int ena_parse_devargs(struct ena_adapter *adapter,
2783 struct rte_devargs *devargs)
2785 static const char * const allowed_args[] = {
2786 ENA_DEVARG_LARGE_LLQ_HDR,
2788 struct rte_kvargs *kvlist;
2791 if (devargs == NULL)
2794 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2795 if (kvlist == NULL) {
2796 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2801 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2802 ena_process_bool_devarg, adapter);
2804 rte_kvargs_free(kvlist);
2809 /*********************************************************************
2811 *********************************************************************/
2812 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2813 struct rte_pci_device *pci_dev)
2815 return rte_eth_dev_pci_generic_probe(pci_dev,
2816 sizeof(struct ena_adapter), eth_ena_dev_init);
2819 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2821 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2824 static struct rte_pci_driver rte_ena_pmd = {
2825 .id_table = pci_id_ena_map,
2826 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2827 RTE_PCI_DRV_WC_ACTIVATE,
2828 .probe = eth_ena_pci_probe,
2829 .remove = eth_ena_pci_remove,
2832 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2833 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2834 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2835 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2836 RTE_LOG_REGISTER(ena_logtype_init, pmd.net.ena.init, NOTICE);
2837 RTE_LOG_REGISTER(ena_logtype_driver, pmd.net.ena.driver, NOTICE);
2838 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2839 RTE_LOG_REGISTER(ena_logtype_rx, pmd.net.ena.rx, NOTICE);
2841 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2842 RTE_LOG_REGISTER(ena_logtype_tx, pmd.net.ena.tx, NOTICE);
2844 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2845 RTE_LOG_REGISTER(ena_logtype_tx_free, pmd.net.ena.tx_free, NOTICE);
2847 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2848 RTE_LOG_REGISTER(ena_logtype_com, pmd.net.ena.com, NOTICE);
2851 /******************************************************************************
2852 ******************************** AENQ Handlers *******************************
2853 *****************************************************************************/
2854 static void ena_update_on_link_change(void *adapter_data,
2855 struct ena_admin_aenq_entry *aenq_e)
2857 struct rte_eth_dev *eth_dev;
2858 struct ena_adapter *adapter;
2859 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2862 adapter = adapter_data;
2863 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2864 eth_dev = adapter->rte_dev;
2866 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2867 adapter->link_status = status;
2869 ena_link_update(eth_dev, 0);
2870 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2873 static void ena_notification(void *data,
2874 struct ena_admin_aenq_entry *aenq_e)
2876 struct ena_adapter *adapter = data;
2877 struct ena_admin_ena_hw_hints *hints;
2879 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2880 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2881 aenq_e->aenq_common_desc.group,
2882 ENA_ADMIN_NOTIFICATION);
2884 switch (aenq_e->aenq_common_desc.syndrom) {
2885 case ENA_ADMIN_UPDATE_HINTS:
2886 hints = (struct ena_admin_ena_hw_hints *)
2887 (&aenq_e->inline_data_w4);
2888 ena_update_hints(adapter, hints);
2891 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2892 aenq_e->aenq_common_desc.syndrom);
2896 static void ena_keep_alive(void *adapter_data,
2897 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2899 struct ena_adapter *adapter = adapter_data;
2900 struct ena_admin_aenq_keep_alive_desc *desc;
2904 adapter->timestamp_wd = rte_get_timer_cycles();
2906 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2907 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2908 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2910 adapter->drv_stats->rx_drops = rx_drops;
2911 adapter->dev_stats.tx_drops = tx_drops;
2915 * This handler will called for unknown event group or unimplemented handlers
2917 static void unimplemented_aenq_handler(__rte_unused void *data,
2918 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2920 PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2921 "unimplemented handler\n");
2924 static struct ena_aenq_handlers aenq_handlers = {
2926 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2927 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2928 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2930 .unimplemented_handler = unimplemented_aenq_handler