drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    5
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 enum ethtool_stringset {
  42         ETH_SS_TEST             = 0,
  43         ETH_SS_STATS,
  44 };
  45
  46 struct ena_stats {
  47         char name[ETH_GSTRING_LEN];
  48         int stat_offset;
  49 };
  50
  51 #define ENA_STAT_ENTRY(stat, stat_type) { \
  52         .name = #stat, \
  53         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  54 }
  55
  56 #define ENA_STAT_RX_ENTRY(stat) \
  57         ENA_STAT_ENTRY(stat, rx)
  58
  59 #define ENA_STAT_TX_ENTRY(stat) \
  60         ENA_STAT_ENTRY(stat, tx)
  61
  62 #define ENA_STAT_ENI_ENTRY(stat) \
  63         ENA_STAT_ENTRY(stat, eni)
  64
  65 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  66         ENA_STAT_ENTRY(stat, dev)
  67
  68 /* Device arguments */
  69 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  70
  71 /*
  72  * Each rte_memzone should have unique name.
  73  * To satisfy it, count number of allocation and add it to name.
  74  */
  75 rte_atomic64_t ena_alloc_cnt;
  76
  77 static const struct ena_stats ena_stats_global_strings[] = {
  78         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  79         ENA_STAT_GLOBAL_ENTRY(dev_start),
  80         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  81         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  82 };
  83
  84 static const struct ena_stats ena_stats_eni_strings[] = {
  85         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  86         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  87         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  88         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  89         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  90 };
  91
  92 static const struct ena_stats ena_stats_tx_strings[] = {
  93         ENA_STAT_TX_ENTRY(cnt),
  94         ENA_STAT_TX_ENTRY(bytes),
  95         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  96         ENA_STAT_TX_ENTRY(tx_poll),
  97         ENA_STAT_TX_ENTRY(doorbells),
  98         ENA_STAT_TX_ENTRY(bad_req_id),
  99         ENA_STAT_TX_ENTRY(available_desc),
 100         ENA_STAT_TX_ENTRY(missed_tx),
 101 };
 102
 103 static const struct ena_stats ena_stats_rx_strings[] = {
 104         ENA_STAT_RX_ENTRY(cnt),
 105         ENA_STAT_RX_ENTRY(bytes),
 106         ENA_STAT_RX_ENTRY(refill_partial),
 107         ENA_STAT_RX_ENTRY(bad_csum),
 108         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 109         ENA_STAT_RX_ENTRY(bad_desc_num),
 110         ENA_STAT_RX_ENTRY(bad_req_id),
 111 };
 112
 113 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 114 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 115 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 116 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 117
 118 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
 119                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
 120                         RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
 121                         RTE_ETH_TX_OFFLOAD_TCP_TSO)
 122 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
 123                        RTE_MBUF_F_TX_IP_CKSUM |\
 124                        RTE_MBUF_F_TX_TCP_SEG)
 125
 126 /** Vendor ID used by Amazon devices */
 127 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 128 /** Amazon devices */
 129 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 130 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 131
 132 #define ENA_TX_OFFLOAD_MASK     (RTE_MBUF_F_TX_L4_MASK |         \
 133         RTE_MBUF_F_TX_IPV6 |            \
 134         RTE_MBUF_F_TX_IPV4 |            \
 135         RTE_MBUF_F_TX_IP_CKSUM |        \
 136         RTE_MBUF_F_TX_TCP_SEG)
 137
 138 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 139         (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 140
 141 /** HW specific offloads capabilities. */
 142 /* IPv4 checksum offload. */
 143 #define ENA_L3_IPV4_CSUM                0x0001
 144 /* TCP/UDP checksum offload for IPv4 packets. */
 145 #define ENA_L4_IPV4_CSUM                0x0002
 146 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 147 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 148 /* TCP/UDP checksum offload for IPv6 packets. */
 149 #define ENA_L4_IPV6_CSUM                0x0008
 150 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 151 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 152 /* TSO support for IPv4 packets. */
 153 #define ENA_IPV4_TSO                    0x0020
 154
 155 /* Device supports setting RSS hash. */
 156 #define ENA_RX_RSS_HASH                 0x0040
 157
 158 static const struct rte_pci_id pci_id_ena_map[] = {
 159         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 160         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 161         { .device_id = 0 },
 162 };
 163
 164 static struct ena_aenq_handlers aenq_handlers;
 165
 166 static int ena_device_init(struct ena_com_dev *ena_dev,
 167                            struct rte_pci_device *pdev,
 168                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 169                            bool *wd_state);
 170 static int ena_dev_configure(struct rte_eth_dev *dev);
 171 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 172         struct ena_tx_buffer *tx_info,
 173         struct rte_mbuf *mbuf,
 174         void **push_header,
 175         uint16_t *header_len);
 176 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 177 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 179                                   uint16_t nb_pkts);
 180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                 uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 190 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 191                                     struct ena_com_rx_buf_info *ena_bufs,
 192                                     uint32_t descs,
 193                                     uint16_t *next_to_clean,
 194                                     uint8_t offset);
 195 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 196                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 197 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 198                                   struct rte_mbuf *mbuf, uint16_t id);
 199 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 200 static void ena_init_rings(struct ena_adapter *adapter,
 201                            bool disable_meta_caching);
 202 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 203 static int ena_start(struct rte_eth_dev *dev);
 204 static int ena_stop(struct rte_eth_dev *dev);
 205 static int ena_close(struct rte_eth_dev *dev);
 206 static int ena_dev_reset(struct rte_eth_dev *dev);
 207 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 208 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 209 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 211 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 212 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 213 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 214 static int ena_link_update(struct rte_eth_dev *dev,
 215                            int wait_to_complete);
 216 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 217 static void ena_queue_stop(struct ena_ring *ring);
 218 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 219                               enum ena_ring_type ring_type);
 220 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 221 static int ena_queue_start_all(struct rte_eth_dev *dev,
 222                                enum ena_ring_type ring_type);
 223 static void ena_stats_restart(struct rte_eth_dev *dev);
 224 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 225 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 226 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 227 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 228 static int ena_infos_get(struct rte_eth_dev *dev,
 229                          struct rte_eth_dev_info *dev_info);
 230 static void ena_interrupt_handler_rte(void *cb_arg);
 231 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 232 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 233 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 234 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 235                                 struct rte_eth_xstat_name *xstats_names,
 236                                 unsigned int n);
 237 static int ena_xstats_get(struct rte_eth_dev *dev,
 238                           struct rte_eth_xstat *stats,
 239                           unsigned int n);
 240 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 241                                 const uint64_t *ids,
 242                                 uint64_t *values,
 243                                 unsigned int n);
 244 static int ena_process_bool_devarg(const char *key,
 245                                    const char *value,
 246                                    void *opaque);
 247 static int ena_parse_devargs(struct ena_adapter *adapter,
 248                              struct rte_devargs *devargs);
 249 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 250 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 251 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                     uint16_t queue_id);
 253 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                      uint16_t queue_id);
 255
 256 static const struct eth_dev_ops ena_dev_ops = {
 257         .dev_configure        = ena_dev_configure,
 258         .dev_infos_get        = ena_infos_get,
 259         .rx_queue_setup       = ena_rx_queue_setup,
 260         .tx_queue_setup       = ena_tx_queue_setup,
 261         .dev_start            = ena_start,
 262         .dev_stop             = ena_stop,
 263         .link_update          = ena_link_update,
 264         .stats_get            = ena_stats_get,
 265         .xstats_get_names     = ena_xstats_get_names,
 266         .xstats_get           = ena_xstats_get,
 267         .xstats_get_by_id     = ena_xstats_get_by_id,
 268         .mtu_set              = ena_mtu_set,
 269         .rx_queue_release     = ena_rx_queue_release,
 270         .tx_queue_release     = ena_tx_queue_release,
 271         .dev_close            = ena_close,
 272         .dev_reset            = ena_dev_reset,
 273         .reta_update          = ena_rss_reta_update,
 274         .reta_query           = ena_rss_reta_query,
 275         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 276         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 277         .rss_hash_update      = ena_rss_hash_update,
 278         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 279 };
 280
 281 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 282                                        struct ena_com_rx_ctx *ena_rx_ctx,
 283                                        bool fill_hash)
 284 {
 285         uint64_t ol_flags = 0;
 286         uint32_t packet_type = 0;
 287
 288         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 289                 packet_type |= RTE_PTYPE_L4_TCP;
 290         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 291                 packet_type |= RTE_PTYPE_L4_UDP;
 292
 293         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 294                 packet_type |= RTE_PTYPE_L3_IPV4;
 295                 if (unlikely(ena_rx_ctx->l3_csum_err))
 296                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 297                 else
 298                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 299         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 300                 packet_type |= RTE_PTYPE_L3_IPV6;
 301         }
 302
 303         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 304                 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
 305         else
 306                 if (unlikely(ena_rx_ctx->l4_csum_err))
 307                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 308                 else
 309                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 310
 311         if (fill_hash &&
 312             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 313                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 314                 mbuf->hash.rss = ena_rx_ctx->hash;
 315         }
 316
 317         mbuf->ol_flags = ol_flags;
 318         mbuf->packet_type = packet_type;
 319 }
 320
 321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 322                                        struct ena_com_tx_ctx *ena_tx_ctx,
 323                                        uint64_t queue_offloads,
 324                                        bool disable_meta_caching)
 325 {
 326         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 327
 328         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 329             (queue_offloads & QUEUE_OFFLOADS)) {
 330                 /* check if TSO is required */
 331                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
 332                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
 333                         ena_tx_ctx->tso_enable = true;
 334
 335                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 336                 }
 337
 338                 /* check if L3 checksum is needed */
 339                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
 340                     (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
 341                         ena_tx_ctx->l3_csum_enable = true;
 342
 343                 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
 344                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 345                 } else {
 346                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 347
 348                         /* set don't fragment (DF) flag */
 349                         if (mbuf->packet_type &
 350                                 (RTE_PTYPE_L4_NONFRAG
 351                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 352                                 ena_tx_ctx->df = true;
 353                 }
 354
 355                 /* check if L4 checksum is needed */
 356                 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
 357                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
 358                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 359                         ena_tx_ctx->l4_csum_enable = true;
 360                 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
 361                                 RTE_MBUF_F_TX_UDP_CKSUM) &&
 362                                 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else {
 366                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 367                         ena_tx_ctx->l4_csum_enable = false;
 368                 }
 369
 370                 ena_meta->mss = mbuf->tso_segsz;
 371                 ena_meta->l3_hdr_len = mbuf->l3_len;
 372                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 373
 374                 ena_tx_ctx->meta_valid = true;
 375         } else if (disable_meta_caching) {
 376                 memset(ena_meta, 0, sizeof(*ena_meta));
 377                 ena_tx_ctx->meta_valid = true;
 378         } else {
 379                 ena_tx_ctx->meta_valid = false;
 380         }
 381 }
 382
 383 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 384 {
 385         struct ena_tx_buffer *tx_info = NULL;
 386
 387         if (likely(req_id < tx_ring->ring_size)) {
 388                 tx_info = &tx_ring->tx_buffer_info[req_id];
 389                 if (likely(tx_info->mbuf))
 390                         return 0;
 391         }
 392
 393         if (tx_info)
 394                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 395         else
 396                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 397
 398         /* Trigger device reset */
 399         ++tx_ring->tx_stats.bad_req_id;
 400         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 401         tx_ring->adapter->trigger_reset = true;
 402         return -EFAULT;
 403 }
 404
 405 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 406 {
 407         struct ena_admin_host_info *host_info;
 408         int rc;
 409
 410         /* Allocate only the host info */
 411         rc = ena_com_allocate_host_info(ena_dev);
 412         if (rc) {
 413                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 414                 return;
 415         }
 416
 417         host_info = ena_dev->host_attr.host_info;
 418
 419         host_info->os_type = ENA_ADMIN_OS_DPDK;
 420         host_info->kernel_ver = RTE_VERSION;
 421         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 422                 sizeof(host_info->kernel_ver_str));
 423         host_info->os_dist = RTE_VERSION;
 424         strlcpy((char *)host_info->os_dist_str, rte_version(),
 425                 sizeof(host_info->os_dist_str));
 426         host_info->driver_version =
 427                 (DRV_MODULE_VER_MAJOR) |
 428                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 429                 (DRV_MODULE_VER_SUBMINOR <<
 430                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 431         host_info->num_cpus = rte_lcore_count();
 432
 433         host_info->driver_supported_features =
 434                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 435                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 436
 437         rc = ena_com_set_host_attributes(ena_dev);
 438         if (rc) {
 439                 if (rc == -ENA_COM_UNSUPPORTED)
 440                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 441                 else
 442                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 443
 444                 goto err;
 445         }
 446
 447         return;
 448
 449 err:
 450         ena_com_delete_host_info(ena_dev);
 451 }
 452
 453 /* This function calculates the number of xstats based on the current config */
 454 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 455 {
 456         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 457                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 458                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 459 }
 460
 461 static void ena_config_debug_area(struct ena_adapter *adapter)
 462 {
 463         u32 debug_area_size;
 464         int rc, ss_count;
 465
 466         ss_count = ena_xstats_calc_num(adapter->edev_data);
 467
 468         /* allocate 32 bytes for each string and 64bit for the value */
 469         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 470
 471         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 472         if (rc) {
 473                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 474                 return;
 475         }
 476
 477         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 478         if (rc) {
 479                 if (rc == -ENA_COM_UNSUPPORTED)
 480                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 481                 else
 482                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 483
 484                 goto err;
 485         }
 486
 487         return;
 488 err:
 489         ena_com_delete_debug_area(&adapter->ena_dev);
 490 }
 491
 492 static int ena_close(struct rte_eth_dev *dev)
 493 {
 494         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 495         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 496         struct ena_adapter *adapter = dev->data->dev_private;
 497         int ret = 0;
 498
 499         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 500                 return 0;
 501
 502         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 503                 ret = ena_stop(dev);
 504         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 505
 506         ena_rx_queue_release_all(dev);
 507         ena_tx_queue_release_all(dev);
 508
 509         rte_free(adapter->drv_stats);
 510         adapter->drv_stats = NULL;
 511
 512         rte_intr_disable(intr_handle);
 513         rte_intr_callback_unregister(intr_handle,
 514                                      ena_interrupt_handler_rte,
 515                                      dev);
 516
 517         /*
 518          * MAC is not allocated dynamically. Setting NULL should prevent from
 519          * release of the resource in the rte_eth_dev_release_port().
 520          */
 521         dev->data->mac_addrs = NULL;
 522
 523         return ret;
 524 }
 525
 526 static int
 527 ena_dev_reset(struct rte_eth_dev *dev)
 528 {
 529         int rc = 0;
 530
 531         /* Cannot release memory in secondary process */
 532         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 533                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 534                 return -EPERM;
 535         }
 536
 537         ena_destroy_device(dev);
 538         rc = eth_ena_dev_init(dev);
 539         if (rc)
 540                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 541
 542         return rc;
 543 }
 544
 545 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 546 {
 547         int nb_queues = dev->data->nb_rx_queues;
 548         int i;
 549
 550         for (i = 0; i < nb_queues; i++)
 551                 ena_rx_queue_release(dev, i);
 552 }
 553
 554 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 555 {
 556         int nb_queues = dev->data->nb_tx_queues;
 557         int i;
 558
 559         for (i = 0; i < nb_queues; i++)
 560                 ena_tx_queue_release(dev, i);
 561 }
 562
 563 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 564 {
 565         struct ena_ring *ring = dev->data->rx_queues[qid];
 566
 567         /* Free ring resources */
 568         rte_free(ring->rx_buffer_info);
 569         ring->rx_buffer_info = NULL;
 570
 571         rte_free(ring->rx_refill_buffer);
 572         ring->rx_refill_buffer = NULL;
 573
 574         rte_free(ring->empty_rx_reqs);
 575         ring->empty_rx_reqs = NULL;
 576
 577         ring->configured = 0;
 578
 579         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 580                 ring->port_id, ring->id);
 581 }
 582
 583 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 584 {
 585         struct ena_ring *ring = dev->data->tx_queues[qid];
 586
 587         /* Free ring resources */
 588         rte_free(ring->push_buf_intermediate_buf);
 589
 590         rte_free(ring->tx_buffer_info);
 591
 592         rte_free(ring->empty_tx_reqs);
 593
 594         ring->empty_tx_reqs = NULL;
 595         ring->tx_buffer_info = NULL;
 596         ring->push_buf_intermediate_buf = NULL;
 597
 598         ring->configured = 0;
 599
 600         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 601                 ring->port_id, ring->id);
 602 }
 603
 604 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 605 {
 606         unsigned int i;
 607
 608         for (i = 0; i < ring->ring_size; ++i) {
 609                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 610                 if (rx_info->mbuf) {
 611                         rte_mbuf_raw_free(rx_info->mbuf);
 612                         rx_info->mbuf = NULL;
 613                 }
 614         }
 615 }
 616
 617 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 618 {
 619         unsigned int i;
 620
 621         for (i = 0; i < ring->ring_size; ++i) {
 622                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 623
 624                 if (tx_buf->mbuf) {
 625                         rte_pktmbuf_free(tx_buf->mbuf);
 626                         tx_buf->mbuf = NULL;
 627                 }
 628         }
 629 }
 630
 631 static int ena_link_update(struct rte_eth_dev *dev,
 632                            __rte_unused int wait_to_complete)
 633 {
 634         struct rte_eth_link *link = &dev->data->dev_link;
 635         struct ena_adapter *adapter = dev->data->dev_private;
 636
 637         link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
 638         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
 639         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 640
 641         return 0;
 642 }
 643
 644 static int ena_queue_start_all(struct rte_eth_dev *dev,
 645                                enum ena_ring_type ring_type)
 646 {
 647         struct ena_adapter *adapter = dev->data->dev_private;
 648         struct ena_ring *queues = NULL;
 649         int nb_queues;
 650         int i = 0;
 651         int rc = 0;
 652
 653         if (ring_type == ENA_RING_TYPE_RX) {
 654                 queues = adapter->rx_ring;
 655                 nb_queues = dev->data->nb_rx_queues;
 656         } else {
 657                 queues = adapter->tx_ring;
 658                 nb_queues = dev->data->nb_tx_queues;
 659         }
 660         for (i = 0; i < nb_queues; i++) {
 661                 if (queues[i].configured) {
 662                         if (ring_type == ENA_RING_TYPE_RX) {
 663                                 ena_assert_msg(
 664                                         dev->data->rx_queues[i] == &queues[i],
 665                                         "Inconsistent state of Rx queues\n");
 666                         } else {
 667                                 ena_assert_msg(
 668                                         dev->data->tx_queues[i] == &queues[i],
 669                                         "Inconsistent state of Tx queues\n");
 670                         }
 671
 672                         rc = ena_queue_start(dev, &queues[i]);
 673
 674                         if (rc) {
 675                                 PMD_INIT_LOG(ERR,
 676                                         "Failed to start queue[%d] of type(%d)\n",
 677                                         i, ring_type);
 678                                 goto err;
 679                         }
 680                 }
 681         }
 682
 683         return 0;
 684
 685 err:
 686         while (i--)
 687                 if (queues[i].configured)
 688                         ena_queue_stop(&queues[i]);
 689
 690         return rc;
 691 }
 692
 693 static int ena_check_valid_conf(struct ena_adapter *adapter)
 694 {
 695         uint32_t mtu = adapter->edev_data->mtu;
 696
 697         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 698                 PMD_INIT_LOG(ERR,
 699                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 700                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 701                 return ENA_COM_UNSUPPORTED;
 702         }
 703
 704         return 0;
 705 }
 706
 707 static int
 708 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 709                        bool use_large_llq_hdr)
 710 {
 711         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 712         struct ena_com_dev *ena_dev = ctx->ena_dev;
 713         uint32_t max_tx_queue_size;
 714         uint32_t max_rx_queue_size;
 715
 716         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 717                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 718                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 719                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 720                         max_queue_ext->max_rx_sq_depth);
 721                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 722
 723                 if (ena_dev->tx_mem_queue_type ==
 724                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 725                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 726                                 llq->max_llq_depth);
 727                 } else {
 728                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 729                                 max_queue_ext->max_tx_sq_depth);
 730                 }
 731
 732                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 733                         max_queue_ext->max_per_packet_rx_descs);
 734                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 735                         max_queue_ext->max_per_packet_tx_descs);
 736         } else {
 737                 struct ena_admin_queue_feature_desc *max_queues =
 738                         &ctx->get_feat_ctx->max_queues;
 739                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 740                         max_queues->max_sq_depth);
 741                 max_tx_queue_size = max_queues->max_cq_depth;
 742
 743                 if (ena_dev->tx_mem_queue_type ==
 744                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 745                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 746                                 llq->max_llq_depth);
 747                 } else {
 748                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 749                                 max_queues->max_sq_depth);
 750                 }
 751
 752                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 753                         max_queues->max_packet_rx_descs);
 754                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 755                         max_queues->max_packet_tx_descs);
 756         }
 757
 758         /* Round down to the nearest power of 2 */
 759         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 760         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 761
 762         if (use_large_llq_hdr) {
 763                 if ((llq->entry_size_ctrl_supported &
 764                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 765                     (ena_dev->tx_mem_queue_type ==
 766                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 767                         max_tx_queue_size /= 2;
 768                         PMD_INIT_LOG(INFO,
 769                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
 770                                 max_tx_queue_size);
 771                 } else {
 772                         PMD_INIT_LOG(ERR,
 773                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 774                 }
 775         }
 776
 777         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 778                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 779                 return -EFAULT;
 780         }
 781
 782         ctx->max_tx_queue_size = max_tx_queue_size;
 783         ctx->max_rx_queue_size = max_rx_queue_size;
 784
 785         return 0;
 786 }
 787
 788 static void ena_stats_restart(struct rte_eth_dev *dev)
 789 {
 790         struct ena_adapter *adapter = dev->data->dev_private;
 791
 792         rte_atomic64_init(&adapter->drv_stats->ierrors);
 793         rte_atomic64_init(&adapter->drv_stats->oerrors);
 794         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 795         adapter->drv_stats->rx_drops = 0;
 796 }
 797
 798 static int ena_stats_get(struct rte_eth_dev *dev,
 799                           struct rte_eth_stats *stats)
 800 {
 801         struct ena_admin_basic_stats ena_stats;
 802         struct ena_adapter *adapter = dev->data->dev_private;
 803         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 804         int rc;
 805         int i;
 806         int max_rings_stats;
 807
 808         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 809                 return -ENOTSUP;
 810
 811         memset(&ena_stats, 0, sizeof(ena_stats));
 812
 813         rte_spinlock_lock(&adapter->admin_lock);
 814         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 815         rte_spinlock_unlock(&adapter->admin_lock);
 816         if (unlikely(rc)) {
 817                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 818                 return rc;
 819         }
 820
 821         /* Set of basic statistics from ENA */
 822         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 823                                           ena_stats.rx_pkts_low);
 824         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 825                                           ena_stats.tx_pkts_low);
 826         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 827                                         ena_stats.rx_bytes_low);
 828         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 829                                         ena_stats.tx_bytes_low);
 830
 831         /* Driver related stats */
 832         stats->imissed = adapter->drv_stats->rx_drops;
 833         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 834         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 835         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 836
 837         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 838                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 839         for (i = 0; i < max_rings_stats; ++i) {
 840                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 841
 842                 stats->q_ibytes[i] = rx_stats->bytes;
 843                 stats->q_ipackets[i] = rx_stats->cnt;
 844                 stats->q_errors[i] = rx_stats->bad_desc_num +
 845                         rx_stats->bad_req_id;
 846         }
 847
 848         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 849                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 850         for (i = 0; i < max_rings_stats; ++i) {
 851                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 852
 853                 stats->q_obytes[i] = tx_stats->bytes;
 854                 stats->q_opackets[i] = tx_stats->cnt;
 855         }
 856
 857         return 0;
 858 }
 859
 860 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 861 {
 862         struct ena_adapter *adapter;
 863         struct ena_com_dev *ena_dev;
 864         int rc = 0;
 865
 866         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 867         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 868         adapter = dev->data->dev_private;
 869
 870         ena_dev = &adapter->ena_dev;
 871         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 872
 873         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 874                 PMD_DRV_LOG(ERR,
 875                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
 876                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 877                 return -EINVAL;
 878         }
 879
 880         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 881         if (rc)
 882                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 883         else
 884                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
 885
 886         return rc;
 887 }
 888
 889 static int ena_start(struct rte_eth_dev *dev)
 890 {
 891         struct ena_adapter *adapter = dev->data->dev_private;
 892         uint64_t ticks;
 893         int rc = 0;
 894
 895         /* Cannot allocate memory in secondary process */
 896         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 897                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
 898                 return -EPERM;
 899         }
 900
 901         rc = ena_check_valid_conf(adapter);
 902         if (rc)
 903                 return rc;
 904
 905         rc = ena_setup_rx_intr(dev);
 906         if (rc)
 907                 return rc;
 908
 909         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
 910         if (rc)
 911                 return rc;
 912
 913         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
 914         if (rc)
 915                 goto err_start_tx;
 916
 917         if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 918                 rc = ena_rss_configure(adapter);
 919                 if (rc)
 920                         goto err_rss_init;
 921         }
 922
 923         ena_stats_restart(dev);
 924
 925         adapter->timestamp_wd = rte_get_timer_cycles();
 926         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
 927
 928         ticks = rte_get_timer_hz();
 929         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
 930                         ena_timer_wd_callback, dev);
 931
 932         ++adapter->dev_stats.dev_start;
 933         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 934
 935         return 0;
 936
 937 err_rss_init:
 938         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 939 err_start_tx:
 940         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 941         return rc;
 942 }
 943
 944 static int ena_stop(struct rte_eth_dev *dev)
 945 {
 946         struct ena_adapter *adapter = dev->data->dev_private;
 947         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 948         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 949         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 950         int rc;
 951
 952         /* Cannot free memory in secondary process */
 953         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 954                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
 955                 return -EPERM;
 956         }
 957
 958         rte_timer_stop_sync(&adapter->timer_wd);
 959         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 960         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 961
 962         if (adapter->trigger_reset) {
 963                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 964                 if (rc)
 965                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
 966         }
 967
 968         rte_intr_disable(intr_handle);
 969
 970         rte_intr_efd_disable(intr_handle);
 971
 972         /* Cleanup vector list */
 973         rte_intr_vec_list_free(intr_handle);
 974
 975         rte_intr_enable(intr_handle);
 976
 977         ++adapter->dev_stats.dev_stop;
 978         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 979         dev->data->dev_started = 0;
 980
 981         return 0;
 982 }
 983
 984 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
 985 {
 986         struct ena_adapter *adapter = ring->adapter;
 987         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 988         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 989         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 990         struct ena_com_create_io_ctx ctx =
 991                 /* policy set to _HOST just to satisfy icc compiler */
 992                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 993                   0, 0, 0, 0, 0 };
 994         uint16_t ena_qid;
 995         unsigned int i;
 996         int rc;
 997
 998         ctx.msix_vector = -1;
 999         if (ring->type == ENA_RING_TYPE_TX) {
1000                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1001                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1002                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1003                 for (i = 0; i < ring->ring_size; i++)
1004                         ring->empty_tx_reqs[i] = i;
1005         } else {
1006                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1007                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1008                 if (rte_intr_dp_is_en(intr_handle))
1009                         ctx.msix_vector =
1010                                 rte_intr_vec_list_index_get(intr_handle,
1011                                                                    ring->id);
1012
1013                 for (i = 0; i < ring->ring_size; i++)
1014                         ring->empty_rx_reqs[i] = i;
1015         }
1016         ctx.queue_size = ring->ring_size;
1017         ctx.qid = ena_qid;
1018         ctx.numa_node = ring->numa_socket_id;
1019
1020         rc = ena_com_create_io_queue(ena_dev, &ctx);
1021         if (rc) {
1022                 PMD_DRV_LOG(ERR,
1023                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1024                         ring->id, ena_qid, rc);
1025                 return rc;
1026         }
1027
1028         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1029                                      &ring->ena_com_io_sq,
1030                                      &ring->ena_com_io_cq);
1031         if (rc) {
1032                 PMD_DRV_LOG(ERR,
1033                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1034                         ring->id, rc);
1035                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1036                 return rc;
1037         }
1038
1039         if (ring->type == ENA_RING_TYPE_TX)
1040                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1041
1042         /* Start with Rx interrupts being masked. */
1043         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1044                 ena_rx_queue_intr_disable(dev, ring->id);
1045
1046         return 0;
1047 }
1048
1049 static void ena_queue_stop(struct ena_ring *ring)
1050 {
1051         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1052
1053         if (ring->type == ENA_RING_TYPE_RX) {
1054                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1055                 ena_rx_queue_release_bufs(ring);
1056         } else {
1057                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1058                 ena_tx_queue_release_bufs(ring);
1059         }
1060 }
1061
1062 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1063                               enum ena_ring_type ring_type)
1064 {
1065         struct ena_adapter *adapter = dev->data->dev_private;
1066         struct ena_ring *queues = NULL;
1067         uint16_t nb_queues, i;
1068
1069         if (ring_type == ENA_RING_TYPE_RX) {
1070                 queues = adapter->rx_ring;
1071                 nb_queues = dev->data->nb_rx_queues;
1072         } else {
1073                 queues = adapter->tx_ring;
1074                 nb_queues = dev->data->nb_tx_queues;
1075         }
1076
1077         for (i = 0; i < nb_queues; ++i)
1078                 if (queues[i].configured)
1079                         ena_queue_stop(&queues[i]);
1080 }
1081
1082 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1083 {
1084         int rc, bufs_num;
1085
1086         ena_assert_msg(ring->configured == 1,
1087                        "Trying to start unconfigured queue\n");
1088
1089         rc = ena_create_io_queue(dev, ring);
1090         if (rc) {
1091                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1092                 return rc;
1093         }
1094
1095         ring->next_to_clean = 0;
1096         ring->next_to_use = 0;
1097
1098         if (ring->type == ENA_RING_TYPE_TX) {
1099                 ring->tx_stats.available_desc =
1100                         ena_com_free_q_entries(ring->ena_com_io_sq);
1101                 return 0;
1102         }
1103
1104         bufs_num = ring->ring_size - 1;
1105         rc = ena_populate_rx_queue(ring, bufs_num);
1106         if (rc != bufs_num) {
1107                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1108                                          ENA_IO_RXQ_IDX(ring->id));
1109                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1110                 return ENA_COM_FAULT;
1111         }
1112         /* Flush per-core RX buffers pools cache as they can be used on other
1113          * cores as well.
1114          */
1115         rte_mempool_cache_flush(NULL, ring->mb_pool);
1116
1117         return 0;
1118 }
1119
1120 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1121                               uint16_t queue_idx,
1122                               uint16_t nb_desc,
1123                               unsigned int socket_id,
1124                               const struct rte_eth_txconf *tx_conf)
1125 {
1126         struct ena_ring *txq = NULL;
1127         struct ena_adapter *adapter = dev->data->dev_private;
1128         unsigned int i;
1129         uint16_t dyn_thresh;
1130
1131         txq = &adapter->tx_ring[queue_idx];
1132
1133         if (txq->configured) {
1134                 PMD_DRV_LOG(CRIT,
1135                         "API violation. Queue[%d] is already configured\n",
1136                         queue_idx);
1137                 return ENA_COM_FAULT;
1138         }
1139
1140         if (!rte_is_power_of_2(nb_desc)) {
1141                 PMD_DRV_LOG(ERR,
1142                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1143                         nb_desc);
1144                 return -EINVAL;
1145         }
1146
1147         if (nb_desc > adapter->max_tx_ring_size) {
1148                 PMD_DRV_LOG(ERR,
1149                         "Unsupported size of Tx queue (max size: %d)\n",
1150                         adapter->max_tx_ring_size);
1151                 return -EINVAL;
1152         }
1153
1154         txq->port_id = dev->data->port_id;
1155         txq->next_to_clean = 0;
1156         txq->next_to_use = 0;
1157         txq->ring_size = nb_desc;
1158         txq->size_mask = nb_desc - 1;
1159         txq->numa_socket_id = socket_id;
1160         txq->pkts_without_db = false;
1161         txq->last_cleanup_ticks = 0;
1162
1163         txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1164                 sizeof(struct ena_tx_buffer) * txq->ring_size,
1165                 RTE_CACHE_LINE_SIZE,
1166                 socket_id);
1167         if (!txq->tx_buffer_info) {
1168                 PMD_DRV_LOG(ERR,
1169                         "Failed to allocate memory for Tx buffer info\n");
1170                 return -ENOMEM;
1171         }
1172
1173         txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1174                 sizeof(uint16_t) * txq->ring_size,
1175                 RTE_CACHE_LINE_SIZE,
1176                 socket_id);
1177         if (!txq->empty_tx_reqs) {
1178                 PMD_DRV_LOG(ERR,
1179                         "Failed to allocate memory for empty Tx requests\n");
1180                 rte_free(txq->tx_buffer_info);
1181                 return -ENOMEM;
1182         }
1183
1184         txq->push_buf_intermediate_buf =
1185                 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1186                         txq->tx_max_header_size,
1187                         RTE_CACHE_LINE_SIZE,
1188                         socket_id);
1189         if (!txq->push_buf_intermediate_buf) {
1190                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1191                 rte_free(txq->tx_buffer_info);
1192                 rte_free(txq->empty_tx_reqs);
1193                 return -ENOMEM;
1194         }
1195
1196         for (i = 0; i < txq->ring_size; i++)
1197                 txq->empty_tx_reqs[i] = i;
1198
1199         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1200
1201         /* Check if caller provided the Tx cleanup threshold value. */
1202         if (tx_conf->tx_free_thresh != 0) {
1203                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1204         } else {
1205                 dyn_thresh = txq->ring_size -
1206                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1207                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1208                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1209         }
1210
1211         txq->missing_tx_completion_threshold =
1212                 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1213
1214         /* Store pointer to this queue in upper layer */
1215         txq->configured = 1;
1216         dev->data->tx_queues[queue_idx] = txq;
1217
1218         return 0;
1219 }
1220
1221 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1222                               uint16_t queue_idx,
1223                               uint16_t nb_desc,
1224                               unsigned int socket_id,
1225                               const struct rte_eth_rxconf *rx_conf,
1226                               struct rte_mempool *mp)
1227 {
1228         struct ena_adapter *adapter = dev->data->dev_private;
1229         struct ena_ring *rxq = NULL;
1230         size_t buffer_size;
1231         int i;
1232         uint16_t dyn_thresh;
1233
1234         rxq = &adapter->rx_ring[queue_idx];
1235         if (rxq->configured) {
1236                 PMD_DRV_LOG(CRIT,
1237                         "API violation. Queue[%d] is already configured\n",
1238                         queue_idx);
1239                 return ENA_COM_FAULT;
1240         }
1241
1242         if (!rte_is_power_of_2(nb_desc)) {
1243                 PMD_DRV_LOG(ERR,
1244                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1245                         nb_desc);
1246                 return -EINVAL;
1247         }
1248
1249         if (nb_desc > adapter->max_rx_ring_size) {
1250                 PMD_DRV_LOG(ERR,
1251                         "Unsupported size of Rx queue (max size: %d)\n",
1252                         adapter->max_rx_ring_size);
1253                 return -EINVAL;
1254         }
1255
1256         /* ENA isn't supporting buffers smaller than 1400 bytes */
1257         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1258         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1259                 PMD_DRV_LOG(ERR,
1260                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1261                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1262                 return -EINVAL;
1263         }
1264
1265         rxq->port_id = dev->data->port_id;
1266         rxq->next_to_clean = 0;
1267         rxq->next_to_use = 0;
1268         rxq->ring_size = nb_desc;
1269         rxq->size_mask = nb_desc - 1;
1270         rxq->numa_socket_id = socket_id;
1271         rxq->mb_pool = mp;
1272
1273         rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1274                 sizeof(struct ena_rx_buffer) * nb_desc,
1275                 RTE_CACHE_LINE_SIZE,
1276                 socket_id);
1277         if (!rxq->rx_buffer_info) {
1278                 PMD_DRV_LOG(ERR,
1279                         "Failed to allocate memory for Rx buffer info\n");
1280                 return -ENOMEM;
1281         }
1282
1283         rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1284                 sizeof(struct rte_mbuf *) * nb_desc,
1285                 RTE_CACHE_LINE_SIZE,
1286                 socket_id);
1287         if (!rxq->rx_refill_buffer) {
1288                 PMD_DRV_LOG(ERR,
1289                         "Failed to allocate memory for Rx refill buffer\n");
1290                 rte_free(rxq->rx_buffer_info);
1291                 rxq->rx_buffer_info = NULL;
1292                 return -ENOMEM;
1293         }
1294
1295         rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1296                 sizeof(uint16_t) * nb_desc,
1297                 RTE_CACHE_LINE_SIZE,
1298                 socket_id);
1299         if (!rxq->empty_rx_reqs) {
1300                 PMD_DRV_LOG(ERR,
1301                         "Failed to allocate memory for empty Rx requests\n");
1302                 rte_free(rxq->rx_buffer_info);
1303                 rxq->rx_buffer_info = NULL;
1304                 rte_free(rxq->rx_refill_buffer);
1305                 rxq->rx_refill_buffer = NULL;
1306                 return -ENOMEM;
1307         }
1308
1309         for (i = 0; i < nb_desc; i++)
1310                 rxq->empty_rx_reqs[i] = i;
1311
1312         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1313
1314         if (rx_conf->rx_free_thresh != 0) {
1315                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1316         } else {
1317                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1318                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1319                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1320         }
1321
1322         /* Store pointer to this queue in upper layer */
1323         rxq->configured = 1;
1324         dev->data->rx_queues[queue_idx] = rxq;
1325
1326         return 0;
1327 }
1328
1329 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1330                                   struct rte_mbuf *mbuf, uint16_t id)
1331 {
1332         struct ena_com_buf ebuf;
1333         int rc;
1334
1335         /* prepare physical address for DMA transaction */
1336         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1337         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1338
1339         /* pass resource to device */
1340         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1341         if (unlikely(rc != 0))
1342                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1343
1344         return rc;
1345 }
1346
1347 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1348 {
1349         unsigned int i;
1350         int rc;
1351         uint16_t next_to_use = rxq->next_to_use;
1352         uint16_t req_id;
1353 #ifdef RTE_ETHDEV_DEBUG_RX
1354         uint16_t in_use;
1355 #endif
1356         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1357
1358         if (unlikely(!count))
1359                 return 0;
1360
1361 #ifdef RTE_ETHDEV_DEBUG_RX
1362         in_use = rxq->ring_size - 1 -
1363                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1364         if (unlikely((in_use + count) >= rxq->ring_size))
1365                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1366 #endif
1367
1368         /* get resources for incoming packets */
1369         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1370         if (unlikely(rc < 0)) {
1371                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1372                 ++rxq->rx_stats.mbuf_alloc_fail;
1373                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1374                 return 0;
1375         }
1376
1377         for (i = 0; i < count; i++) {
1378                 struct rte_mbuf *mbuf = mbufs[i];
1379                 struct ena_rx_buffer *rx_info;
1380
1381                 if (likely((i + 4) < count))
1382                         rte_prefetch0(mbufs[i + 4]);
1383
1384                 req_id = rxq->empty_rx_reqs[next_to_use];
1385                 rx_info = &rxq->rx_buffer_info[req_id];
1386
1387                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1388                 if (unlikely(rc != 0))
1389                         break;
1390
1391                 rx_info->mbuf = mbuf;
1392                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1393         }
1394
1395         if (unlikely(i < count)) {
1396                 PMD_RX_LOG(WARNING,
1397                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1398                         rxq->id, i, count);
1399                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1400                 ++rxq->rx_stats.refill_partial;
1401         }
1402
1403         /* When we submitted free resources to device... */
1404         if (likely(i > 0)) {
1405                 /* ...let HW know that it can fill buffers with data. */
1406                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1407
1408                 rxq->next_to_use = next_to_use;
1409         }
1410
1411         return i;
1412 }
1413
1414 static int ena_device_init(struct ena_com_dev *ena_dev,
1415                            struct rte_pci_device *pdev,
1416                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1417                            bool *wd_state)
1418 {
1419         uint32_t aenq_groups;
1420         int rc;
1421         bool readless_supported;
1422
1423         /* Initialize mmio registers */
1424         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1425         if (rc) {
1426                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1427                 return rc;
1428         }
1429
1430         /* The PCIe configuration space revision id indicate if mmio reg
1431          * read is disabled.
1432          */
1433         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1434         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1435
1436         /* reset device */
1437         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1438         if (rc) {
1439                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1440                 goto err_mmio_read_less;
1441         }
1442
1443         /* check FW version */
1444         rc = ena_com_validate_version(ena_dev);
1445         if (rc) {
1446                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1447                 goto err_mmio_read_less;
1448         }
1449
1450         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1451
1452         /* ENA device administration layer init */
1453         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1454         if (rc) {
1455                 PMD_DRV_LOG(ERR,
1456                         "Cannot initialize ENA admin queue\n");
1457                 goto err_mmio_read_less;
1458         }
1459
1460         /* To enable the msix interrupts the driver needs to know the number
1461          * of queues. So the driver uses polling mode to retrieve this
1462          * information.
1463          */
1464         ena_com_set_admin_polling_mode(ena_dev, true);
1465
1466         ena_config_host_info(ena_dev);
1467
1468         /* Get Device Attributes and features */
1469         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1470         if (rc) {
1471                 PMD_DRV_LOG(ERR,
1472                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1473                 goto err_admin_init;
1474         }
1475
1476         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1477                       BIT(ENA_ADMIN_NOTIFICATION) |
1478                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1479                       BIT(ENA_ADMIN_FATAL_ERROR) |
1480                       BIT(ENA_ADMIN_WARNING);
1481
1482         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1483         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1484         if (rc) {
1485                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc);
1486                 goto err_admin_init;
1487         }
1488
1489         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1490
1491         return 0;
1492
1493 err_admin_init:
1494         ena_com_admin_destroy(ena_dev);
1495
1496 err_mmio_read_less:
1497         ena_com_mmio_reg_read_request_destroy(ena_dev);
1498
1499         return rc;
1500 }
1501
1502 static void ena_interrupt_handler_rte(void *cb_arg)
1503 {
1504         struct rte_eth_dev *dev = cb_arg;
1505         struct ena_adapter *adapter = dev->data->dev_private;
1506         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1507
1508         ena_com_admin_q_comp_intr_handler(ena_dev);
1509         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1510                 ena_com_aenq_intr_handler(ena_dev, dev);
1511 }
1512
1513 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1514 {
1515         if (!adapter->wd_state)
1516                 return;
1517
1518         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1519                 return;
1520
1521         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1522             adapter->keep_alive_timeout)) {
1523                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1524                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1525                 adapter->trigger_reset = true;
1526                 ++adapter->dev_stats.wd_expired;
1527         }
1528 }
1529
1530 /* Check if admin queue is enabled */
1531 static void check_for_admin_com_state(struct ena_adapter *adapter)
1532 {
1533         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1534                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1535                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1536                 adapter->trigger_reset = true;
1537         }
1538 }
1539
1540 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1541                                             struct ena_ring *tx_ring)
1542 {
1543         struct ena_tx_buffer *tx_buf;
1544         uint64_t timestamp;
1545         uint64_t completion_delay;
1546         uint32_t missed_tx = 0;
1547         unsigned int i;
1548         int rc = 0;
1549
1550         for (i = 0; i < tx_ring->ring_size; ++i) {
1551                 tx_buf = &tx_ring->tx_buffer_info[i];
1552                 timestamp = tx_buf->timestamp;
1553
1554                 if (timestamp == 0)
1555                         continue;
1556
1557                 completion_delay = rte_get_timer_cycles() - timestamp;
1558                 if (completion_delay > adapter->missing_tx_completion_to) {
1559                         if (unlikely(!tx_buf->print_once)) {
1560                                 PMD_TX_LOG(WARNING,
1561                                         "Found a Tx that wasn't completed on time, qid %d, index %d. "
1562                                         "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1563                                         tx_ring->id, i, completion_delay /
1564                                         rte_get_timer_hz() * 1000);
1565                                 tx_buf->print_once = true;
1566                         }
1567                         ++missed_tx;
1568                 }
1569         }
1570
1571         if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1572                 PMD_DRV_LOG(ERR,
1573                         "The number of lost Tx completions is above the threshold (%d > %d). "
1574                         "Trigger the device reset.\n",
1575                         missed_tx,
1576                         tx_ring->missing_tx_completion_threshold);
1577                 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1578                 adapter->trigger_reset = true;
1579                 rc = -EIO;
1580         }
1581
1582         tx_ring->tx_stats.missed_tx += missed_tx;
1583
1584         return rc;
1585 }
1586
1587 static void check_for_tx_completions(struct ena_adapter *adapter)
1588 {
1589         struct ena_ring *tx_ring;
1590         uint64_t tx_cleanup_delay;
1591         size_t qid;
1592         int budget;
1593         uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1594
1595         if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1596                 return;
1597
1598         nb_tx_queues = adapter->edev_data->nb_tx_queues;
1599         budget = adapter->missing_tx_completion_budget;
1600
1601         qid = adapter->last_tx_comp_qid;
1602         while (budget-- > 0) {
1603                 tx_ring = &adapter->tx_ring[qid];
1604
1605                 /* Tx cleanup is called only by the burst function and can be
1606                  * called dynamically by the application. Also cleanup is
1607                  * limited by the threshold. To avoid false detection of the
1608                  * missing HW Tx completion, get the delay since last cleanup
1609                  * function was called.
1610                  */
1611                 tx_cleanup_delay = rte_get_timer_cycles() -
1612                         tx_ring->last_cleanup_ticks;
1613                 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1614                         check_for_tx_completion_in_queue(adapter, tx_ring);
1615                 qid = (qid + 1) % nb_tx_queues;
1616         }
1617
1618         adapter->last_tx_comp_qid = qid;
1619 }
1620
1621 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1622                                   void *arg)
1623 {
1624         struct rte_eth_dev *dev = arg;
1625         struct ena_adapter *adapter = dev->data->dev_private;
1626
1627         check_for_missing_keep_alive(adapter);
1628         check_for_admin_com_state(adapter);
1629         check_for_tx_completions(adapter);
1630
1631         if (unlikely(adapter->trigger_reset)) {
1632                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1633                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1634                         NULL);
1635         }
1636 }
1637
1638 static inline void
1639 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1640                                struct ena_admin_feature_llq_desc *llq,
1641                                bool use_large_llq_hdr)
1642 {
1643         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1644         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1645         llq_config->llq_num_decs_before_header =
1646                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1647
1648         if (use_large_llq_hdr &&
1649             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1650                 llq_config->llq_ring_entry_size =
1651                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1652                 llq_config->llq_ring_entry_size_value = 256;
1653         } else {
1654                 llq_config->llq_ring_entry_size =
1655                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1656                 llq_config->llq_ring_entry_size_value = 128;
1657         }
1658 }
1659
1660 static int
1661 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1662                                 struct ena_com_dev *ena_dev,
1663                                 struct ena_admin_feature_llq_desc *llq,
1664                                 struct ena_llq_configurations *llq_default_configurations)
1665 {
1666         int rc;
1667         u32 llq_feature_mask;
1668
1669         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1670         if (!(ena_dev->supported_features & llq_feature_mask)) {
1671                 PMD_DRV_LOG(INFO,
1672                         "LLQ is not supported. Fallback to host mode policy.\n");
1673                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1674                 return 0;
1675         }
1676
1677         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1678         if (unlikely(rc)) {
1679                 PMD_INIT_LOG(WARNING,
1680                         "Failed to config dev mode. Fallback to host mode policy.\n");
1681                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1682                 return 0;
1683         }
1684
1685         /* Nothing to config, exit */
1686         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1687                 return 0;
1688
1689         if (!adapter->dev_mem_base) {
1690                 PMD_DRV_LOG(ERR,
1691                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1692                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1693                 return 0;
1694         }
1695
1696         ena_dev->mem_bar = adapter->dev_mem_base;
1697
1698         return 0;
1699 }
1700
1701 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1702         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1703 {
1704         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1705
1706         /* Regular queues capabilities */
1707         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1708                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1709                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1710                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1711                                     max_queue_ext->max_rx_cq_num);
1712                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1713                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1714         } else {
1715                 struct ena_admin_queue_feature_desc *max_queues =
1716                         &get_feat_ctx->max_queues;
1717                 io_tx_sq_num = max_queues->max_sq_num;
1718                 io_tx_cq_num = max_queues->max_cq_num;
1719                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1720         }
1721
1722         /* In case of LLQ use the llq number in the get feature cmd */
1723         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1724                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1725
1726         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1727         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1728         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1729
1730         if (unlikely(max_num_io_queues == 0)) {
1731                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1732                 return -EFAULT;
1733         }
1734
1735         return max_num_io_queues;
1736 }
1737
1738 static void
1739 ena_set_offloads(struct ena_offloads *offloads,
1740                  struct ena_admin_feature_offload_desc *offload_desc)
1741 {
1742         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1743                 offloads->tx_offloads |= ENA_IPV4_TSO;
1744
1745         /* Tx IPv4 checksum offloads */
1746         if (offload_desc->tx &
1747             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
1748                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
1749         if (offload_desc->tx &
1750             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
1751                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
1752         if (offload_desc->tx &
1753             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1754                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
1755
1756         /* Tx IPv6 checksum offloads */
1757         if (offload_desc->tx &
1758             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
1759                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
1760         if (offload_desc->tx &
1761              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
1762                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
1763
1764         /* Rx IPv4 checksum offloads */
1765         if (offload_desc->rx_supported &
1766             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
1767                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
1768         if (offload_desc->rx_supported &
1769             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1770                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
1771
1772         /* Rx IPv6 checksum offloads */
1773         if (offload_desc->rx_supported &
1774             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
1775                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
1776
1777         if (offload_desc->rx_supported &
1778             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
1779                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
1780 }
1781
1782 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1783 {
1784         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1785         struct rte_pci_device *pci_dev;
1786         struct rte_intr_handle *intr_handle;
1787         struct ena_adapter *adapter = eth_dev->data->dev_private;
1788         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1789         struct ena_com_dev_get_features_ctx get_feat_ctx;
1790         struct ena_llq_configurations llq_config;
1791         const char *queue_type_str;
1792         uint32_t max_num_io_queues;
1793         int rc;
1794         static int adapters_found;
1795         bool disable_meta_caching;
1796         bool wd_state = false;
1797
1798         eth_dev->dev_ops = &ena_dev_ops;
1799         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1800         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1801         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1802
1803         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1804                 return 0;
1805
1806         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1807
1808         memset(adapter, 0, sizeof(struct ena_adapter));
1809         ena_dev = &adapter->ena_dev;
1810
1811         adapter->edev_data = eth_dev->data;
1812
1813         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1814
1815         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1816                      pci_dev->addr.domain,
1817                      pci_dev->addr.bus,
1818                      pci_dev->addr.devid,
1819                      pci_dev->addr.function);
1820
1821         intr_handle = pci_dev->intr_handle;
1822
1823         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1824         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1825
1826         if (!adapter->regs) {
1827                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1828                              ENA_REGS_BAR);
1829                 return -ENXIO;
1830         }
1831
1832         ena_dev->reg_bar = adapter->regs;
1833         /* This is a dummy pointer for ena_com functions. */
1834         ena_dev->dmadev = adapter;
1835
1836         adapter->id_number = adapters_found;
1837
1838         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1839                  adapter->id_number);
1840
1841         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1842         if (rc != 0) {
1843                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1844                 goto err;
1845         }
1846
1847         /* device specific initialization routine */
1848         rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1849         if (rc) {
1850                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1851                 goto err;
1852         }
1853         adapter->wd_state = wd_state;
1854
1855         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1856                 adapter->use_large_llq_hdr);
1857         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1858                                              &get_feat_ctx.llq, &llq_config);
1859         if (unlikely(rc)) {
1860                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1861                 return rc;
1862         }
1863
1864         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1865                 queue_type_str = "Regular";
1866         else
1867                 queue_type_str = "Low latency";
1868         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1869
1870         calc_queue_ctx.ena_dev = ena_dev;
1871         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1872
1873         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1874         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1875                 adapter->use_large_llq_hdr);
1876         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1877                 rc = -EFAULT;
1878                 goto err_device_destroy;
1879         }
1880
1881         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1882         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1883         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1884         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1885         adapter->max_num_io_queues = max_num_io_queues;
1886
1887         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1888                 disable_meta_caching =
1889                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1890                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1891         } else {
1892                 disable_meta_caching = false;
1893         }
1894
1895         /* prepare ring structures */
1896         ena_init_rings(adapter, disable_meta_caching);
1897
1898         ena_config_debug_area(adapter);
1899
1900         /* Set max MTU for this device */
1901         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1902
1903         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
1904
1905         /* Copy MAC address and point DPDK to it */
1906         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1907         rte_ether_addr_copy((struct rte_ether_addr *)
1908                         get_feat_ctx.dev_attr.mac_addr,
1909                         (struct rte_ether_addr *)adapter->mac_addr);
1910
1911         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1912         if (unlikely(rc != 0)) {
1913                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1914                 goto err_delete_debug_area;
1915         }
1916
1917         adapter->drv_stats = rte_zmalloc("adapter stats",
1918                                          sizeof(*adapter->drv_stats),
1919                                          RTE_CACHE_LINE_SIZE);
1920         if (!adapter->drv_stats) {
1921                 PMD_DRV_LOG(ERR,
1922                         "Failed to allocate memory for adapter statistics\n");
1923                 rc = -ENOMEM;
1924                 goto err_rss_destroy;
1925         }
1926
1927         rte_spinlock_init(&adapter->admin_lock);
1928
1929         rte_intr_callback_register(intr_handle,
1930                                    ena_interrupt_handler_rte,
1931                                    eth_dev);
1932         rte_intr_enable(intr_handle);
1933         ena_com_set_admin_polling_mode(ena_dev, false);
1934         ena_com_admin_aenq_enable(ena_dev);
1935
1936         if (adapters_found == 0)
1937                 rte_timer_subsystem_init();
1938         rte_timer_init(&adapter->timer_wd);
1939
1940         adapters_found++;
1941         adapter->state = ENA_ADAPTER_STATE_INIT;
1942
1943         return 0;
1944
1945 err_rss_destroy:
1946         ena_com_rss_destroy(ena_dev);
1947 err_delete_debug_area:
1948         ena_com_delete_debug_area(ena_dev);
1949
1950 err_device_destroy:
1951         ena_com_delete_host_info(ena_dev);
1952         ena_com_admin_destroy(ena_dev);
1953
1954 err:
1955         return rc;
1956 }
1957
1958 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1959 {
1960         struct ena_adapter *adapter = eth_dev->data->dev_private;
1961         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1962
1963         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1964                 return;
1965
1966         ena_com_set_admin_running_state(ena_dev, false);
1967
1968         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1969                 ena_close(eth_dev);
1970
1971         ena_com_rss_destroy(ena_dev);
1972
1973         ena_com_delete_debug_area(ena_dev);
1974         ena_com_delete_host_info(ena_dev);
1975
1976         ena_com_abort_admin_commands(ena_dev);
1977         ena_com_wait_for_abort_completion(ena_dev);
1978         ena_com_admin_destroy(ena_dev);
1979         ena_com_mmio_reg_read_request_destroy(ena_dev);
1980
1981         adapter->state = ENA_ADAPTER_STATE_FREE;
1982 }
1983
1984 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1985 {
1986         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1987                 return 0;
1988
1989         ena_destroy_device(eth_dev);
1990
1991         return 0;
1992 }
1993
1994 static int ena_dev_configure(struct rte_eth_dev *dev)
1995 {
1996         struct ena_adapter *adapter = dev->data->dev_private;
1997
1998         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1999
2000         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2001                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2002         dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2003
2004         /* Scattered Rx cannot be turned off in the HW, so this capability must
2005          * be forced.
2006          */
2007         dev->data->scattered_rx = 1;
2008
2009         adapter->last_tx_comp_qid = 0;
2010
2011         adapter->missing_tx_completion_budget =
2012                 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2013
2014         adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2015         /* To avoid detection of the spurious Tx completion timeout due to
2016          * application not calling the Tx cleanup function, set timeout for the
2017          * Tx queue which should be half of the missing completion timeout for a
2018          * safety. If there will be a lot of missing Tx completions in the
2019          * queue, they will be detected sooner or later.
2020          */
2021         adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2022
2023         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
2024         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
2025
2026         return 0;
2027 }
2028
2029 static void ena_init_rings(struct ena_adapter *adapter,
2030                            bool disable_meta_caching)
2031 {
2032         size_t i;
2033
2034         for (i = 0; i < adapter->max_num_io_queues; i++) {
2035                 struct ena_ring *ring = &adapter->tx_ring[i];
2036
2037                 ring->configured = 0;
2038                 ring->type = ENA_RING_TYPE_TX;
2039                 ring->adapter = adapter;
2040                 ring->id = i;
2041                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2042                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2043                 ring->sgl_size = adapter->max_tx_sgl_size;
2044                 ring->disable_meta_caching = disable_meta_caching;
2045         }
2046
2047         for (i = 0; i < adapter->max_num_io_queues; i++) {
2048                 struct ena_ring *ring = &adapter->rx_ring[i];
2049
2050                 ring->configured = 0;
2051                 ring->type = ENA_RING_TYPE_RX;
2052                 ring->adapter = adapter;
2053                 ring->id = i;
2054                 ring->sgl_size = adapter->max_rx_sgl_size;
2055         }
2056 }
2057
2058 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2059 {
2060         uint64_t port_offloads = 0;
2061
2062         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2063                 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2064
2065         if (adapter->offloads.rx_offloads &
2066             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2067                 port_offloads |=
2068                         RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2069
2070         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2071                 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2072
2073         port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2074
2075         return port_offloads;
2076 }
2077
2078 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2079 {
2080         uint64_t port_offloads = 0;
2081
2082         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2083                 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2084
2085         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2086                 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2087         if (adapter->offloads.tx_offloads &
2088             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2089              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2090                 port_offloads |=
2091                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2092
2093         port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2094
2095         return port_offloads;
2096 }
2097
2098 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2099 {
2100         RTE_SET_USED(adapter);
2101
2102         return 0;
2103 }
2104
2105 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2106 {
2107         RTE_SET_USED(adapter);
2108
2109         return 0;
2110 }
2111
2112 static int ena_infos_get(struct rte_eth_dev *dev,
2113                           struct rte_eth_dev_info *dev_info)
2114 {
2115         struct ena_adapter *adapter;
2116         struct ena_com_dev *ena_dev;
2117
2118         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2119         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2120         adapter = dev->data->dev_private;
2121
2122         ena_dev = &adapter->ena_dev;
2123         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2124
2125         dev_info->speed_capa =
2126                         RTE_ETH_LINK_SPEED_1G   |
2127                         RTE_ETH_LINK_SPEED_2_5G |
2128                         RTE_ETH_LINK_SPEED_5G   |
2129                         RTE_ETH_LINK_SPEED_10G  |
2130                         RTE_ETH_LINK_SPEED_25G  |
2131                         RTE_ETH_LINK_SPEED_40G  |
2132                         RTE_ETH_LINK_SPEED_50G  |
2133                         RTE_ETH_LINK_SPEED_100G;
2134
2135         /* Inform framework about available features */
2136         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2137         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2138         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2139         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2140
2141         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2142         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2143
2144         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2145         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2146                 RTE_ETHER_CRC_LEN;
2147         dev_info->min_mtu = ENA_MIN_MTU;
2148         dev_info->max_mtu = adapter->max_mtu;
2149         dev_info->max_mac_addrs = 1;
2150
2151         dev_info->max_rx_queues = adapter->max_num_io_queues;
2152         dev_info->max_tx_queues = adapter->max_num_io_queues;
2153         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2154
2155         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2156         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2157         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2158                                         adapter->max_rx_sgl_size);
2159         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2160                                         adapter->max_rx_sgl_size);
2161
2162         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2163         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2164         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2165                                         adapter->max_tx_sgl_size);
2166         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2167                                         adapter->max_tx_sgl_size);
2168
2169         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2170         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2171
2172         return 0;
2173 }
2174
2175 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2176 {
2177         mbuf->data_len = len;
2178         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2179         mbuf->refcnt = 1;
2180         mbuf->next = NULL;
2181 }
2182
2183 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2184                                     struct ena_com_rx_buf_info *ena_bufs,
2185                                     uint32_t descs,
2186                                     uint16_t *next_to_clean,
2187                                     uint8_t offset)
2188 {
2189         struct rte_mbuf *mbuf;
2190         struct rte_mbuf *mbuf_head;
2191         struct ena_rx_buffer *rx_info;
2192         int rc;
2193         uint16_t ntc, len, req_id, buf = 0;
2194
2195         if (unlikely(descs == 0))
2196                 return NULL;
2197
2198         ntc = *next_to_clean;
2199
2200         len = ena_bufs[buf].len;
2201         req_id = ena_bufs[buf].req_id;
2202
2203         rx_info = &rx_ring->rx_buffer_info[req_id];
2204
2205         mbuf = rx_info->mbuf;
2206         RTE_ASSERT(mbuf != NULL);
2207
2208         ena_init_rx_mbuf(mbuf, len);
2209
2210         /* Fill the mbuf head with the data specific for 1st segment. */
2211         mbuf_head = mbuf;
2212         mbuf_head->nb_segs = descs;
2213         mbuf_head->port = rx_ring->port_id;
2214         mbuf_head->pkt_len = len;
2215         mbuf_head->data_off += offset;
2216
2217         rx_info->mbuf = NULL;
2218         rx_ring->empty_rx_reqs[ntc] = req_id;
2219         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2220
2221         while (--descs) {
2222                 ++buf;
2223                 len = ena_bufs[buf].len;
2224                 req_id = ena_bufs[buf].req_id;
2225
2226                 rx_info = &rx_ring->rx_buffer_info[req_id];
2227                 RTE_ASSERT(rx_info->mbuf != NULL);
2228
2229                 if (unlikely(len == 0)) {
2230                         /*
2231                          * Some devices can pass descriptor with the length 0.
2232                          * To avoid confusion, the PMD is simply putting the
2233                          * descriptor back, as it was never used. We'll avoid
2234                          * mbuf allocation that way.
2235                          */
2236                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2237                                 rx_info->mbuf, req_id);
2238                         if (unlikely(rc != 0)) {
2239                                 /* Free the mbuf in case of an error. */
2240                                 rte_mbuf_raw_free(rx_info->mbuf);
2241                         } else {
2242                                 /*
2243                                  * If there was no error, just exit the loop as
2244                                  * 0 length descriptor is always the last one.
2245                                  */
2246                                 break;
2247                         }
2248                 } else {
2249                         /* Create an mbuf chain. */
2250                         mbuf->next = rx_info->mbuf;
2251                         mbuf = mbuf->next;
2252
2253                         ena_init_rx_mbuf(mbuf, len);
2254                         mbuf_head->pkt_len += len;
2255                 }
2256
2257                 /*
2258                  * Mark the descriptor as depleted and perform necessary
2259                  * cleanup.
2260                  * This code will execute in two cases:
2261                  *  1. Descriptor len was greater than 0 - normal situation.
2262                  *  2. Descriptor len was 0 and we failed to add the descriptor
2263                  *     to the device. In that situation, we should try to add
2264                  *     the mbuf again in the populate routine and mark the
2265                  *     descriptor as used up by the device.
2266                  */
2267                 rx_info->mbuf = NULL;
2268                 rx_ring->empty_rx_reqs[ntc] = req_id;
2269                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2270         }
2271
2272         *next_to_clean = ntc;
2273
2274         return mbuf_head;
2275 }
2276
2277 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2278                                   uint16_t nb_pkts)
2279 {
2280         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2281         unsigned int free_queue_entries;
2282         uint16_t next_to_clean = rx_ring->next_to_clean;
2283         uint16_t descs_in_use;
2284         struct rte_mbuf *mbuf;
2285         uint16_t completed;
2286         struct ena_com_rx_ctx ena_rx_ctx;
2287         int i, rc = 0;
2288         bool fill_hash;
2289
2290 #ifdef RTE_ETHDEV_DEBUG_RX
2291         /* Check adapter state */
2292         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2293                 PMD_RX_LOG(ALERT,
2294                         "Trying to receive pkts while device is NOT running\n");
2295                 return 0;
2296         }
2297 #endif
2298
2299         fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2300
2301         descs_in_use = rx_ring->ring_size -
2302                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2303         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2304
2305         for (completed = 0; completed < nb_pkts; completed++) {
2306                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2307                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2308                 ena_rx_ctx.descs = 0;
2309                 ena_rx_ctx.pkt_offset = 0;
2310                 /* receive packet context */
2311                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2312                                     rx_ring->ena_com_io_sq,
2313                                     &ena_rx_ctx);
2314                 if (unlikely(rc)) {
2315                         PMD_RX_LOG(ERR,
2316                                 "Failed to get the packet from the device, rc: %d\n",
2317                                 rc);
2318                         if (rc == ENA_COM_NO_SPACE) {
2319                                 ++rx_ring->rx_stats.bad_desc_num;
2320                                 rx_ring->adapter->reset_reason =
2321                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2322                         } else {
2323                                 ++rx_ring->rx_stats.bad_req_id;
2324                                 rx_ring->adapter->reset_reason =
2325                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2326                         }
2327                         rx_ring->adapter->trigger_reset = true;
2328                         return 0;
2329                 }
2330
2331                 mbuf = ena_rx_mbuf(rx_ring,
2332                         ena_rx_ctx.ena_bufs,
2333                         ena_rx_ctx.descs,
2334                         &next_to_clean,
2335                         ena_rx_ctx.pkt_offset);
2336                 if (unlikely(mbuf == NULL)) {
2337                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2338                                 rx_ring->empty_rx_reqs[next_to_clean] =
2339                                         rx_ring->ena_bufs[i].req_id;
2340                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2341                                         next_to_clean, rx_ring->size_mask);
2342                         }
2343                         break;
2344                 }
2345
2346                 /* fill mbuf attributes if any */
2347                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash);
2348
2349                 if (unlikely(mbuf->ol_flags &
2350                                 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD))) {
2351                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2352                         ++rx_ring->rx_stats.bad_csum;
2353                 }
2354
2355                 rx_pkts[completed] = mbuf;
2356                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2357         }
2358
2359         rx_ring->rx_stats.cnt += completed;
2360         rx_ring->next_to_clean = next_to_clean;
2361
2362         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2363
2364         /* Burst refill to save doorbells, memory barriers, const interval */
2365         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2366                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2367                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2368         }
2369
2370         return completed;
2371 }
2372
2373 static uint16_t
2374 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2375                 uint16_t nb_pkts)
2376 {
2377         int32_t ret;
2378         uint32_t i;
2379         struct rte_mbuf *m;
2380         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2381         struct ena_adapter *adapter = tx_ring->adapter;
2382         struct rte_ipv4_hdr *ip_hdr;
2383         uint64_t ol_flags;
2384         uint64_t l4_csum_flag;
2385         uint64_t dev_offload_capa;
2386         uint16_t frag_field;
2387         bool need_pseudo_csum;
2388
2389         dev_offload_capa = adapter->offloads.tx_offloads;
2390         for (i = 0; i != nb_pkts; i++) {
2391                 m = tx_pkts[i];
2392                 ol_flags = m->ol_flags;
2393
2394                 /* Check if any offload flag was set */
2395                 if (ol_flags == 0)
2396                         continue;
2397
2398                 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2399                 /* SCTP checksum offload is not supported by the ENA. */
2400                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2401                     l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2402                         PMD_TX_LOG(DEBUG,
2403                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2404                                 i, ol_flags);
2405                         rte_errno = ENOTSUP;
2406                         return i;
2407                 }
2408
2409                 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2410                     !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2411                       m->nb_segs == tx_ring->sgl_size &&
2412                       m->data_len < tx_ring->tx_max_header_size))) {
2413                         PMD_TX_LOG(DEBUG,
2414                                 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2415                                 i, m->nb_segs);
2416                         rte_errno = EINVAL;
2417                         return i;
2418                 }
2419
2420 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2421                 /* Check if requested offload is also enabled for the queue */
2422                 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2423                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2424                     (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2425                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2426                     (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2427                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2428                         PMD_TX_LOG(DEBUG,
2429                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2430                                 i, m->nb_segs, tx_ring->id);
2431                         rte_errno = EINVAL;
2432                         return i;
2433                 }
2434
2435                 /* The caller is obligated to set l2 and l3 len if any cksum
2436                  * offload is enabled.
2437                  */
2438                 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2439                     (m->l2_len == 0 || m->l3_len == 0))) {
2440                         PMD_TX_LOG(DEBUG,
2441                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2442                                 i);
2443                         rte_errno = EINVAL;
2444                         return i;
2445                 }
2446                 ret = rte_validate_tx_offload(m);
2447                 if (ret != 0) {
2448                         rte_errno = -ret;
2449                         return i;
2450                 }
2451 #endif
2452
2453                 /* Verify HW support for requested offloads and determine if
2454                  * pseudo header checksum is needed.
2455                  */
2456                 need_pseudo_csum = false;
2457                 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2458                         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2459                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2460                                 rte_errno = ENOTSUP;
2461                                 return i;
2462                         }
2463
2464                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2465                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2466                                 rte_errno = ENOTSUP;
2467                                 return i;
2468                         }
2469
2470                         /* Check HW capabilities and if pseudo csum is needed
2471                          * for L4 offloads.
2472                          */
2473                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2474                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2475                                 if (dev_offload_capa &
2476                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2477                                         need_pseudo_csum = true;
2478                                 } else {
2479                                         rte_errno = ENOTSUP;
2480                                         return i;
2481                                 }
2482                         }
2483
2484                         /* Parse the DF flag */
2485                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2486                                 struct rte_ipv4_hdr *, m->l2_len);
2487                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2488                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2489                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2490                         } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2491                                 /* In case we are supposed to TSO and have DF
2492                                  * not set (DF=0) hardware must be provided with
2493                                  * partial checksum.
2494                                  */
2495                                 need_pseudo_csum = true;
2496                         }
2497                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2498                         /* There is no support for IPv6 TSO as for now. */
2499                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2500                                 rte_errno = ENOTSUP;
2501                                 return i;
2502                         }
2503
2504                         /* Check HW capabilities and if pseudo csum is needed */
2505                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2506                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2507                                 if (dev_offload_capa &
2508                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2509                                         need_pseudo_csum = true;
2510                                 } else {
2511                                         rte_errno = ENOTSUP;
2512                                         return i;
2513                                 }
2514                         }
2515                 }
2516
2517                 if (need_pseudo_csum) {
2518                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2519                         if (ret != 0) {
2520                                 rte_errno = -ret;
2521                                 return i;
2522                         }
2523                 }
2524         }
2525
2526         return i;
2527 }
2528
2529 static void ena_update_hints(struct ena_adapter *adapter,
2530                              struct ena_admin_ena_hw_hints *hints)
2531 {
2532         if (hints->admin_completion_tx_timeout)
2533                 adapter->ena_dev.admin_queue.completion_timeout =
2534                         hints->admin_completion_tx_timeout * 1000;
2535
2536         if (hints->mmio_read_timeout)
2537                 /* convert to usec */
2538                 adapter->ena_dev.mmio_read.reg_read_to =
2539                         hints->mmio_read_timeout * 1000;
2540
2541         if (hints->missing_tx_completion_timeout) {
2542                 if (hints->missing_tx_completion_timeout ==
2543                     ENA_HW_HINTS_NO_TIMEOUT) {
2544                         adapter->missing_tx_completion_to =
2545                                 ENA_HW_HINTS_NO_TIMEOUT;
2546                 } else {
2547                         /* Convert from msecs to ticks */
2548                         adapter->missing_tx_completion_to = rte_get_timer_hz() *
2549                                 hints->missing_tx_completion_timeout / 1000;
2550                         adapter->tx_cleanup_stall_delay =
2551                                 adapter->missing_tx_completion_to / 2;
2552                 }
2553         }
2554
2555         if (hints->driver_watchdog_timeout) {
2556                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2557                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2558                 else
2559                         // Convert msecs to ticks
2560                         adapter->keep_alive_timeout =
2561                                 (hints->driver_watchdog_timeout *
2562                                 rte_get_timer_hz()) / 1000;
2563         }
2564 }
2565
2566 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2567         struct ena_tx_buffer *tx_info,
2568         struct rte_mbuf *mbuf,
2569         void **push_header,
2570         uint16_t *header_len)
2571 {
2572         struct ena_com_buf *ena_buf;
2573         uint16_t delta, seg_len, push_len;
2574
2575         delta = 0;
2576         seg_len = mbuf->data_len;
2577
2578         tx_info->mbuf = mbuf;
2579         ena_buf = tx_info->bufs;
2580
2581         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2582                 /*
2583                  * Tx header might be (and will be in most cases) smaller than
2584                  * tx_max_header_size. But it's not an issue to send more data
2585                  * to the device, than actually needed if the mbuf size is
2586                  * greater than tx_max_header_size.
2587                  */
2588                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2589                 *header_len = push_len;
2590
2591                 if (likely(push_len <= seg_len)) {
2592                         /* If the push header is in the single segment, then
2593                          * just point it to the 1st mbuf data.
2594                          */
2595                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2596                 } else {
2597                         /* If the push header lays in the several segments, copy
2598                          * it to the intermediate buffer.
2599                          */
2600                         rte_pktmbuf_read(mbuf, 0, push_len,
2601                                 tx_ring->push_buf_intermediate_buf);
2602                         *push_header = tx_ring->push_buf_intermediate_buf;
2603                         delta = push_len - seg_len;
2604                 }
2605         } else {
2606                 *push_header = NULL;
2607                 *header_len = 0;
2608                 push_len = 0;
2609         }
2610
2611         /* Process first segment taking into consideration pushed header */
2612         if (seg_len > push_len) {
2613                 ena_buf->paddr = mbuf->buf_iova +
2614                                 mbuf->data_off +
2615                                 push_len;
2616                 ena_buf->len = seg_len - push_len;
2617                 ena_buf++;
2618                 tx_info->num_of_bufs++;
2619         }
2620
2621         while ((mbuf = mbuf->next) != NULL) {
2622                 seg_len = mbuf->data_len;
2623
2624                 /* Skip mbufs if whole data is pushed as a header */
2625                 if (unlikely(delta > seg_len)) {
2626                         delta -= seg_len;
2627                         continue;
2628                 }
2629
2630                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2631                 ena_buf->len = seg_len - delta;
2632                 ena_buf++;
2633                 tx_info->num_of_bufs++;
2634
2635                 delta = 0;
2636         }
2637 }
2638
2639 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2640 {
2641         struct ena_tx_buffer *tx_info;
2642         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2643         uint16_t next_to_use;
2644         uint16_t header_len;
2645         uint16_t req_id;
2646         void *push_header;
2647         int nb_hw_desc;
2648         int rc;
2649
2650         /* Checking for space for 2 additional metadata descriptors due to
2651          * possible header split and metadata descriptor
2652          */
2653         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2654                                           mbuf->nb_segs + 2)) {
2655                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2656                 return ENA_COM_NO_MEM;
2657         }
2658
2659         next_to_use = tx_ring->next_to_use;
2660
2661         req_id = tx_ring->empty_tx_reqs[next_to_use];
2662         tx_info = &tx_ring->tx_buffer_info[req_id];
2663         tx_info->num_of_bufs = 0;
2664
2665         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2666
2667         ena_tx_ctx.ena_bufs = tx_info->bufs;
2668         ena_tx_ctx.push_header = push_header;
2669         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2670         ena_tx_ctx.req_id = req_id;
2671         ena_tx_ctx.header_len = header_len;
2672
2673         /* Set Tx offloads flags, if applicable */
2674         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2675                 tx_ring->disable_meta_caching);
2676
2677         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2678                         &ena_tx_ctx))) {
2679                 PMD_TX_LOG(DEBUG,
2680                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2681                         tx_ring->id);
2682                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2683                 tx_ring->tx_stats.doorbells++;
2684                 tx_ring->pkts_without_db = false;
2685         }
2686
2687         /* prepare the packet's descriptors to dma engine */
2688         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2689                 &nb_hw_desc);
2690         if (unlikely(rc)) {
2691                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2692                 ++tx_ring->tx_stats.prepare_ctx_err;
2693                 tx_ring->adapter->reset_reason =
2694                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2695                 tx_ring->adapter->trigger_reset = true;
2696                 return rc;
2697         }
2698
2699         tx_info->tx_descs = nb_hw_desc;
2700         tx_info->timestamp = rte_get_timer_cycles();
2701
2702         tx_ring->tx_stats.cnt++;
2703         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2704
2705         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2706                 tx_ring->size_mask);
2707
2708         return 0;
2709 }
2710
2711 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2712 {
2713         unsigned int total_tx_descs = 0;
2714         uint16_t cleanup_budget;
2715         uint16_t next_to_clean = tx_ring->next_to_clean;
2716
2717         /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
2718         cleanup_budget = tx_ring->size_mask;
2719
2720         while (likely(total_tx_descs < cleanup_budget)) {
2721                 struct rte_mbuf *mbuf;
2722                 struct ena_tx_buffer *tx_info;
2723                 uint16_t req_id;
2724
2725                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2726                         break;
2727
2728                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2729                         break;
2730
2731                 /* Get Tx info & store how many descs were processed  */
2732                 tx_info = &tx_ring->tx_buffer_info[req_id];
2733                 tx_info->timestamp = 0;
2734
2735                 mbuf = tx_info->mbuf;
2736                 rte_pktmbuf_free(mbuf);
2737
2738                 tx_info->mbuf = NULL;
2739                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2740
2741                 total_tx_descs += tx_info->tx_descs;
2742
2743                 /* Put back descriptor to the ring for reuse */
2744                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2745                         tx_ring->size_mask);
2746         }
2747
2748         if (likely(total_tx_descs > 0)) {
2749                 /* acknowledge completion of sent packets */
2750                 tx_ring->next_to_clean = next_to_clean;
2751                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2752                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2753         }
2754
2755         /* Notify completion handler that the cleanup was just called */
2756         tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
2757 }
2758
2759 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2760                                   uint16_t nb_pkts)
2761 {
2762         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2763         int available_desc;
2764         uint16_t sent_idx = 0;
2765
2766 #ifdef RTE_ETHDEV_DEBUG_TX
2767         /* Check adapter state */
2768         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2769                 PMD_TX_LOG(ALERT,
2770                         "Trying to xmit pkts while device is NOT running\n");
2771                 return 0;
2772         }
2773 #endif
2774
2775         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2776                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2777                         break;
2778                 tx_ring->pkts_without_db = true;
2779                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2780                         tx_ring->size_mask)]);
2781         }
2782
2783         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2784         tx_ring->tx_stats.available_desc = available_desc;
2785
2786         /* If there are ready packets to be xmitted... */
2787         if (likely(tx_ring->pkts_without_db)) {
2788                 /* ...let HW do its best :-) */
2789                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2790                 tx_ring->tx_stats.doorbells++;
2791                 tx_ring->pkts_without_db = false;
2792         }
2793
2794         if (available_desc < tx_ring->tx_free_thresh)
2795                 ena_tx_cleanup(tx_ring);
2796
2797         tx_ring->tx_stats.available_desc =
2798                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2799         tx_ring->tx_stats.tx_poll++;
2800
2801         return sent_idx;
2802 }
2803
2804 int ena_copy_eni_stats(struct ena_adapter *adapter)
2805 {
2806         struct ena_admin_eni_stats admin_eni_stats;
2807         int rc;
2808
2809         rte_spinlock_lock(&adapter->admin_lock);
2810         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2811         rte_spinlock_unlock(&adapter->admin_lock);
2812         if (rc != 0) {
2813                 if (rc == ENA_COM_UNSUPPORTED) {
2814                         PMD_DRV_LOG(DEBUG,
2815                                 "Retrieving ENI metrics is not supported\n");
2816                 } else {
2817                         PMD_DRV_LOG(WARNING,
2818                                 "Failed to get ENI metrics, rc: %d\n", rc);
2819                 }
2820                 return rc;
2821         }
2822
2823         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2824                 sizeof(struct ena_stats_eni));
2825
2826         return 0;
2827 }
2828
2829 /**
2830  * DPDK callback to retrieve names of extended device statistics
2831  *
2832  * @param dev
2833  *   Pointer to Ethernet device structure.
2834  * @param[out] xstats_names
2835  *   Buffer to insert names into.
2836  * @param n
2837  *   Number of names.
2838  *
2839  * @return
2840  *   Number of xstats names.
2841  */
2842 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2843                                 struct rte_eth_xstat_name *xstats_names,
2844                                 unsigned int n)
2845 {
2846         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2847         unsigned int stat, i, count = 0;
2848
2849         if (n < xstats_count || !xstats_names)
2850                 return xstats_count;
2851
2852         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2853                 strcpy(xstats_names[count].name,
2854                         ena_stats_global_strings[stat].name);
2855
2856         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2857                 strcpy(xstats_names[count].name,
2858                         ena_stats_eni_strings[stat].name);
2859
2860         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2861                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2862                         snprintf(xstats_names[count].name,
2863                                 sizeof(xstats_names[count].name),
2864                                 "rx_q%d_%s", i,
2865                                 ena_stats_rx_strings[stat].name);
2866
2867         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2868                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2869                         snprintf(xstats_names[count].name,
2870                                 sizeof(xstats_names[count].name),
2871                                 "tx_q%d_%s", i,
2872                                 ena_stats_tx_strings[stat].name);
2873
2874         return xstats_count;
2875 }
2876
2877 /**
2878  * DPDK callback to get extended device statistics.
2879  *
2880  * @param dev
2881  *   Pointer to Ethernet device structure.
2882  * @param[out] stats
2883  *   Stats table output buffer.
2884  * @param n
2885  *   The size of the stats table.
2886  *
2887  * @return
2888  *   Number of xstats on success, negative on failure.
2889  */
2890 static int ena_xstats_get(struct rte_eth_dev *dev,
2891                           struct rte_eth_xstat *xstats,
2892                           unsigned int n)
2893 {
2894         struct ena_adapter *adapter = dev->data->dev_private;
2895         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2896         unsigned int stat, i, count = 0;
2897         int stat_offset;
2898         void *stats_begin;
2899
2900         if (n < xstats_count)
2901                 return xstats_count;
2902
2903         if (!xstats)
2904                 return 0;
2905
2906         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2907                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2908                 stats_begin = &adapter->dev_stats;
2909
2910                 xstats[count].id = count;
2911                 xstats[count].value = *((uint64_t *)
2912                         ((char *)stats_begin + stat_offset));
2913         }
2914
2915         /* Even if the function below fails, we should copy previous (or initial
2916          * values) to keep structure of rte_eth_xstat consistent.
2917          */
2918         ena_copy_eni_stats(adapter);
2919         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2920                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2921                 stats_begin = &adapter->eni_stats;
2922
2923                 xstats[count].id = count;
2924                 xstats[count].value = *((uint64_t *)
2925                     ((char *)stats_begin + stat_offset));
2926         }
2927
2928         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2929                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2930                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2931                         stats_begin = &adapter->rx_ring[i].rx_stats;
2932
2933                         xstats[count].id = count;
2934                         xstats[count].value = *((uint64_t *)
2935                                 ((char *)stats_begin + stat_offset));
2936                 }
2937         }
2938
2939         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2940                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2941                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2942                         stats_begin = &adapter->tx_ring[i].rx_stats;
2943
2944                         xstats[count].id = count;
2945                         xstats[count].value = *((uint64_t *)
2946                                 ((char *)stats_begin + stat_offset));
2947                 }
2948         }
2949
2950         return count;
2951 }
2952
2953 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2954                                 const uint64_t *ids,
2955                                 uint64_t *values,
2956                                 unsigned int n)
2957 {
2958         struct ena_adapter *adapter = dev->data->dev_private;
2959         uint64_t id;
2960         uint64_t rx_entries, tx_entries;
2961         unsigned int i;
2962         int qid;
2963         int valid = 0;
2964         bool was_eni_copied = false;
2965
2966         for (i = 0; i < n; ++i) {
2967                 id = ids[i];
2968                 /* Check if id belongs to global statistics */
2969                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2970                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2971                         ++valid;
2972                         continue;
2973                 }
2974
2975                 /* Check if id belongs to ENI statistics */
2976                 id -= ENA_STATS_ARRAY_GLOBAL;
2977                 if (id < ENA_STATS_ARRAY_ENI) {
2978                         /* Avoid reading ENI stats multiple times in a single
2979                          * function call, as it requires communication with the
2980                          * admin queue.
2981                          */
2982                         if (!was_eni_copied) {
2983                                 was_eni_copied = true;
2984                                 ena_copy_eni_stats(adapter);
2985                         }
2986                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2987                         ++valid;
2988                         continue;
2989                 }
2990
2991                 /* Check if id belongs to rx queue statistics */
2992                 id -= ENA_STATS_ARRAY_ENI;
2993                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2994                 if (id < rx_entries) {
2995                         qid = id % dev->data->nb_rx_queues;
2996                         id /= dev->data->nb_rx_queues;
2997                         values[i] = *((uint64_t *)
2998                                 &adapter->rx_ring[qid].rx_stats + id);
2999                         ++valid;
3000                         continue;
3001                 }
3002                                 /* Check if id belongs to rx queue statistics */
3003                 id -= rx_entries;
3004                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3005                 if (id < tx_entries) {
3006                         qid = id % dev->data->nb_tx_queues;
3007                         id /= dev->data->nb_tx_queues;
3008                         values[i] = *((uint64_t *)
3009                                 &adapter->tx_ring[qid].tx_stats + id);
3010                         ++valid;
3011                         continue;
3012                 }
3013         }
3014
3015         return valid;
3016 }
3017
3018 static int ena_process_bool_devarg(const char *key,
3019                                    const char *value,
3020                                    void *opaque)
3021 {
3022         struct ena_adapter *adapter = opaque;
3023         bool bool_value;
3024
3025         /* Parse the value. */
3026         if (strcmp(value, "1") == 0) {
3027                 bool_value = true;
3028         } else if (strcmp(value, "0") == 0) {
3029                 bool_value = false;
3030         } else {
3031                 PMD_INIT_LOG(ERR,
3032                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3033                         value, key);
3034                 return -EINVAL;
3035         }
3036
3037         /* Now, assign it to the proper adapter field. */
3038         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3039                 adapter->use_large_llq_hdr = bool_value;
3040
3041         return 0;
3042 }
3043
3044 static int ena_parse_devargs(struct ena_adapter *adapter,
3045                              struct rte_devargs *devargs)
3046 {
3047         static const char * const allowed_args[] = {
3048                 ENA_DEVARG_LARGE_LLQ_HDR,
3049                 NULL,
3050         };
3051         struct rte_kvargs *kvlist;
3052         int rc;
3053
3054         if (devargs == NULL)
3055                 return 0;
3056
3057         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3058         if (kvlist == NULL) {
3059                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3060                         devargs->args);
3061                 return -EINVAL;
3062         }
3063
3064         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3065                 ena_process_bool_devarg, adapter);
3066
3067         rte_kvargs_free(kvlist);
3068
3069         return rc;
3070 }
3071
3072 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3073 {
3074         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3075         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3076         int rc;
3077         uint16_t vectors_nb, i;
3078         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3079
3080         if (!rx_intr_requested)
3081                 return 0;
3082
3083         if (!rte_intr_cap_multiple(intr_handle)) {
3084                 PMD_DRV_LOG(ERR,
3085                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3086                 return -ENOTSUP;
3087         }
3088
3089         /* Disable interrupt mapping before the configuration starts. */
3090         rte_intr_disable(intr_handle);
3091
3092         /* Verify if there are enough vectors available. */
3093         vectors_nb = dev->data->nb_rx_queues;
3094         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3095                 PMD_DRV_LOG(ERR,
3096                         "Too many Rx interrupts requested, maximum number: %d\n",
3097                         RTE_MAX_RXTX_INTR_VEC_ID);
3098                 rc = -ENOTSUP;
3099                 goto enable_intr;
3100         }
3101
3102         /* Allocate the vector list */
3103         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3104                                            dev->data->nb_rx_queues)) {
3105                 PMD_DRV_LOG(ERR,
3106                         "Failed to allocate interrupt vector for %d queues\n",
3107                         dev->data->nb_rx_queues);
3108                 rc = -ENOMEM;
3109                 goto enable_intr;
3110         }
3111
3112         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3113         if (rc != 0)
3114                 goto free_intr_vec;
3115
3116         if (!rte_intr_allow_others(intr_handle)) {
3117                 PMD_DRV_LOG(ERR,
3118                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3119                 goto disable_intr_efd;
3120         }
3121
3122         for (i = 0; i < vectors_nb; ++i)
3123                 if (rte_intr_vec_list_index_set(intr_handle, i,
3124                                            RTE_INTR_VEC_RXTX_OFFSET + i))
3125                         goto disable_intr_efd;
3126
3127         rte_intr_enable(intr_handle);
3128         return 0;
3129
3130 disable_intr_efd:
3131         rte_intr_efd_disable(intr_handle);
3132 free_intr_vec:
3133         rte_intr_vec_list_free(intr_handle);
3134 enable_intr:
3135         rte_intr_enable(intr_handle);
3136         return rc;
3137 }
3138
3139 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3140                                  uint16_t queue_id,
3141                                  bool unmask)
3142 {
3143         struct ena_adapter *adapter = dev->data->dev_private;
3144         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3145         struct ena_eth_io_intr_reg intr_reg;
3146
3147         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3148         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3149 }
3150
3151 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3152                                     uint16_t queue_id)
3153 {
3154         ena_rx_queue_intr_set(dev, queue_id, true);
3155
3156         return 0;
3157 }
3158
3159 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3160                                      uint16_t queue_id)
3161 {
3162         ena_rx_queue_intr_set(dev, queue_id, false);
3163
3164         return 0;
3165 }
3166
3167 /*********************************************************************
3168  *  PMD configuration
3169  *********************************************************************/
3170 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3171         struct rte_pci_device *pci_dev)
3172 {
3173         return rte_eth_dev_pci_generic_probe(pci_dev,
3174                 sizeof(struct ena_adapter), eth_ena_dev_init);
3175 }
3176
3177 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3178 {
3179         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3180 }
3181
3182 static struct rte_pci_driver rte_ena_pmd = {
3183         .id_table = pci_id_ena_map,
3184         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3185                      RTE_PCI_DRV_WC_ACTIVATE,
3186         .probe = eth_ena_pci_probe,
3187         .remove = eth_ena_pci_remove,
3188 };
3189
3190 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3191 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3192 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3193 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3194 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3195 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3196 #ifdef RTE_ETHDEV_DEBUG_RX
3197 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3198 #endif
3199 #ifdef RTE_ETHDEV_DEBUG_TX
3200 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3201 #endif
3202 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3203
3204 /******************************************************************************
3205  ******************************** AENQ Handlers *******************************
3206  *****************************************************************************/
3207 static void ena_update_on_link_change(void *adapter_data,
3208                                       struct ena_admin_aenq_entry *aenq_e)
3209 {
3210         struct rte_eth_dev *eth_dev = adapter_data;
3211         struct ena_adapter *adapter = eth_dev->data->dev_private;
3212         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3213         uint32_t status;
3214
3215         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3216
3217         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3218         adapter->link_status = status;
3219
3220         ena_link_update(eth_dev, 0);
3221         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3222 }
3223
3224 static void ena_notification(void *adapter_data,
3225                              struct ena_admin_aenq_entry *aenq_e)
3226 {
3227         struct rte_eth_dev *eth_dev = adapter_data;
3228         struct ena_adapter *adapter = eth_dev->data->dev_private;
3229         struct ena_admin_ena_hw_hints *hints;
3230
3231         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3232                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3233                         aenq_e->aenq_common_desc.group,
3234                         ENA_ADMIN_NOTIFICATION);
3235
3236         switch (aenq_e->aenq_common_desc.syndrome) {
3237         case ENA_ADMIN_UPDATE_HINTS:
3238                 hints = (struct ena_admin_ena_hw_hints *)
3239                         (&aenq_e->inline_data_w4);
3240                 ena_update_hints(adapter, hints);
3241                 break;
3242         default:
3243                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3244                         aenq_e->aenq_common_desc.syndrome);
3245         }
3246 }
3247
3248 static void ena_keep_alive(void *adapter_data,
3249                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3250 {
3251         struct rte_eth_dev *eth_dev = adapter_data;
3252         struct ena_adapter *adapter = eth_dev->data->dev_private;
3253         struct ena_admin_aenq_keep_alive_desc *desc;
3254         uint64_t rx_drops;
3255         uint64_t tx_drops;
3256
3257         adapter->timestamp_wd = rte_get_timer_cycles();
3258
3259         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3260         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3261         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3262
3263         adapter->drv_stats->rx_drops = rx_drops;
3264         adapter->dev_stats.tx_drops = tx_drops;
3265 }
3266
3267 /**
3268  * This handler will called for unknown event group or unimplemented handlers
3269  **/
3270 static void unimplemented_aenq_handler(__rte_unused void *data,
3271                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3272 {
3273         PMD_DRV_LOG(ERR,
3274                 "Unknown event was received or event with unimplemented handler\n");
3275 }
3276
3277 static struct ena_aenq_handlers aenq_handlers = {
3278         .handlers = {
3279                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3280                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3281                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3282         },
3283         .unimplemented_handler = unimplemented_aenq_handler
3284 };