drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <ethdev_driver.h>
   9 #include <ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    3
  31 #define DRV_MODULE_VER_SUBMINOR 0
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) RTE_DIM(x)
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  55
  56 enum ethtool_stringset {
  57         ETH_SS_TEST             = 0,
  58         ETH_SS_STATS,
  59 };
  60
  61 struct ena_stats {
  62         char name[ETH_GSTRING_LEN];
  63         int stat_offset;
  64 };
  65
  66 #define ENA_STAT_ENTRY(stat, stat_type) { \
  67         .name = #stat, \
  68         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  69 }
  70
  71 #define ENA_STAT_RX_ENTRY(stat) \
  72         ENA_STAT_ENTRY(stat, rx)
  73
  74 #define ENA_STAT_TX_ENTRY(stat) \
  75         ENA_STAT_ENTRY(stat, tx)
  76
  77 #define ENA_STAT_ENI_ENTRY(stat) \
  78         ENA_STAT_ENTRY(stat, eni)
  79
  80 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  81         ENA_STAT_ENTRY(stat, dev)
  82
  83 /* Device arguments */
  84 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  85
  86 /*
  87  * Each rte_memzone should have unique name.
  88  * To satisfy it, count number of allocation and add it to name.
  89  */
  90 rte_atomic64_t ena_alloc_cnt;
  91
  92 static const struct ena_stats ena_stats_global_strings[] = {
  93         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  94         ENA_STAT_GLOBAL_ENTRY(dev_start),
  95         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  96         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  97 };
  98
  99 static const struct ena_stats ena_stats_eni_strings[] = {
 100         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
 101         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
 102         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
 103         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
 104         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
 105 };
 106
 107 static const struct ena_stats ena_stats_tx_strings[] = {
 108         ENA_STAT_TX_ENTRY(cnt),
 109         ENA_STAT_TX_ENTRY(bytes),
 110         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 111         ENA_STAT_TX_ENTRY(linearize),
 112         ENA_STAT_TX_ENTRY(linearize_failed),
 113         ENA_STAT_TX_ENTRY(tx_poll),
 114         ENA_STAT_TX_ENTRY(doorbells),
 115         ENA_STAT_TX_ENTRY(bad_req_id),
 116         ENA_STAT_TX_ENTRY(available_desc),
 117 };
 118
 119 static const struct ena_stats ena_stats_rx_strings[] = {
 120         ENA_STAT_RX_ENTRY(cnt),
 121         ENA_STAT_RX_ENTRY(bytes),
 122         ENA_STAT_RX_ENTRY(refill_partial),
 123         ENA_STAT_RX_ENTRY(bad_csum),
 124         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 125         ENA_STAT_RX_ENTRY(bad_desc_num),
 126         ENA_STAT_RX_ENTRY(bad_req_id),
 127 };
 128
 129 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 130 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 131 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 132 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 133
 134 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 135                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 136                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 137                         DEV_TX_OFFLOAD_TCP_TSO)
 138 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 139                        PKT_TX_IP_CKSUM |\
 140                        PKT_TX_TCP_SEG)
 141
 142 /** Vendor ID used by Amazon devices */
 143 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 144 /** Amazon devices */
 145 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 146 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 147
 148 #define ENA_TX_OFFLOAD_MASK     (\
 149         PKT_TX_L4_MASK |         \
 150         PKT_TX_IPV6 |            \
 151         PKT_TX_IPV4 |            \
 152         PKT_TX_IP_CKSUM |        \
 153         PKT_TX_TCP_SEG)
 154
 155 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 156         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 157
 158 static const struct rte_pci_id pci_id_ena_map[] = {
 159         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 160         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 161         { .device_id = 0 },
 162 };
 163
 164 static struct ena_aenq_handlers aenq_handlers;
 165
 166 static int ena_device_init(struct ena_com_dev *ena_dev,
 167                            struct rte_pci_device *pdev,
 168                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 169                            bool *wd_state);
 170 static int ena_dev_configure(struct rte_eth_dev *dev);
 171 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 172         struct ena_tx_buffer *tx_info,
 173         struct rte_mbuf *mbuf,
 174         void **push_header,
 175         uint16_t *header_len);
 176 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 177 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 179                                   uint16_t nb_pkts);
 180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                 uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 190 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 191                                     struct ena_com_rx_buf_info *ena_bufs,
 192                                     uint32_t descs,
 193                                     uint16_t *next_to_clean,
 194                                     uint8_t offset);
 195 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 196                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 197 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 198                                   struct rte_mbuf *mbuf, uint16_t id);
 199 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 200 static void ena_init_rings(struct ena_adapter *adapter,
 201                            bool disable_meta_caching);
 202 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 203 static int ena_start(struct rte_eth_dev *dev);
 204 static int ena_stop(struct rte_eth_dev *dev);
 205 static int ena_close(struct rte_eth_dev *dev);
 206 static int ena_dev_reset(struct rte_eth_dev *dev);
 207 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 208 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 209 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_rx_queue_release(void *queue);
 211 static void ena_tx_queue_release(void *queue);
 212 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 213 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 214 static int ena_link_update(struct rte_eth_dev *dev,
 215                            int wait_to_complete);
 216 static int ena_create_io_queue(struct ena_ring *ring);
 217 static void ena_queue_stop(struct ena_ring *ring);
 218 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 219                               enum ena_ring_type ring_type);
 220 static int ena_queue_start(struct ena_ring *ring);
 221 static int ena_queue_start_all(struct rte_eth_dev *dev,
 222                                enum ena_ring_type ring_type);
 223 static void ena_stats_restart(struct rte_eth_dev *dev);
 224 static int ena_infos_get(struct rte_eth_dev *dev,
 225                          struct rte_eth_dev_info *dev_info);
 226 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 227                                struct rte_eth_rss_reta_entry64 *reta_conf,
 228                                uint16_t reta_size);
 229 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 230                               struct rte_eth_rss_reta_entry64 *reta_conf,
 231                               uint16_t reta_size);
 232 static void ena_interrupt_handler_rte(void *cb_arg);
 233 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 234 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 235 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 236 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 237                                 struct rte_eth_xstat_name *xstats_names,
 238                                 unsigned int n);
 239 static int ena_xstats_get(struct rte_eth_dev *dev,
 240                           struct rte_eth_xstat *stats,
 241                           unsigned int n);
 242 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 243                                 const uint64_t *ids,
 244                                 uint64_t *values,
 245                                 unsigned int n);
 246 static int ena_process_bool_devarg(const char *key,
 247                                    const char *value,
 248                                    void *opaque);
 249 static int ena_parse_devargs(struct ena_adapter *adapter,
 250                              struct rte_devargs *devargs);
 251 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 252
 253 static const struct eth_dev_ops ena_dev_ops = {
 254         .dev_configure        = ena_dev_configure,
 255         .dev_infos_get        = ena_infos_get,
 256         .rx_queue_setup       = ena_rx_queue_setup,
 257         .tx_queue_setup       = ena_tx_queue_setup,
 258         .dev_start            = ena_start,
 259         .dev_stop             = ena_stop,
 260         .link_update          = ena_link_update,
 261         .stats_get            = ena_stats_get,
 262         .xstats_get_names     = ena_xstats_get_names,
 263         .xstats_get           = ena_xstats_get,
 264         .xstats_get_by_id     = ena_xstats_get_by_id,
 265         .mtu_set              = ena_mtu_set,
 266         .rx_queue_release     = ena_rx_queue_release,
 267         .tx_queue_release     = ena_tx_queue_release,
 268         .dev_close            = ena_close,
 269         .dev_reset            = ena_dev_reset,
 270         .reta_update          = ena_rss_reta_update,
 271         .reta_query           = ena_rss_reta_query,
 272 };
 273
 274 void ena_rss_key_fill(void *key, size_t size)
 275 {
 276         static bool key_generated;
 277         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 278         size_t i;
 279
 280         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 281
 282         if (!key_generated) {
 283                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 284                         default_key[i] = rte_rand() & 0xff;
 285                 key_generated = true;
 286         }
 287
 288         rte_memcpy(key, default_key, size);
 289 }
 290
 291 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 292                                        struct ena_com_rx_ctx *ena_rx_ctx)
 293 {
 294         uint64_t ol_flags = 0;
 295         uint32_t packet_type = 0;
 296
 297         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 298                 packet_type |= RTE_PTYPE_L4_TCP;
 299         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 300                 packet_type |= RTE_PTYPE_L4_UDP;
 301
 302         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 303                 packet_type |= RTE_PTYPE_L3_IPV4;
 304                 if (unlikely(ena_rx_ctx->l3_csum_err))
 305                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 306                 else
 307                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 308         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 309                 packet_type |= RTE_PTYPE_L3_IPV6;
 310         }
 311
 312         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 313                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 314         else
 315                 if (unlikely(ena_rx_ctx->l4_csum_err))
 316                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 317                 else
 318                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 319
 320         if (likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 321                 ol_flags |= PKT_RX_RSS_HASH;
 322                 mbuf->hash.rss = ena_rx_ctx->hash;
 323         }
 324
 325         mbuf->ol_flags = ol_flags;
 326         mbuf->packet_type = packet_type;
 327 }
 328
 329 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 330                                        struct ena_com_tx_ctx *ena_tx_ctx,
 331                                        uint64_t queue_offloads,
 332                                        bool disable_meta_caching)
 333 {
 334         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 335
 336         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 337             (queue_offloads & QUEUE_OFFLOADS)) {
 338                 /* check if TSO is required */
 339                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 340                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 341                         ena_tx_ctx->tso_enable = true;
 342
 343                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 344                 }
 345
 346                 /* check if L3 checksum is needed */
 347                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 348                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 349                         ena_tx_ctx->l3_csum_enable = true;
 350
 351                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 352                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 353                 } else {
 354                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 355
 356                         /* set don't fragment (DF) flag */
 357                         if (mbuf->packet_type &
 358                                 (RTE_PTYPE_L4_NONFRAG
 359                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 360                                 ena_tx_ctx->df = true;
 361                 }
 362
 363                 /* check if L4 checksum is needed */
 364                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 365                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 366                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 367                         ena_tx_ctx->l4_csum_enable = true;
 368                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 369                                 PKT_TX_UDP_CKSUM) &&
 370                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 371                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 372                         ena_tx_ctx->l4_csum_enable = true;
 373                 } else {
 374                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 375                         ena_tx_ctx->l4_csum_enable = false;
 376                 }
 377
 378                 ena_meta->mss = mbuf->tso_segsz;
 379                 ena_meta->l3_hdr_len = mbuf->l3_len;
 380                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 381
 382                 ena_tx_ctx->meta_valid = true;
 383         } else if (disable_meta_caching) {
 384                 memset(ena_meta, 0, sizeof(*ena_meta));
 385                 ena_tx_ctx->meta_valid = true;
 386         } else {
 387                 ena_tx_ctx->meta_valid = false;
 388         }
 389 }
 390
 391 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 392 {
 393         struct ena_tx_buffer *tx_info = NULL;
 394
 395         if (likely(req_id < tx_ring->ring_size)) {
 396                 tx_info = &tx_ring->tx_buffer_info[req_id];
 397                 if (likely(tx_info->mbuf))
 398                         return 0;
 399         }
 400
 401         if (tx_info)
 402                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 403         else
 404                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 405
 406         /* Trigger device reset */
 407         ++tx_ring->tx_stats.bad_req_id;
 408         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 409         tx_ring->adapter->trigger_reset = true;
 410         return -EFAULT;
 411 }
 412
 413 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 414 {
 415         struct ena_admin_host_info *host_info;
 416         int rc;
 417
 418         /* Allocate only the host info */
 419         rc = ena_com_allocate_host_info(ena_dev);
 420         if (rc) {
 421                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 422                 return;
 423         }
 424
 425         host_info = ena_dev->host_attr.host_info;
 426
 427         host_info->os_type = ENA_ADMIN_OS_DPDK;
 428         host_info->kernel_ver = RTE_VERSION;
 429         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 430                 sizeof(host_info->kernel_ver_str));
 431         host_info->os_dist = RTE_VERSION;
 432         strlcpy((char *)host_info->os_dist_str, rte_version(),
 433                 sizeof(host_info->os_dist_str));
 434         host_info->driver_version =
 435                 (DRV_MODULE_VER_MAJOR) |
 436                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 437                 (DRV_MODULE_VER_SUBMINOR <<
 438                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 439         host_info->num_cpus = rte_lcore_count();
 440
 441         host_info->driver_supported_features =
 442                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 443
 444         rc = ena_com_set_host_attributes(ena_dev);
 445         if (rc) {
 446                 if (rc == -ENA_COM_UNSUPPORTED)
 447                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 448                 else
 449                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 450
 451                 goto err;
 452         }
 453
 454         return;
 455
 456 err:
 457         ena_com_delete_host_info(ena_dev);
 458 }
 459
 460 /* This function calculates the number of xstats based on the current config */
 461 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 462 {
 463         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 464                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 465                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 466 }
 467
 468 static void ena_config_debug_area(struct ena_adapter *adapter)
 469 {
 470         u32 debug_area_size;
 471         int rc, ss_count;
 472
 473         ss_count = ena_xstats_calc_num(adapter->edev_data);
 474
 475         /* allocate 32 bytes for each string and 64bit for the value */
 476         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 477
 478         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 479         if (rc) {
 480                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 481                 return;
 482         }
 483
 484         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 485         if (rc) {
 486                 if (rc == -ENA_COM_UNSUPPORTED)
 487                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 488                 else
 489                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 490
 491                 goto err;
 492         }
 493
 494         return;
 495 err:
 496         ena_com_delete_debug_area(&adapter->ena_dev);
 497 }
 498
 499 static int ena_close(struct rte_eth_dev *dev)
 500 {
 501         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 502         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 503         struct ena_adapter *adapter = dev->data->dev_private;
 504         int ret = 0;
 505
 506         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 507                 return 0;
 508
 509         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 510                 ret = ena_stop(dev);
 511         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 512
 513         ena_rx_queue_release_all(dev);
 514         ena_tx_queue_release_all(dev);
 515
 516         rte_free(adapter->drv_stats);
 517         adapter->drv_stats = NULL;
 518
 519         rte_intr_disable(intr_handle);
 520         rte_intr_callback_unregister(intr_handle,
 521                                      ena_interrupt_handler_rte,
 522                                      dev);
 523
 524         /*
 525          * MAC is not allocated dynamically. Setting NULL should prevent from
 526          * release of the resource in the rte_eth_dev_release_port().
 527          */
 528         dev->data->mac_addrs = NULL;
 529
 530         return ret;
 531 }
 532
 533 static int
 534 ena_dev_reset(struct rte_eth_dev *dev)
 535 {
 536         int rc = 0;
 537
 538         ena_destroy_device(dev);
 539         rc = eth_ena_dev_init(dev);
 540         if (rc)
 541                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 542
 543         return rc;
 544 }
 545
 546 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 547                                struct rte_eth_rss_reta_entry64 *reta_conf,
 548                                uint16_t reta_size)
 549 {
 550         struct ena_adapter *adapter = dev->data->dev_private;
 551         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 552         int rc, i;
 553         u16 entry_value;
 554         int conf_idx;
 555         int idx;
 556
 557         if ((reta_size == 0) || (reta_conf == NULL))
 558                 return -EINVAL;
 559
 560         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 561                 PMD_DRV_LOG(WARNING,
 562                         "indirection table %d is bigger than supported (%d)\n",
 563                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 564                 return -EINVAL;
 565         }
 566
 567         for (i = 0 ; i < reta_size ; i++) {
 568                 /* each reta_conf is for 64 entries.
 569                  * to support 128 we use 2 conf of 64
 570                  */
 571                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 572                 idx = i % RTE_RETA_GROUP_SIZE;
 573                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 574                         entry_value =
 575                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 576
 577                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 578                                                                i,
 579                                                                entry_value);
 580                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 581                                 PMD_DRV_LOG(ERR,
 582                                         "Cannot fill indirect table\n");
 583                                 return rc;
 584                         }
 585                 }
 586         }
 587
 588         rte_spinlock_lock(&adapter->admin_lock);
 589         rc = ena_com_indirect_table_set(ena_dev);
 590         rte_spinlock_unlock(&adapter->admin_lock);
 591         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 592                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 593                 return rc;
 594         }
 595
 596         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 597                 __func__, reta_size, dev->data->port_id);
 598
 599         return 0;
 600 }
 601
 602 /* Query redirection table. */
 603 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 604                               struct rte_eth_rss_reta_entry64 *reta_conf,
 605                               uint16_t reta_size)
 606 {
 607         struct ena_adapter *adapter = dev->data->dev_private;
 608         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 609         int rc;
 610         int i;
 611         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 612         int reta_conf_idx;
 613         int reta_idx;
 614
 615         if (reta_size == 0 || reta_conf == NULL ||
 616             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 617                 return -EINVAL;
 618
 619         rte_spinlock_lock(&adapter->admin_lock);
 620         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 621         rte_spinlock_unlock(&adapter->admin_lock);
 622         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 623                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 624                 return -ENOTSUP;
 625         }
 626
 627         for (i = 0 ; i < reta_size ; i++) {
 628                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 629                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 630                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 631                         reta_conf[reta_conf_idx].reta[reta_idx] =
 632                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int ena_rss_init_default(struct ena_adapter *adapter)
 639 {
 640         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 641         uint16_t nb_rx_queues = adapter->edev_data->nb_rx_queues;
 642         int rc, i;
 643         u32 val;
 644
 645         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 646         if (unlikely(rc)) {
 647                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 648                 goto err_rss_init;
 649         }
 650
 651         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 652                 val = i % nb_rx_queues;
 653                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 654                                                        ENA_IO_RXQ_IDX(val));
 655                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 656                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 657                         goto err_fill_indir;
 658                 }
 659         }
 660
 661         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 662                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 663         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 664                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 665                 goto err_fill_indir;
 666         }
 667
 668         rc = ena_com_set_default_hash_ctrl(ena_dev);
 669         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 670                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 671                 goto err_fill_indir;
 672         }
 673
 674         rc = ena_com_indirect_table_set(ena_dev);
 675         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 676                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 677                 goto err_fill_indir;
 678         }
 679         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 680                 adapter->edev_data->port_id);
 681
 682         return 0;
 683
 684 err_fill_indir:
 685         ena_com_rss_destroy(ena_dev);
 686 err_rss_init:
 687
 688         return rc;
 689 }
 690
 691 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 692 {
 693         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 694         int nb_queues = dev->data->nb_rx_queues;
 695         int i;
 696
 697         for (i = 0; i < nb_queues; i++)
 698                 ena_rx_queue_release(queues[i]);
 699 }
 700
 701 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 702 {
 703         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 704         int nb_queues = dev->data->nb_tx_queues;
 705         int i;
 706
 707         for (i = 0; i < nb_queues; i++)
 708                 ena_tx_queue_release(queues[i]);
 709 }
 710
 711 static void ena_rx_queue_release(void *queue)
 712 {
 713         struct ena_ring *ring = (struct ena_ring *)queue;
 714
 715         /* Free ring resources */
 716         if (ring->rx_buffer_info)
 717                 rte_free(ring->rx_buffer_info);
 718         ring->rx_buffer_info = NULL;
 719
 720         if (ring->rx_refill_buffer)
 721                 rte_free(ring->rx_refill_buffer);
 722         ring->rx_refill_buffer = NULL;
 723
 724         if (ring->empty_rx_reqs)
 725                 rte_free(ring->empty_rx_reqs);
 726         ring->empty_rx_reqs = NULL;
 727
 728         ring->configured = 0;
 729
 730         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 731                 ring->port_id, ring->id);
 732 }
 733
 734 static void ena_tx_queue_release(void *queue)
 735 {
 736         struct ena_ring *ring = (struct ena_ring *)queue;
 737
 738         /* Free ring resources */
 739         if (ring->push_buf_intermediate_buf)
 740                 rte_free(ring->push_buf_intermediate_buf);
 741
 742         if (ring->tx_buffer_info)
 743                 rte_free(ring->tx_buffer_info);
 744
 745         if (ring->empty_tx_reqs)
 746                 rte_free(ring->empty_tx_reqs);
 747
 748         ring->empty_tx_reqs = NULL;
 749         ring->tx_buffer_info = NULL;
 750         ring->push_buf_intermediate_buf = NULL;
 751
 752         ring->configured = 0;
 753
 754         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 755                 ring->port_id, ring->id);
 756 }
 757
 758 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 759 {
 760         unsigned int i;
 761
 762         for (i = 0; i < ring->ring_size; ++i) {
 763                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 764                 if (rx_info->mbuf) {
 765                         rte_mbuf_raw_free(rx_info->mbuf);
 766                         rx_info->mbuf = NULL;
 767                 }
 768         }
 769 }
 770
 771 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 772 {
 773         unsigned int i;
 774
 775         for (i = 0; i < ring->ring_size; ++i) {
 776                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 777
 778                 if (tx_buf->mbuf) {
 779                         rte_pktmbuf_free(tx_buf->mbuf);
 780                         tx_buf->mbuf = NULL;
 781                 }
 782         }
 783 }
 784
 785 static int ena_link_update(struct rte_eth_dev *dev,
 786                            __rte_unused int wait_to_complete)
 787 {
 788         struct rte_eth_link *link = &dev->data->dev_link;
 789         struct ena_adapter *adapter = dev->data->dev_private;
 790
 791         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 792         link->link_speed = ETH_SPEED_NUM_NONE;
 793         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 794
 795         return 0;
 796 }
 797
 798 static int ena_queue_start_all(struct rte_eth_dev *dev,
 799                                enum ena_ring_type ring_type)
 800 {
 801         struct ena_adapter *adapter = dev->data->dev_private;
 802         struct ena_ring *queues = NULL;
 803         int nb_queues;
 804         int i = 0;
 805         int rc = 0;
 806
 807         if (ring_type == ENA_RING_TYPE_RX) {
 808                 queues = adapter->rx_ring;
 809                 nb_queues = dev->data->nb_rx_queues;
 810         } else {
 811                 queues = adapter->tx_ring;
 812                 nb_queues = dev->data->nb_tx_queues;
 813         }
 814         for (i = 0; i < nb_queues; i++) {
 815                 if (queues[i].configured) {
 816                         if (ring_type == ENA_RING_TYPE_RX) {
 817                                 ena_assert_msg(
 818                                         dev->data->rx_queues[i] == &queues[i],
 819                                         "Inconsistent state of rx queues\n");
 820                         } else {
 821                                 ena_assert_msg(
 822                                         dev->data->tx_queues[i] == &queues[i],
 823                                         "Inconsistent state of tx queues\n");
 824                         }
 825
 826                         rc = ena_queue_start(&queues[i]);
 827
 828                         if (rc) {
 829                                 PMD_INIT_LOG(ERR,
 830                                              "failed to start queue %d type(%d)",
 831                                              i, ring_type);
 832                                 goto err;
 833                         }
 834                 }
 835         }
 836
 837         return 0;
 838
 839 err:
 840         while (i--)
 841                 if (queues[i].configured)
 842                         ena_queue_stop(&queues[i]);
 843
 844         return rc;
 845 }
 846
 847 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 848 {
 849         uint32_t max_frame_len = adapter->max_mtu;
 850
 851         if (adapter->edev_data->dev_conf.rxmode.offloads &
 852             DEV_RX_OFFLOAD_JUMBO_FRAME)
 853                 max_frame_len =
 854                         adapter->edev_data->dev_conf.rxmode.max_rx_pkt_len;
 855
 856         return max_frame_len;
 857 }
 858
 859 static int ena_check_valid_conf(struct ena_adapter *adapter)
 860 {
 861         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 862
 863         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 864                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 865                                   "max mtu: %d, min mtu: %d",
 866                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 867                 return ENA_COM_UNSUPPORTED;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int
 874 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 875                        bool use_large_llq_hdr)
 876 {
 877         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 878         struct ena_com_dev *ena_dev = ctx->ena_dev;
 879         uint32_t max_tx_queue_size;
 880         uint32_t max_rx_queue_size;
 881
 882         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 883                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 884                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 885                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 886                         max_queue_ext->max_rx_sq_depth);
 887                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 888
 889                 if (ena_dev->tx_mem_queue_type ==
 890                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 891                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 892                                 llq->max_llq_depth);
 893                 } else {
 894                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 895                                 max_queue_ext->max_tx_sq_depth);
 896                 }
 897
 898                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 899                         max_queue_ext->max_per_packet_rx_descs);
 900                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 901                         max_queue_ext->max_per_packet_tx_descs);
 902         } else {
 903                 struct ena_admin_queue_feature_desc *max_queues =
 904                         &ctx->get_feat_ctx->max_queues;
 905                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 906                         max_queues->max_sq_depth);
 907                 max_tx_queue_size = max_queues->max_cq_depth;
 908
 909                 if (ena_dev->tx_mem_queue_type ==
 910                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 911                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 912                                 llq->max_llq_depth);
 913                 } else {
 914                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 915                                 max_queues->max_sq_depth);
 916                 }
 917
 918                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 919                         max_queues->max_packet_rx_descs);
 920                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 921                         max_queues->max_packet_tx_descs);
 922         }
 923
 924         /* Round down to the nearest power of 2 */
 925         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 926         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 927
 928         if (use_large_llq_hdr) {
 929                 if ((llq->entry_size_ctrl_supported &
 930                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 931                     (ena_dev->tx_mem_queue_type ==
 932                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 933                         max_tx_queue_size /= 2;
 934                         PMD_INIT_LOG(INFO,
 935                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 936                                 max_tx_queue_size);
 937                 } else {
 938                         PMD_INIT_LOG(ERR,
 939                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 940                 }
 941         }
 942
 943         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 944                 PMD_INIT_LOG(ERR, "Invalid queue size");
 945                 return -EFAULT;
 946         }
 947
 948         ctx->max_tx_queue_size = max_tx_queue_size;
 949         ctx->max_rx_queue_size = max_rx_queue_size;
 950
 951         return 0;
 952 }
 953
 954 static void ena_stats_restart(struct rte_eth_dev *dev)
 955 {
 956         struct ena_adapter *adapter = dev->data->dev_private;
 957
 958         rte_atomic64_init(&adapter->drv_stats->ierrors);
 959         rte_atomic64_init(&adapter->drv_stats->oerrors);
 960         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 961         adapter->drv_stats->rx_drops = 0;
 962 }
 963
 964 static int ena_stats_get(struct rte_eth_dev *dev,
 965                           struct rte_eth_stats *stats)
 966 {
 967         struct ena_admin_basic_stats ena_stats;
 968         struct ena_adapter *adapter = dev->data->dev_private;
 969         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 970         int rc;
 971         int i;
 972         int max_rings_stats;
 973
 974         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 975                 return -ENOTSUP;
 976
 977         memset(&ena_stats, 0, sizeof(ena_stats));
 978
 979         rte_spinlock_lock(&adapter->admin_lock);
 980         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 981         rte_spinlock_unlock(&adapter->admin_lock);
 982         if (unlikely(rc)) {
 983                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 984                 return rc;
 985         }
 986
 987         /* Set of basic statistics from ENA */
 988         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 989                                           ena_stats.rx_pkts_low);
 990         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 991                                           ena_stats.tx_pkts_low);
 992         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 993                                         ena_stats.rx_bytes_low);
 994         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 995                                         ena_stats.tx_bytes_low);
 996
 997         /* Driver related stats */
 998         stats->imissed = adapter->drv_stats->rx_drops;
 999         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1000         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1001         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1002
1003         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1004                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1005         for (i = 0; i < max_rings_stats; ++i) {
1006                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1007
1008                 stats->q_ibytes[i] = rx_stats->bytes;
1009                 stats->q_ipackets[i] = rx_stats->cnt;
1010                 stats->q_errors[i] = rx_stats->bad_desc_num +
1011                         rx_stats->bad_req_id;
1012         }
1013
1014         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1015                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1016         for (i = 0; i < max_rings_stats; ++i) {
1017                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1018
1019                 stats->q_obytes[i] = tx_stats->bytes;
1020                 stats->q_opackets[i] = tx_stats->cnt;
1021         }
1022
1023         return 0;
1024 }
1025
1026 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1027 {
1028         struct ena_adapter *adapter;
1029         struct ena_com_dev *ena_dev;
1030         int rc = 0;
1031
1032         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1033         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1034         adapter = dev->data->dev_private;
1035
1036         ena_dev = &adapter->ena_dev;
1037         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1038
1039         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1040                 PMD_DRV_LOG(ERR,
1041                         "Invalid MTU setting. new_mtu: %d "
1042                         "max mtu: %d min mtu: %d\n",
1043                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1044                 return -EINVAL;
1045         }
1046
1047         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1048         if (rc)
1049                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1050         else
1051                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1052
1053         return rc;
1054 }
1055
1056 static int ena_start(struct rte_eth_dev *dev)
1057 {
1058         struct ena_adapter *adapter = dev->data->dev_private;
1059         uint64_t ticks;
1060         int rc = 0;
1061
1062         rc = ena_check_valid_conf(adapter);
1063         if (rc)
1064                 return rc;
1065
1066         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1067         if (rc)
1068                 return rc;
1069
1070         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1071         if (rc)
1072                 goto err_start_tx;
1073
1074         if (adapter->edev_data->dev_conf.rxmode.mq_mode &
1075             ETH_MQ_RX_RSS_FLAG && adapter->edev_data->nb_rx_queues > 0) {
1076                 rc = ena_rss_init_default(adapter);
1077                 if (rc)
1078                         goto err_rss_init;
1079         }
1080
1081         ena_stats_restart(dev);
1082
1083         adapter->timestamp_wd = rte_get_timer_cycles();
1084         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1085
1086         ticks = rte_get_timer_hz();
1087         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1088                         ena_timer_wd_callback, dev);
1089
1090         ++adapter->dev_stats.dev_start;
1091         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1092
1093         return 0;
1094
1095 err_rss_init:
1096         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1097 err_start_tx:
1098         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1099         return rc;
1100 }
1101
1102 static int ena_stop(struct rte_eth_dev *dev)
1103 {
1104         struct ena_adapter *adapter = dev->data->dev_private;
1105         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1106         int rc;
1107
1108         rte_timer_stop_sync(&adapter->timer_wd);
1109         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1110         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1111
1112         if (adapter->trigger_reset) {
1113                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1114                 if (rc)
1115                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1116         }
1117
1118         ++adapter->dev_stats.dev_stop;
1119         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1120         dev->data->dev_started = 0;
1121
1122         return 0;
1123 }
1124
1125 static int ena_create_io_queue(struct ena_ring *ring)
1126 {
1127         struct ena_adapter *adapter;
1128         struct ena_com_dev *ena_dev;
1129         struct ena_com_create_io_ctx ctx =
1130                 /* policy set to _HOST just to satisfy icc compiler */
1131                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1132                   0, 0, 0, 0, 0 };
1133         uint16_t ena_qid;
1134         unsigned int i;
1135         int rc;
1136
1137         adapter = ring->adapter;
1138         ena_dev = &adapter->ena_dev;
1139
1140         if (ring->type == ENA_RING_TYPE_TX) {
1141                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1142                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1143                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1144                 for (i = 0; i < ring->ring_size; i++)
1145                         ring->empty_tx_reqs[i] = i;
1146         } else {
1147                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1148                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1149                 for (i = 0; i < ring->ring_size; i++)
1150                         ring->empty_rx_reqs[i] = i;
1151         }
1152         ctx.queue_size = ring->ring_size;
1153         ctx.qid = ena_qid;
1154         ctx.msix_vector = -1; /* interrupts not used */
1155         ctx.numa_node = ring->numa_socket_id;
1156
1157         rc = ena_com_create_io_queue(ena_dev, &ctx);
1158         if (rc) {
1159                 PMD_DRV_LOG(ERR,
1160                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1161                         ring->id, ena_qid, rc);
1162                 return rc;
1163         }
1164
1165         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1166                                      &ring->ena_com_io_sq,
1167                                      &ring->ena_com_io_cq);
1168         if (rc) {
1169                 PMD_DRV_LOG(ERR,
1170                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1171                         ring->id, rc);
1172                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1173                 return rc;
1174         }
1175
1176         if (ring->type == ENA_RING_TYPE_TX)
1177                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1178
1179         return 0;
1180 }
1181
1182 static void ena_queue_stop(struct ena_ring *ring)
1183 {
1184         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1185
1186         if (ring->type == ENA_RING_TYPE_RX) {
1187                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1188                 ena_rx_queue_release_bufs(ring);
1189         } else {
1190                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1191                 ena_tx_queue_release_bufs(ring);
1192         }
1193 }
1194
1195 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1196                               enum ena_ring_type ring_type)
1197 {
1198         struct ena_adapter *adapter = dev->data->dev_private;
1199         struct ena_ring *queues = NULL;
1200         uint16_t nb_queues, i;
1201
1202         if (ring_type == ENA_RING_TYPE_RX) {
1203                 queues = adapter->rx_ring;
1204                 nb_queues = dev->data->nb_rx_queues;
1205         } else {
1206                 queues = adapter->tx_ring;
1207                 nb_queues = dev->data->nb_tx_queues;
1208         }
1209
1210         for (i = 0; i < nb_queues; ++i)
1211                 if (queues[i].configured)
1212                         ena_queue_stop(&queues[i]);
1213 }
1214
1215 static int ena_queue_start(struct ena_ring *ring)
1216 {
1217         int rc, bufs_num;
1218
1219         ena_assert_msg(ring->configured == 1,
1220                        "Trying to start unconfigured queue\n");
1221
1222         rc = ena_create_io_queue(ring);
1223         if (rc) {
1224                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1225                 return rc;
1226         }
1227
1228         ring->next_to_clean = 0;
1229         ring->next_to_use = 0;
1230
1231         if (ring->type == ENA_RING_TYPE_TX) {
1232                 ring->tx_stats.available_desc =
1233                         ena_com_free_q_entries(ring->ena_com_io_sq);
1234                 return 0;
1235         }
1236
1237         bufs_num = ring->ring_size - 1;
1238         rc = ena_populate_rx_queue(ring, bufs_num);
1239         if (rc != bufs_num) {
1240                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1241                                          ENA_IO_RXQ_IDX(ring->id));
1242                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1243                 return ENA_COM_FAULT;
1244         }
1245         /* Flush per-core RX buffers pools cache as they can be used on other
1246          * cores as well.
1247          */
1248         rte_mempool_cache_flush(NULL, ring->mb_pool);
1249
1250         return 0;
1251 }
1252
1253 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1254                               uint16_t queue_idx,
1255                               uint16_t nb_desc,
1256                               unsigned int socket_id,
1257                               const struct rte_eth_txconf *tx_conf)
1258 {
1259         struct ena_ring *txq = NULL;
1260         struct ena_adapter *adapter = dev->data->dev_private;
1261         unsigned int i;
1262
1263         txq = &adapter->tx_ring[queue_idx];
1264
1265         if (txq->configured) {
1266                 PMD_DRV_LOG(CRIT,
1267                         "API violation. Queue %d is already configured\n",
1268                         queue_idx);
1269                 return ENA_COM_FAULT;
1270         }
1271
1272         if (!rte_is_power_of_2(nb_desc)) {
1273                 PMD_DRV_LOG(ERR,
1274                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1275                         nb_desc);
1276                 return -EINVAL;
1277         }
1278
1279         if (nb_desc > adapter->max_tx_ring_size) {
1280                 PMD_DRV_LOG(ERR,
1281                         "Unsupported size of TX queue (max size: %d)\n",
1282                         adapter->max_tx_ring_size);
1283                 return -EINVAL;
1284         }
1285
1286         txq->port_id = dev->data->port_id;
1287         txq->next_to_clean = 0;
1288         txq->next_to_use = 0;
1289         txq->ring_size = nb_desc;
1290         txq->size_mask = nb_desc - 1;
1291         txq->numa_socket_id = socket_id;
1292         txq->pkts_without_db = false;
1293
1294         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1295                                           sizeof(struct ena_tx_buffer) *
1296                                           txq->ring_size,
1297                                           RTE_CACHE_LINE_SIZE);
1298         if (!txq->tx_buffer_info) {
1299                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1300                 return -ENOMEM;
1301         }
1302
1303         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1304                                          sizeof(u16) * txq->ring_size,
1305                                          RTE_CACHE_LINE_SIZE);
1306         if (!txq->empty_tx_reqs) {
1307                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1308                 rte_free(txq->tx_buffer_info);
1309                 return -ENOMEM;
1310         }
1311
1312         txq->push_buf_intermediate_buf =
1313                 rte_zmalloc("txq->push_buf_intermediate_buf",
1314                             txq->tx_max_header_size,
1315                             RTE_CACHE_LINE_SIZE);
1316         if (!txq->push_buf_intermediate_buf) {
1317                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1318                 rte_free(txq->tx_buffer_info);
1319                 rte_free(txq->empty_tx_reqs);
1320                 return -ENOMEM;
1321         }
1322
1323         for (i = 0; i < txq->ring_size; i++)
1324                 txq->empty_tx_reqs[i] = i;
1325
1326         if (tx_conf != NULL) {
1327                 txq->offloads =
1328                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1329         }
1330         /* Store pointer to this queue in upper layer */
1331         txq->configured = 1;
1332         dev->data->tx_queues[queue_idx] = txq;
1333
1334         return 0;
1335 }
1336
1337 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1338                               uint16_t queue_idx,
1339                               uint16_t nb_desc,
1340                               unsigned int socket_id,
1341                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1342                               struct rte_mempool *mp)
1343 {
1344         struct ena_adapter *adapter = dev->data->dev_private;
1345         struct ena_ring *rxq = NULL;
1346         size_t buffer_size;
1347         int i;
1348
1349         rxq = &adapter->rx_ring[queue_idx];
1350         if (rxq->configured) {
1351                 PMD_DRV_LOG(CRIT,
1352                         "API violation. Queue %d is already configured\n",
1353                         queue_idx);
1354                 return ENA_COM_FAULT;
1355         }
1356
1357         if (!rte_is_power_of_2(nb_desc)) {
1358                 PMD_DRV_LOG(ERR,
1359                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1360                         nb_desc);
1361                 return -EINVAL;
1362         }
1363
1364         if (nb_desc > adapter->max_rx_ring_size) {
1365                 PMD_DRV_LOG(ERR,
1366                         "Unsupported size of RX queue (max size: %d)\n",
1367                         adapter->max_rx_ring_size);
1368                 return -EINVAL;
1369         }
1370
1371         /* ENA isn't supporting buffers smaller than 1400 bytes */
1372         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1373         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1374                 PMD_DRV_LOG(ERR,
1375                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1376                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1377                 return -EINVAL;
1378         }
1379
1380         rxq->port_id = dev->data->port_id;
1381         rxq->next_to_clean = 0;
1382         rxq->next_to_use = 0;
1383         rxq->ring_size = nb_desc;
1384         rxq->size_mask = nb_desc - 1;
1385         rxq->numa_socket_id = socket_id;
1386         rxq->mb_pool = mp;
1387
1388         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1389                 sizeof(struct ena_rx_buffer) * nb_desc,
1390                 RTE_CACHE_LINE_SIZE);
1391         if (!rxq->rx_buffer_info) {
1392                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1393                 return -ENOMEM;
1394         }
1395
1396         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1397                                             sizeof(struct rte_mbuf *) * nb_desc,
1398                                             RTE_CACHE_LINE_SIZE);
1399
1400         if (!rxq->rx_refill_buffer) {
1401                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1402                 rte_free(rxq->rx_buffer_info);
1403                 rxq->rx_buffer_info = NULL;
1404                 return -ENOMEM;
1405         }
1406
1407         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1408                                          sizeof(uint16_t) * nb_desc,
1409                                          RTE_CACHE_LINE_SIZE);
1410         if (!rxq->empty_rx_reqs) {
1411                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1412                 rte_free(rxq->rx_buffer_info);
1413                 rxq->rx_buffer_info = NULL;
1414                 rte_free(rxq->rx_refill_buffer);
1415                 rxq->rx_refill_buffer = NULL;
1416                 return -ENOMEM;
1417         }
1418
1419         for (i = 0; i < nb_desc; i++)
1420                 rxq->empty_rx_reqs[i] = i;
1421
1422         /* Store pointer to this queue in upper layer */
1423         rxq->configured = 1;
1424         dev->data->rx_queues[queue_idx] = rxq;
1425
1426         return 0;
1427 }
1428
1429 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1430                                   struct rte_mbuf *mbuf, uint16_t id)
1431 {
1432         struct ena_com_buf ebuf;
1433         int rc;
1434
1435         /* prepare physical address for DMA transaction */
1436         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1437         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1438
1439         /* pass resource to device */
1440         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1441         if (unlikely(rc != 0))
1442                 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1443
1444         return rc;
1445 }
1446
1447 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1448 {
1449         unsigned int i;
1450         int rc;
1451         uint16_t next_to_use = rxq->next_to_use;
1452         uint16_t in_use, req_id;
1453         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1454
1455         if (unlikely(!count))
1456                 return 0;
1457
1458         in_use = rxq->ring_size - 1 -
1459                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1460         ena_assert_msg(((in_use + count) < rxq->ring_size),
1461                 "bad ring state\n");
1462
1463         /* get resources for incoming packets */
1464         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1465         if (unlikely(rc < 0)) {
1466                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1467                 ++rxq->rx_stats.mbuf_alloc_fail;
1468                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1469                 return 0;
1470         }
1471
1472         for (i = 0; i < count; i++) {
1473                 struct rte_mbuf *mbuf = mbufs[i];
1474                 struct ena_rx_buffer *rx_info;
1475
1476                 if (likely((i + 4) < count))
1477                         rte_prefetch0(mbufs[i + 4]);
1478
1479                 req_id = rxq->empty_rx_reqs[next_to_use];
1480                 rx_info = &rxq->rx_buffer_info[req_id];
1481
1482                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1483                 if (unlikely(rc != 0))
1484                         break;
1485
1486                 rx_info->mbuf = mbuf;
1487                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1488         }
1489
1490         if (unlikely(i < count)) {
1491                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1492                         "buffers (from %d)\n", rxq->id, i, count);
1493                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1494                 ++rxq->rx_stats.refill_partial;
1495         }
1496
1497         /* When we submitted free recources to device... */
1498         if (likely(i > 0)) {
1499                 /* ...let HW know that it can fill buffers with data. */
1500                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1501
1502                 rxq->next_to_use = next_to_use;
1503         }
1504
1505         return i;
1506 }
1507
1508 static int ena_device_init(struct ena_com_dev *ena_dev,
1509                            struct rte_pci_device *pdev,
1510                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1511                            bool *wd_state)
1512 {
1513         uint32_t aenq_groups;
1514         int rc;
1515         bool readless_supported;
1516
1517         /* Initialize mmio registers */
1518         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1519         if (rc) {
1520                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1521                 return rc;
1522         }
1523
1524         /* The PCIe configuration space revision id indicate if mmio reg
1525          * read is disabled.
1526          */
1527         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1528         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1529
1530         /* reset device */
1531         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1532         if (rc) {
1533                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1534                 goto err_mmio_read_less;
1535         }
1536
1537         /* check FW version */
1538         rc = ena_com_validate_version(ena_dev);
1539         if (rc) {
1540                 PMD_DRV_LOG(ERR, "device version is too low\n");
1541                 goto err_mmio_read_less;
1542         }
1543
1544         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1545
1546         /* ENA device administration layer init */
1547         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1548         if (rc) {
1549                 PMD_DRV_LOG(ERR,
1550                         "cannot initialize ena admin queue with device\n");
1551                 goto err_mmio_read_less;
1552         }
1553
1554         /* To enable the msix interrupts the driver needs to know the number
1555          * of queues. So the driver uses polling mode to retrieve this
1556          * information.
1557          */
1558         ena_com_set_admin_polling_mode(ena_dev, true);
1559
1560         ena_config_host_info(ena_dev);
1561
1562         /* Get Device Attributes and features */
1563         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1564         if (rc) {
1565                 PMD_DRV_LOG(ERR,
1566                         "cannot get attribute for ena device rc= %d\n", rc);
1567                 goto err_admin_init;
1568         }
1569
1570         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1571                       BIT(ENA_ADMIN_NOTIFICATION) |
1572                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1573                       BIT(ENA_ADMIN_FATAL_ERROR) |
1574                       BIT(ENA_ADMIN_WARNING);
1575
1576         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1577         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1578         if (rc) {
1579                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1580                 goto err_admin_init;
1581         }
1582
1583         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1584
1585         return 0;
1586
1587 err_admin_init:
1588         ena_com_admin_destroy(ena_dev);
1589
1590 err_mmio_read_less:
1591         ena_com_mmio_reg_read_request_destroy(ena_dev);
1592
1593         return rc;
1594 }
1595
1596 static void ena_interrupt_handler_rte(void *cb_arg)
1597 {
1598         struct rte_eth_dev *dev = cb_arg;
1599         struct ena_adapter *adapter = dev->data->dev_private;
1600         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1601
1602         ena_com_admin_q_comp_intr_handler(ena_dev);
1603         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1604                 ena_com_aenq_intr_handler(ena_dev, dev);
1605 }
1606
1607 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1608 {
1609         if (!adapter->wd_state)
1610                 return;
1611
1612         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1613                 return;
1614
1615         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1616             adapter->keep_alive_timeout)) {
1617                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1618                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1619                 adapter->trigger_reset = true;
1620                 ++adapter->dev_stats.wd_expired;
1621         }
1622 }
1623
1624 /* Check if admin queue is enabled */
1625 static void check_for_admin_com_state(struct ena_adapter *adapter)
1626 {
1627         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1628                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1629                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1630                 adapter->trigger_reset = true;
1631         }
1632 }
1633
1634 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1635                                   void *arg)
1636 {
1637         struct rte_eth_dev *dev = arg;
1638         struct ena_adapter *adapter = dev->data->dev_private;
1639
1640         check_for_missing_keep_alive(adapter);
1641         check_for_admin_com_state(adapter);
1642
1643         if (unlikely(adapter->trigger_reset)) {
1644                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1645                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1646                         NULL);
1647         }
1648 }
1649
1650 static inline void
1651 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1652                                struct ena_admin_feature_llq_desc *llq,
1653                                bool use_large_llq_hdr)
1654 {
1655         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1656         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1657         llq_config->llq_num_decs_before_header =
1658                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1659
1660         if (use_large_llq_hdr &&
1661             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1662                 llq_config->llq_ring_entry_size =
1663                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1664                 llq_config->llq_ring_entry_size_value = 256;
1665         } else {
1666                 llq_config->llq_ring_entry_size =
1667                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1668                 llq_config->llq_ring_entry_size_value = 128;
1669         }
1670 }
1671
1672 static int
1673 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1674                                 struct ena_com_dev *ena_dev,
1675                                 struct ena_admin_feature_llq_desc *llq,
1676                                 struct ena_llq_configurations *llq_default_configurations)
1677 {
1678         int rc;
1679         u32 llq_feature_mask;
1680
1681         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1682         if (!(ena_dev->supported_features & llq_feature_mask)) {
1683                 PMD_DRV_LOG(INFO,
1684                         "LLQ is not supported. Fallback to host mode policy.\n");
1685                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1686                 return 0;
1687         }
1688
1689         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1690         if (unlikely(rc)) {
1691                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1692                         "Fallback to host mode policy.");
1693                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1694                 return 0;
1695         }
1696
1697         /* Nothing to config, exit */
1698         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1699                 return 0;
1700
1701         if (!adapter->dev_mem_base) {
1702                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1703                         "Fallback to host mode policy.\n.");
1704                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1705                 return 0;
1706         }
1707
1708         ena_dev->mem_bar = adapter->dev_mem_base;
1709
1710         return 0;
1711 }
1712
1713 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1714         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1715 {
1716         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1717
1718         /* Regular queues capabilities */
1719         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1720                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1721                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1722                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1723                                     max_queue_ext->max_rx_cq_num);
1724                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1725                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1726         } else {
1727                 struct ena_admin_queue_feature_desc *max_queues =
1728                         &get_feat_ctx->max_queues;
1729                 io_tx_sq_num = max_queues->max_sq_num;
1730                 io_tx_cq_num = max_queues->max_cq_num;
1731                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1732         }
1733
1734         /* In case of LLQ use the llq number in the get feature cmd */
1735         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1736                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1737
1738         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1739         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1740         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1741
1742         if (unlikely(max_num_io_queues == 0)) {
1743                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1744                 return -EFAULT;
1745         }
1746
1747         return max_num_io_queues;
1748 }
1749
1750 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1751 {
1752         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1753         struct rte_pci_device *pci_dev;
1754         struct rte_intr_handle *intr_handle;
1755         struct ena_adapter *adapter = eth_dev->data->dev_private;
1756         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1757         struct ena_com_dev_get_features_ctx get_feat_ctx;
1758         struct ena_llq_configurations llq_config;
1759         const char *queue_type_str;
1760         uint32_t max_num_io_queues;
1761         int rc;
1762         static int adapters_found;
1763         bool disable_meta_caching;
1764         bool wd_state = false;
1765
1766         eth_dev->dev_ops = &ena_dev_ops;
1767         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1768         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1769         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1770
1771         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1772                 return 0;
1773
1774         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1775
1776         memset(adapter, 0, sizeof(struct ena_adapter));
1777         ena_dev = &adapter->ena_dev;
1778
1779         adapter->edev_data = eth_dev->data;
1780
1781         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1782
1783         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1784                      pci_dev->addr.domain,
1785                      pci_dev->addr.bus,
1786                      pci_dev->addr.devid,
1787                      pci_dev->addr.function);
1788
1789         intr_handle = &pci_dev->intr_handle;
1790
1791         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1792         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1793
1794         if (!adapter->regs) {
1795                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1796                              ENA_REGS_BAR);
1797                 return -ENXIO;
1798         }
1799
1800         ena_dev->reg_bar = adapter->regs;
1801         /* This is a dummy pointer for ena_com functions. */
1802         ena_dev->dmadev = adapter;
1803
1804         adapter->id_number = adapters_found;
1805
1806         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1807                  adapter->id_number);
1808
1809         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1810         if (rc != 0) {
1811                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1812                 goto err;
1813         }
1814
1815         /* device specific initialization routine */
1816         rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1817         if (rc) {
1818                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1819                 goto err;
1820         }
1821         adapter->wd_state = wd_state;
1822
1823         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1824                 adapter->use_large_llq_hdr);
1825         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1826                                              &get_feat_ctx.llq, &llq_config);
1827         if (unlikely(rc)) {
1828                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1829                 return rc;
1830         }
1831
1832         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1833                 queue_type_str = "Regular";
1834         else
1835                 queue_type_str = "Low latency";
1836         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1837
1838         calc_queue_ctx.ena_dev = ena_dev;
1839         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1840
1841         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1842         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1843                 adapter->use_large_llq_hdr);
1844         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1845                 rc = -EFAULT;
1846                 goto err_device_destroy;
1847         }
1848
1849         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1850         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1851         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1852         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1853         adapter->max_num_io_queues = max_num_io_queues;
1854
1855         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1856                 disable_meta_caching =
1857                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1858                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1859         } else {
1860                 disable_meta_caching = false;
1861         }
1862
1863         /* prepare ring structures */
1864         ena_init_rings(adapter, disable_meta_caching);
1865
1866         ena_config_debug_area(adapter);
1867
1868         /* Set max MTU for this device */
1869         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1870
1871         /* set device support for offloads */
1872         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1873                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1874         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1875                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1876         adapter->offloads.rx_csum_supported =
1877                 (get_feat_ctx.offload.rx_supported &
1878                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1879
1880         /* Copy MAC address and point DPDK to it */
1881         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1882         rte_ether_addr_copy((struct rte_ether_addr *)
1883                         get_feat_ctx.dev_attr.mac_addr,
1884                         (struct rte_ether_addr *)adapter->mac_addr);
1885
1886         adapter->drv_stats = rte_zmalloc("adapter stats",
1887                                          sizeof(*adapter->drv_stats),
1888                                          RTE_CACHE_LINE_SIZE);
1889         if (!adapter->drv_stats) {
1890                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1891                 rc = -ENOMEM;
1892                 goto err_delete_debug_area;
1893         }
1894
1895         rte_spinlock_init(&adapter->admin_lock);
1896
1897         rte_intr_callback_register(intr_handle,
1898                                    ena_interrupt_handler_rte,
1899                                    eth_dev);
1900         rte_intr_enable(intr_handle);
1901         ena_com_set_admin_polling_mode(ena_dev, false);
1902         ena_com_admin_aenq_enable(ena_dev);
1903
1904         if (adapters_found == 0)
1905                 rte_timer_subsystem_init();
1906         rte_timer_init(&adapter->timer_wd);
1907
1908         adapters_found++;
1909         adapter->state = ENA_ADAPTER_STATE_INIT;
1910
1911         return 0;
1912
1913 err_delete_debug_area:
1914         ena_com_delete_debug_area(ena_dev);
1915
1916 err_device_destroy:
1917         ena_com_delete_host_info(ena_dev);
1918         ena_com_admin_destroy(ena_dev);
1919
1920 err:
1921         return rc;
1922 }
1923
1924 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1925 {
1926         struct ena_adapter *adapter = eth_dev->data->dev_private;
1927         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1928
1929         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1930                 return;
1931
1932         ena_com_set_admin_running_state(ena_dev, false);
1933
1934         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1935                 ena_close(eth_dev);
1936
1937         ena_com_delete_debug_area(ena_dev);
1938         ena_com_delete_host_info(ena_dev);
1939
1940         ena_com_abort_admin_commands(ena_dev);
1941         ena_com_wait_for_abort_completion(ena_dev);
1942         ena_com_admin_destroy(ena_dev);
1943         ena_com_mmio_reg_read_request_destroy(ena_dev);
1944
1945         adapter->state = ENA_ADAPTER_STATE_FREE;
1946 }
1947
1948 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1949 {
1950         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1951                 return 0;
1952
1953         ena_destroy_device(eth_dev);
1954
1955         return 0;
1956 }
1957
1958 static int ena_dev_configure(struct rte_eth_dev *dev)
1959 {
1960         struct ena_adapter *adapter = dev->data->dev_private;
1961
1962         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1963
1964         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1965                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1966
1967         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1968         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1969         return 0;
1970 }
1971
1972 static void ena_init_rings(struct ena_adapter *adapter,
1973                            bool disable_meta_caching)
1974 {
1975         size_t i;
1976
1977         for (i = 0; i < adapter->max_num_io_queues; i++) {
1978                 struct ena_ring *ring = &adapter->tx_ring[i];
1979
1980                 ring->configured = 0;
1981                 ring->type = ENA_RING_TYPE_TX;
1982                 ring->adapter = adapter;
1983                 ring->id = i;
1984                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1985                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1986                 ring->sgl_size = adapter->max_tx_sgl_size;
1987                 ring->disable_meta_caching = disable_meta_caching;
1988         }
1989
1990         for (i = 0; i < adapter->max_num_io_queues; i++) {
1991                 struct ena_ring *ring = &adapter->rx_ring[i];
1992
1993                 ring->configured = 0;
1994                 ring->type = ENA_RING_TYPE_RX;
1995                 ring->adapter = adapter;
1996                 ring->id = i;
1997                 ring->sgl_size = adapter->max_rx_sgl_size;
1998         }
1999 }
2000
2001 static int ena_infos_get(struct rte_eth_dev *dev,
2002                           struct rte_eth_dev_info *dev_info)
2003 {
2004         struct ena_adapter *adapter;
2005         struct ena_com_dev *ena_dev;
2006         uint64_t rx_feat = 0, tx_feat = 0;
2007
2008         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2009         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2010         adapter = dev->data->dev_private;
2011
2012         ena_dev = &adapter->ena_dev;
2013         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2014
2015         dev_info->speed_capa =
2016                         ETH_LINK_SPEED_1G   |
2017                         ETH_LINK_SPEED_2_5G |
2018                         ETH_LINK_SPEED_5G   |
2019                         ETH_LINK_SPEED_10G  |
2020                         ETH_LINK_SPEED_25G  |
2021                         ETH_LINK_SPEED_40G  |
2022                         ETH_LINK_SPEED_50G  |
2023                         ETH_LINK_SPEED_100G;
2024
2025         /* Set Tx & Rx features available for device */
2026         if (adapter->offloads.tso4_supported)
2027                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2028
2029         if (adapter->offloads.tx_csum_supported)
2030                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2031                         DEV_TX_OFFLOAD_UDP_CKSUM |
2032                         DEV_TX_OFFLOAD_TCP_CKSUM;
2033
2034         if (adapter->offloads.rx_csum_supported)
2035                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2036                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2037                         DEV_RX_OFFLOAD_TCP_CKSUM;
2038
2039         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2040
2041         /* Inform framework about available features */
2042         dev_info->rx_offload_capa = rx_feat;
2043         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
2044         dev_info->rx_queue_offload_capa = rx_feat;
2045         dev_info->tx_offload_capa = tx_feat;
2046         dev_info->tx_queue_offload_capa = tx_feat;
2047
2048         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2049                                            ETH_RSS_UDP;
2050
2051         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2052         dev_info->max_rx_pktlen  = adapter->max_mtu;
2053         dev_info->max_mac_addrs = 1;
2054
2055         dev_info->max_rx_queues = adapter->max_num_io_queues;
2056         dev_info->max_tx_queues = adapter->max_num_io_queues;
2057         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2058
2059         adapter->tx_supported_offloads = tx_feat;
2060         adapter->rx_supported_offloads = rx_feat;
2061
2062         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2063         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2064         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2065                                         adapter->max_rx_sgl_size);
2066         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2067                                         adapter->max_rx_sgl_size);
2068
2069         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2070         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2071         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2072                                         adapter->max_tx_sgl_size);
2073         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2074                                         adapter->max_tx_sgl_size);
2075
2076         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2077         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2078
2079         return 0;
2080 }
2081
2082 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2083 {
2084         mbuf->data_len = len;
2085         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2086         mbuf->refcnt = 1;
2087         mbuf->next = NULL;
2088 }
2089
2090 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2091                                     struct ena_com_rx_buf_info *ena_bufs,
2092                                     uint32_t descs,
2093                                     uint16_t *next_to_clean,
2094                                     uint8_t offset)
2095 {
2096         struct rte_mbuf *mbuf;
2097         struct rte_mbuf *mbuf_head;
2098         struct ena_rx_buffer *rx_info;
2099         int rc;
2100         uint16_t ntc, len, req_id, buf = 0;
2101
2102         if (unlikely(descs == 0))
2103                 return NULL;
2104
2105         ntc = *next_to_clean;
2106
2107         len = ena_bufs[buf].len;
2108         req_id = ena_bufs[buf].req_id;
2109
2110         rx_info = &rx_ring->rx_buffer_info[req_id];
2111
2112         mbuf = rx_info->mbuf;
2113         RTE_ASSERT(mbuf != NULL);
2114
2115         ena_init_rx_mbuf(mbuf, len);
2116
2117         /* Fill the mbuf head with the data specific for 1st segment. */
2118         mbuf_head = mbuf;
2119         mbuf_head->nb_segs = descs;
2120         mbuf_head->port = rx_ring->port_id;
2121         mbuf_head->pkt_len = len;
2122         mbuf_head->data_off += offset;
2123
2124         rx_info->mbuf = NULL;
2125         rx_ring->empty_rx_reqs[ntc] = req_id;
2126         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2127
2128         while (--descs) {
2129                 ++buf;
2130                 len = ena_bufs[buf].len;
2131                 req_id = ena_bufs[buf].req_id;
2132
2133                 rx_info = &rx_ring->rx_buffer_info[req_id];
2134                 RTE_ASSERT(rx_info->mbuf != NULL);
2135
2136                 if (unlikely(len == 0)) {
2137                         /*
2138                          * Some devices can pass descriptor with the length 0.
2139                          * To avoid confusion, the PMD is simply putting the
2140                          * descriptor back, as it was never used. We'll avoid
2141                          * mbuf allocation that way.
2142                          */
2143                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2144                                 rx_info->mbuf, req_id);
2145                         if (unlikely(rc != 0)) {
2146                                 /* Free the mbuf in case of an error. */
2147                                 rte_mbuf_raw_free(rx_info->mbuf);
2148                         } else {
2149                                 /*
2150                                  * If there was no error, just exit the loop as
2151                                  * 0 length descriptor is always the last one.
2152                                  */
2153                                 break;
2154                         }
2155                 } else {
2156                         /* Create an mbuf chain. */
2157                         mbuf->next = rx_info->mbuf;
2158                         mbuf = mbuf->next;
2159
2160                         ena_init_rx_mbuf(mbuf, len);
2161                         mbuf_head->pkt_len += len;
2162                 }
2163
2164                 /*
2165                  * Mark the descriptor as depleted and perform necessary
2166                  * cleanup.
2167                  * This code will execute in two cases:
2168                  *  1. Descriptor len was greater than 0 - normal situation.
2169                  *  2. Descriptor len was 0 and we failed to add the descriptor
2170                  *     to the device. In that situation, we should try to add
2171                  *     the mbuf again in the populate routine and mark the
2172                  *     descriptor as used up by the device.
2173                  */
2174                 rx_info->mbuf = NULL;
2175                 rx_ring->empty_rx_reqs[ntc] = req_id;
2176                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2177         }
2178
2179         *next_to_clean = ntc;
2180
2181         return mbuf_head;
2182 }
2183
2184 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2185                                   uint16_t nb_pkts)
2186 {
2187         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2188         unsigned int free_queue_entries;
2189         unsigned int refill_threshold;
2190         uint16_t next_to_clean = rx_ring->next_to_clean;
2191         uint16_t descs_in_use;
2192         struct rte_mbuf *mbuf;
2193         uint16_t completed;
2194         struct ena_com_rx_ctx ena_rx_ctx;
2195         int i, rc = 0;
2196
2197         /* Check adapter state */
2198         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2199                 PMD_DRV_LOG(ALERT,
2200                         "Trying to receive pkts while device is NOT running\n");
2201                 return 0;
2202         }
2203
2204         descs_in_use = rx_ring->ring_size -
2205                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2206         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2207
2208         for (completed = 0; completed < nb_pkts; completed++) {
2209                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2210                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2211                 ena_rx_ctx.descs = 0;
2212                 ena_rx_ctx.pkt_offset = 0;
2213                 /* receive packet context */
2214                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2215                                     rx_ring->ena_com_io_sq,
2216                                     &ena_rx_ctx);
2217                 if (unlikely(rc)) {
2218                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2219                         if (rc == ENA_COM_NO_SPACE) {
2220                                 ++rx_ring->rx_stats.bad_desc_num;
2221                                 rx_ring->adapter->reset_reason =
2222                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2223                         } else {
2224                                 ++rx_ring->rx_stats.bad_req_id;
2225                                 rx_ring->adapter->reset_reason =
2226                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2227                         }
2228                         rx_ring->adapter->trigger_reset = true;
2229                         return 0;
2230                 }
2231
2232                 mbuf = ena_rx_mbuf(rx_ring,
2233                         ena_rx_ctx.ena_bufs,
2234                         ena_rx_ctx.descs,
2235                         &next_to_clean,
2236                         ena_rx_ctx.pkt_offset);
2237                 if (unlikely(mbuf == NULL)) {
2238                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2239                                 rx_ring->empty_rx_reqs[next_to_clean] =
2240                                         rx_ring->ena_bufs[i].req_id;
2241                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2242                                         next_to_clean, rx_ring->size_mask);
2243                         }
2244                         break;
2245                 }
2246
2247                 /* fill mbuf attributes if any */
2248                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2249
2250                 if (unlikely(mbuf->ol_flags &
2251                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2252                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2253                         ++rx_ring->rx_stats.bad_csum;
2254                 }
2255
2256                 rx_pkts[completed] = mbuf;
2257                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2258         }
2259
2260         rx_ring->rx_stats.cnt += completed;
2261         rx_ring->next_to_clean = next_to_clean;
2262
2263         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2264         refill_threshold =
2265                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2266                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2267
2268         /* Burst refill to save doorbells, memory barriers, const interval */
2269         if (free_queue_entries > refill_threshold) {
2270                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2271                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2272         }
2273
2274         return completed;
2275 }
2276
2277 static uint16_t
2278 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2279                 uint16_t nb_pkts)
2280 {
2281         int32_t ret;
2282         uint32_t i;
2283         struct rte_mbuf *m;
2284         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2285         struct rte_ipv4_hdr *ip_hdr;
2286         uint64_t ol_flags;
2287         uint16_t frag_field;
2288
2289         for (i = 0; i != nb_pkts; i++) {
2290                 m = tx_pkts[i];
2291                 ol_flags = m->ol_flags;
2292
2293                 if (!(ol_flags & PKT_TX_IPV4))
2294                         continue;
2295
2296                 /* If there was not L2 header length specified, assume it is
2297                  * length of the ethernet header.
2298                  */
2299                 if (unlikely(m->l2_len == 0))
2300                         m->l2_len = sizeof(struct rte_ether_hdr);
2301
2302                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2303                                                  m->l2_len);
2304                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2305
2306                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2307                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2308
2309                         /* If IPv4 header has DF flag enabled and TSO support is
2310                          * disabled, partial chcecksum should not be calculated.
2311                          */
2312                         if (!tx_ring->adapter->offloads.tso4_supported)
2313                                 continue;
2314                 }
2315
2316                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2317                                 (ol_flags & PKT_TX_L4_MASK) ==
2318                                 PKT_TX_SCTP_CKSUM) {
2319                         rte_errno = ENOTSUP;
2320                         return i;
2321                 }
2322
2323 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2324                 ret = rte_validate_tx_offload(m);
2325                 if (ret != 0) {
2326                         rte_errno = -ret;
2327                         return i;
2328                 }
2329 #endif
2330
2331                 /* In case we are supposed to TSO and have DF not set (DF=0)
2332                  * hardware must be provided with partial checksum, otherwise
2333                  * it will take care of necessary calculations.
2334                  */
2335
2336                 ret = rte_net_intel_cksum_flags_prepare(m,
2337                         ol_flags & ~PKT_TX_TCP_SEG);
2338                 if (ret != 0) {
2339                         rte_errno = -ret;
2340                         return i;
2341                 }
2342         }
2343
2344         return i;
2345 }
2346
2347 static void ena_update_hints(struct ena_adapter *adapter,
2348                              struct ena_admin_ena_hw_hints *hints)
2349 {
2350         if (hints->admin_completion_tx_timeout)
2351                 adapter->ena_dev.admin_queue.completion_timeout =
2352                         hints->admin_completion_tx_timeout * 1000;
2353
2354         if (hints->mmio_read_timeout)
2355                 /* convert to usec */
2356                 adapter->ena_dev.mmio_read.reg_read_to =
2357                         hints->mmio_read_timeout * 1000;
2358
2359         if (hints->driver_watchdog_timeout) {
2360                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2361                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2362                 else
2363                         // Convert msecs to ticks
2364                         adapter->keep_alive_timeout =
2365                                 (hints->driver_watchdog_timeout *
2366                                 rte_get_timer_hz()) / 1000;
2367         }
2368 }
2369
2370 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2371                                               struct rte_mbuf *mbuf)
2372 {
2373         struct ena_com_dev *ena_dev;
2374         int num_segments, header_len, rc;
2375
2376         ena_dev = &tx_ring->adapter->ena_dev;
2377         num_segments = mbuf->nb_segs;
2378         header_len = mbuf->data_len;
2379
2380         if (likely(num_segments < tx_ring->sgl_size))
2381                 goto checkspace;
2382
2383         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2384             (num_segments == tx_ring->sgl_size) &&
2385             (header_len < tx_ring->tx_max_header_size))
2386                 goto checkspace;
2387
2388         /* Checking for space for 2 additional metadata descriptors due to
2389          * possible header split and metadata descriptor. Linearization will
2390          * be needed so we reduce the segments number from num_segments to 1
2391          */
2392         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2393                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2394                 return ENA_COM_NO_MEM;
2395         }
2396         ++tx_ring->tx_stats.linearize;
2397         rc = rte_pktmbuf_linearize(mbuf);
2398         if (unlikely(rc)) {
2399                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2400                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2401                 ++tx_ring->tx_stats.linearize_failed;
2402                 return rc;
2403         }
2404
2405         return 0;
2406
2407 checkspace:
2408         /* Checking for space for 2 additional metadata descriptors due to
2409          * possible header split and metadata descriptor
2410          */
2411         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2412                                           num_segments + 2)) {
2413                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2414                 return ENA_COM_NO_MEM;
2415         }
2416
2417         return 0;
2418 }
2419
2420 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2421         struct ena_tx_buffer *tx_info,
2422         struct rte_mbuf *mbuf,
2423         void **push_header,
2424         uint16_t *header_len)
2425 {
2426         struct ena_com_buf *ena_buf;
2427         uint16_t delta, seg_len, push_len;
2428
2429         delta = 0;
2430         seg_len = mbuf->data_len;
2431
2432         tx_info->mbuf = mbuf;
2433         ena_buf = tx_info->bufs;
2434
2435         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2436                 /*
2437                  * Tx header might be (and will be in most cases) smaller than
2438                  * tx_max_header_size. But it's not an issue to send more data
2439                  * to the device, than actually needed if the mbuf size is
2440                  * greater than tx_max_header_size.
2441                  */
2442                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2443                 *header_len = push_len;
2444
2445                 if (likely(push_len <= seg_len)) {
2446                         /* If the push header is in the single segment, then
2447                          * just point it to the 1st mbuf data.
2448                          */
2449                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2450                 } else {
2451                         /* If the push header lays in the several segments, copy
2452                          * it to the intermediate buffer.
2453                          */
2454                         rte_pktmbuf_read(mbuf, 0, push_len,
2455                                 tx_ring->push_buf_intermediate_buf);
2456                         *push_header = tx_ring->push_buf_intermediate_buf;
2457                         delta = push_len - seg_len;
2458                 }
2459         } else {
2460                 *push_header = NULL;
2461                 *header_len = 0;
2462                 push_len = 0;
2463         }
2464
2465         /* Process first segment taking into consideration pushed header */
2466         if (seg_len > push_len) {
2467                 ena_buf->paddr = mbuf->buf_iova +
2468                                 mbuf->data_off +
2469                                 push_len;
2470                 ena_buf->len = seg_len - push_len;
2471                 ena_buf++;
2472                 tx_info->num_of_bufs++;
2473         }
2474
2475         while ((mbuf = mbuf->next) != NULL) {
2476                 seg_len = mbuf->data_len;
2477
2478                 /* Skip mbufs if whole data is pushed as a header */
2479                 if (unlikely(delta > seg_len)) {
2480                         delta -= seg_len;
2481                         continue;
2482                 }
2483
2484                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2485                 ena_buf->len = seg_len - delta;
2486                 ena_buf++;
2487                 tx_info->num_of_bufs++;
2488
2489                 delta = 0;
2490         }
2491 }
2492
2493 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2494 {
2495         struct ena_tx_buffer *tx_info;
2496         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2497         uint16_t next_to_use;
2498         uint16_t header_len;
2499         uint16_t req_id;
2500         void *push_header;
2501         int nb_hw_desc;
2502         int rc;
2503
2504         rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2505         if (unlikely(rc))
2506                 return rc;
2507
2508         next_to_use = tx_ring->next_to_use;
2509
2510         req_id = tx_ring->empty_tx_reqs[next_to_use];
2511         tx_info = &tx_ring->tx_buffer_info[req_id];
2512         tx_info->num_of_bufs = 0;
2513
2514         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2515
2516         ena_tx_ctx.ena_bufs = tx_info->bufs;
2517         ena_tx_ctx.push_header = push_header;
2518         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2519         ena_tx_ctx.req_id = req_id;
2520         ena_tx_ctx.header_len = header_len;
2521
2522         /* Set Tx offloads flags, if applicable */
2523         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2524                 tx_ring->disable_meta_caching);
2525
2526         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2527                         &ena_tx_ctx))) {
2528                 PMD_DRV_LOG(DEBUG,
2529                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2530                         tx_ring->id);
2531                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2532                 tx_ring->tx_stats.doorbells++;
2533                 tx_ring->pkts_without_db = false;
2534         }
2535
2536         /* prepare the packet's descriptors to dma engine */
2537         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2538                 &nb_hw_desc);
2539         if (unlikely(rc)) {
2540                 ++tx_ring->tx_stats.prepare_ctx_err;
2541                 return rc;
2542         }
2543
2544         tx_info->tx_descs = nb_hw_desc;
2545
2546         tx_ring->tx_stats.cnt++;
2547         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2548
2549         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2550                 tx_ring->size_mask);
2551
2552         return 0;
2553 }
2554
2555 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2556 {
2557         unsigned int cleanup_budget;
2558         unsigned int total_tx_descs = 0;
2559         uint16_t next_to_clean = tx_ring->next_to_clean;
2560
2561         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2562                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2563
2564         while (likely(total_tx_descs < cleanup_budget)) {
2565                 struct rte_mbuf *mbuf;
2566                 struct ena_tx_buffer *tx_info;
2567                 uint16_t req_id;
2568
2569                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2570                         break;
2571
2572                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2573                         break;
2574
2575                 /* Get Tx info & store how many descs were processed  */
2576                 tx_info = &tx_ring->tx_buffer_info[req_id];
2577
2578                 mbuf = tx_info->mbuf;
2579                 rte_pktmbuf_free(mbuf);
2580
2581                 tx_info->mbuf = NULL;
2582                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2583
2584                 total_tx_descs += tx_info->tx_descs;
2585
2586                 /* Put back descriptor to the ring for reuse */
2587                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2588                         tx_ring->size_mask);
2589         }
2590
2591         if (likely(total_tx_descs > 0)) {
2592                 /* acknowledge completion of sent packets */
2593                 tx_ring->next_to_clean = next_to_clean;
2594                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2595                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2596         }
2597 }
2598
2599 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2600                                   uint16_t nb_pkts)
2601 {
2602         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2603         uint16_t sent_idx = 0;
2604
2605         /* Check adapter state */
2606         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2607                 PMD_DRV_LOG(ALERT,
2608                         "Trying to xmit pkts while device is NOT running\n");
2609                 return 0;
2610         }
2611
2612         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2613                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2614                         break;
2615                 tx_ring->pkts_without_db = true;
2616                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2617                         tx_ring->size_mask)]);
2618         }
2619
2620         tx_ring->tx_stats.available_desc =
2621                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2622
2623         /* If there are ready packets to be xmitted... */
2624         if (likely(tx_ring->pkts_without_db)) {
2625                 /* ...let HW do its best :-) */
2626                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2627                 tx_ring->tx_stats.doorbells++;
2628                 tx_ring->pkts_without_db = false;
2629         }
2630
2631         ena_tx_cleanup(tx_ring);
2632
2633         tx_ring->tx_stats.available_desc =
2634                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2635         tx_ring->tx_stats.tx_poll++;
2636
2637         return sent_idx;
2638 }
2639
2640 int ena_copy_eni_stats(struct ena_adapter *adapter)
2641 {
2642         struct ena_admin_eni_stats admin_eni_stats;
2643         int rc;
2644
2645         rte_spinlock_lock(&adapter->admin_lock);
2646         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2647         rte_spinlock_unlock(&adapter->admin_lock);
2648         if (rc != 0) {
2649                 if (rc == ENA_COM_UNSUPPORTED) {
2650                         PMD_DRV_LOG(DEBUG,
2651                                 "Retrieving ENI metrics is not supported.\n");
2652                 } else {
2653                         PMD_DRV_LOG(WARNING,
2654                                 "Failed to get ENI metrics: %d\n", rc);
2655                 }
2656                 return rc;
2657         }
2658
2659         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2660                 sizeof(struct ena_stats_eni));
2661
2662         return 0;
2663 }
2664
2665 /**
2666  * DPDK callback to retrieve names of extended device statistics
2667  *
2668  * @param dev
2669  *   Pointer to Ethernet device structure.
2670  * @param[out] xstats_names
2671  *   Buffer to insert names into.
2672  * @param n
2673  *   Number of names.
2674  *
2675  * @return
2676  *   Number of xstats names.
2677  */
2678 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2679                                 struct rte_eth_xstat_name *xstats_names,
2680                                 unsigned int n)
2681 {
2682         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2683         unsigned int stat, i, count = 0;
2684
2685         if (n < xstats_count || !xstats_names)
2686                 return xstats_count;
2687
2688         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2689                 strcpy(xstats_names[count].name,
2690                         ena_stats_global_strings[stat].name);
2691
2692         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2693                 strcpy(xstats_names[count].name,
2694                         ena_stats_eni_strings[stat].name);
2695
2696         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2697                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2698                         snprintf(xstats_names[count].name,
2699                                 sizeof(xstats_names[count].name),
2700                                 "rx_q%d_%s", i,
2701                                 ena_stats_rx_strings[stat].name);
2702
2703         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2704                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2705                         snprintf(xstats_names[count].name,
2706                                 sizeof(xstats_names[count].name),
2707                                 "tx_q%d_%s", i,
2708                                 ena_stats_tx_strings[stat].name);
2709
2710         return xstats_count;
2711 }
2712
2713 /**
2714  * DPDK callback to get extended device statistics.
2715  *
2716  * @param dev
2717  *   Pointer to Ethernet device structure.
2718  * @param[out] stats
2719  *   Stats table output buffer.
2720  * @param n
2721  *   The size of the stats table.
2722  *
2723  * @return
2724  *   Number of xstats on success, negative on failure.
2725  */
2726 static int ena_xstats_get(struct rte_eth_dev *dev,
2727                           struct rte_eth_xstat *xstats,
2728                           unsigned int n)
2729 {
2730         struct ena_adapter *adapter = dev->data->dev_private;
2731         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2732         unsigned int stat, i, count = 0;
2733         int stat_offset;
2734         void *stats_begin;
2735
2736         if (n < xstats_count)
2737                 return xstats_count;
2738
2739         if (!xstats)
2740                 return 0;
2741
2742         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2743                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2744                 stats_begin = &adapter->dev_stats;
2745
2746                 xstats[count].id = count;
2747                 xstats[count].value = *((uint64_t *)
2748                         ((char *)stats_begin + stat_offset));
2749         }
2750
2751         /* Even if the function below fails, we should copy previous (or initial
2752          * values) to keep structure of rte_eth_xstat consistent.
2753          */
2754         ena_copy_eni_stats(adapter);
2755         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2756                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2757                 stats_begin = &adapter->eni_stats;
2758
2759                 xstats[count].id = count;
2760                 xstats[count].value = *((uint64_t *)
2761                     ((char *)stats_begin + stat_offset));
2762         }
2763
2764         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2765                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2766                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2767                         stats_begin = &adapter->rx_ring[i].rx_stats;
2768
2769                         xstats[count].id = count;
2770                         xstats[count].value = *((uint64_t *)
2771                                 ((char *)stats_begin + stat_offset));
2772                 }
2773         }
2774
2775         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2776                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2777                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2778                         stats_begin = &adapter->tx_ring[i].rx_stats;
2779
2780                         xstats[count].id = count;
2781                         xstats[count].value = *((uint64_t *)
2782                                 ((char *)stats_begin + stat_offset));
2783                 }
2784         }
2785
2786         return count;
2787 }
2788
2789 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2790                                 const uint64_t *ids,
2791                                 uint64_t *values,
2792                                 unsigned int n)
2793 {
2794         struct ena_adapter *adapter = dev->data->dev_private;
2795         uint64_t id;
2796         uint64_t rx_entries, tx_entries;
2797         unsigned int i;
2798         int qid;
2799         int valid = 0;
2800         bool was_eni_copied = false;
2801
2802         for (i = 0; i < n; ++i) {
2803                 id = ids[i];
2804                 /* Check if id belongs to global statistics */
2805                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2806                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2807                         ++valid;
2808                         continue;
2809                 }
2810
2811                 /* Check if id belongs to ENI statistics */
2812                 id -= ENA_STATS_ARRAY_GLOBAL;
2813                 if (id < ENA_STATS_ARRAY_ENI) {
2814                         /* Avoid reading ENI stats multiple times in a single
2815                          * function call, as it requires communication with the
2816                          * admin queue.
2817                          */
2818                         if (!was_eni_copied) {
2819                                 was_eni_copied = true;
2820                                 ena_copy_eni_stats(adapter);
2821                         }
2822                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2823                         ++valid;
2824                         continue;
2825                 }
2826
2827                 /* Check if id belongs to rx queue statistics */
2828                 id -= ENA_STATS_ARRAY_ENI;
2829                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2830                 if (id < rx_entries) {
2831                         qid = id % dev->data->nb_rx_queues;
2832                         id /= dev->data->nb_rx_queues;
2833                         values[i] = *((uint64_t *)
2834                                 &adapter->rx_ring[qid].rx_stats + id);
2835                         ++valid;
2836                         continue;
2837                 }
2838                                 /* Check if id belongs to rx queue statistics */
2839                 id -= rx_entries;
2840                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2841                 if (id < tx_entries) {
2842                         qid = id % dev->data->nb_tx_queues;
2843                         id /= dev->data->nb_tx_queues;
2844                         values[i] = *((uint64_t *)
2845                                 &adapter->tx_ring[qid].tx_stats + id);
2846                         ++valid;
2847                         continue;
2848                 }
2849         }
2850
2851         return valid;
2852 }
2853
2854 static int ena_process_bool_devarg(const char *key,
2855                                    const char *value,
2856                                    void *opaque)
2857 {
2858         struct ena_adapter *adapter = opaque;
2859         bool bool_value;
2860
2861         /* Parse the value. */
2862         if (strcmp(value, "1") == 0) {
2863                 bool_value = true;
2864         } else if (strcmp(value, "0") == 0) {
2865                 bool_value = false;
2866         } else {
2867                 PMD_INIT_LOG(ERR,
2868                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2869                         value, key);
2870                 return -EINVAL;
2871         }
2872
2873         /* Now, assign it to the proper adapter field. */
2874         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2875                 adapter->use_large_llq_hdr = bool_value;
2876
2877         return 0;
2878 }
2879
2880 static int ena_parse_devargs(struct ena_adapter *adapter,
2881                              struct rte_devargs *devargs)
2882 {
2883         static const char * const allowed_args[] = {
2884                 ENA_DEVARG_LARGE_LLQ_HDR,
2885                 NULL,
2886         };
2887         struct rte_kvargs *kvlist;
2888         int rc;
2889
2890         if (devargs == NULL)
2891                 return 0;
2892
2893         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2894         if (kvlist == NULL) {
2895                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2896                         devargs->args);
2897                 return -EINVAL;
2898         }
2899
2900         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2901                 ena_process_bool_devarg, adapter);
2902
2903         rte_kvargs_free(kvlist);
2904
2905         return rc;
2906 }
2907
2908 /*********************************************************************
2909  *  PMD configuration
2910  *********************************************************************/
2911 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2912         struct rte_pci_device *pci_dev)
2913 {
2914         return rte_eth_dev_pci_generic_probe(pci_dev,
2915                 sizeof(struct ena_adapter), eth_ena_dev_init);
2916 }
2917
2918 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2919 {
2920         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2921 }
2922
2923 static struct rte_pci_driver rte_ena_pmd = {
2924         .id_table = pci_id_ena_map,
2925         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2926                      RTE_PCI_DRV_WC_ACTIVATE,
2927         .probe = eth_ena_pci_probe,
2928         .remove = eth_ena_pci_remove,
2929 };
2930
2931 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2932 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2933 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2934 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2935 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
2936 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
2937 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2938 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, NOTICE);
2939 #endif
2940 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2941 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, NOTICE);
2942 #endif
2943 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2944 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx_free, tx_free, NOTICE);
2945 #endif
2946 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2947 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, NOTICE);
2948 #endif
2949
2950 /******************************************************************************
2951  ******************************** AENQ Handlers *******************************
2952  *****************************************************************************/
2953 static void ena_update_on_link_change(void *adapter_data,
2954                                       struct ena_admin_aenq_entry *aenq_e)
2955 {
2956         struct rte_eth_dev *eth_dev = adapter_data;
2957         struct ena_adapter *adapter = eth_dev->data->dev_private;
2958         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2959         uint32_t status;
2960
2961         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2962
2963         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2964         adapter->link_status = status;
2965
2966         ena_link_update(eth_dev, 0);
2967         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2968 }
2969
2970 static void ena_notification(void *adapter_data,
2971                              struct ena_admin_aenq_entry *aenq_e)
2972 {
2973         struct rte_eth_dev *eth_dev = adapter_data;
2974         struct ena_adapter *adapter = eth_dev->data->dev_private;
2975         struct ena_admin_ena_hw_hints *hints;
2976
2977         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2978                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2979                         aenq_e->aenq_common_desc.group,
2980                         ENA_ADMIN_NOTIFICATION);
2981
2982         switch (aenq_e->aenq_common_desc.syndrome) {
2983         case ENA_ADMIN_UPDATE_HINTS:
2984                 hints = (struct ena_admin_ena_hw_hints *)
2985                         (&aenq_e->inline_data_w4);
2986                 ena_update_hints(adapter, hints);
2987                 break;
2988         default:
2989                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2990                         aenq_e->aenq_common_desc.syndrome);
2991         }
2992 }
2993
2994 static void ena_keep_alive(void *adapter_data,
2995                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2996 {
2997         struct rte_eth_dev *eth_dev = adapter_data;
2998         struct ena_adapter *adapter = eth_dev->data->dev_private;
2999         struct ena_admin_aenq_keep_alive_desc *desc;
3000         uint64_t rx_drops;
3001         uint64_t tx_drops;
3002
3003         adapter->timestamp_wd = rte_get_timer_cycles();
3004
3005         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3006         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3007         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3008
3009         adapter->drv_stats->rx_drops = rx_drops;
3010         adapter->dev_stats.tx_drops = tx_drops;
3011 }
3012
3013 /**
3014  * This handler will called for unknown event group or unimplemented handlers
3015  **/
3016 static void unimplemented_aenq_handler(__rte_unused void *data,
3017                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3018 {
3019         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
3020                           "unimplemented handler\n");
3021 }
3022
3023 static struct ena_aenq_handlers aenq_handlers = {
3024         .handlers = {
3025                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3026                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3027                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3028         },
3029         .unimplemented_handler = unimplemented_aenq_handler
3030 };