drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    5
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 struct ena_stats {
  42         char name[ETH_GSTRING_LEN];
  43         int stat_offset;
  44 };
  45
  46 #define ENA_STAT_ENTRY(stat, stat_type) { \
  47         .name = #stat, \
  48         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  49 }
  50
  51 #define ENA_STAT_RX_ENTRY(stat) \
  52         ENA_STAT_ENTRY(stat, rx)
  53
  54 #define ENA_STAT_TX_ENTRY(stat) \
  55         ENA_STAT_ENTRY(stat, tx)
  56
  57 #define ENA_STAT_ENI_ENTRY(stat) \
  58         ENA_STAT_ENTRY(stat, eni)
  59
  60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  61         ENA_STAT_ENTRY(stat, dev)
  62
  63 /* Device arguments */
  64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  65
  66 /*
  67  * Each rte_memzone should have unique name.
  68  * To satisfy it, count number of allocation and add it to name.
  69  */
  70 rte_atomic64_t ena_alloc_cnt;
  71
  72 static const struct ena_stats ena_stats_global_strings[] = {
  73         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  74         ENA_STAT_GLOBAL_ENTRY(dev_start),
  75         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  76         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  77 };
  78
  79 static const struct ena_stats ena_stats_eni_strings[] = {
  80         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  81         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  82         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  83         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  84         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  85 };
  86
  87 static const struct ena_stats ena_stats_tx_strings[] = {
  88         ENA_STAT_TX_ENTRY(cnt),
  89         ENA_STAT_TX_ENTRY(bytes),
  90         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  91         ENA_STAT_TX_ENTRY(tx_poll),
  92         ENA_STAT_TX_ENTRY(doorbells),
  93         ENA_STAT_TX_ENTRY(bad_req_id),
  94         ENA_STAT_TX_ENTRY(available_desc),
  95         ENA_STAT_TX_ENTRY(missed_tx),
  96 };
  97
  98 static const struct ena_stats ena_stats_rx_strings[] = {
  99         ENA_STAT_RX_ENTRY(cnt),
 100         ENA_STAT_RX_ENTRY(bytes),
 101         ENA_STAT_RX_ENTRY(refill_partial),
 102         ENA_STAT_RX_ENTRY(l3_csum_bad),
 103         ENA_STAT_RX_ENTRY(l4_csum_bad),
 104         ENA_STAT_RX_ENTRY(l4_csum_good),
 105         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 106         ENA_STAT_RX_ENTRY(bad_desc_num),
 107         ENA_STAT_RX_ENTRY(bad_req_id),
 108 };
 109
 110 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 111 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 112 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 113 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 114
 115 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
 116                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
 117                         RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
 118                         RTE_ETH_TX_OFFLOAD_TCP_TSO)
 119 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
 120                        RTE_MBUF_F_TX_IP_CKSUM |\
 121                        RTE_MBUF_F_TX_TCP_SEG)
 122
 123 /** Vendor ID used by Amazon devices */
 124 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 125 /** Amazon devices */
 126 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 127 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 128
 129 #define ENA_TX_OFFLOAD_MASK     (RTE_MBUF_F_TX_L4_MASK |         \
 130         RTE_MBUF_F_TX_IPV6 |            \
 131         RTE_MBUF_F_TX_IPV4 |            \
 132         RTE_MBUF_F_TX_IP_CKSUM |        \
 133         RTE_MBUF_F_TX_TCP_SEG)
 134
 135 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 136         (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 137
 138 /** HW specific offloads capabilities. */
 139 /* IPv4 checksum offload. */
 140 #define ENA_L3_IPV4_CSUM                0x0001
 141 /* TCP/UDP checksum offload for IPv4 packets. */
 142 #define ENA_L4_IPV4_CSUM                0x0002
 143 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 144 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 145 /* TCP/UDP checksum offload for IPv6 packets. */
 146 #define ENA_L4_IPV6_CSUM                0x0008
 147 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 148 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 149 /* TSO support for IPv4 packets. */
 150 #define ENA_IPV4_TSO                    0x0020
 151
 152 /* Device supports setting RSS hash. */
 153 #define ENA_RX_RSS_HASH                 0x0040
 154
 155 static const struct rte_pci_id pci_id_ena_map[] = {
 156         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 157         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 158         { .device_id = 0 },
 159 };
 160
 161 static struct ena_aenq_handlers aenq_handlers;
 162
 163 static int ena_device_init(struct ena_adapter *adapter,
 164                            struct rte_pci_device *pdev,
 165                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 166 static int ena_dev_configure(struct rte_eth_dev *dev);
 167 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 168         struct ena_tx_buffer *tx_info,
 169         struct rte_mbuf *mbuf,
 170         void **push_header,
 171         uint16_t *header_len);
 172 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 173 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 174 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 175                                   uint16_t nb_pkts);
 176 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 177                 uint16_t nb_pkts);
 178 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 179                               uint16_t nb_desc, unsigned int socket_id,
 180                               const struct rte_eth_txconf *tx_conf);
 181 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 182                               uint16_t nb_desc, unsigned int socket_id,
 183                               const struct rte_eth_rxconf *rx_conf,
 184                               struct rte_mempool *mp);
 185 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 186 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 187                                     struct ena_com_rx_buf_info *ena_bufs,
 188                                     uint32_t descs,
 189                                     uint16_t *next_to_clean,
 190                                     uint8_t offset);
 191 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 192                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 193 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 194                                   struct rte_mbuf *mbuf, uint16_t id);
 195 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 196 static void ena_init_rings(struct ena_adapter *adapter,
 197                            bool disable_meta_caching);
 198 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 199 static int ena_start(struct rte_eth_dev *dev);
 200 static int ena_stop(struct rte_eth_dev *dev);
 201 static int ena_close(struct rte_eth_dev *dev);
 202 static int ena_dev_reset(struct rte_eth_dev *dev);
 203 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 204 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 205 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 206 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 207 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 208 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 209 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 210 static int ena_link_update(struct rte_eth_dev *dev,
 211                            int wait_to_complete);
 212 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 213 static void ena_queue_stop(struct ena_ring *ring);
 214 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 215                               enum ena_ring_type ring_type);
 216 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 217 static int ena_queue_start_all(struct rte_eth_dev *dev,
 218                                enum ena_ring_type ring_type);
 219 static void ena_stats_restart(struct rte_eth_dev *dev);
 220 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 221 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 222 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 223 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 224 static int ena_infos_get(struct rte_eth_dev *dev,
 225                          struct rte_eth_dev_info *dev_info);
 226 static void ena_interrupt_handler_rte(void *cb_arg);
 227 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 228 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 229 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 230 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 231                                 struct rte_eth_xstat_name *xstats_names,
 232                                 unsigned int n);
 233 static int ena_xstats_get(struct rte_eth_dev *dev,
 234                           struct rte_eth_xstat *stats,
 235                           unsigned int n);
 236 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 237                                 const uint64_t *ids,
 238                                 uint64_t *values,
 239                                 unsigned int n);
 240 static int ena_process_bool_devarg(const char *key,
 241                                    const char *value,
 242                                    void *opaque);
 243 static int ena_parse_devargs(struct ena_adapter *adapter,
 244                              struct rte_devargs *devargs);
 245 static int ena_copy_eni_stats(struct ena_adapter *adapter,
 246                               struct ena_stats_eni *stats);
 247 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 248 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                     uint16_t queue_id);
 250 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                      uint16_t queue_id);
 252 static int ena_configure_aenq(struct ena_adapter *adapter);
 253 static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg,
 254                                  const void *peer);
 255
 256 static const struct eth_dev_ops ena_dev_ops = {
 257         .dev_configure        = ena_dev_configure,
 258         .dev_infos_get        = ena_infos_get,
 259         .rx_queue_setup       = ena_rx_queue_setup,
 260         .tx_queue_setup       = ena_tx_queue_setup,
 261         .dev_start            = ena_start,
 262         .dev_stop             = ena_stop,
 263         .link_update          = ena_link_update,
 264         .stats_get            = ena_stats_get,
 265         .xstats_get_names     = ena_xstats_get_names,
 266         .xstats_get           = ena_xstats_get,
 267         .xstats_get_by_id     = ena_xstats_get_by_id,
 268         .mtu_set              = ena_mtu_set,
 269         .rx_queue_release     = ena_rx_queue_release,
 270         .tx_queue_release     = ena_tx_queue_release,
 271         .dev_close            = ena_close,
 272         .dev_reset            = ena_dev_reset,
 273         .reta_update          = ena_rss_reta_update,
 274         .reta_query           = ena_rss_reta_query,
 275         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 276         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 277         .rss_hash_update      = ena_rss_hash_update,
 278         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 279 };
 280
 281 /*********************************************************************
 282  *  Multi-Process communication bits
 283  *********************************************************************/
 284 /* rte_mp IPC message name */
 285 #define ENA_MP_NAME     "net_ena_mp"
 286 /* Request timeout in seconds */
 287 #define ENA_MP_REQ_TMO  5
 288
 289 /** Proxy request type */
 290 enum ena_mp_req {
 291         ENA_MP_DEV_STATS_GET,
 292         ENA_MP_ENI_STATS_GET,
 293         ENA_MP_MTU_SET,
 294         ENA_MP_IND_TBL_GET,
 295         ENA_MP_IND_TBL_SET
 296 };
 297
 298 /** Proxy message body. Shared between requests and responses. */
 299 struct ena_mp_body {
 300         /* Message type */
 301         enum ena_mp_req type;
 302         int port_id;
 303         /* Processing result. Set in replies. 0 if message succeeded, negative
 304          * error code otherwise.
 305          */
 306         int result;
 307         union {
 308                 int mtu; /* For ENA_MP_MTU_SET */
 309         } args;
 310 };
 311
 312 /**
 313  * Initialize IPC message.
 314  *
 315  * @param[out] msg
 316  *   Pointer to the message to initialize.
 317  * @param[in] type
 318  *   Message type.
 319  * @param[in] port_id
 320  *   Port ID of target device.
 321  *
 322  */
 323 static void
 324 mp_msg_init(struct rte_mp_msg *msg, enum ena_mp_req type, int port_id)
 325 {
 326         struct ena_mp_body *body = (struct ena_mp_body *)&msg->param;
 327
 328         memset(msg, 0, sizeof(*msg));
 329         strlcpy(msg->name, ENA_MP_NAME, sizeof(msg->name));
 330         msg->len_param = sizeof(*body);
 331         body->type = type;
 332         body->port_id = port_id;
 333 }
 334
 335 /*********************************************************************
 336  *  Multi-Process communication PMD API
 337  *********************************************************************/
 338 /**
 339  * Define proxy request descriptor
 340  *
 341  * Used to define all structures and functions required for proxying a given
 342  * function to the primary process including the code to perform to prepare the
 343  * request and process the response.
 344  *
 345  * @param[in] f
 346  *   Name of the function to proxy
 347  * @param[in] t
 348  *   Message type to use
 349  * @param[in] prep
 350  *   Body of a function to prepare the request in form of a statement
 351  *   expression. It is passed all the original function arguments along with two
 352  *   extra ones:
 353  *   - struct ena_adapter *adapter - PMD data of the device calling the proxy.
 354  *   - struct ena_mp_body *req - body of a request to prepare.
 355  * @param[in] proc
 356  *   Body of a function to process the response in form of a statement
 357  *   expression. It is passed all the original function arguments along with two
 358  *   extra ones:
 359  *   - struct ena_adapter *adapter - PMD data of the device calling the proxy.
 360  *   - struct ena_mp_body *rsp - body of a response to process.
 361  * @param ...
 362  *   Proxied function's arguments
 363  *
 364  * @note Inside prep and proc any parameters which aren't used should be marked
 365  *       as such (with ENA_TOUCH or __rte_unused).
 366  */
 367 #define ENA_PROXY_DESC(f, t, prep, proc, ...)                   \
 368         static const enum ena_mp_req mp_type_ ## f =  t;        \
 369         static const char *mp_name_ ## f = #t;                  \
 370         static void mp_prep_ ## f(struct ena_adapter *adapter,  \
 371                                   struct ena_mp_body *req,      \
 372                                   __VA_ARGS__)                  \
 373         {                                                       \
 374                 prep;                                           \
 375         }                                                       \
 376         static void mp_proc_ ## f(struct ena_adapter *adapter,  \
 377                                   struct ena_mp_body *rsp,      \
 378                                   __VA_ARGS__)                  \
 379         {                                                       \
 380                 proc;                                           \
 381         }
 382
 383 /**
 384  * Proxy wrapper for calling primary functions in a secondary process.
 385  *
 386  * Depending on whether called in primary or secondary process, calls the
 387  * @p func directly or proxies the call to the primary process via rte_mp IPC.
 388  * This macro requires a proxy request descriptor to be defined for @p func
 389  * using ENA_PROXY_DESC() macro.
 390  *
 391  * @param[in/out] a
 392  *   Device PMD data. Used for sending the message and sharing message results
 393  *   between primary and secondary.
 394  * @param[in] f
 395  *   Function to proxy.
 396  * @param ...
 397  *   Arguments of @p func.
 398  *
 399  * @return
 400  *   - 0: Processing succeeded and response handler was called.
 401  *   - -EPERM: IPC is unavailable on this platform. This means only primary
 402  *             process may call the proxied function.
 403  *   - -EIO:   IPC returned error on request send. Inspect rte_errno detailed
 404  *             error code.
 405  *   - Negative error code from the proxied function.
 406  *
 407  * @note This mechanism is geared towards control-path tasks. Avoid calling it
 408  *       in fast-path unless unbound delays are allowed. This is due to the IPC
 409  *       mechanism itself (socket based).
 410  * @note Due to IPC parameter size limitations the proxy logic shares call
 411  *       results through the struct ena_adapter shared memory. This makes the
 412  *       proxy mechanism strictly single-threaded. Therefore be sure to make all
 413  *       calls to the same proxied function under the same lock.
 414  */
 415 #define ENA_PROXY(a, f, ...)                                            \
 416 ({                                                                      \
 417         struct ena_adapter *_a = (a);                                   \
 418         struct timespec ts = { .tv_sec = ENA_MP_REQ_TMO };              \
 419         struct ena_mp_body *req, *rsp;                                  \
 420         struct rte_mp_reply mp_rep;                                     \
 421         struct rte_mp_msg mp_req;                                       \
 422         int ret;                                                        \
 423                                                                         \
 424         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {               \
 425                 ret = f(__VA_ARGS__);                                   \
 426         } else {                                                        \
 427                 /* Prepare and send request */                          \
 428                 req = (struct ena_mp_body *)&mp_req.param;              \
 429                 mp_msg_init(&mp_req, mp_type_ ## f, _a->edev_data->port_id); \
 430                 mp_prep_ ## f(_a, req, ## __VA_ARGS__);                 \
 431                                                                         \
 432                 ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);       \
 433                 if (likely(!ret)) {                                     \
 434                         RTE_ASSERT(mp_rep.nb_received == 1);            \
 435                         rsp = (struct ena_mp_body *)&mp_rep.msgs[0].param; \
 436                         ret = rsp->result;                              \
 437                         if (ret == 0) {                                 \
 438                                 mp_proc_##f(_a, rsp, ## __VA_ARGS__);   \
 439                         } else {                                        \
 440                                 PMD_DRV_LOG(ERR,                        \
 441                                             "%s returned error: %d\n",  \
 442                                             mp_name_ ## f, rsp->result);\
 443                         }                                               \
 444                         free(mp_rep.msgs);                              \
 445                 } else if (rte_errno == ENOTSUP) {                      \
 446                         PMD_DRV_LOG(ERR,                                \
 447                                     "No IPC, can't proxy to primary\n");\
 448                         ret = -rte_errno;                               \
 449                 } else {                                                \
 450                         PMD_DRV_LOG(ERR, "Request %s failed: %s\n",     \
 451                                     mp_name_ ## f,                      \
 452                                     rte_strerror(rte_errno));           \
 453                         ret = -EIO;                                     \
 454                 }                                                       \
 455         }                                                               \
 456         ret;                                                            \
 457 })
 458
 459 /*********************************************************************
 460  *  Multi-Process communication request descriptors
 461  *********************************************************************/
 462
 463 ENA_PROXY_DESC(ena_com_get_dev_basic_stats, ENA_MP_DEV_STATS_GET,
 464 ({
 465         ENA_TOUCH(adapter);
 466         ENA_TOUCH(req);
 467         ENA_TOUCH(ena_dev);
 468         ENA_TOUCH(stats);
 469 }),
 470 ({
 471         ENA_TOUCH(rsp);
 472         ENA_TOUCH(ena_dev);
 473         if (stats != &adapter->basic_stats)
 474                 rte_memcpy(stats, &adapter->basic_stats, sizeof(*stats));
 475 }),
 476         struct ena_com_dev *ena_dev, struct ena_admin_basic_stats *stats);
 477
 478 ENA_PROXY_DESC(ena_com_get_eni_stats, ENA_MP_ENI_STATS_GET,
 479 ({
 480         ENA_TOUCH(adapter);
 481         ENA_TOUCH(req);
 482         ENA_TOUCH(ena_dev);
 483         ENA_TOUCH(stats);
 484 }),
 485 ({
 486         ENA_TOUCH(rsp);
 487         ENA_TOUCH(ena_dev);
 488         if (stats != (struct ena_admin_eni_stats *)&adapter->eni_stats)
 489                 rte_memcpy(stats, &adapter->eni_stats, sizeof(*stats));
 490 }),
 491         struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
 492
 493 ENA_PROXY_DESC(ena_com_set_dev_mtu, ENA_MP_MTU_SET,
 494 ({
 495         ENA_TOUCH(adapter);
 496         ENA_TOUCH(ena_dev);
 497         req->args.mtu = mtu;
 498 }),
 499 ({
 500         ENA_TOUCH(adapter);
 501         ENA_TOUCH(rsp);
 502         ENA_TOUCH(ena_dev);
 503         ENA_TOUCH(mtu);
 504 }),
 505         struct ena_com_dev *ena_dev, int mtu);
 506
 507 ENA_PROXY_DESC(ena_com_indirect_table_set, ENA_MP_IND_TBL_SET,
 508 ({
 509         ENA_TOUCH(adapter);
 510         ENA_TOUCH(req);
 511         ENA_TOUCH(ena_dev);
 512 }),
 513 ({
 514         ENA_TOUCH(adapter);
 515         ENA_TOUCH(rsp);
 516         ENA_TOUCH(ena_dev);
 517 }),
 518         struct ena_com_dev *ena_dev);
 519
 520 ENA_PROXY_DESC(ena_com_indirect_table_get, ENA_MP_IND_TBL_GET,
 521 ({
 522         ENA_TOUCH(adapter);
 523         ENA_TOUCH(req);
 524         ENA_TOUCH(ena_dev);
 525         ENA_TOUCH(ind_tbl);
 526 }),
 527 ({
 528         ENA_TOUCH(rsp);
 529         ENA_TOUCH(ena_dev);
 530         if (ind_tbl != adapter->indirect_table)
 531                 rte_memcpy(ind_tbl, adapter->indirect_table,
 532                            sizeof(adapter->indirect_table));
 533 }),
 534         struct ena_com_dev *ena_dev, u32 *ind_tbl);
 535
 536 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring,
 537                                        struct rte_mbuf *mbuf,
 538                                        struct ena_com_rx_ctx *ena_rx_ctx,
 539                                        bool fill_hash)
 540 {
 541         struct ena_stats_rx *rx_stats = &rx_ring->rx_stats;
 542         uint64_t ol_flags = 0;
 543         uint32_t packet_type = 0;
 544
 545         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 546                 packet_type |= RTE_PTYPE_L4_TCP;
 547         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 548                 packet_type |= RTE_PTYPE_L4_UDP;
 549
 550         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 551                 packet_type |= RTE_PTYPE_L3_IPV4;
 552                 if (unlikely(ena_rx_ctx->l3_csum_err)) {
 553                         ++rx_stats->l3_csum_bad;
 554                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 555                 } else {
 556                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 557                 }
 558         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 559                 packet_type |= RTE_PTYPE_L3_IPV6;
 560         }
 561
 562         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) {
 563                 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
 564         } else {
 565                 if (unlikely(ena_rx_ctx->l4_csum_err)) {
 566                         ++rx_stats->l4_csum_bad;
 567                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 568                 } else {
 569                         ++rx_stats->l4_csum_good;
 570                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 571                 }
 572         }
 573
 574         if (fill_hash &&
 575             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 576                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 577                 mbuf->hash.rss = ena_rx_ctx->hash;
 578         }
 579
 580         mbuf->ol_flags = ol_flags;
 581         mbuf->packet_type = packet_type;
 582 }
 583
 584 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 585                                        struct ena_com_tx_ctx *ena_tx_ctx,
 586                                        uint64_t queue_offloads,
 587                                        bool disable_meta_caching)
 588 {
 589         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 590
 591         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 592             (queue_offloads & QUEUE_OFFLOADS)) {
 593                 /* check if TSO is required */
 594                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
 595                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
 596                         ena_tx_ctx->tso_enable = true;
 597
 598                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 599                 }
 600
 601                 /* check if L3 checksum is needed */
 602                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
 603                     (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
 604                         ena_tx_ctx->l3_csum_enable = true;
 605
 606                 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
 607                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 608                 } else {
 609                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 610
 611                         /* set don't fragment (DF) flag */
 612                         if (mbuf->packet_type &
 613                                 (RTE_PTYPE_L4_NONFRAG
 614                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 615                                 ena_tx_ctx->df = true;
 616                 }
 617
 618                 /* check if L4 checksum is needed */
 619                 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
 620                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
 621                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 622                         ena_tx_ctx->l4_csum_enable = true;
 623                 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
 624                                 RTE_MBUF_F_TX_UDP_CKSUM) &&
 625                                 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
 626                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 627                         ena_tx_ctx->l4_csum_enable = true;
 628                 } else {
 629                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 630                         ena_tx_ctx->l4_csum_enable = false;
 631                 }
 632
 633                 ena_meta->mss = mbuf->tso_segsz;
 634                 ena_meta->l3_hdr_len = mbuf->l3_len;
 635                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 636
 637                 ena_tx_ctx->meta_valid = true;
 638         } else if (disable_meta_caching) {
 639                 memset(ena_meta, 0, sizeof(*ena_meta));
 640                 ena_tx_ctx->meta_valid = true;
 641         } else {
 642                 ena_tx_ctx->meta_valid = false;
 643         }
 644 }
 645
 646 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 647 {
 648         struct ena_tx_buffer *tx_info = NULL;
 649
 650         if (likely(req_id < tx_ring->ring_size)) {
 651                 tx_info = &tx_ring->tx_buffer_info[req_id];
 652                 if (likely(tx_info->mbuf))
 653                         return 0;
 654         }
 655
 656         if (tx_info)
 657                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 658         else
 659                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 660
 661         /* Trigger device reset */
 662         ++tx_ring->tx_stats.bad_req_id;
 663         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 664         tx_ring->adapter->trigger_reset = true;
 665         return -EFAULT;
 666 }
 667
 668 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 669 {
 670         struct ena_admin_host_info *host_info;
 671         int rc;
 672
 673         /* Allocate only the host info */
 674         rc = ena_com_allocate_host_info(ena_dev);
 675         if (rc) {
 676                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 677                 return;
 678         }
 679
 680         host_info = ena_dev->host_attr.host_info;
 681
 682         host_info->os_type = ENA_ADMIN_OS_DPDK;
 683         host_info->kernel_ver = RTE_VERSION;
 684         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 685                 sizeof(host_info->kernel_ver_str));
 686         host_info->os_dist = RTE_VERSION;
 687         strlcpy((char *)host_info->os_dist_str, rte_version(),
 688                 sizeof(host_info->os_dist_str));
 689         host_info->driver_version =
 690                 (DRV_MODULE_VER_MAJOR) |
 691                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 692                 (DRV_MODULE_VER_SUBMINOR <<
 693                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 694         host_info->num_cpus = rte_lcore_count();
 695
 696         host_info->driver_supported_features =
 697                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 698                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 699
 700         rc = ena_com_set_host_attributes(ena_dev);
 701         if (rc) {
 702                 if (rc == -ENA_COM_UNSUPPORTED)
 703                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 704                 else
 705                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 706
 707                 goto err;
 708         }
 709
 710         return;
 711
 712 err:
 713         ena_com_delete_host_info(ena_dev);
 714 }
 715
 716 /* This function calculates the number of xstats based on the current config */
 717 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 718 {
 719         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 720                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 721                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 722 }
 723
 724 static void ena_config_debug_area(struct ena_adapter *adapter)
 725 {
 726         u32 debug_area_size;
 727         int rc, ss_count;
 728
 729         ss_count = ena_xstats_calc_num(adapter->edev_data);
 730
 731         /* allocate 32 bytes for each string and 64bit for the value */
 732         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 733
 734         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 735         if (rc) {
 736                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 737                 return;
 738         }
 739
 740         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 741         if (rc) {
 742                 if (rc == -ENA_COM_UNSUPPORTED)
 743                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 744                 else
 745                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 746
 747                 goto err;
 748         }
 749
 750         return;
 751 err:
 752         ena_com_delete_debug_area(&adapter->ena_dev);
 753 }
 754
 755 static int ena_close(struct rte_eth_dev *dev)
 756 {
 757         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 758         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 759         struct ena_adapter *adapter = dev->data->dev_private;
 760         int ret = 0;
 761
 762         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 763                 return 0;
 764
 765         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 766                 ret = ena_stop(dev);
 767         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 768
 769         ena_rx_queue_release_all(dev);
 770         ena_tx_queue_release_all(dev);
 771
 772         rte_free(adapter->drv_stats);
 773         adapter->drv_stats = NULL;
 774
 775         rte_intr_disable(intr_handle);
 776         rte_intr_callback_unregister(intr_handle,
 777                                      ena_interrupt_handler_rte,
 778                                      dev);
 779
 780         /*
 781          * MAC is not allocated dynamically. Setting NULL should prevent from
 782          * release of the resource in the rte_eth_dev_release_port().
 783          */
 784         dev->data->mac_addrs = NULL;
 785
 786         return ret;
 787 }
 788
 789 static int
 790 ena_dev_reset(struct rte_eth_dev *dev)
 791 {
 792         int rc = 0;
 793
 794         /* Cannot release memory in secondary process */
 795         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 796                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 797                 return -EPERM;
 798         }
 799
 800         ena_destroy_device(dev);
 801         rc = eth_ena_dev_init(dev);
 802         if (rc)
 803                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 804
 805         return rc;
 806 }
 807
 808 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 809 {
 810         int nb_queues = dev->data->nb_rx_queues;
 811         int i;
 812
 813         for (i = 0; i < nb_queues; i++)
 814                 ena_rx_queue_release(dev, i);
 815 }
 816
 817 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 818 {
 819         int nb_queues = dev->data->nb_tx_queues;
 820         int i;
 821
 822         for (i = 0; i < nb_queues; i++)
 823                 ena_tx_queue_release(dev, i);
 824 }
 825
 826 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 827 {
 828         struct ena_ring *ring = dev->data->rx_queues[qid];
 829
 830         /* Free ring resources */
 831         rte_free(ring->rx_buffer_info);
 832         ring->rx_buffer_info = NULL;
 833
 834         rte_free(ring->rx_refill_buffer);
 835         ring->rx_refill_buffer = NULL;
 836
 837         rte_free(ring->empty_rx_reqs);
 838         ring->empty_rx_reqs = NULL;
 839
 840         ring->configured = 0;
 841
 842         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 843                 ring->port_id, ring->id);
 844 }
 845
 846 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 847 {
 848         struct ena_ring *ring = dev->data->tx_queues[qid];
 849
 850         /* Free ring resources */
 851         rte_free(ring->push_buf_intermediate_buf);
 852
 853         rte_free(ring->tx_buffer_info);
 854
 855         rte_free(ring->empty_tx_reqs);
 856
 857         ring->empty_tx_reqs = NULL;
 858         ring->tx_buffer_info = NULL;
 859         ring->push_buf_intermediate_buf = NULL;
 860
 861         ring->configured = 0;
 862
 863         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 864                 ring->port_id, ring->id);
 865 }
 866
 867 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 868 {
 869         unsigned int i;
 870
 871         for (i = 0; i < ring->ring_size; ++i) {
 872                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 873                 if (rx_info->mbuf) {
 874                         rte_mbuf_raw_free(rx_info->mbuf);
 875                         rx_info->mbuf = NULL;
 876                 }
 877         }
 878 }
 879
 880 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 881 {
 882         unsigned int i;
 883
 884         for (i = 0; i < ring->ring_size; ++i) {
 885                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 886
 887                 if (tx_buf->mbuf) {
 888                         rte_pktmbuf_free(tx_buf->mbuf);
 889                         tx_buf->mbuf = NULL;
 890                 }
 891         }
 892 }
 893
 894 static int ena_link_update(struct rte_eth_dev *dev,
 895                            __rte_unused int wait_to_complete)
 896 {
 897         struct rte_eth_link *link = &dev->data->dev_link;
 898         struct ena_adapter *adapter = dev->data->dev_private;
 899
 900         link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
 901         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
 902         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 903
 904         return 0;
 905 }
 906
 907 static int ena_queue_start_all(struct rte_eth_dev *dev,
 908                                enum ena_ring_type ring_type)
 909 {
 910         struct ena_adapter *adapter = dev->data->dev_private;
 911         struct ena_ring *queues = NULL;
 912         int nb_queues;
 913         int i = 0;
 914         int rc = 0;
 915
 916         if (ring_type == ENA_RING_TYPE_RX) {
 917                 queues = adapter->rx_ring;
 918                 nb_queues = dev->data->nb_rx_queues;
 919         } else {
 920                 queues = adapter->tx_ring;
 921                 nb_queues = dev->data->nb_tx_queues;
 922         }
 923         for (i = 0; i < nb_queues; i++) {
 924                 if (queues[i].configured) {
 925                         if (ring_type == ENA_RING_TYPE_RX) {
 926                                 ena_assert_msg(
 927                                         dev->data->rx_queues[i] == &queues[i],
 928                                         "Inconsistent state of Rx queues\n");
 929                         } else {
 930                                 ena_assert_msg(
 931                                         dev->data->tx_queues[i] == &queues[i],
 932                                         "Inconsistent state of Tx queues\n");
 933                         }
 934
 935                         rc = ena_queue_start(dev, &queues[i]);
 936
 937                         if (rc) {
 938                                 PMD_INIT_LOG(ERR,
 939                                         "Failed to start queue[%d] of type(%d)\n",
 940                                         i, ring_type);
 941                                 goto err;
 942                         }
 943                 }
 944         }
 945
 946         return 0;
 947
 948 err:
 949         while (i--)
 950                 if (queues[i].configured)
 951                         ena_queue_stop(&queues[i]);
 952
 953         return rc;
 954 }
 955
 956 static int ena_check_valid_conf(struct ena_adapter *adapter)
 957 {
 958         uint32_t mtu = adapter->edev_data->mtu;
 959
 960         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 961                 PMD_INIT_LOG(ERR,
 962                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 963                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 964                 return ENA_COM_UNSUPPORTED;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int
 971 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 972                        bool use_large_llq_hdr)
 973 {
 974         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 975         struct ena_com_dev *ena_dev = ctx->ena_dev;
 976         uint32_t max_tx_queue_size;
 977         uint32_t max_rx_queue_size;
 978
 979         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 980                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 981                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 982                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 983                         max_queue_ext->max_rx_sq_depth);
 984                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 985
 986                 if (ena_dev->tx_mem_queue_type ==
 987                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 988                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 989                                 llq->max_llq_depth);
 990                 } else {
 991                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 992                                 max_queue_ext->max_tx_sq_depth);
 993                 }
 994
 995                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 996                         max_queue_ext->max_per_packet_rx_descs);
 997                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 998                         max_queue_ext->max_per_packet_tx_descs);
 999         } else {
1000                 struct ena_admin_queue_feature_desc *max_queues =
1001                         &ctx->get_feat_ctx->max_queues;
1002                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
1003                         max_queues->max_sq_depth);
1004                 max_tx_queue_size = max_queues->max_cq_depth;
1005
1006                 if (ena_dev->tx_mem_queue_type ==
1007                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1008                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1009                                 llq->max_llq_depth);
1010                 } else {
1011                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
1012                                 max_queues->max_sq_depth);
1013                 }
1014
1015                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1016                         max_queues->max_packet_rx_descs);
1017                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
1018                         max_queues->max_packet_tx_descs);
1019         }
1020
1021         /* Round down to the nearest power of 2 */
1022         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
1023         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
1024
1025         if (use_large_llq_hdr) {
1026                 if ((llq->entry_size_ctrl_supported &
1027                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
1028                     (ena_dev->tx_mem_queue_type ==
1029                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
1030                         max_tx_queue_size /= 2;
1031                         PMD_INIT_LOG(INFO,
1032                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
1033                                 max_tx_queue_size);
1034                 } else {
1035                         PMD_INIT_LOG(ERR,
1036                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
1037                 }
1038         }
1039
1040         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
1041                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
1042                 return -EFAULT;
1043         }
1044
1045         ctx->max_tx_queue_size = max_tx_queue_size;
1046         ctx->max_rx_queue_size = max_rx_queue_size;
1047
1048         return 0;
1049 }
1050
1051 static void ena_stats_restart(struct rte_eth_dev *dev)
1052 {
1053         struct ena_adapter *adapter = dev->data->dev_private;
1054
1055         rte_atomic64_init(&adapter->drv_stats->ierrors);
1056         rte_atomic64_init(&adapter->drv_stats->oerrors);
1057         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
1058         adapter->drv_stats->rx_drops = 0;
1059 }
1060
1061 static int ena_stats_get(struct rte_eth_dev *dev,
1062                           struct rte_eth_stats *stats)
1063 {
1064         struct ena_admin_basic_stats ena_stats;
1065         struct ena_adapter *adapter = dev->data->dev_private;
1066         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1067         int rc;
1068         int i;
1069         int max_rings_stats;
1070
1071         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1072                 return -ENOTSUP;
1073
1074         memset(&ena_stats, 0, sizeof(ena_stats));
1075
1076         rte_spinlock_lock(&adapter->admin_lock);
1077         rc = ENA_PROXY(adapter, ena_com_get_dev_basic_stats, ena_dev,
1078                        &ena_stats);
1079         rte_spinlock_unlock(&adapter->admin_lock);
1080         if (unlikely(rc)) {
1081                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
1082                 return rc;
1083         }
1084
1085         /* Set of basic statistics from ENA */
1086         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1087                                           ena_stats.rx_pkts_low);
1088         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1089                                           ena_stats.tx_pkts_low);
1090         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1091                                         ena_stats.rx_bytes_low);
1092         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1093                                         ena_stats.tx_bytes_low);
1094
1095         /* Driver related stats */
1096         stats->imissed = adapter->drv_stats->rx_drops;
1097         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1098         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1099         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1100
1101         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1102                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1103         for (i = 0; i < max_rings_stats; ++i) {
1104                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1105
1106                 stats->q_ibytes[i] = rx_stats->bytes;
1107                 stats->q_ipackets[i] = rx_stats->cnt;
1108                 stats->q_errors[i] = rx_stats->bad_desc_num +
1109                         rx_stats->bad_req_id;
1110         }
1111
1112         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1113                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1114         for (i = 0; i < max_rings_stats; ++i) {
1115                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1116
1117                 stats->q_obytes[i] = tx_stats->bytes;
1118                 stats->q_opackets[i] = tx_stats->cnt;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1125 {
1126         struct ena_adapter *adapter;
1127         struct ena_com_dev *ena_dev;
1128         int rc = 0;
1129
1130         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1131         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1132         adapter = dev->data->dev_private;
1133
1134         ena_dev = &adapter->ena_dev;
1135         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1136
1137         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
1138                 PMD_DRV_LOG(ERR,
1139                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
1140                         mtu, adapter->max_mtu, ENA_MIN_MTU);
1141                 return -EINVAL;
1142         }
1143
1144         rc = ENA_PROXY(adapter, ena_com_set_dev_mtu, ena_dev, mtu);
1145         if (rc)
1146                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1147         else
1148                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
1149
1150         return rc;
1151 }
1152
1153 static int ena_start(struct rte_eth_dev *dev)
1154 {
1155         struct ena_adapter *adapter = dev->data->dev_private;
1156         uint64_t ticks;
1157         int rc = 0;
1158
1159         /* Cannot allocate memory in secondary process */
1160         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1161                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
1162                 return -EPERM;
1163         }
1164
1165         rc = ena_check_valid_conf(adapter);
1166         if (rc)
1167                 return rc;
1168
1169         rc = ena_setup_rx_intr(dev);
1170         if (rc)
1171                 return rc;
1172
1173         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1174         if (rc)
1175                 return rc;
1176
1177         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1178         if (rc)
1179                 goto err_start_tx;
1180
1181         if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
1182                 rc = ena_rss_configure(adapter);
1183                 if (rc)
1184                         goto err_rss_init;
1185         }
1186
1187         ena_stats_restart(dev);
1188
1189         adapter->timestamp_wd = rte_get_timer_cycles();
1190         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1191
1192         ticks = rte_get_timer_hz();
1193         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1194                         ena_timer_wd_callback, dev);
1195
1196         ++adapter->dev_stats.dev_start;
1197         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1198
1199         return 0;
1200
1201 err_rss_init:
1202         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1203 err_start_tx:
1204         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1205         return rc;
1206 }
1207
1208 static int ena_stop(struct rte_eth_dev *dev)
1209 {
1210         struct ena_adapter *adapter = dev->data->dev_private;
1211         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1212         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1213         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1214         int rc;
1215
1216         /* Cannot free memory in secondary process */
1217         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1218                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
1219                 return -EPERM;
1220         }
1221
1222         rte_timer_stop_sync(&adapter->timer_wd);
1223         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1224         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1225
1226         if (adapter->trigger_reset) {
1227                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1228                 if (rc)
1229                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
1230         }
1231
1232         rte_intr_disable(intr_handle);
1233
1234         rte_intr_efd_disable(intr_handle);
1235
1236         /* Cleanup vector list */
1237         rte_intr_vec_list_free(intr_handle);
1238
1239         rte_intr_enable(intr_handle);
1240
1241         ++adapter->dev_stats.dev_stop;
1242         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1243         dev->data->dev_started = 0;
1244
1245         return 0;
1246 }
1247
1248 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
1249 {
1250         struct ena_adapter *adapter = ring->adapter;
1251         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1252         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1253         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1254         struct ena_com_create_io_ctx ctx =
1255                 /* policy set to _HOST just to satisfy icc compiler */
1256                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1257                   0, 0, 0, 0, 0 };
1258         uint16_t ena_qid;
1259         unsigned int i;
1260         int rc;
1261
1262         ctx.msix_vector = -1;
1263         if (ring->type == ENA_RING_TYPE_TX) {
1264                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1265                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1266                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1267                 for (i = 0; i < ring->ring_size; i++)
1268                         ring->empty_tx_reqs[i] = i;
1269         } else {
1270                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1271                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1272                 if (rte_intr_dp_is_en(intr_handle))
1273                         ctx.msix_vector =
1274                                 rte_intr_vec_list_index_get(intr_handle,
1275                                                                    ring->id);
1276
1277                 for (i = 0; i < ring->ring_size; i++)
1278                         ring->empty_rx_reqs[i] = i;
1279         }
1280         ctx.queue_size = ring->ring_size;
1281         ctx.qid = ena_qid;
1282         ctx.numa_node = ring->numa_socket_id;
1283
1284         rc = ena_com_create_io_queue(ena_dev, &ctx);
1285         if (rc) {
1286                 PMD_DRV_LOG(ERR,
1287                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1288                         ring->id, ena_qid, rc);
1289                 return rc;
1290         }
1291
1292         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1293                                      &ring->ena_com_io_sq,
1294                                      &ring->ena_com_io_cq);
1295         if (rc) {
1296                 PMD_DRV_LOG(ERR,
1297                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1298                         ring->id, rc);
1299                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1300                 return rc;
1301         }
1302
1303         if (ring->type == ENA_RING_TYPE_TX)
1304                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1305
1306         /* Start with Rx interrupts being masked. */
1307         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1308                 ena_rx_queue_intr_disable(dev, ring->id);
1309
1310         return 0;
1311 }
1312
1313 static void ena_queue_stop(struct ena_ring *ring)
1314 {
1315         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1316
1317         if (ring->type == ENA_RING_TYPE_RX) {
1318                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1319                 ena_rx_queue_release_bufs(ring);
1320         } else {
1321                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1322                 ena_tx_queue_release_bufs(ring);
1323         }
1324 }
1325
1326 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1327                               enum ena_ring_type ring_type)
1328 {
1329         struct ena_adapter *adapter = dev->data->dev_private;
1330         struct ena_ring *queues = NULL;
1331         uint16_t nb_queues, i;
1332
1333         if (ring_type == ENA_RING_TYPE_RX) {
1334                 queues = adapter->rx_ring;
1335                 nb_queues = dev->data->nb_rx_queues;
1336         } else {
1337                 queues = adapter->tx_ring;
1338                 nb_queues = dev->data->nb_tx_queues;
1339         }
1340
1341         for (i = 0; i < nb_queues; ++i)
1342                 if (queues[i].configured)
1343                         ena_queue_stop(&queues[i]);
1344 }
1345
1346 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1347 {
1348         int rc, bufs_num;
1349
1350         ena_assert_msg(ring->configured == 1,
1351                        "Trying to start unconfigured queue\n");
1352
1353         rc = ena_create_io_queue(dev, ring);
1354         if (rc) {
1355                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1356                 return rc;
1357         }
1358
1359         ring->next_to_clean = 0;
1360         ring->next_to_use = 0;
1361
1362         if (ring->type == ENA_RING_TYPE_TX) {
1363                 ring->tx_stats.available_desc =
1364                         ena_com_free_q_entries(ring->ena_com_io_sq);
1365                 return 0;
1366         }
1367
1368         bufs_num = ring->ring_size - 1;
1369         rc = ena_populate_rx_queue(ring, bufs_num);
1370         if (rc != bufs_num) {
1371                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1372                                          ENA_IO_RXQ_IDX(ring->id));
1373                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1374                 return ENA_COM_FAULT;
1375         }
1376         /* Flush per-core RX buffers pools cache as they can be used on other
1377          * cores as well.
1378          */
1379         rte_mempool_cache_flush(NULL, ring->mb_pool);
1380
1381         return 0;
1382 }
1383
1384 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1385                               uint16_t queue_idx,
1386                               uint16_t nb_desc,
1387                               unsigned int socket_id,
1388                               const struct rte_eth_txconf *tx_conf)
1389 {
1390         struct ena_ring *txq = NULL;
1391         struct ena_adapter *adapter = dev->data->dev_private;
1392         unsigned int i;
1393         uint16_t dyn_thresh;
1394
1395         txq = &adapter->tx_ring[queue_idx];
1396
1397         if (txq->configured) {
1398                 PMD_DRV_LOG(CRIT,
1399                         "API violation. Queue[%d] is already configured\n",
1400                         queue_idx);
1401                 return ENA_COM_FAULT;
1402         }
1403
1404         if (!rte_is_power_of_2(nb_desc)) {
1405                 PMD_DRV_LOG(ERR,
1406                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1407                         nb_desc);
1408                 return -EINVAL;
1409         }
1410
1411         if (nb_desc > adapter->max_tx_ring_size) {
1412                 PMD_DRV_LOG(ERR,
1413                         "Unsupported size of Tx queue (max size: %d)\n",
1414                         adapter->max_tx_ring_size);
1415                 return -EINVAL;
1416         }
1417
1418         txq->port_id = dev->data->port_id;
1419         txq->next_to_clean = 0;
1420         txq->next_to_use = 0;
1421         txq->ring_size = nb_desc;
1422         txq->size_mask = nb_desc - 1;
1423         txq->numa_socket_id = socket_id;
1424         txq->pkts_without_db = false;
1425         txq->last_cleanup_ticks = 0;
1426
1427         txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1428                 sizeof(struct ena_tx_buffer) * txq->ring_size,
1429                 RTE_CACHE_LINE_SIZE,
1430                 socket_id);
1431         if (!txq->tx_buffer_info) {
1432                 PMD_DRV_LOG(ERR,
1433                         "Failed to allocate memory for Tx buffer info\n");
1434                 return -ENOMEM;
1435         }
1436
1437         txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1438                 sizeof(uint16_t) * txq->ring_size,
1439                 RTE_CACHE_LINE_SIZE,
1440                 socket_id);
1441         if (!txq->empty_tx_reqs) {
1442                 PMD_DRV_LOG(ERR,
1443                         "Failed to allocate memory for empty Tx requests\n");
1444                 rte_free(txq->tx_buffer_info);
1445                 return -ENOMEM;
1446         }
1447
1448         txq->push_buf_intermediate_buf =
1449                 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1450                         txq->tx_max_header_size,
1451                         RTE_CACHE_LINE_SIZE,
1452                         socket_id);
1453         if (!txq->push_buf_intermediate_buf) {
1454                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1455                 rte_free(txq->tx_buffer_info);
1456                 rte_free(txq->empty_tx_reqs);
1457                 return -ENOMEM;
1458         }
1459
1460         for (i = 0; i < txq->ring_size; i++)
1461                 txq->empty_tx_reqs[i] = i;
1462
1463         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1464
1465         /* Check if caller provided the Tx cleanup threshold value. */
1466         if (tx_conf->tx_free_thresh != 0) {
1467                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1468         } else {
1469                 dyn_thresh = txq->ring_size -
1470                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1471                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1472                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1473         }
1474
1475         txq->missing_tx_completion_threshold =
1476                 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1477
1478         /* Store pointer to this queue in upper layer */
1479         txq->configured = 1;
1480         dev->data->tx_queues[queue_idx] = txq;
1481
1482         return 0;
1483 }
1484
1485 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1486                               uint16_t queue_idx,
1487                               uint16_t nb_desc,
1488                               unsigned int socket_id,
1489                               const struct rte_eth_rxconf *rx_conf,
1490                               struct rte_mempool *mp)
1491 {
1492         struct ena_adapter *adapter = dev->data->dev_private;
1493         struct ena_ring *rxq = NULL;
1494         size_t buffer_size;
1495         int i;
1496         uint16_t dyn_thresh;
1497
1498         rxq = &adapter->rx_ring[queue_idx];
1499         if (rxq->configured) {
1500                 PMD_DRV_LOG(CRIT,
1501                         "API violation. Queue[%d] is already configured\n",
1502                         queue_idx);
1503                 return ENA_COM_FAULT;
1504         }
1505
1506         if (!rte_is_power_of_2(nb_desc)) {
1507                 PMD_DRV_LOG(ERR,
1508                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1509                         nb_desc);
1510                 return -EINVAL;
1511         }
1512
1513         if (nb_desc > adapter->max_rx_ring_size) {
1514                 PMD_DRV_LOG(ERR,
1515                         "Unsupported size of Rx queue (max size: %d)\n",
1516                         adapter->max_rx_ring_size);
1517                 return -EINVAL;
1518         }
1519
1520         /* ENA isn't supporting buffers smaller than 1400 bytes */
1521         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1522         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1523                 PMD_DRV_LOG(ERR,
1524                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1525                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1526                 return -EINVAL;
1527         }
1528
1529         rxq->port_id = dev->data->port_id;
1530         rxq->next_to_clean = 0;
1531         rxq->next_to_use = 0;
1532         rxq->ring_size = nb_desc;
1533         rxq->size_mask = nb_desc - 1;
1534         rxq->numa_socket_id = socket_id;
1535         rxq->mb_pool = mp;
1536
1537         rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1538                 sizeof(struct ena_rx_buffer) * nb_desc,
1539                 RTE_CACHE_LINE_SIZE,
1540                 socket_id);
1541         if (!rxq->rx_buffer_info) {
1542                 PMD_DRV_LOG(ERR,
1543                         "Failed to allocate memory for Rx buffer info\n");
1544                 return -ENOMEM;
1545         }
1546
1547         rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1548                 sizeof(struct rte_mbuf *) * nb_desc,
1549                 RTE_CACHE_LINE_SIZE,
1550                 socket_id);
1551         if (!rxq->rx_refill_buffer) {
1552                 PMD_DRV_LOG(ERR,
1553                         "Failed to allocate memory for Rx refill buffer\n");
1554                 rte_free(rxq->rx_buffer_info);
1555                 rxq->rx_buffer_info = NULL;
1556                 return -ENOMEM;
1557         }
1558
1559         rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1560                 sizeof(uint16_t) * nb_desc,
1561                 RTE_CACHE_LINE_SIZE,
1562                 socket_id);
1563         if (!rxq->empty_rx_reqs) {
1564                 PMD_DRV_LOG(ERR,
1565                         "Failed to allocate memory for empty Rx requests\n");
1566                 rte_free(rxq->rx_buffer_info);
1567                 rxq->rx_buffer_info = NULL;
1568                 rte_free(rxq->rx_refill_buffer);
1569                 rxq->rx_refill_buffer = NULL;
1570                 return -ENOMEM;
1571         }
1572
1573         for (i = 0; i < nb_desc; i++)
1574                 rxq->empty_rx_reqs[i] = i;
1575
1576         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1577
1578         if (rx_conf->rx_free_thresh != 0) {
1579                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1580         } else {
1581                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1582                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1583                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1584         }
1585
1586         /* Store pointer to this queue in upper layer */
1587         rxq->configured = 1;
1588         dev->data->rx_queues[queue_idx] = rxq;
1589
1590         return 0;
1591 }
1592
1593 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1594                                   struct rte_mbuf *mbuf, uint16_t id)
1595 {
1596         struct ena_com_buf ebuf;
1597         int rc;
1598
1599         /* prepare physical address for DMA transaction */
1600         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1601         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1602
1603         /* pass resource to device */
1604         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1605         if (unlikely(rc != 0))
1606                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1607
1608         return rc;
1609 }
1610
1611 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1612 {
1613         unsigned int i;
1614         int rc;
1615         uint16_t next_to_use = rxq->next_to_use;
1616         uint16_t req_id;
1617 #ifdef RTE_ETHDEV_DEBUG_RX
1618         uint16_t in_use;
1619 #endif
1620         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1621
1622         if (unlikely(!count))
1623                 return 0;
1624
1625 #ifdef RTE_ETHDEV_DEBUG_RX
1626         in_use = rxq->ring_size - 1 -
1627                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1628         if (unlikely((in_use + count) >= rxq->ring_size))
1629                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1630 #endif
1631
1632         /* get resources for incoming packets */
1633         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1634         if (unlikely(rc < 0)) {
1635                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1636                 ++rxq->rx_stats.mbuf_alloc_fail;
1637                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1638                 return 0;
1639         }
1640
1641         for (i = 0; i < count; i++) {
1642                 struct rte_mbuf *mbuf = mbufs[i];
1643                 struct ena_rx_buffer *rx_info;
1644
1645                 if (likely((i + 4) < count))
1646                         rte_prefetch0(mbufs[i + 4]);
1647
1648                 req_id = rxq->empty_rx_reqs[next_to_use];
1649                 rx_info = &rxq->rx_buffer_info[req_id];
1650
1651                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1652                 if (unlikely(rc != 0))
1653                         break;
1654
1655                 rx_info->mbuf = mbuf;
1656                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1657         }
1658
1659         if (unlikely(i < count)) {
1660                 PMD_RX_LOG(WARNING,
1661                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1662                         rxq->id, i, count);
1663                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1664                 ++rxq->rx_stats.refill_partial;
1665         }
1666
1667         /* When we submitted free resources to device... */
1668         if (likely(i > 0)) {
1669                 /* ...let HW know that it can fill buffers with data. */
1670                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1671
1672                 rxq->next_to_use = next_to_use;
1673         }
1674
1675         return i;
1676 }
1677
1678 static int ena_device_init(struct ena_adapter *adapter,
1679                            struct rte_pci_device *pdev,
1680                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1681 {
1682         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1683         uint32_t aenq_groups;
1684         int rc;
1685         bool readless_supported;
1686
1687         /* Initialize mmio registers */
1688         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1689         if (rc) {
1690                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1691                 return rc;
1692         }
1693
1694         /* The PCIe configuration space revision id indicate if mmio reg
1695          * read is disabled.
1696          */
1697         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1698         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1699
1700         /* reset device */
1701         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1702         if (rc) {
1703                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1704                 goto err_mmio_read_less;
1705         }
1706
1707         /* check FW version */
1708         rc = ena_com_validate_version(ena_dev);
1709         if (rc) {
1710                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1711                 goto err_mmio_read_less;
1712         }
1713
1714         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1715
1716         /* ENA device administration layer init */
1717         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1718         if (rc) {
1719                 PMD_DRV_LOG(ERR,
1720                         "Cannot initialize ENA admin queue\n");
1721                 goto err_mmio_read_less;
1722         }
1723
1724         /* To enable the msix interrupts the driver needs to know the number
1725          * of queues. So the driver uses polling mode to retrieve this
1726          * information.
1727          */
1728         ena_com_set_admin_polling_mode(ena_dev, true);
1729
1730         ena_config_host_info(ena_dev);
1731
1732         /* Get Device Attributes and features */
1733         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1734         if (rc) {
1735                 PMD_DRV_LOG(ERR,
1736                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1737                 goto err_admin_init;
1738         }
1739
1740         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1741                       BIT(ENA_ADMIN_NOTIFICATION) |
1742                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1743                       BIT(ENA_ADMIN_FATAL_ERROR) |
1744                       BIT(ENA_ADMIN_WARNING);
1745
1746         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1747
1748         adapter->all_aenq_groups = aenq_groups;
1749
1750         return 0;
1751
1752 err_admin_init:
1753         ena_com_admin_destroy(ena_dev);
1754
1755 err_mmio_read_less:
1756         ena_com_mmio_reg_read_request_destroy(ena_dev);
1757
1758         return rc;
1759 }
1760
1761 static void ena_interrupt_handler_rte(void *cb_arg)
1762 {
1763         struct rte_eth_dev *dev = cb_arg;
1764         struct ena_adapter *adapter = dev->data->dev_private;
1765         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1766
1767         ena_com_admin_q_comp_intr_handler(ena_dev);
1768         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1769                 ena_com_aenq_intr_handler(ena_dev, dev);
1770 }
1771
1772 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1773 {
1774         if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)))
1775                 return;
1776
1777         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1778                 return;
1779
1780         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1781             adapter->keep_alive_timeout)) {
1782                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1783                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1784                 adapter->trigger_reset = true;
1785                 ++adapter->dev_stats.wd_expired;
1786         }
1787 }
1788
1789 /* Check if admin queue is enabled */
1790 static void check_for_admin_com_state(struct ena_adapter *adapter)
1791 {
1792         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1793                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1794                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1795                 adapter->trigger_reset = true;
1796         }
1797 }
1798
1799 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1800                                             struct ena_ring *tx_ring)
1801 {
1802         struct ena_tx_buffer *tx_buf;
1803         uint64_t timestamp;
1804         uint64_t completion_delay;
1805         uint32_t missed_tx = 0;
1806         unsigned int i;
1807         int rc = 0;
1808
1809         for (i = 0; i < tx_ring->ring_size; ++i) {
1810                 tx_buf = &tx_ring->tx_buffer_info[i];
1811                 timestamp = tx_buf->timestamp;
1812
1813                 if (timestamp == 0)
1814                         continue;
1815
1816                 completion_delay = rte_get_timer_cycles() - timestamp;
1817                 if (completion_delay > adapter->missing_tx_completion_to) {
1818                         if (unlikely(!tx_buf->print_once)) {
1819                                 PMD_TX_LOG(WARNING,
1820                                         "Found a Tx that wasn't completed on time, qid %d, index %d. "
1821                                         "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1822                                         tx_ring->id, i, completion_delay /
1823                                         rte_get_timer_hz() * 1000);
1824                                 tx_buf->print_once = true;
1825                         }
1826                         ++missed_tx;
1827                 }
1828         }
1829
1830         if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1831                 PMD_DRV_LOG(ERR,
1832                         "The number of lost Tx completions is above the threshold (%d > %d). "
1833                         "Trigger the device reset.\n",
1834                         missed_tx,
1835                         tx_ring->missing_tx_completion_threshold);
1836                 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1837                 adapter->trigger_reset = true;
1838                 rc = -EIO;
1839         }
1840
1841         tx_ring->tx_stats.missed_tx += missed_tx;
1842
1843         return rc;
1844 }
1845
1846 static void check_for_tx_completions(struct ena_adapter *adapter)
1847 {
1848         struct ena_ring *tx_ring;
1849         uint64_t tx_cleanup_delay;
1850         size_t qid;
1851         int budget;
1852         uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1853
1854         if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1855                 return;
1856
1857         nb_tx_queues = adapter->edev_data->nb_tx_queues;
1858         budget = adapter->missing_tx_completion_budget;
1859
1860         qid = adapter->last_tx_comp_qid;
1861         while (budget-- > 0) {
1862                 tx_ring = &adapter->tx_ring[qid];
1863
1864                 /* Tx cleanup is called only by the burst function and can be
1865                  * called dynamically by the application. Also cleanup is
1866                  * limited by the threshold. To avoid false detection of the
1867                  * missing HW Tx completion, get the delay since last cleanup
1868                  * function was called.
1869                  */
1870                 tx_cleanup_delay = rte_get_timer_cycles() -
1871                         tx_ring->last_cleanup_ticks;
1872                 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1873                         check_for_tx_completion_in_queue(adapter, tx_ring);
1874                 qid = (qid + 1) % nb_tx_queues;
1875         }
1876
1877         adapter->last_tx_comp_qid = qid;
1878 }
1879
1880 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1881                                   void *arg)
1882 {
1883         struct rte_eth_dev *dev = arg;
1884         struct ena_adapter *adapter = dev->data->dev_private;
1885
1886         if (unlikely(adapter->trigger_reset))
1887                 return;
1888
1889         check_for_missing_keep_alive(adapter);
1890         check_for_admin_com_state(adapter);
1891         check_for_tx_completions(adapter);
1892
1893         if (unlikely(adapter->trigger_reset)) {
1894                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1895                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1896                         NULL);
1897         }
1898 }
1899
1900 static inline void
1901 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1902                                struct ena_admin_feature_llq_desc *llq,
1903                                bool use_large_llq_hdr)
1904 {
1905         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1906         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1907         llq_config->llq_num_decs_before_header =
1908                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1909
1910         if (use_large_llq_hdr &&
1911             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1912                 llq_config->llq_ring_entry_size =
1913                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1914                 llq_config->llq_ring_entry_size_value = 256;
1915         } else {
1916                 llq_config->llq_ring_entry_size =
1917                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1918                 llq_config->llq_ring_entry_size_value = 128;
1919         }
1920 }
1921
1922 static int
1923 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1924                                 struct ena_com_dev *ena_dev,
1925                                 struct ena_admin_feature_llq_desc *llq,
1926                                 struct ena_llq_configurations *llq_default_configurations)
1927 {
1928         int rc;
1929         u32 llq_feature_mask;
1930
1931         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1932         if (!(ena_dev->supported_features & llq_feature_mask)) {
1933                 PMD_DRV_LOG(INFO,
1934                         "LLQ is not supported. Fallback to host mode policy.\n");
1935                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1936                 return 0;
1937         }
1938
1939         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1940         if (unlikely(rc)) {
1941                 PMD_INIT_LOG(WARNING,
1942                         "Failed to config dev mode. Fallback to host mode policy.\n");
1943                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1944                 return 0;
1945         }
1946
1947         /* Nothing to config, exit */
1948         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1949                 return 0;
1950
1951         if (!adapter->dev_mem_base) {
1952                 PMD_DRV_LOG(ERR,
1953                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1954                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1955                 return 0;
1956         }
1957
1958         ena_dev->mem_bar = adapter->dev_mem_base;
1959
1960         return 0;
1961 }
1962
1963 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1964         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1965 {
1966         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1967
1968         /* Regular queues capabilities */
1969         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1970                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1971                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1972                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1973                                     max_queue_ext->max_rx_cq_num);
1974                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1975                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1976         } else {
1977                 struct ena_admin_queue_feature_desc *max_queues =
1978                         &get_feat_ctx->max_queues;
1979                 io_tx_sq_num = max_queues->max_sq_num;
1980                 io_tx_cq_num = max_queues->max_cq_num;
1981                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1982         }
1983
1984         /* In case of LLQ use the llq number in the get feature cmd */
1985         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1986                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1987
1988         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1989         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1990         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1991
1992         if (unlikely(max_num_io_queues == 0)) {
1993                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1994                 return -EFAULT;
1995         }
1996
1997         return max_num_io_queues;
1998 }
1999
2000 static void
2001 ena_set_offloads(struct ena_offloads *offloads,
2002                  struct ena_admin_feature_offload_desc *offload_desc)
2003 {
2004         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2005                 offloads->tx_offloads |= ENA_IPV4_TSO;
2006
2007         /* Tx IPv4 checksum offloads */
2008         if (offload_desc->tx &
2009             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
2010                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
2011         if (offload_desc->tx &
2012             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
2013                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
2014         if (offload_desc->tx &
2015             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2016                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
2017
2018         /* Tx IPv6 checksum offloads */
2019         if (offload_desc->tx &
2020             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
2021                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
2022         if (offload_desc->tx &
2023              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2024                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
2025
2026         /* Rx IPv4 checksum offloads */
2027         if (offload_desc->rx_supported &
2028             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
2029                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
2030         if (offload_desc->rx_supported &
2031             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2032                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
2033
2034         /* Rx IPv6 checksum offloads */
2035         if (offload_desc->rx_supported &
2036             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2037                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
2038
2039         if (offload_desc->rx_supported &
2040             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
2041                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
2042 }
2043
2044 static int ena_init_once(void)
2045 {
2046         static bool init_done;
2047
2048         if (init_done)
2049                 return 0;
2050
2051         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2052                 /* Init timer subsystem for the ENA timer service. */
2053                 rte_timer_subsystem_init();
2054                 /* Register handler for requests from secondary processes. */
2055                 rte_mp_action_register(ENA_MP_NAME, ena_mp_primary_handle);
2056         }
2057
2058         init_done = true;
2059         return 0;
2060 }
2061
2062 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
2063 {
2064         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
2065         struct rte_pci_device *pci_dev;
2066         struct rte_intr_handle *intr_handle;
2067         struct ena_adapter *adapter = eth_dev->data->dev_private;
2068         struct ena_com_dev *ena_dev = &adapter->ena_dev;
2069         struct ena_com_dev_get_features_ctx get_feat_ctx;
2070         struct ena_llq_configurations llq_config;
2071         const char *queue_type_str;
2072         uint32_t max_num_io_queues;
2073         int rc;
2074         static int adapters_found;
2075         bool disable_meta_caching;
2076
2077         eth_dev->dev_ops = &ena_dev_ops;
2078         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
2079         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
2080         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
2081
2082         rc = ena_init_once();
2083         if (rc != 0)
2084                 return rc;
2085
2086         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2087                 return 0;
2088
2089         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2090
2091         memset(adapter, 0, sizeof(struct ena_adapter));
2092         ena_dev = &adapter->ena_dev;
2093
2094         adapter->edev_data = eth_dev->data;
2095
2096         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2097
2098         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
2099                      pci_dev->addr.domain,
2100                      pci_dev->addr.bus,
2101                      pci_dev->addr.devid,
2102                      pci_dev->addr.function);
2103
2104         intr_handle = pci_dev->intr_handle;
2105
2106         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
2107         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
2108
2109         if (!adapter->regs) {
2110                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
2111                              ENA_REGS_BAR);
2112                 return -ENXIO;
2113         }
2114
2115         ena_dev->reg_bar = adapter->regs;
2116         /* This is a dummy pointer for ena_com functions. */
2117         ena_dev->dmadev = adapter;
2118
2119         adapter->id_number = adapters_found;
2120
2121         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
2122                  adapter->id_number);
2123
2124         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
2125         if (rc != 0) {
2126                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
2127                 goto err;
2128         }
2129
2130         /* device specific initialization routine */
2131         rc = ena_device_init(adapter, pci_dev, &get_feat_ctx);
2132         if (rc) {
2133                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
2134                 goto err;
2135         }
2136
2137         /* Check if device supports LSC */
2138         if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE)))
2139                 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
2140
2141         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
2142                 adapter->use_large_llq_hdr);
2143         rc = ena_set_queues_placement_policy(adapter, ena_dev,
2144                                              &get_feat_ctx.llq, &llq_config);
2145         if (unlikely(rc)) {
2146                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
2147                 return rc;
2148         }
2149
2150         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
2151                 queue_type_str = "Regular";
2152         else
2153                 queue_type_str = "Low latency";
2154         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
2155
2156         calc_queue_ctx.ena_dev = ena_dev;
2157         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
2158
2159         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
2160         rc = ena_calc_io_queue_size(&calc_queue_ctx,
2161                 adapter->use_large_llq_hdr);
2162         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
2163                 rc = -EFAULT;
2164                 goto err_device_destroy;
2165         }
2166
2167         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
2168         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
2169         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
2170         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
2171         adapter->max_num_io_queues = max_num_io_queues;
2172
2173         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2174                 disable_meta_caching =
2175                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
2176                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
2177         } else {
2178                 disable_meta_caching = false;
2179         }
2180
2181         /* prepare ring structures */
2182         ena_init_rings(adapter, disable_meta_caching);
2183
2184         ena_config_debug_area(adapter);
2185
2186         /* Set max MTU for this device */
2187         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
2188
2189         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
2190
2191         /* Copy MAC address and point DPDK to it */
2192         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
2193         rte_ether_addr_copy((struct rte_ether_addr *)
2194                         get_feat_ctx.dev_attr.mac_addr,
2195                         (struct rte_ether_addr *)adapter->mac_addr);
2196
2197         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2198         if (unlikely(rc != 0)) {
2199                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
2200                 goto err_delete_debug_area;
2201         }
2202
2203         adapter->drv_stats = rte_zmalloc("adapter stats",
2204                                          sizeof(*adapter->drv_stats),
2205                                          RTE_CACHE_LINE_SIZE);
2206         if (!adapter->drv_stats) {
2207                 PMD_DRV_LOG(ERR,
2208                         "Failed to allocate memory for adapter statistics\n");
2209                 rc = -ENOMEM;
2210                 goto err_rss_destroy;
2211         }
2212
2213         rte_spinlock_init(&adapter->admin_lock);
2214
2215         rte_intr_callback_register(intr_handle,
2216                                    ena_interrupt_handler_rte,
2217                                    eth_dev);
2218         rte_intr_enable(intr_handle);
2219         ena_com_set_admin_polling_mode(ena_dev, false);
2220         ena_com_admin_aenq_enable(ena_dev);
2221
2222         rte_timer_init(&adapter->timer_wd);
2223
2224         adapters_found++;
2225         adapter->state = ENA_ADAPTER_STATE_INIT;
2226
2227         return 0;
2228
2229 err_rss_destroy:
2230         ena_com_rss_destroy(ena_dev);
2231 err_delete_debug_area:
2232         ena_com_delete_debug_area(ena_dev);
2233
2234 err_device_destroy:
2235         ena_com_delete_host_info(ena_dev);
2236         ena_com_admin_destroy(ena_dev);
2237
2238 err:
2239         return rc;
2240 }
2241
2242 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
2243 {
2244         struct ena_adapter *adapter = eth_dev->data->dev_private;
2245         struct ena_com_dev *ena_dev = &adapter->ena_dev;
2246
2247         if (adapter->state == ENA_ADAPTER_STATE_FREE)
2248                 return;
2249
2250         ena_com_set_admin_running_state(ena_dev, false);
2251
2252         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
2253                 ena_close(eth_dev);
2254
2255         ena_com_rss_destroy(ena_dev);
2256
2257         ena_com_delete_debug_area(ena_dev);
2258         ena_com_delete_host_info(ena_dev);
2259
2260         ena_com_abort_admin_commands(ena_dev);
2261         ena_com_wait_for_abort_completion(ena_dev);
2262         ena_com_admin_destroy(ena_dev);
2263         ena_com_mmio_reg_read_request_destroy(ena_dev);
2264
2265         adapter->state = ENA_ADAPTER_STATE_FREE;
2266 }
2267
2268 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
2269 {
2270         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2271                 return 0;
2272
2273         ena_destroy_device(eth_dev);
2274
2275         return 0;
2276 }
2277
2278 static int ena_dev_configure(struct rte_eth_dev *dev)
2279 {
2280         struct ena_adapter *adapter = dev->data->dev_private;
2281         int rc;
2282
2283         adapter->state = ENA_ADAPTER_STATE_CONFIG;
2284
2285         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2286                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2287         dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2288
2289         /* Scattered Rx cannot be turned off in the HW, so this capability must
2290          * be forced.
2291          */
2292         dev->data->scattered_rx = 1;
2293
2294         adapter->last_tx_comp_qid = 0;
2295
2296         adapter->missing_tx_completion_budget =
2297                 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2298
2299         adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2300         /* To avoid detection of the spurious Tx completion timeout due to
2301          * application not calling the Tx cleanup function, set timeout for the
2302          * Tx queue which should be half of the missing completion timeout for a
2303          * safety. If there will be a lot of missing Tx completions in the
2304          * queue, they will be detected sooner or later.
2305          */
2306         adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2307
2308         rc = ena_configure_aenq(adapter);
2309
2310         return rc;
2311 }
2312
2313 static void ena_init_rings(struct ena_adapter *adapter,
2314                            bool disable_meta_caching)
2315 {
2316         size_t i;
2317
2318         for (i = 0; i < adapter->max_num_io_queues; i++) {
2319                 struct ena_ring *ring = &adapter->tx_ring[i];
2320
2321                 ring->configured = 0;
2322                 ring->type = ENA_RING_TYPE_TX;
2323                 ring->adapter = adapter;
2324                 ring->id = i;
2325                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2326                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2327                 ring->sgl_size = adapter->max_tx_sgl_size;
2328                 ring->disable_meta_caching = disable_meta_caching;
2329         }
2330
2331         for (i = 0; i < adapter->max_num_io_queues; i++) {
2332                 struct ena_ring *ring = &adapter->rx_ring[i];
2333
2334                 ring->configured = 0;
2335                 ring->type = ENA_RING_TYPE_RX;
2336                 ring->adapter = adapter;
2337                 ring->id = i;
2338                 ring->sgl_size = adapter->max_rx_sgl_size;
2339         }
2340 }
2341
2342 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2343 {
2344         uint64_t port_offloads = 0;
2345
2346         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2347                 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2348
2349         if (adapter->offloads.rx_offloads &
2350             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2351                 port_offloads |=
2352                         RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2353
2354         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2355                 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2356
2357         port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2358
2359         return port_offloads;
2360 }
2361
2362 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2363 {
2364         uint64_t port_offloads = 0;
2365
2366         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2367                 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2368
2369         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2370                 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2371         if (adapter->offloads.tx_offloads &
2372             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2373              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2374                 port_offloads |=
2375                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2376
2377         port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2378
2379         return port_offloads;
2380 }
2381
2382 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2383 {
2384         RTE_SET_USED(adapter);
2385
2386         return 0;
2387 }
2388
2389 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2390 {
2391         RTE_SET_USED(adapter);
2392
2393         return 0;
2394 }
2395
2396 static int ena_infos_get(struct rte_eth_dev *dev,
2397                           struct rte_eth_dev_info *dev_info)
2398 {
2399         struct ena_adapter *adapter;
2400         struct ena_com_dev *ena_dev;
2401
2402         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2403         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2404         adapter = dev->data->dev_private;
2405
2406         ena_dev = &adapter->ena_dev;
2407         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2408
2409         dev_info->speed_capa =
2410                         RTE_ETH_LINK_SPEED_1G   |
2411                         RTE_ETH_LINK_SPEED_2_5G |
2412                         RTE_ETH_LINK_SPEED_5G   |
2413                         RTE_ETH_LINK_SPEED_10G  |
2414                         RTE_ETH_LINK_SPEED_25G  |
2415                         RTE_ETH_LINK_SPEED_40G  |
2416                         RTE_ETH_LINK_SPEED_50G  |
2417                         RTE_ETH_LINK_SPEED_100G;
2418
2419         /* Inform framework about available features */
2420         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2421         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2422         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2423         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2424
2425         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2426         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2427
2428         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2429         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2430                 RTE_ETHER_CRC_LEN;
2431         dev_info->min_mtu = ENA_MIN_MTU;
2432         dev_info->max_mtu = adapter->max_mtu;
2433         dev_info->max_mac_addrs = 1;
2434
2435         dev_info->max_rx_queues = adapter->max_num_io_queues;
2436         dev_info->max_tx_queues = adapter->max_num_io_queues;
2437         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2438
2439         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2440         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2441         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2442                                         adapter->max_rx_sgl_size);
2443         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2444                                         adapter->max_rx_sgl_size);
2445
2446         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2447         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2448         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2449                                         adapter->max_tx_sgl_size);
2450         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2451                                         adapter->max_tx_sgl_size);
2452
2453         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2454         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2455
2456         return 0;
2457 }
2458
2459 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2460 {
2461         mbuf->data_len = len;
2462         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2463         mbuf->refcnt = 1;
2464         mbuf->next = NULL;
2465 }
2466
2467 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2468                                     struct ena_com_rx_buf_info *ena_bufs,
2469                                     uint32_t descs,
2470                                     uint16_t *next_to_clean,
2471                                     uint8_t offset)
2472 {
2473         struct rte_mbuf *mbuf;
2474         struct rte_mbuf *mbuf_head;
2475         struct ena_rx_buffer *rx_info;
2476         int rc;
2477         uint16_t ntc, len, req_id, buf = 0;
2478
2479         if (unlikely(descs == 0))
2480                 return NULL;
2481
2482         ntc = *next_to_clean;
2483
2484         len = ena_bufs[buf].len;
2485         req_id = ena_bufs[buf].req_id;
2486
2487         rx_info = &rx_ring->rx_buffer_info[req_id];
2488
2489         mbuf = rx_info->mbuf;
2490         RTE_ASSERT(mbuf != NULL);
2491
2492         ena_init_rx_mbuf(mbuf, len);
2493
2494         /* Fill the mbuf head with the data specific for 1st segment. */
2495         mbuf_head = mbuf;
2496         mbuf_head->nb_segs = descs;
2497         mbuf_head->port = rx_ring->port_id;
2498         mbuf_head->pkt_len = len;
2499         mbuf_head->data_off += offset;
2500
2501         rx_info->mbuf = NULL;
2502         rx_ring->empty_rx_reqs[ntc] = req_id;
2503         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2504
2505         while (--descs) {
2506                 ++buf;
2507                 len = ena_bufs[buf].len;
2508                 req_id = ena_bufs[buf].req_id;
2509
2510                 rx_info = &rx_ring->rx_buffer_info[req_id];
2511                 RTE_ASSERT(rx_info->mbuf != NULL);
2512
2513                 if (unlikely(len == 0)) {
2514                         /*
2515                          * Some devices can pass descriptor with the length 0.
2516                          * To avoid confusion, the PMD is simply putting the
2517                          * descriptor back, as it was never used. We'll avoid
2518                          * mbuf allocation that way.
2519                          */
2520                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2521                                 rx_info->mbuf, req_id);
2522                         if (unlikely(rc != 0)) {
2523                                 /* Free the mbuf in case of an error. */
2524                                 rte_mbuf_raw_free(rx_info->mbuf);
2525                         } else {
2526                                 /*
2527                                  * If there was no error, just exit the loop as
2528                                  * 0 length descriptor is always the last one.
2529                                  */
2530                                 break;
2531                         }
2532                 } else {
2533                         /* Create an mbuf chain. */
2534                         mbuf->next = rx_info->mbuf;
2535                         mbuf = mbuf->next;
2536
2537                         ena_init_rx_mbuf(mbuf, len);
2538                         mbuf_head->pkt_len += len;
2539                 }
2540
2541                 /*
2542                  * Mark the descriptor as depleted and perform necessary
2543                  * cleanup.
2544                  * This code will execute in two cases:
2545                  *  1. Descriptor len was greater than 0 - normal situation.
2546                  *  2. Descriptor len was 0 and we failed to add the descriptor
2547                  *     to the device. In that situation, we should try to add
2548                  *     the mbuf again in the populate routine and mark the
2549                  *     descriptor as used up by the device.
2550                  */
2551                 rx_info->mbuf = NULL;
2552                 rx_ring->empty_rx_reqs[ntc] = req_id;
2553                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2554         }
2555
2556         *next_to_clean = ntc;
2557
2558         return mbuf_head;
2559 }
2560
2561 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2562                                   uint16_t nb_pkts)
2563 {
2564         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2565         unsigned int free_queue_entries;
2566         uint16_t next_to_clean = rx_ring->next_to_clean;
2567         uint16_t descs_in_use;
2568         struct rte_mbuf *mbuf;
2569         uint16_t completed;
2570         struct ena_com_rx_ctx ena_rx_ctx;
2571         int i, rc = 0;
2572         bool fill_hash;
2573
2574 #ifdef RTE_ETHDEV_DEBUG_RX
2575         /* Check adapter state */
2576         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2577                 PMD_RX_LOG(ALERT,
2578                         "Trying to receive pkts while device is NOT running\n");
2579                 return 0;
2580         }
2581 #endif
2582
2583         fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2584
2585         descs_in_use = rx_ring->ring_size -
2586                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2587         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2588
2589         for (completed = 0; completed < nb_pkts; completed++) {
2590                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2591                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2592                 ena_rx_ctx.descs = 0;
2593                 ena_rx_ctx.pkt_offset = 0;
2594                 /* receive packet context */
2595                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2596                                     rx_ring->ena_com_io_sq,
2597                                     &ena_rx_ctx);
2598                 if (unlikely(rc)) {
2599                         PMD_RX_LOG(ERR,
2600                                 "Failed to get the packet from the device, rc: %d\n",
2601                                 rc);
2602                         if (rc == ENA_COM_NO_SPACE) {
2603                                 ++rx_ring->rx_stats.bad_desc_num;
2604                                 rx_ring->adapter->reset_reason =
2605                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2606                         } else {
2607                                 ++rx_ring->rx_stats.bad_req_id;
2608                                 rx_ring->adapter->reset_reason =
2609                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2610                         }
2611                         rx_ring->adapter->trigger_reset = true;
2612                         return 0;
2613                 }
2614
2615                 mbuf = ena_rx_mbuf(rx_ring,
2616                         ena_rx_ctx.ena_bufs,
2617                         ena_rx_ctx.descs,
2618                         &next_to_clean,
2619                         ena_rx_ctx.pkt_offset);
2620                 if (unlikely(mbuf == NULL)) {
2621                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2622                                 rx_ring->empty_rx_reqs[next_to_clean] =
2623                                         rx_ring->ena_bufs[i].req_id;
2624                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2625                                         next_to_clean, rx_ring->size_mask);
2626                         }
2627                         break;
2628                 }
2629
2630                 /* fill mbuf attributes if any */
2631                 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash);
2632
2633                 if (unlikely(mbuf->ol_flags &
2634                                 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD)))
2635                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2636
2637                 rx_pkts[completed] = mbuf;
2638                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2639         }
2640
2641         rx_ring->rx_stats.cnt += completed;
2642         rx_ring->next_to_clean = next_to_clean;
2643
2644         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2645
2646         /* Burst refill to save doorbells, memory barriers, const interval */
2647         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2648                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2649                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2650         }
2651
2652         return completed;
2653 }
2654
2655 static uint16_t
2656 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2657                 uint16_t nb_pkts)
2658 {
2659         int32_t ret;
2660         uint32_t i;
2661         struct rte_mbuf *m;
2662         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2663         struct ena_adapter *adapter = tx_ring->adapter;
2664         struct rte_ipv4_hdr *ip_hdr;
2665         uint64_t ol_flags;
2666         uint64_t l4_csum_flag;
2667         uint64_t dev_offload_capa;
2668         uint16_t frag_field;
2669         bool need_pseudo_csum;
2670
2671         dev_offload_capa = adapter->offloads.tx_offloads;
2672         for (i = 0; i != nb_pkts; i++) {
2673                 m = tx_pkts[i];
2674                 ol_flags = m->ol_flags;
2675
2676                 /* Check if any offload flag was set */
2677                 if (ol_flags == 0)
2678                         continue;
2679
2680                 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2681                 /* SCTP checksum offload is not supported by the ENA. */
2682                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2683                     l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2684                         PMD_TX_LOG(DEBUG,
2685                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2686                                 i, ol_flags);
2687                         rte_errno = ENOTSUP;
2688                         return i;
2689                 }
2690
2691                 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2692                     !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2693                       m->nb_segs == tx_ring->sgl_size &&
2694                       m->data_len < tx_ring->tx_max_header_size))) {
2695                         PMD_TX_LOG(DEBUG,
2696                                 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2697                                 i, m->nb_segs);
2698                         rte_errno = EINVAL;
2699                         return i;
2700                 }
2701
2702 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2703                 /* Check if requested offload is also enabled for the queue */
2704                 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2705                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2706                     (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2707                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2708                     (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2709                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2710                         PMD_TX_LOG(DEBUG,
2711                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2712                                 i, m->nb_segs, tx_ring->id);
2713                         rte_errno = EINVAL;
2714                         return i;
2715                 }
2716
2717                 /* The caller is obligated to set l2 and l3 len if any cksum
2718                  * offload is enabled.
2719                  */
2720                 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2721                     (m->l2_len == 0 || m->l3_len == 0))) {
2722                         PMD_TX_LOG(DEBUG,
2723                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2724                                 i);
2725                         rte_errno = EINVAL;
2726                         return i;
2727                 }
2728                 ret = rte_validate_tx_offload(m);
2729                 if (ret != 0) {
2730                         rte_errno = -ret;
2731                         return i;
2732                 }
2733 #endif
2734
2735                 /* Verify HW support for requested offloads and determine if
2736                  * pseudo header checksum is needed.
2737                  */
2738                 need_pseudo_csum = false;
2739                 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2740                         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2741                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2742                                 rte_errno = ENOTSUP;
2743                                 return i;
2744                         }
2745
2746                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2747                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2748                                 rte_errno = ENOTSUP;
2749                                 return i;
2750                         }
2751
2752                         /* Check HW capabilities and if pseudo csum is needed
2753                          * for L4 offloads.
2754                          */
2755                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2756                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2757                                 if (dev_offload_capa &
2758                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2759                                         need_pseudo_csum = true;
2760                                 } else {
2761                                         rte_errno = ENOTSUP;
2762                                         return i;
2763                                 }
2764                         }
2765
2766                         /* Parse the DF flag */
2767                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2768                                 struct rte_ipv4_hdr *, m->l2_len);
2769                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2770                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2771                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2772                         } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2773                                 /* In case we are supposed to TSO and have DF
2774                                  * not set (DF=0) hardware must be provided with
2775                                  * partial checksum.
2776                                  */
2777                                 need_pseudo_csum = true;
2778                         }
2779                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2780                         /* There is no support for IPv6 TSO as for now. */
2781                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2782                                 rte_errno = ENOTSUP;
2783                                 return i;
2784                         }
2785
2786                         /* Check HW capabilities and if pseudo csum is needed */
2787                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2788                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2789                                 if (dev_offload_capa &
2790                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2791                                         need_pseudo_csum = true;
2792                                 } else {
2793                                         rte_errno = ENOTSUP;
2794                                         return i;
2795                                 }
2796                         }
2797                 }
2798
2799                 if (need_pseudo_csum) {
2800                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2801                         if (ret != 0) {
2802                                 rte_errno = -ret;
2803                                 return i;
2804                         }
2805                 }
2806         }
2807
2808         return i;
2809 }
2810
2811 static void ena_update_hints(struct ena_adapter *adapter,
2812                              struct ena_admin_ena_hw_hints *hints)
2813 {
2814         if (hints->admin_completion_tx_timeout)
2815                 adapter->ena_dev.admin_queue.completion_timeout =
2816                         hints->admin_completion_tx_timeout * 1000;
2817
2818         if (hints->mmio_read_timeout)
2819                 /* convert to usec */
2820                 adapter->ena_dev.mmio_read.reg_read_to =
2821                         hints->mmio_read_timeout * 1000;
2822
2823         if (hints->missing_tx_completion_timeout) {
2824                 if (hints->missing_tx_completion_timeout ==
2825                     ENA_HW_HINTS_NO_TIMEOUT) {
2826                         adapter->missing_tx_completion_to =
2827                                 ENA_HW_HINTS_NO_TIMEOUT;
2828                 } else {
2829                         /* Convert from msecs to ticks */
2830                         adapter->missing_tx_completion_to = rte_get_timer_hz() *
2831                                 hints->missing_tx_completion_timeout / 1000;
2832                         adapter->tx_cleanup_stall_delay =
2833                                 adapter->missing_tx_completion_to / 2;
2834                 }
2835         }
2836
2837         if (hints->driver_watchdog_timeout) {
2838                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2839                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2840                 else
2841                         // Convert msecs to ticks
2842                         adapter->keep_alive_timeout =
2843                                 (hints->driver_watchdog_timeout *
2844                                 rte_get_timer_hz()) / 1000;
2845         }
2846 }
2847
2848 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2849         struct ena_tx_buffer *tx_info,
2850         struct rte_mbuf *mbuf,
2851         void **push_header,
2852         uint16_t *header_len)
2853 {
2854         struct ena_com_buf *ena_buf;
2855         uint16_t delta, seg_len, push_len;
2856
2857         delta = 0;
2858         seg_len = mbuf->data_len;
2859
2860         tx_info->mbuf = mbuf;
2861         ena_buf = tx_info->bufs;
2862
2863         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2864                 /*
2865                  * Tx header might be (and will be in most cases) smaller than
2866                  * tx_max_header_size. But it's not an issue to send more data
2867                  * to the device, than actually needed if the mbuf size is
2868                  * greater than tx_max_header_size.
2869                  */
2870                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2871                 *header_len = push_len;
2872
2873                 if (likely(push_len <= seg_len)) {
2874                         /* If the push header is in the single segment, then
2875                          * just point it to the 1st mbuf data.
2876                          */
2877                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2878                 } else {
2879                         /* If the push header lays in the several segments, copy
2880                          * it to the intermediate buffer.
2881                          */
2882                         rte_pktmbuf_read(mbuf, 0, push_len,
2883                                 tx_ring->push_buf_intermediate_buf);
2884                         *push_header = tx_ring->push_buf_intermediate_buf;
2885                         delta = push_len - seg_len;
2886                 }
2887         } else {
2888                 *push_header = NULL;
2889                 *header_len = 0;
2890                 push_len = 0;
2891         }
2892
2893         /* Process first segment taking into consideration pushed header */
2894         if (seg_len > push_len) {
2895                 ena_buf->paddr = mbuf->buf_iova +
2896                                 mbuf->data_off +
2897                                 push_len;
2898                 ena_buf->len = seg_len - push_len;
2899                 ena_buf++;
2900                 tx_info->num_of_bufs++;
2901         }
2902
2903         while ((mbuf = mbuf->next) != NULL) {
2904                 seg_len = mbuf->data_len;
2905
2906                 /* Skip mbufs if whole data is pushed as a header */
2907                 if (unlikely(delta > seg_len)) {
2908                         delta -= seg_len;
2909                         continue;
2910                 }
2911
2912                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2913                 ena_buf->len = seg_len - delta;
2914                 ena_buf++;
2915                 tx_info->num_of_bufs++;
2916
2917                 delta = 0;
2918         }
2919 }
2920
2921 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2922 {
2923         struct ena_tx_buffer *tx_info;
2924         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2925         uint16_t next_to_use;
2926         uint16_t header_len;
2927         uint16_t req_id;
2928         void *push_header;
2929         int nb_hw_desc;
2930         int rc;
2931
2932         /* Checking for space for 2 additional metadata descriptors due to
2933          * possible header split and metadata descriptor
2934          */
2935         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2936                                           mbuf->nb_segs + 2)) {
2937                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2938                 return ENA_COM_NO_MEM;
2939         }
2940
2941         next_to_use = tx_ring->next_to_use;
2942
2943         req_id = tx_ring->empty_tx_reqs[next_to_use];
2944         tx_info = &tx_ring->tx_buffer_info[req_id];
2945         tx_info->num_of_bufs = 0;
2946         RTE_ASSERT(tx_info->mbuf == NULL);
2947
2948         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2949
2950         ena_tx_ctx.ena_bufs = tx_info->bufs;
2951         ena_tx_ctx.push_header = push_header;
2952         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2953         ena_tx_ctx.req_id = req_id;
2954         ena_tx_ctx.header_len = header_len;
2955
2956         /* Set Tx offloads flags, if applicable */
2957         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2958                 tx_ring->disable_meta_caching);
2959
2960         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2961                         &ena_tx_ctx))) {
2962                 PMD_TX_LOG(DEBUG,
2963                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2964                         tx_ring->id);
2965                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2966                 tx_ring->tx_stats.doorbells++;
2967                 tx_ring->pkts_without_db = false;
2968         }
2969
2970         /* prepare the packet's descriptors to dma engine */
2971         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2972                 &nb_hw_desc);
2973         if (unlikely(rc)) {
2974                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2975                 ++tx_ring->tx_stats.prepare_ctx_err;
2976                 tx_ring->adapter->reset_reason =
2977                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2978                 tx_ring->adapter->trigger_reset = true;
2979                 return rc;
2980         }
2981
2982         tx_info->tx_descs = nb_hw_desc;
2983         tx_info->timestamp = rte_get_timer_cycles();
2984
2985         tx_ring->tx_stats.cnt++;
2986         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2987
2988         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2989                 tx_ring->size_mask);
2990
2991         return 0;
2992 }
2993
2994 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2995 {
2996         unsigned int total_tx_descs = 0;
2997         uint16_t cleanup_budget;
2998         uint16_t next_to_clean = tx_ring->next_to_clean;
2999
3000         /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
3001         cleanup_budget = tx_ring->size_mask;
3002
3003         while (likely(total_tx_descs < cleanup_budget)) {
3004                 struct rte_mbuf *mbuf;
3005                 struct ena_tx_buffer *tx_info;
3006                 uint16_t req_id;
3007
3008                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
3009                         break;
3010
3011                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
3012                         break;
3013
3014                 /* Get Tx info & store how many descs were processed  */
3015                 tx_info = &tx_ring->tx_buffer_info[req_id];
3016                 tx_info->timestamp = 0;
3017
3018                 mbuf = tx_info->mbuf;
3019                 rte_pktmbuf_free(mbuf);
3020
3021                 tx_info->mbuf = NULL;
3022                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
3023
3024                 total_tx_descs += tx_info->tx_descs;
3025
3026                 /* Put back descriptor to the ring for reuse */
3027                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
3028                         tx_ring->size_mask);
3029         }
3030
3031         if (likely(total_tx_descs > 0)) {
3032                 /* acknowledge completion of sent packets */
3033                 tx_ring->next_to_clean = next_to_clean;
3034                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
3035                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
3036         }
3037
3038         /* Notify completion handler that the cleanup was just called */
3039         tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
3040 }
3041
3042 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
3043                                   uint16_t nb_pkts)
3044 {
3045         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
3046         int available_desc;
3047         uint16_t sent_idx = 0;
3048
3049 #ifdef RTE_ETHDEV_DEBUG_TX
3050         /* Check adapter state */
3051         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
3052                 PMD_TX_LOG(ALERT,
3053                         "Trying to xmit pkts while device is NOT running\n");
3054                 return 0;
3055         }
3056 #endif
3057
3058         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3059         if (available_desc < tx_ring->tx_free_thresh)
3060                 ena_tx_cleanup(tx_ring);
3061
3062         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
3063                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
3064                         break;
3065                 tx_ring->pkts_without_db = true;
3066                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
3067                         tx_ring->size_mask)]);
3068         }
3069
3070         /* If there are ready packets to be xmitted... */
3071         if (likely(tx_ring->pkts_without_db)) {
3072                 /* ...let HW do its best :-) */
3073                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
3074                 tx_ring->tx_stats.doorbells++;
3075                 tx_ring->pkts_without_db = false;
3076         }
3077
3078         tx_ring->tx_stats.available_desc =
3079                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
3080         tx_ring->tx_stats.tx_poll++;
3081
3082         return sent_idx;
3083 }
3084
3085 int ena_copy_eni_stats(struct ena_adapter *adapter, struct ena_stats_eni *stats)
3086 {
3087         int rc;
3088
3089         rte_spinlock_lock(&adapter->admin_lock);
3090         /* Retrieve and store the latest statistics from the AQ. This ensures
3091          * that previous value is returned in case of a com error.
3092          */
3093         rc = ENA_PROXY(adapter, ena_com_get_eni_stats, &adapter->ena_dev,
3094                 (struct ena_admin_eni_stats *)stats);
3095         rte_spinlock_unlock(&adapter->admin_lock);
3096         if (rc != 0) {
3097                 if (rc == ENA_COM_UNSUPPORTED) {
3098                         PMD_DRV_LOG(DEBUG,
3099                                 "Retrieving ENI metrics is not supported\n");
3100                 } else {
3101                         PMD_DRV_LOG(WARNING,
3102                                 "Failed to get ENI metrics, rc: %d\n", rc);
3103                 }
3104                 return rc;
3105         }
3106
3107         return 0;
3108 }
3109
3110 /**
3111  * DPDK callback to retrieve names of extended device statistics
3112  *
3113  * @param dev
3114  *   Pointer to Ethernet device structure.
3115  * @param[out] xstats_names
3116  *   Buffer to insert names into.
3117  * @param n
3118  *   Number of names.
3119  *
3120  * @return
3121  *   Number of xstats names.
3122  */
3123 static int ena_xstats_get_names(struct rte_eth_dev *dev,
3124                                 struct rte_eth_xstat_name *xstats_names,
3125                                 unsigned int n)
3126 {
3127         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3128         unsigned int stat, i, count = 0;
3129
3130         if (n < xstats_count || !xstats_names)
3131                 return xstats_count;
3132
3133         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
3134                 strcpy(xstats_names[count].name,
3135                         ena_stats_global_strings[stat].name);
3136
3137         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
3138                 strcpy(xstats_names[count].name,
3139                         ena_stats_eni_strings[stat].name);
3140
3141         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
3142                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
3143                         snprintf(xstats_names[count].name,
3144                                 sizeof(xstats_names[count].name),
3145                                 "rx_q%d_%s", i,
3146                                 ena_stats_rx_strings[stat].name);
3147
3148         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
3149                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
3150                         snprintf(xstats_names[count].name,
3151                                 sizeof(xstats_names[count].name),
3152                                 "tx_q%d_%s", i,
3153                                 ena_stats_tx_strings[stat].name);
3154
3155         return xstats_count;
3156 }
3157
3158 /**
3159  * DPDK callback to get extended device statistics.
3160  *
3161  * @param dev
3162  *   Pointer to Ethernet device structure.
3163  * @param[out] stats
3164  *   Stats table output buffer.
3165  * @param n
3166  *   The size of the stats table.
3167  *
3168  * @return
3169  *   Number of xstats on success, negative on failure.
3170  */
3171 static int ena_xstats_get(struct rte_eth_dev *dev,
3172                           struct rte_eth_xstat *xstats,
3173                           unsigned int n)
3174 {
3175         struct ena_adapter *adapter = dev->data->dev_private;
3176         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
3177         struct ena_stats_eni eni_stats;
3178         unsigned int stat, i, count = 0;
3179         int stat_offset;
3180         void *stats_begin;
3181
3182         if (n < xstats_count)
3183                 return xstats_count;
3184
3185         if (!xstats)
3186                 return 0;
3187
3188         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
3189                 stat_offset = ena_stats_global_strings[stat].stat_offset;
3190                 stats_begin = &adapter->dev_stats;
3191
3192                 xstats[count].id = count;
3193                 xstats[count].value = *((uint64_t *)
3194                         ((char *)stats_begin + stat_offset));
3195         }
3196
3197         /* Even if the function below fails, we should copy previous (or initial
3198          * values) to keep structure of rte_eth_xstat consistent.
3199          */
3200         ena_copy_eni_stats(adapter, &eni_stats);
3201         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
3202                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
3203                 stats_begin = &eni_stats;
3204
3205                 xstats[count].id = count;
3206                 xstats[count].value = *((uint64_t *)
3207                     ((char *)stats_begin + stat_offset));
3208         }
3209
3210         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
3211                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
3212                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
3213                         stats_begin = &adapter->rx_ring[i].rx_stats;
3214
3215                         xstats[count].id = count;
3216                         xstats[count].value = *((uint64_t *)
3217                                 ((char *)stats_begin + stat_offset));
3218                 }
3219         }
3220
3221         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
3222                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
3223                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
3224                         stats_begin = &adapter->tx_ring[i].rx_stats;
3225
3226                         xstats[count].id = count;
3227                         xstats[count].value = *((uint64_t *)
3228                                 ((char *)stats_begin + stat_offset));
3229                 }
3230         }
3231
3232         return count;
3233 }
3234
3235 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
3236                                 const uint64_t *ids,
3237                                 uint64_t *values,
3238                                 unsigned int n)
3239 {
3240         struct ena_adapter *adapter = dev->data->dev_private;
3241         struct ena_stats_eni eni_stats;
3242         uint64_t id;
3243         uint64_t rx_entries, tx_entries;
3244         unsigned int i;
3245         int qid;
3246         int valid = 0;
3247         bool was_eni_copied = false;
3248
3249         for (i = 0; i < n; ++i) {
3250                 id = ids[i];
3251                 /* Check if id belongs to global statistics */
3252                 if (id < ENA_STATS_ARRAY_GLOBAL) {
3253                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
3254                         ++valid;
3255                         continue;
3256                 }
3257
3258                 /* Check if id belongs to ENI statistics */
3259                 id -= ENA_STATS_ARRAY_GLOBAL;
3260                 if (id < ENA_STATS_ARRAY_ENI) {
3261                         /* Avoid reading ENI stats multiple times in a single
3262                          * function call, as it requires communication with the
3263                          * admin queue.
3264                          */
3265                         if (!was_eni_copied) {
3266                                 was_eni_copied = true;
3267                                 ena_copy_eni_stats(adapter, &eni_stats);
3268                         }
3269                         values[i] = *((uint64_t *)&eni_stats + id);
3270                         ++valid;
3271                         continue;
3272                 }
3273
3274                 /* Check if id belongs to rx queue statistics */
3275                 id -= ENA_STATS_ARRAY_ENI;
3276                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
3277                 if (id < rx_entries) {
3278                         qid = id % dev->data->nb_rx_queues;
3279                         id /= dev->data->nb_rx_queues;
3280                         values[i] = *((uint64_t *)
3281                                 &adapter->rx_ring[qid].rx_stats + id);
3282                         ++valid;
3283                         continue;
3284                 }
3285                                 /* Check if id belongs to rx queue statistics */
3286                 id -= rx_entries;
3287                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3288                 if (id < tx_entries) {
3289                         qid = id % dev->data->nb_tx_queues;
3290                         id /= dev->data->nb_tx_queues;
3291                         values[i] = *((uint64_t *)
3292                                 &adapter->tx_ring[qid].tx_stats + id);
3293                         ++valid;
3294                         continue;
3295                 }
3296         }
3297
3298         return valid;
3299 }
3300
3301 static int ena_process_bool_devarg(const char *key,
3302                                    const char *value,
3303                                    void *opaque)
3304 {
3305         struct ena_adapter *adapter = opaque;
3306         bool bool_value;
3307
3308         /* Parse the value. */
3309         if (strcmp(value, "1") == 0) {
3310                 bool_value = true;
3311         } else if (strcmp(value, "0") == 0) {
3312                 bool_value = false;
3313         } else {
3314                 PMD_INIT_LOG(ERR,
3315                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3316                         value, key);
3317                 return -EINVAL;
3318         }
3319
3320         /* Now, assign it to the proper adapter field. */
3321         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3322                 adapter->use_large_llq_hdr = bool_value;
3323
3324         return 0;
3325 }
3326
3327 static int ena_parse_devargs(struct ena_adapter *adapter,
3328                              struct rte_devargs *devargs)
3329 {
3330         static const char * const allowed_args[] = {
3331                 ENA_DEVARG_LARGE_LLQ_HDR,
3332                 NULL,
3333         };
3334         struct rte_kvargs *kvlist;
3335         int rc;
3336
3337         if (devargs == NULL)
3338                 return 0;
3339
3340         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3341         if (kvlist == NULL) {
3342                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3343                         devargs->args);
3344                 return -EINVAL;
3345         }
3346
3347         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3348                 ena_process_bool_devarg, adapter);
3349
3350         rte_kvargs_free(kvlist);
3351
3352         return rc;
3353 }
3354
3355 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3356 {
3357         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3358         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3359         int rc;
3360         uint16_t vectors_nb, i;
3361         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3362
3363         if (!rx_intr_requested)
3364                 return 0;
3365
3366         if (!rte_intr_cap_multiple(intr_handle)) {
3367                 PMD_DRV_LOG(ERR,
3368                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3369                 return -ENOTSUP;
3370         }
3371
3372         /* Disable interrupt mapping before the configuration starts. */
3373         rte_intr_disable(intr_handle);
3374
3375         /* Verify if there are enough vectors available. */
3376         vectors_nb = dev->data->nb_rx_queues;
3377         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3378                 PMD_DRV_LOG(ERR,
3379                         "Too many Rx interrupts requested, maximum number: %d\n",
3380                         RTE_MAX_RXTX_INTR_VEC_ID);
3381                 rc = -ENOTSUP;
3382                 goto enable_intr;
3383         }
3384
3385         /* Allocate the vector list */
3386         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3387                                            dev->data->nb_rx_queues)) {
3388                 PMD_DRV_LOG(ERR,
3389                         "Failed to allocate interrupt vector for %d queues\n",
3390                         dev->data->nb_rx_queues);
3391                 rc = -ENOMEM;
3392                 goto enable_intr;
3393         }
3394
3395         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3396         if (rc != 0)
3397                 goto free_intr_vec;
3398
3399         if (!rte_intr_allow_others(intr_handle)) {
3400                 PMD_DRV_LOG(ERR,
3401                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3402                 goto disable_intr_efd;
3403         }
3404
3405         for (i = 0; i < vectors_nb; ++i)
3406                 if (rte_intr_vec_list_index_set(intr_handle, i,
3407                                            RTE_INTR_VEC_RXTX_OFFSET + i))
3408                         goto disable_intr_efd;
3409
3410         rte_intr_enable(intr_handle);
3411         return 0;
3412
3413 disable_intr_efd:
3414         rte_intr_efd_disable(intr_handle);
3415 free_intr_vec:
3416         rte_intr_vec_list_free(intr_handle);
3417 enable_intr:
3418         rte_intr_enable(intr_handle);
3419         return rc;
3420 }
3421
3422 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3423                                  uint16_t queue_id,
3424                                  bool unmask)
3425 {
3426         struct ena_adapter *adapter = dev->data->dev_private;
3427         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3428         struct ena_eth_io_intr_reg intr_reg;
3429
3430         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3431         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3432 }
3433
3434 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3435                                     uint16_t queue_id)
3436 {
3437         ena_rx_queue_intr_set(dev, queue_id, true);
3438
3439         return 0;
3440 }
3441
3442 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3443                                      uint16_t queue_id)
3444 {
3445         ena_rx_queue_intr_set(dev, queue_id, false);
3446
3447         return 0;
3448 }
3449
3450 static int ena_configure_aenq(struct ena_adapter *adapter)
3451 {
3452         uint32_t aenq_groups = adapter->all_aenq_groups;
3453         int rc;
3454
3455         /* All_aenq_groups holds all AENQ functions supported by the device and
3456          * the HW, so at first we need to be sure the LSC request is valid.
3457          */
3458         if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) {
3459                 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) {
3460                         PMD_DRV_LOG(ERR,
3461                                 "LSC requested, but it's not supported by the AENQ\n");
3462                         return -EINVAL;
3463                 }
3464         } else {
3465                 /* If LSC wasn't enabled by the app, let's enable all supported
3466                  * AENQ procedures except the LSC.
3467                  */
3468                 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE);
3469         }
3470
3471         rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups);
3472         if (rc != 0) {
3473                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc);
3474                 return rc;
3475         }
3476
3477         adapter->active_aenq_groups = aenq_groups;
3478
3479         return 0;
3480 }
3481
3482 int ena_mp_indirect_table_set(struct ena_adapter *adapter)
3483 {
3484         return ENA_PROXY(adapter, ena_com_indirect_table_set, &adapter->ena_dev);
3485 }
3486
3487 int ena_mp_indirect_table_get(struct ena_adapter *adapter,
3488                               uint32_t *indirect_table)
3489 {
3490         return ENA_PROXY(adapter, ena_com_indirect_table_get, &adapter->ena_dev,
3491                 indirect_table);
3492 }
3493
3494 /*********************************************************************
3495  *  PMD configuration
3496  *********************************************************************/
3497 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3498         struct rte_pci_device *pci_dev)
3499 {
3500         return rte_eth_dev_pci_generic_probe(pci_dev,
3501                 sizeof(struct ena_adapter), eth_ena_dev_init);
3502 }
3503
3504 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3505 {
3506         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3507 }
3508
3509 static struct rte_pci_driver rte_ena_pmd = {
3510         .id_table = pci_id_ena_map,
3511         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3512                      RTE_PCI_DRV_WC_ACTIVATE,
3513         .probe = eth_ena_pci_probe,
3514         .remove = eth_ena_pci_remove,
3515 };
3516
3517 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3518 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3519 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3520 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3521 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3522 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3523 #ifdef RTE_ETHDEV_DEBUG_RX
3524 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3525 #endif
3526 #ifdef RTE_ETHDEV_DEBUG_TX
3527 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3528 #endif
3529 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3530
3531 /******************************************************************************
3532  ******************************** AENQ Handlers *******************************
3533  *****************************************************************************/
3534 static void ena_update_on_link_change(void *adapter_data,
3535                                       struct ena_admin_aenq_entry *aenq_e)
3536 {
3537         struct rte_eth_dev *eth_dev = adapter_data;
3538         struct ena_adapter *adapter = eth_dev->data->dev_private;
3539         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3540         uint32_t status;
3541
3542         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3543
3544         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3545         adapter->link_status = status;
3546
3547         ena_link_update(eth_dev, 0);
3548         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3549 }
3550
3551 static void ena_notification(void *adapter_data,
3552                              struct ena_admin_aenq_entry *aenq_e)
3553 {
3554         struct rte_eth_dev *eth_dev = adapter_data;
3555         struct ena_adapter *adapter = eth_dev->data->dev_private;
3556         struct ena_admin_ena_hw_hints *hints;
3557
3558         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3559                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3560                         aenq_e->aenq_common_desc.group,
3561                         ENA_ADMIN_NOTIFICATION);
3562
3563         switch (aenq_e->aenq_common_desc.syndrome) {
3564         case ENA_ADMIN_UPDATE_HINTS:
3565                 hints = (struct ena_admin_ena_hw_hints *)
3566                         (&aenq_e->inline_data_w4);
3567                 ena_update_hints(adapter, hints);
3568                 break;
3569         default:
3570                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3571                         aenq_e->aenq_common_desc.syndrome);
3572         }
3573 }
3574
3575 static void ena_keep_alive(void *adapter_data,
3576                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3577 {
3578         struct rte_eth_dev *eth_dev = adapter_data;
3579         struct ena_adapter *adapter = eth_dev->data->dev_private;
3580         struct ena_admin_aenq_keep_alive_desc *desc;
3581         uint64_t rx_drops;
3582         uint64_t tx_drops;
3583
3584         adapter->timestamp_wd = rte_get_timer_cycles();
3585
3586         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3587         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3588         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3589
3590         adapter->drv_stats->rx_drops = rx_drops;
3591         adapter->dev_stats.tx_drops = tx_drops;
3592 }
3593
3594 /**
3595  * This handler will called for unknown event group or unimplemented handlers
3596  **/
3597 static void unimplemented_aenq_handler(__rte_unused void *data,
3598                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3599 {
3600         PMD_DRV_LOG(ERR,
3601                 "Unknown event was received or event with unimplemented handler\n");
3602 }
3603
3604 static struct ena_aenq_handlers aenq_handlers = {
3605         .handlers = {
3606                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3607                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3608                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3609         },
3610         .unimplemented_handler = unimplemented_aenq_handler
3611 };
3612
3613 /*********************************************************************
3614  *  Multi-Process communication request handling (in primary)
3615  *********************************************************************/
3616 static int
3617 ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)
3618 {
3619         const struct ena_mp_body *req =
3620                 (const struct ena_mp_body *)mp_msg->param;
3621         struct ena_adapter *adapter;
3622         struct ena_com_dev *ena_dev;
3623         struct ena_mp_body *rsp;
3624         struct rte_mp_msg mp_rsp;
3625         struct rte_eth_dev *dev;
3626         int res = 0;
3627
3628         rsp = (struct ena_mp_body *)&mp_rsp.param;
3629         mp_msg_init(&mp_rsp, req->type, req->port_id);
3630
3631         if (!rte_eth_dev_is_valid_port(req->port_id)) {
3632                 rte_errno = ENODEV;
3633                 res = -rte_errno;
3634                 PMD_DRV_LOG(ERR, "Unknown port %d in request %d\n",
3635                             req->port_id, req->type);
3636                 goto end;
3637         }
3638         dev = &rte_eth_devices[req->port_id];
3639         adapter = dev->data->dev_private;
3640         ena_dev = &adapter->ena_dev;
3641
3642         switch (req->type) {
3643         case ENA_MP_DEV_STATS_GET:
3644                 res = ena_com_get_dev_basic_stats(ena_dev,
3645                                                   &adapter->basic_stats);
3646                 break;
3647         case ENA_MP_ENI_STATS_GET:
3648                 res = ena_com_get_eni_stats(ena_dev,
3649                         (struct ena_admin_eni_stats *)&adapter->eni_stats);
3650                 break;
3651         case ENA_MP_MTU_SET:
3652                 res = ena_com_set_dev_mtu(ena_dev, req->args.mtu);
3653                 break;
3654         case ENA_MP_IND_TBL_GET:
3655                 res = ena_com_indirect_table_get(ena_dev,
3656                                                  adapter->indirect_table);
3657                 break;
3658         case ENA_MP_IND_TBL_SET:
3659                 res = ena_com_indirect_table_set(ena_dev);
3660                 break;
3661         default:
3662                 PMD_DRV_LOG(ERR, "Unknown request type %d\n", req->type);
3663                 res = -EINVAL;
3664                 break;
3665         }
3666
3667 end:
3668         /* Save processing result in the reply */
3669         rsp->result = res;
3670         /* Return just IPC processing status */
3671         return rte_mp_reply(&mp_rsp, peer);
3672 }