drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    5
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 struct ena_stats {
  42         char name[ETH_GSTRING_LEN];
  43         int stat_offset;
  44 };
  45
  46 #define ENA_STAT_ENTRY(stat, stat_type) { \
  47         .name = #stat, \
  48         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  49 }
  50
  51 #define ENA_STAT_RX_ENTRY(stat) \
  52         ENA_STAT_ENTRY(stat, rx)
  53
  54 #define ENA_STAT_TX_ENTRY(stat) \
  55         ENA_STAT_ENTRY(stat, tx)
  56
  57 #define ENA_STAT_ENI_ENTRY(stat) \
  58         ENA_STAT_ENTRY(stat, eni)
  59
  60 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  61         ENA_STAT_ENTRY(stat, dev)
  62
  63 /* Device arguments */
  64 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  65
  66 /*
  67  * Each rte_memzone should have unique name.
  68  * To satisfy it, count number of allocation and add it to name.
  69  */
  70 rte_atomic64_t ena_alloc_cnt;
  71
  72 static const struct ena_stats ena_stats_global_strings[] = {
  73         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  74         ENA_STAT_GLOBAL_ENTRY(dev_start),
  75         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  76         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  77 };
  78
  79 static const struct ena_stats ena_stats_eni_strings[] = {
  80         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  81         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  82         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  83         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  84         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  85 };
  86
  87 static const struct ena_stats ena_stats_tx_strings[] = {
  88         ENA_STAT_TX_ENTRY(cnt),
  89         ENA_STAT_TX_ENTRY(bytes),
  90         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  91         ENA_STAT_TX_ENTRY(tx_poll),
  92         ENA_STAT_TX_ENTRY(doorbells),
  93         ENA_STAT_TX_ENTRY(bad_req_id),
  94         ENA_STAT_TX_ENTRY(available_desc),
  95         ENA_STAT_TX_ENTRY(missed_tx),
  96 };
  97
  98 static const struct ena_stats ena_stats_rx_strings[] = {
  99         ENA_STAT_RX_ENTRY(cnt),
 100         ENA_STAT_RX_ENTRY(bytes),
 101         ENA_STAT_RX_ENTRY(refill_partial),
 102         ENA_STAT_RX_ENTRY(l3_csum_bad),
 103         ENA_STAT_RX_ENTRY(l4_csum_bad),
 104         ENA_STAT_RX_ENTRY(l4_csum_good),
 105         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 106         ENA_STAT_RX_ENTRY(bad_desc_num),
 107         ENA_STAT_RX_ENTRY(bad_req_id),
 108 };
 109
 110 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 111 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 112 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 113 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 114
 115 #define QUEUE_OFFLOADS (RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\
 116                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM |\
 117                         RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\
 118                         RTE_ETH_TX_OFFLOAD_TCP_TSO)
 119 #define MBUF_OFFLOADS (RTE_MBUF_F_TX_L4_MASK |\
 120                        RTE_MBUF_F_TX_IP_CKSUM |\
 121                        RTE_MBUF_F_TX_TCP_SEG)
 122
 123 /** Vendor ID used by Amazon devices */
 124 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 125 /** Amazon devices */
 126 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 127 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 128
 129 #define ENA_TX_OFFLOAD_MASK     (RTE_MBUF_F_TX_L4_MASK |         \
 130         RTE_MBUF_F_TX_IPV6 |            \
 131         RTE_MBUF_F_TX_IPV4 |            \
 132         RTE_MBUF_F_TX_IP_CKSUM |        \
 133         RTE_MBUF_F_TX_TCP_SEG)
 134
 135 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 136         (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 137
 138 /** HW specific offloads capabilities. */
 139 /* IPv4 checksum offload. */
 140 #define ENA_L3_IPV4_CSUM                0x0001
 141 /* TCP/UDP checksum offload for IPv4 packets. */
 142 #define ENA_L4_IPV4_CSUM                0x0002
 143 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
 144 #define ENA_L4_IPV4_CSUM_PARTIAL        0x0004
 145 /* TCP/UDP checksum offload for IPv6 packets. */
 146 #define ENA_L4_IPV6_CSUM                0x0008
 147 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
 148 #define ENA_L4_IPV6_CSUM_PARTIAL        0x0010
 149 /* TSO support for IPv4 packets. */
 150 #define ENA_IPV4_TSO                    0x0020
 151
 152 /* Device supports setting RSS hash. */
 153 #define ENA_RX_RSS_HASH                 0x0040
 154
 155 static const struct rte_pci_id pci_id_ena_map[] = {
 156         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 157         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 158         { .device_id = 0 },
 159 };
 160
 161 static struct ena_aenq_handlers aenq_handlers;
 162
 163 static int ena_device_init(struct ena_adapter *adapter,
 164                            struct rte_pci_device *pdev,
 165                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 166 static int ena_dev_configure(struct rte_eth_dev *dev);
 167 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 168         struct ena_tx_buffer *tx_info,
 169         struct rte_mbuf *mbuf,
 170         void **push_header,
 171         uint16_t *header_len);
 172 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 173 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 174 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 175                                   uint16_t nb_pkts);
 176 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 177                 uint16_t nb_pkts);
 178 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 179                               uint16_t nb_desc, unsigned int socket_id,
 180                               const struct rte_eth_txconf *tx_conf);
 181 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 182                               uint16_t nb_desc, unsigned int socket_id,
 183                               const struct rte_eth_rxconf *rx_conf,
 184                               struct rte_mempool *mp);
 185 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 186 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 187                                     struct ena_com_rx_buf_info *ena_bufs,
 188                                     uint32_t descs,
 189                                     uint16_t *next_to_clean,
 190                                     uint8_t offset);
 191 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 192                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 193 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 194                                   struct rte_mbuf *mbuf, uint16_t id);
 195 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 196 static void ena_init_rings(struct ena_adapter *adapter,
 197                            bool disable_meta_caching);
 198 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 199 static int ena_start(struct rte_eth_dev *dev);
 200 static int ena_stop(struct rte_eth_dev *dev);
 201 static int ena_close(struct rte_eth_dev *dev);
 202 static int ena_dev_reset(struct rte_eth_dev *dev);
 203 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 204 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 205 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 206 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 207 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 208 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 209 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 210 static int ena_link_update(struct rte_eth_dev *dev,
 211                            int wait_to_complete);
 212 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 213 static void ena_queue_stop(struct ena_ring *ring);
 214 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 215                               enum ena_ring_type ring_type);
 216 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 217 static int ena_queue_start_all(struct rte_eth_dev *dev,
 218                                enum ena_ring_type ring_type);
 219 static void ena_stats_restart(struct rte_eth_dev *dev);
 220 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter);
 221 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter);
 222 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);
 223 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);
 224 static int ena_infos_get(struct rte_eth_dev *dev,
 225                          struct rte_eth_dev_info *dev_info);
 226 static void ena_interrupt_handler_rte(void *cb_arg);
 227 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 228 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 229 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 230 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 231                                 struct rte_eth_xstat_name *xstats_names,
 232                                 unsigned int n);
 233 static int ena_xstats_get(struct rte_eth_dev *dev,
 234                           struct rte_eth_xstat *stats,
 235                           unsigned int n);
 236 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 237                                 const uint64_t *ids,
 238                                 uint64_t *values,
 239                                 unsigned int n);
 240 static int ena_process_bool_devarg(const char *key,
 241                                    const char *value,
 242                                    void *opaque);
 243 static int ena_parse_devargs(struct ena_adapter *adapter,
 244                              struct rte_devargs *devargs);
 245 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 246 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 247 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 248                                     uint16_t queue_id);
 249 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 250                                      uint16_t queue_id);
 251 static int ena_configure_aenq(struct ena_adapter *adapter);
 252
 253 static const struct eth_dev_ops ena_dev_ops = {
 254         .dev_configure        = ena_dev_configure,
 255         .dev_infos_get        = ena_infos_get,
 256         .rx_queue_setup       = ena_rx_queue_setup,
 257         .tx_queue_setup       = ena_tx_queue_setup,
 258         .dev_start            = ena_start,
 259         .dev_stop             = ena_stop,
 260         .link_update          = ena_link_update,
 261         .stats_get            = ena_stats_get,
 262         .xstats_get_names     = ena_xstats_get_names,
 263         .xstats_get           = ena_xstats_get,
 264         .xstats_get_by_id     = ena_xstats_get_by_id,
 265         .mtu_set              = ena_mtu_set,
 266         .rx_queue_release     = ena_rx_queue_release,
 267         .tx_queue_release     = ena_tx_queue_release,
 268         .dev_close            = ena_close,
 269         .dev_reset            = ena_dev_reset,
 270         .reta_update          = ena_rss_reta_update,
 271         .reta_query           = ena_rss_reta_query,
 272         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 273         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 274         .rss_hash_update      = ena_rss_hash_update,
 275         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 276 };
 277
 278 static inline void ena_rx_mbuf_prepare(struct ena_ring *rx_ring,
 279                                        struct rte_mbuf *mbuf,
 280                                        struct ena_com_rx_ctx *ena_rx_ctx,
 281                                        bool fill_hash)
 282 {
 283         struct ena_stats_rx *rx_stats = &rx_ring->rx_stats;
 284         uint64_t ol_flags = 0;
 285         uint32_t packet_type = 0;
 286
 287         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 288                 packet_type |= RTE_PTYPE_L4_TCP;
 289         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 290                 packet_type |= RTE_PTYPE_L4_UDP;
 291
 292         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 293                 packet_type |= RTE_PTYPE_L3_IPV4;
 294                 if (unlikely(ena_rx_ctx->l3_csum_err)) {
 295                         ++rx_stats->l3_csum_bad;
 296                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
 297                 } else {
 298                         ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
 299                 }
 300         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 301                 packet_type |= RTE_PTYPE_L3_IPV6;
 302         }
 303
 304         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag) {
 305                 ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;
 306         } else {
 307                 if (unlikely(ena_rx_ctx->l4_csum_err)) {
 308                         ++rx_stats->l4_csum_bad;
 309                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
 310                 } else {
 311                         ++rx_stats->l4_csum_good;
 312                         ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
 313                 }
 314         }
 315
 316         if (fill_hash &&
 317             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 318                 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 319                 mbuf->hash.rss = ena_rx_ctx->hash;
 320         }
 321
 322         mbuf->ol_flags = ol_flags;
 323         mbuf->packet_type = packet_type;
 324 }
 325
 326 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 327                                        struct ena_com_tx_ctx *ena_tx_ctx,
 328                                        uint64_t queue_offloads,
 329                                        bool disable_meta_caching)
 330 {
 331         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 332
 333         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 334             (queue_offloads & QUEUE_OFFLOADS)) {
 335                 /* check if TSO is required */
 336                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
 337                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO)) {
 338                         ena_tx_ctx->tso_enable = true;
 339
 340                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 341                 }
 342
 343                 /* check if L3 checksum is needed */
 344                 if ((mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
 345                     (queue_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM))
 346                         ena_tx_ctx->l3_csum_enable = true;
 347
 348                 if (mbuf->ol_flags & RTE_MBUF_F_TX_IPV6) {
 349                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 350                 } else {
 351                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 352
 353                         /* set don't fragment (DF) flag */
 354                         if (mbuf->packet_type &
 355                                 (RTE_PTYPE_L4_NONFRAG
 356                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 357                                 ena_tx_ctx->df = true;
 358                 }
 359
 360                 /* check if L4 checksum is needed */
 361                 if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM) &&
 362                     (queue_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else if (((mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
 366                                 RTE_MBUF_F_TX_UDP_CKSUM) &&
 367                                 (queue_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) {
 368                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 369                         ena_tx_ctx->l4_csum_enable = true;
 370                 } else {
 371                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 372                         ena_tx_ctx->l4_csum_enable = false;
 373                 }
 374
 375                 ena_meta->mss = mbuf->tso_segsz;
 376                 ena_meta->l3_hdr_len = mbuf->l3_len;
 377                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 378
 379                 ena_tx_ctx->meta_valid = true;
 380         } else if (disable_meta_caching) {
 381                 memset(ena_meta, 0, sizeof(*ena_meta));
 382                 ena_tx_ctx->meta_valid = true;
 383         } else {
 384                 ena_tx_ctx->meta_valid = false;
 385         }
 386 }
 387
 388 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 389 {
 390         struct ena_tx_buffer *tx_info = NULL;
 391
 392         if (likely(req_id < tx_ring->ring_size)) {
 393                 tx_info = &tx_ring->tx_buffer_info[req_id];
 394                 if (likely(tx_info->mbuf))
 395                         return 0;
 396         }
 397
 398         if (tx_info)
 399                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 400         else
 401                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 402
 403         /* Trigger device reset */
 404         ++tx_ring->tx_stats.bad_req_id;
 405         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 406         tx_ring->adapter->trigger_reset = true;
 407         return -EFAULT;
 408 }
 409
 410 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 411 {
 412         struct ena_admin_host_info *host_info;
 413         int rc;
 414
 415         /* Allocate only the host info */
 416         rc = ena_com_allocate_host_info(ena_dev);
 417         if (rc) {
 418                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 419                 return;
 420         }
 421
 422         host_info = ena_dev->host_attr.host_info;
 423
 424         host_info->os_type = ENA_ADMIN_OS_DPDK;
 425         host_info->kernel_ver = RTE_VERSION;
 426         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 427                 sizeof(host_info->kernel_ver_str));
 428         host_info->os_dist = RTE_VERSION;
 429         strlcpy((char *)host_info->os_dist_str, rte_version(),
 430                 sizeof(host_info->os_dist_str));
 431         host_info->driver_version =
 432                 (DRV_MODULE_VER_MAJOR) |
 433                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 434                 (DRV_MODULE_VER_SUBMINOR <<
 435                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 436         host_info->num_cpus = rte_lcore_count();
 437
 438         host_info->driver_supported_features =
 439                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 440                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 441
 442         rc = ena_com_set_host_attributes(ena_dev);
 443         if (rc) {
 444                 if (rc == -ENA_COM_UNSUPPORTED)
 445                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 446                 else
 447                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 448
 449                 goto err;
 450         }
 451
 452         return;
 453
 454 err:
 455         ena_com_delete_host_info(ena_dev);
 456 }
 457
 458 /* This function calculates the number of xstats based on the current config */
 459 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 460 {
 461         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 462                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 463                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 464 }
 465
 466 static void ena_config_debug_area(struct ena_adapter *adapter)
 467 {
 468         u32 debug_area_size;
 469         int rc, ss_count;
 470
 471         ss_count = ena_xstats_calc_num(adapter->edev_data);
 472
 473         /* allocate 32 bytes for each string and 64bit for the value */
 474         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 475
 476         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 477         if (rc) {
 478                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 479                 return;
 480         }
 481
 482         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 483         if (rc) {
 484                 if (rc == -ENA_COM_UNSUPPORTED)
 485                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 486                 else
 487                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 488
 489                 goto err;
 490         }
 491
 492         return;
 493 err:
 494         ena_com_delete_debug_area(&adapter->ena_dev);
 495 }
 496
 497 static int ena_close(struct rte_eth_dev *dev)
 498 {
 499         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 500         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 501         struct ena_adapter *adapter = dev->data->dev_private;
 502         int ret = 0;
 503
 504         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 505                 return 0;
 506
 507         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 508                 ret = ena_stop(dev);
 509         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 510
 511         ena_rx_queue_release_all(dev);
 512         ena_tx_queue_release_all(dev);
 513
 514         rte_free(adapter->drv_stats);
 515         adapter->drv_stats = NULL;
 516
 517         rte_intr_disable(intr_handle);
 518         rte_intr_callback_unregister(intr_handle,
 519                                      ena_interrupt_handler_rte,
 520                                      dev);
 521
 522         /*
 523          * MAC is not allocated dynamically. Setting NULL should prevent from
 524          * release of the resource in the rte_eth_dev_release_port().
 525          */
 526         dev->data->mac_addrs = NULL;
 527
 528         return ret;
 529 }
 530
 531 static int
 532 ena_dev_reset(struct rte_eth_dev *dev)
 533 {
 534         int rc = 0;
 535
 536         /* Cannot release memory in secondary process */
 537         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 538                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 539                 return -EPERM;
 540         }
 541
 542         ena_destroy_device(dev);
 543         rc = eth_ena_dev_init(dev);
 544         if (rc)
 545                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 546
 547         return rc;
 548 }
 549
 550 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 551 {
 552         int nb_queues = dev->data->nb_rx_queues;
 553         int i;
 554
 555         for (i = 0; i < nb_queues; i++)
 556                 ena_rx_queue_release(dev, i);
 557 }
 558
 559 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 560 {
 561         int nb_queues = dev->data->nb_tx_queues;
 562         int i;
 563
 564         for (i = 0; i < nb_queues; i++)
 565                 ena_tx_queue_release(dev, i);
 566 }
 567
 568 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 569 {
 570         struct ena_ring *ring = dev->data->rx_queues[qid];
 571
 572         /* Free ring resources */
 573         rte_free(ring->rx_buffer_info);
 574         ring->rx_buffer_info = NULL;
 575
 576         rte_free(ring->rx_refill_buffer);
 577         ring->rx_refill_buffer = NULL;
 578
 579         rte_free(ring->empty_rx_reqs);
 580         ring->empty_rx_reqs = NULL;
 581
 582         ring->configured = 0;
 583
 584         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 585                 ring->port_id, ring->id);
 586 }
 587
 588 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 589 {
 590         struct ena_ring *ring = dev->data->tx_queues[qid];
 591
 592         /* Free ring resources */
 593         rte_free(ring->push_buf_intermediate_buf);
 594
 595         rte_free(ring->tx_buffer_info);
 596
 597         rte_free(ring->empty_tx_reqs);
 598
 599         ring->empty_tx_reqs = NULL;
 600         ring->tx_buffer_info = NULL;
 601         ring->push_buf_intermediate_buf = NULL;
 602
 603         ring->configured = 0;
 604
 605         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 606                 ring->port_id, ring->id);
 607 }
 608
 609 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 610 {
 611         unsigned int i;
 612
 613         for (i = 0; i < ring->ring_size; ++i) {
 614                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 615                 if (rx_info->mbuf) {
 616                         rte_mbuf_raw_free(rx_info->mbuf);
 617                         rx_info->mbuf = NULL;
 618                 }
 619         }
 620 }
 621
 622 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 623 {
 624         unsigned int i;
 625
 626         for (i = 0; i < ring->ring_size; ++i) {
 627                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 628
 629                 if (tx_buf->mbuf) {
 630                         rte_pktmbuf_free(tx_buf->mbuf);
 631                         tx_buf->mbuf = NULL;
 632                 }
 633         }
 634 }
 635
 636 static int ena_link_update(struct rte_eth_dev *dev,
 637                            __rte_unused int wait_to_complete)
 638 {
 639         struct rte_eth_link *link = &dev->data->dev_link;
 640         struct ena_adapter *adapter = dev->data->dev_private;
 641
 642         link->link_status = adapter->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
 643         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
 644         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
 645
 646         return 0;
 647 }
 648
 649 static int ena_queue_start_all(struct rte_eth_dev *dev,
 650                                enum ena_ring_type ring_type)
 651 {
 652         struct ena_adapter *adapter = dev->data->dev_private;
 653         struct ena_ring *queues = NULL;
 654         int nb_queues;
 655         int i = 0;
 656         int rc = 0;
 657
 658         if (ring_type == ENA_RING_TYPE_RX) {
 659                 queues = adapter->rx_ring;
 660                 nb_queues = dev->data->nb_rx_queues;
 661         } else {
 662                 queues = adapter->tx_ring;
 663                 nb_queues = dev->data->nb_tx_queues;
 664         }
 665         for (i = 0; i < nb_queues; i++) {
 666                 if (queues[i].configured) {
 667                         if (ring_type == ENA_RING_TYPE_RX) {
 668                                 ena_assert_msg(
 669                                         dev->data->rx_queues[i] == &queues[i],
 670                                         "Inconsistent state of Rx queues\n");
 671                         } else {
 672                                 ena_assert_msg(
 673                                         dev->data->tx_queues[i] == &queues[i],
 674                                         "Inconsistent state of Tx queues\n");
 675                         }
 676
 677                         rc = ena_queue_start(dev, &queues[i]);
 678
 679                         if (rc) {
 680                                 PMD_INIT_LOG(ERR,
 681                                         "Failed to start queue[%d] of type(%d)\n",
 682                                         i, ring_type);
 683                                 goto err;
 684                         }
 685                 }
 686         }
 687
 688         return 0;
 689
 690 err:
 691         while (i--)
 692                 if (queues[i].configured)
 693                         ena_queue_stop(&queues[i]);
 694
 695         return rc;
 696 }
 697
 698 static int ena_check_valid_conf(struct ena_adapter *adapter)
 699 {
 700         uint32_t mtu = adapter->edev_data->mtu;
 701
 702         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 703                 PMD_INIT_LOG(ERR,
 704                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 705                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 706                 return ENA_COM_UNSUPPORTED;
 707         }
 708
 709         return 0;
 710 }
 711
 712 static int
 713 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 714                        bool use_large_llq_hdr)
 715 {
 716         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 717         struct ena_com_dev *ena_dev = ctx->ena_dev;
 718         uint32_t max_tx_queue_size;
 719         uint32_t max_rx_queue_size;
 720
 721         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 722                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 723                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 724                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 725                         max_queue_ext->max_rx_sq_depth);
 726                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 727
 728                 if (ena_dev->tx_mem_queue_type ==
 729                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 730                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 731                                 llq->max_llq_depth);
 732                 } else {
 733                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 734                                 max_queue_ext->max_tx_sq_depth);
 735                 }
 736
 737                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 738                         max_queue_ext->max_per_packet_rx_descs);
 739                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 740                         max_queue_ext->max_per_packet_tx_descs);
 741         } else {
 742                 struct ena_admin_queue_feature_desc *max_queues =
 743                         &ctx->get_feat_ctx->max_queues;
 744                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 745                         max_queues->max_sq_depth);
 746                 max_tx_queue_size = max_queues->max_cq_depth;
 747
 748                 if (ena_dev->tx_mem_queue_type ==
 749                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 750                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 751                                 llq->max_llq_depth);
 752                 } else {
 753                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 754                                 max_queues->max_sq_depth);
 755                 }
 756
 757                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 758                         max_queues->max_packet_rx_descs);
 759                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 760                         max_queues->max_packet_tx_descs);
 761         }
 762
 763         /* Round down to the nearest power of 2 */
 764         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 765         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 766
 767         if (use_large_llq_hdr) {
 768                 if ((llq->entry_size_ctrl_supported &
 769                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 770                     (ena_dev->tx_mem_queue_type ==
 771                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 772                         max_tx_queue_size /= 2;
 773                         PMD_INIT_LOG(INFO,
 774                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
 775                                 max_tx_queue_size);
 776                 } else {
 777                         PMD_INIT_LOG(ERR,
 778                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 779                 }
 780         }
 781
 782         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 783                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 784                 return -EFAULT;
 785         }
 786
 787         ctx->max_tx_queue_size = max_tx_queue_size;
 788         ctx->max_rx_queue_size = max_rx_queue_size;
 789
 790         return 0;
 791 }
 792
 793 static void ena_stats_restart(struct rte_eth_dev *dev)
 794 {
 795         struct ena_adapter *adapter = dev->data->dev_private;
 796
 797         rte_atomic64_init(&adapter->drv_stats->ierrors);
 798         rte_atomic64_init(&adapter->drv_stats->oerrors);
 799         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 800         adapter->drv_stats->rx_drops = 0;
 801 }
 802
 803 static int ena_stats_get(struct rte_eth_dev *dev,
 804                           struct rte_eth_stats *stats)
 805 {
 806         struct ena_admin_basic_stats ena_stats;
 807         struct ena_adapter *adapter = dev->data->dev_private;
 808         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 809         int rc;
 810         int i;
 811         int max_rings_stats;
 812
 813         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 814                 return -ENOTSUP;
 815
 816         memset(&ena_stats, 0, sizeof(ena_stats));
 817
 818         rte_spinlock_lock(&adapter->admin_lock);
 819         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 820         rte_spinlock_unlock(&adapter->admin_lock);
 821         if (unlikely(rc)) {
 822                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 823                 return rc;
 824         }
 825
 826         /* Set of basic statistics from ENA */
 827         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 828                                           ena_stats.rx_pkts_low);
 829         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 830                                           ena_stats.tx_pkts_low);
 831         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 832                                         ena_stats.rx_bytes_low);
 833         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 834                                         ena_stats.tx_bytes_low);
 835
 836         /* Driver related stats */
 837         stats->imissed = adapter->drv_stats->rx_drops;
 838         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 839         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 840         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 841
 842         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 843                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 844         for (i = 0; i < max_rings_stats; ++i) {
 845                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 846
 847                 stats->q_ibytes[i] = rx_stats->bytes;
 848                 stats->q_ipackets[i] = rx_stats->cnt;
 849                 stats->q_errors[i] = rx_stats->bad_desc_num +
 850                         rx_stats->bad_req_id;
 851         }
 852
 853         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 854                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 855         for (i = 0; i < max_rings_stats; ++i) {
 856                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 857
 858                 stats->q_obytes[i] = tx_stats->bytes;
 859                 stats->q_opackets[i] = tx_stats->cnt;
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 866 {
 867         struct ena_adapter *adapter;
 868         struct ena_com_dev *ena_dev;
 869         int rc = 0;
 870
 871         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 872         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 873         adapter = dev->data->dev_private;
 874
 875         ena_dev = &adapter->ena_dev;
 876         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 877
 878         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 879                 PMD_DRV_LOG(ERR,
 880                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
 881                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 882                 return -EINVAL;
 883         }
 884
 885         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 886         if (rc)
 887                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 888         else
 889                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
 890
 891         return rc;
 892 }
 893
 894 static int ena_start(struct rte_eth_dev *dev)
 895 {
 896         struct ena_adapter *adapter = dev->data->dev_private;
 897         uint64_t ticks;
 898         int rc = 0;
 899
 900         /* Cannot allocate memory in secondary process */
 901         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 902                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
 903                 return -EPERM;
 904         }
 905
 906         rc = ena_check_valid_conf(adapter);
 907         if (rc)
 908                 return rc;
 909
 910         rc = ena_setup_rx_intr(dev);
 911         if (rc)
 912                 return rc;
 913
 914         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
 915         if (rc)
 916                 return rc;
 917
 918         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
 919         if (rc)
 920                 goto err_start_tx;
 921
 922         if (adapter->edev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 923                 rc = ena_rss_configure(adapter);
 924                 if (rc)
 925                         goto err_rss_init;
 926         }
 927
 928         ena_stats_restart(dev);
 929
 930         adapter->timestamp_wd = rte_get_timer_cycles();
 931         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
 932
 933         ticks = rte_get_timer_hz();
 934         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
 935                         ena_timer_wd_callback, dev);
 936
 937         ++adapter->dev_stats.dev_start;
 938         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 939
 940         return 0;
 941
 942 err_rss_init:
 943         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 944 err_start_tx:
 945         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 946         return rc;
 947 }
 948
 949 static int ena_stop(struct rte_eth_dev *dev)
 950 {
 951         struct ena_adapter *adapter = dev->data->dev_private;
 952         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 953         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 954         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 955         int rc;
 956
 957         /* Cannot free memory in secondary process */
 958         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 959                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
 960                 return -EPERM;
 961         }
 962
 963         rte_timer_stop_sync(&adapter->timer_wd);
 964         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 965         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 966
 967         if (adapter->trigger_reset) {
 968                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 969                 if (rc)
 970                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
 971         }
 972
 973         rte_intr_disable(intr_handle);
 974
 975         rte_intr_efd_disable(intr_handle);
 976
 977         /* Cleanup vector list */
 978         rte_intr_vec_list_free(intr_handle);
 979
 980         rte_intr_enable(intr_handle);
 981
 982         ++adapter->dev_stats.dev_stop;
 983         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 984         dev->data->dev_started = 0;
 985
 986         return 0;
 987 }
 988
 989 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
 990 {
 991         struct ena_adapter *adapter = ring->adapter;
 992         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 994         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 995         struct ena_com_create_io_ctx ctx =
 996                 /* policy set to _HOST just to satisfy icc compiler */
 997                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 998                   0, 0, 0, 0, 0 };
 999         uint16_t ena_qid;
1000         unsigned int i;
1001         int rc;
1002
1003         ctx.msix_vector = -1;
1004         if (ring->type == ENA_RING_TYPE_TX) {
1005                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1006                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1007                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1008                 for (i = 0; i < ring->ring_size; i++)
1009                         ring->empty_tx_reqs[i] = i;
1010         } else {
1011                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1012                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1013                 if (rte_intr_dp_is_en(intr_handle))
1014                         ctx.msix_vector =
1015                                 rte_intr_vec_list_index_get(intr_handle,
1016                                                                    ring->id);
1017
1018                 for (i = 0; i < ring->ring_size; i++)
1019                         ring->empty_rx_reqs[i] = i;
1020         }
1021         ctx.queue_size = ring->ring_size;
1022         ctx.qid = ena_qid;
1023         ctx.numa_node = ring->numa_socket_id;
1024
1025         rc = ena_com_create_io_queue(ena_dev, &ctx);
1026         if (rc) {
1027                 PMD_DRV_LOG(ERR,
1028                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1029                         ring->id, ena_qid, rc);
1030                 return rc;
1031         }
1032
1033         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1034                                      &ring->ena_com_io_sq,
1035                                      &ring->ena_com_io_cq);
1036         if (rc) {
1037                 PMD_DRV_LOG(ERR,
1038                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1039                         ring->id, rc);
1040                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1041                 return rc;
1042         }
1043
1044         if (ring->type == ENA_RING_TYPE_TX)
1045                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1046
1047         /* Start with Rx interrupts being masked. */
1048         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1049                 ena_rx_queue_intr_disable(dev, ring->id);
1050
1051         return 0;
1052 }
1053
1054 static void ena_queue_stop(struct ena_ring *ring)
1055 {
1056         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1057
1058         if (ring->type == ENA_RING_TYPE_RX) {
1059                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1060                 ena_rx_queue_release_bufs(ring);
1061         } else {
1062                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1063                 ena_tx_queue_release_bufs(ring);
1064         }
1065 }
1066
1067 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1068                               enum ena_ring_type ring_type)
1069 {
1070         struct ena_adapter *adapter = dev->data->dev_private;
1071         struct ena_ring *queues = NULL;
1072         uint16_t nb_queues, i;
1073
1074         if (ring_type == ENA_RING_TYPE_RX) {
1075                 queues = adapter->rx_ring;
1076                 nb_queues = dev->data->nb_rx_queues;
1077         } else {
1078                 queues = adapter->tx_ring;
1079                 nb_queues = dev->data->nb_tx_queues;
1080         }
1081
1082         for (i = 0; i < nb_queues; ++i)
1083                 if (queues[i].configured)
1084                         ena_queue_stop(&queues[i]);
1085 }
1086
1087 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1088 {
1089         int rc, bufs_num;
1090
1091         ena_assert_msg(ring->configured == 1,
1092                        "Trying to start unconfigured queue\n");
1093
1094         rc = ena_create_io_queue(dev, ring);
1095         if (rc) {
1096                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1097                 return rc;
1098         }
1099
1100         ring->next_to_clean = 0;
1101         ring->next_to_use = 0;
1102
1103         if (ring->type == ENA_RING_TYPE_TX) {
1104                 ring->tx_stats.available_desc =
1105                         ena_com_free_q_entries(ring->ena_com_io_sq);
1106                 return 0;
1107         }
1108
1109         bufs_num = ring->ring_size - 1;
1110         rc = ena_populate_rx_queue(ring, bufs_num);
1111         if (rc != bufs_num) {
1112                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1113                                          ENA_IO_RXQ_IDX(ring->id));
1114                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1115                 return ENA_COM_FAULT;
1116         }
1117         /* Flush per-core RX buffers pools cache as they can be used on other
1118          * cores as well.
1119          */
1120         rte_mempool_cache_flush(NULL, ring->mb_pool);
1121
1122         return 0;
1123 }
1124
1125 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1126                               uint16_t queue_idx,
1127                               uint16_t nb_desc,
1128                               unsigned int socket_id,
1129                               const struct rte_eth_txconf *tx_conf)
1130 {
1131         struct ena_ring *txq = NULL;
1132         struct ena_adapter *adapter = dev->data->dev_private;
1133         unsigned int i;
1134         uint16_t dyn_thresh;
1135
1136         txq = &adapter->tx_ring[queue_idx];
1137
1138         if (txq->configured) {
1139                 PMD_DRV_LOG(CRIT,
1140                         "API violation. Queue[%d] is already configured\n",
1141                         queue_idx);
1142                 return ENA_COM_FAULT;
1143         }
1144
1145         if (!rte_is_power_of_2(nb_desc)) {
1146                 PMD_DRV_LOG(ERR,
1147                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1148                         nb_desc);
1149                 return -EINVAL;
1150         }
1151
1152         if (nb_desc > adapter->max_tx_ring_size) {
1153                 PMD_DRV_LOG(ERR,
1154                         "Unsupported size of Tx queue (max size: %d)\n",
1155                         adapter->max_tx_ring_size);
1156                 return -EINVAL;
1157         }
1158
1159         txq->port_id = dev->data->port_id;
1160         txq->next_to_clean = 0;
1161         txq->next_to_use = 0;
1162         txq->ring_size = nb_desc;
1163         txq->size_mask = nb_desc - 1;
1164         txq->numa_socket_id = socket_id;
1165         txq->pkts_without_db = false;
1166         txq->last_cleanup_ticks = 0;
1167
1168         txq->tx_buffer_info = rte_zmalloc_socket("txq->tx_buffer_info",
1169                 sizeof(struct ena_tx_buffer) * txq->ring_size,
1170                 RTE_CACHE_LINE_SIZE,
1171                 socket_id);
1172         if (!txq->tx_buffer_info) {
1173                 PMD_DRV_LOG(ERR,
1174                         "Failed to allocate memory for Tx buffer info\n");
1175                 return -ENOMEM;
1176         }
1177
1178         txq->empty_tx_reqs = rte_zmalloc_socket("txq->empty_tx_reqs",
1179                 sizeof(uint16_t) * txq->ring_size,
1180                 RTE_CACHE_LINE_SIZE,
1181                 socket_id);
1182         if (!txq->empty_tx_reqs) {
1183                 PMD_DRV_LOG(ERR,
1184                         "Failed to allocate memory for empty Tx requests\n");
1185                 rte_free(txq->tx_buffer_info);
1186                 return -ENOMEM;
1187         }
1188
1189         txq->push_buf_intermediate_buf =
1190                 rte_zmalloc_socket("txq->push_buf_intermediate_buf",
1191                         txq->tx_max_header_size,
1192                         RTE_CACHE_LINE_SIZE,
1193                         socket_id);
1194         if (!txq->push_buf_intermediate_buf) {
1195                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1196                 rte_free(txq->tx_buffer_info);
1197                 rte_free(txq->empty_tx_reqs);
1198                 return -ENOMEM;
1199         }
1200
1201         for (i = 0; i < txq->ring_size; i++)
1202                 txq->empty_tx_reqs[i] = i;
1203
1204         txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1205
1206         /* Check if caller provided the Tx cleanup threshold value. */
1207         if (tx_conf->tx_free_thresh != 0) {
1208                 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1209         } else {
1210                 dyn_thresh = txq->ring_size -
1211                         txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1212                 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1213                         txq->ring_size - ENA_REFILL_THRESH_PACKET);
1214         }
1215
1216         txq->missing_tx_completion_threshold =
1217                 RTE_MIN(txq->ring_size / 2, ENA_DEFAULT_MISSING_COMP);
1218
1219         /* Store pointer to this queue in upper layer */
1220         txq->configured = 1;
1221         dev->data->tx_queues[queue_idx] = txq;
1222
1223         return 0;
1224 }
1225
1226 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1227                               uint16_t queue_idx,
1228                               uint16_t nb_desc,
1229                               unsigned int socket_id,
1230                               const struct rte_eth_rxconf *rx_conf,
1231                               struct rte_mempool *mp)
1232 {
1233         struct ena_adapter *adapter = dev->data->dev_private;
1234         struct ena_ring *rxq = NULL;
1235         size_t buffer_size;
1236         int i;
1237         uint16_t dyn_thresh;
1238
1239         rxq = &adapter->rx_ring[queue_idx];
1240         if (rxq->configured) {
1241                 PMD_DRV_LOG(CRIT,
1242                         "API violation. Queue[%d] is already configured\n",
1243                         queue_idx);
1244                 return ENA_COM_FAULT;
1245         }
1246
1247         if (!rte_is_power_of_2(nb_desc)) {
1248                 PMD_DRV_LOG(ERR,
1249                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1250                         nb_desc);
1251                 return -EINVAL;
1252         }
1253
1254         if (nb_desc > adapter->max_rx_ring_size) {
1255                 PMD_DRV_LOG(ERR,
1256                         "Unsupported size of Rx queue (max size: %d)\n",
1257                         adapter->max_rx_ring_size);
1258                 return -EINVAL;
1259         }
1260
1261         /* ENA isn't supporting buffers smaller than 1400 bytes */
1262         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1263         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1264                 PMD_DRV_LOG(ERR,
1265                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1266                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1267                 return -EINVAL;
1268         }
1269
1270         rxq->port_id = dev->data->port_id;
1271         rxq->next_to_clean = 0;
1272         rxq->next_to_use = 0;
1273         rxq->ring_size = nb_desc;
1274         rxq->size_mask = nb_desc - 1;
1275         rxq->numa_socket_id = socket_id;
1276         rxq->mb_pool = mp;
1277
1278         rxq->rx_buffer_info = rte_zmalloc_socket("rxq->buffer_info",
1279                 sizeof(struct ena_rx_buffer) * nb_desc,
1280                 RTE_CACHE_LINE_SIZE,
1281                 socket_id);
1282         if (!rxq->rx_buffer_info) {
1283                 PMD_DRV_LOG(ERR,
1284                         "Failed to allocate memory for Rx buffer info\n");
1285                 return -ENOMEM;
1286         }
1287
1288         rxq->rx_refill_buffer = rte_zmalloc_socket("rxq->rx_refill_buffer",
1289                 sizeof(struct rte_mbuf *) * nb_desc,
1290                 RTE_CACHE_LINE_SIZE,
1291                 socket_id);
1292         if (!rxq->rx_refill_buffer) {
1293                 PMD_DRV_LOG(ERR,
1294                         "Failed to allocate memory for Rx refill buffer\n");
1295                 rte_free(rxq->rx_buffer_info);
1296                 rxq->rx_buffer_info = NULL;
1297                 return -ENOMEM;
1298         }
1299
1300         rxq->empty_rx_reqs = rte_zmalloc_socket("rxq->empty_rx_reqs",
1301                 sizeof(uint16_t) * nb_desc,
1302                 RTE_CACHE_LINE_SIZE,
1303                 socket_id);
1304         if (!rxq->empty_rx_reqs) {
1305                 PMD_DRV_LOG(ERR,
1306                         "Failed to allocate memory for empty Rx requests\n");
1307                 rte_free(rxq->rx_buffer_info);
1308                 rxq->rx_buffer_info = NULL;
1309                 rte_free(rxq->rx_refill_buffer);
1310                 rxq->rx_refill_buffer = NULL;
1311                 return -ENOMEM;
1312         }
1313
1314         for (i = 0; i < nb_desc; i++)
1315                 rxq->empty_rx_reqs[i] = i;
1316
1317         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1318
1319         if (rx_conf->rx_free_thresh != 0) {
1320                 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1321         } else {
1322                 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1323                 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1324                         (uint16_t)(ENA_REFILL_THRESH_PACKET));
1325         }
1326
1327         /* Store pointer to this queue in upper layer */
1328         rxq->configured = 1;
1329         dev->data->rx_queues[queue_idx] = rxq;
1330
1331         return 0;
1332 }
1333
1334 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1335                                   struct rte_mbuf *mbuf, uint16_t id)
1336 {
1337         struct ena_com_buf ebuf;
1338         int rc;
1339
1340         /* prepare physical address for DMA transaction */
1341         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1342         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1343
1344         /* pass resource to device */
1345         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1346         if (unlikely(rc != 0))
1347                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1348
1349         return rc;
1350 }
1351
1352 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1353 {
1354         unsigned int i;
1355         int rc;
1356         uint16_t next_to_use = rxq->next_to_use;
1357         uint16_t req_id;
1358 #ifdef RTE_ETHDEV_DEBUG_RX
1359         uint16_t in_use;
1360 #endif
1361         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1362
1363         if (unlikely(!count))
1364                 return 0;
1365
1366 #ifdef RTE_ETHDEV_DEBUG_RX
1367         in_use = rxq->ring_size - 1 -
1368                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1369         if (unlikely((in_use + count) >= rxq->ring_size))
1370                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1371 #endif
1372
1373         /* get resources for incoming packets */
1374         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1375         if (unlikely(rc < 0)) {
1376                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1377                 ++rxq->rx_stats.mbuf_alloc_fail;
1378                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1379                 return 0;
1380         }
1381
1382         for (i = 0; i < count; i++) {
1383                 struct rte_mbuf *mbuf = mbufs[i];
1384                 struct ena_rx_buffer *rx_info;
1385
1386                 if (likely((i + 4) < count))
1387                         rte_prefetch0(mbufs[i + 4]);
1388
1389                 req_id = rxq->empty_rx_reqs[next_to_use];
1390                 rx_info = &rxq->rx_buffer_info[req_id];
1391
1392                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1393                 if (unlikely(rc != 0))
1394                         break;
1395
1396                 rx_info->mbuf = mbuf;
1397                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1398         }
1399
1400         if (unlikely(i < count)) {
1401                 PMD_RX_LOG(WARNING,
1402                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1403                         rxq->id, i, count);
1404                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1405                 ++rxq->rx_stats.refill_partial;
1406         }
1407
1408         /* When we submitted free resources to device... */
1409         if (likely(i > 0)) {
1410                 /* ...let HW know that it can fill buffers with data. */
1411                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1412
1413                 rxq->next_to_use = next_to_use;
1414         }
1415
1416         return i;
1417 }
1418
1419 static int ena_device_init(struct ena_adapter *adapter,
1420                            struct rte_pci_device *pdev,
1421                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1422 {
1423         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1424         uint32_t aenq_groups;
1425         int rc;
1426         bool readless_supported;
1427
1428         /* Initialize mmio registers */
1429         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1430         if (rc) {
1431                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1432                 return rc;
1433         }
1434
1435         /* The PCIe configuration space revision id indicate if mmio reg
1436          * read is disabled.
1437          */
1438         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1439         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1440
1441         /* reset device */
1442         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1443         if (rc) {
1444                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1445                 goto err_mmio_read_less;
1446         }
1447
1448         /* check FW version */
1449         rc = ena_com_validate_version(ena_dev);
1450         if (rc) {
1451                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1452                 goto err_mmio_read_less;
1453         }
1454
1455         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1456
1457         /* ENA device administration layer init */
1458         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1459         if (rc) {
1460                 PMD_DRV_LOG(ERR,
1461                         "Cannot initialize ENA admin queue\n");
1462                 goto err_mmio_read_less;
1463         }
1464
1465         /* To enable the msix interrupts the driver needs to know the number
1466          * of queues. So the driver uses polling mode to retrieve this
1467          * information.
1468          */
1469         ena_com_set_admin_polling_mode(ena_dev, true);
1470
1471         ena_config_host_info(ena_dev);
1472
1473         /* Get Device Attributes and features */
1474         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1475         if (rc) {
1476                 PMD_DRV_LOG(ERR,
1477                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1478                 goto err_admin_init;
1479         }
1480
1481         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1482                       BIT(ENA_ADMIN_NOTIFICATION) |
1483                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1484                       BIT(ENA_ADMIN_FATAL_ERROR) |
1485                       BIT(ENA_ADMIN_WARNING);
1486
1487         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1488
1489         adapter->all_aenq_groups = aenq_groups;
1490
1491         return 0;
1492
1493 err_admin_init:
1494         ena_com_admin_destroy(ena_dev);
1495
1496 err_mmio_read_less:
1497         ena_com_mmio_reg_read_request_destroy(ena_dev);
1498
1499         return rc;
1500 }
1501
1502 static void ena_interrupt_handler_rte(void *cb_arg)
1503 {
1504         struct rte_eth_dev *dev = cb_arg;
1505         struct ena_adapter *adapter = dev->data->dev_private;
1506         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1507
1508         ena_com_admin_q_comp_intr_handler(ena_dev);
1509         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1510                 ena_com_aenq_intr_handler(ena_dev, dev);
1511 }
1512
1513 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1514 {
1515         if (!(adapter->active_aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)))
1516                 return;
1517
1518         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1519                 return;
1520
1521         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1522             adapter->keep_alive_timeout)) {
1523                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1524                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1525                 adapter->trigger_reset = true;
1526                 ++adapter->dev_stats.wd_expired;
1527         }
1528 }
1529
1530 /* Check if admin queue is enabled */
1531 static void check_for_admin_com_state(struct ena_adapter *adapter)
1532 {
1533         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1534                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1535                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1536                 adapter->trigger_reset = true;
1537         }
1538 }
1539
1540 static int check_for_tx_completion_in_queue(struct ena_adapter *adapter,
1541                                             struct ena_ring *tx_ring)
1542 {
1543         struct ena_tx_buffer *tx_buf;
1544         uint64_t timestamp;
1545         uint64_t completion_delay;
1546         uint32_t missed_tx = 0;
1547         unsigned int i;
1548         int rc = 0;
1549
1550         for (i = 0; i < tx_ring->ring_size; ++i) {
1551                 tx_buf = &tx_ring->tx_buffer_info[i];
1552                 timestamp = tx_buf->timestamp;
1553
1554                 if (timestamp == 0)
1555                         continue;
1556
1557                 completion_delay = rte_get_timer_cycles() - timestamp;
1558                 if (completion_delay > adapter->missing_tx_completion_to) {
1559                         if (unlikely(!tx_buf->print_once)) {
1560                                 PMD_TX_LOG(WARNING,
1561                                         "Found a Tx that wasn't completed on time, qid %d, index %d. "
1562                                         "Missing Tx outstanding for %" PRIu64 " msecs.\n",
1563                                         tx_ring->id, i, completion_delay /
1564                                         rte_get_timer_hz() * 1000);
1565                                 tx_buf->print_once = true;
1566                         }
1567                         ++missed_tx;
1568                 }
1569         }
1570
1571         if (unlikely(missed_tx > tx_ring->missing_tx_completion_threshold)) {
1572                 PMD_DRV_LOG(ERR,
1573                         "The number of lost Tx completions is above the threshold (%d > %d). "
1574                         "Trigger the device reset.\n",
1575                         missed_tx,
1576                         tx_ring->missing_tx_completion_threshold);
1577                 adapter->reset_reason = ENA_REGS_RESET_MISS_TX_CMPL;
1578                 adapter->trigger_reset = true;
1579                 rc = -EIO;
1580         }
1581
1582         tx_ring->tx_stats.missed_tx += missed_tx;
1583
1584         return rc;
1585 }
1586
1587 static void check_for_tx_completions(struct ena_adapter *adapter)
1588 {
1589         struct ena_ring *tx_ring;
1590         uint64_t tx_cleanup_delay;
1591         size_t qid;
1592         int budget;
1593         uint16_t nb_tx_queues = adapter->edev_data->nb_tx_queues;
1594
1595         if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
1596                 return;
1597
1598         nb_tx_queues = adapter->edev_data->nb_tx_queues;
1599         budget = adapter->missing_tx_completion_budget;
1600
1601         qid = adapter->last_tx_comp_qid;
1602         while (budget-- > 0) {
1603                 tx_ring = &adapter->tx_ring[qid];
1604
1605                 /* Tx cleanup is called only by the burst function and can be
1606                  * called dynamically by the application. Also cleanup is
1607                  * limited by the threshold. To avoid false detection of the
1608                  * missing HW Tx completion, get the delay since last cleanup
1609                  * function was called.
1610                  */
1611                 tx_cleanup_delay = rte_get_timer_cycles() -
1612                         tx_ring->last_cleanup_ticks;
1613                 if (tx_cleanup_delay < adapter->tx_cleanup_stall_delay)
1614                         check_for_tx_completion_in_queue(adapter, tx_ring);
1615                 qid = (qid + 1) % nb_tx_queues;
1616         }
1617
1618         adapter->last_tx_comp_qid = qid;
1619 }
1620
1621 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1622                                   void *arg)
1623 {
1624         struct rte_eth_dev *dev = arg;
1625         struct ena_adapter *adapter = dev->data->dev_private;
1626
1627         if (unlikely(adapter->trigger_reset))
1628                 return;
1629
1630         check_for_missing_keep_alive(adapter);
1631         check_for_admin_com_state(adapter);
1632         check_for_tx_completions(adapter);
1633
1634         if (unlikely(adapter->trigger_reset)) {
1635                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1636                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1637                         NULL);
1638         }
1639 }
1640
1641 static inline void
1642 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1643                                struct ena_admin_feature_llq_desc *llq,
1644                                bool use_large_llq_hdr)
1645 {
1646         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1647         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1648         llq_config->llq_num_decs_before_header =
1649                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1650
1651         if (use_large_llq_hdr &&
1652             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1653                 llq_config->llq_ring_entry_size =
1654                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1655                 llq_config->llq_ring_entry_size_value = 256;
1656         } else {
1657                 llq_config->llq_ring_entry_size =
1658                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1659                 llq_config->llq_ring_entry_size_value = 128;
1660         }
1661 }
1662
1663 static int
1664 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1665                                 struct ena_com_dev *ena_dev,
1666                                 struct ena_admin_feature_llq_desc *llq,
1667                                 struct ena_llq_configurations *llq_default_configurations)
1668 {
1669         int rc;
1670         u32 llq_feature_mask;
1671
1672         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1673         if (!(ena_dev->supported_features & llq_feature_mask)) {
1674                 PMD_DRV_LOG(INFO,
1675                         "LLQ is not supported. Fallback to host mode policy.\n");
1676                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1677                 return 0;
1678         }
1679
1680         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1681         if (unlikely(rc)) {
1682                 PMD_INIT_LOG(WARNING,
1683                         "Failed to config dev mode. Fallback to host mode policy.\n");
1684                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1685                 return 0;
1686         }
1687
1688         /* Nothing to config, exit */
1689         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1690                 return 0;
1691
1692         if (!adapter->dev_mem_base) {
1693                 PMD_DRV_LOG(ERR,
1694                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1695                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1696                 return 0;
1697         }
1698
1699         ena_dev->mem_bar = adapter->dev_mem_base;
1700
1701         return 0;
1702 }
1703
1704 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1705         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1706 {
1707         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1708
1709         /* Regular queues capabilities */
1710         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1711                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1712                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1713                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1714                                     max_queue_ext->max_rx_cq_num);
1715                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1716                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1717         } else {
1718                 struct ena_admin_queue_feature_desc *max_queues =
1719                         &get_feat_ctx->max_queues;
1720                 io_tx_sq_num = max_queues->max_sq_num;
1721                 io_tx_cq_num = max_queues->max_cq_num;
1722                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1723         }
1724
1725         /* In case of LLQ use the llq number in the get feature cmd */
1726         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1727                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1728
1729         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1730         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1731         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1732
1733         if (unlikely(max_num_io_queues == 0)) {
1734                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1735                 return -EFAULT;
1736         }
1737
1738         return max_num_io_queues;
1739 }
1740
1741 static void
1742 ena_set_offloads(struct ena_offloads *offloads,
1743                  struct ena_admin_feature_offload_desc *offload_desc)
1744 {
1745         if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1746                 offloads->tx_offloads |= ENA_IPV4_TSO;
1747
1748         /* Tx IPv4 checksum offloads */
1749         if (offload_desc->tx &
1750             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
1751                 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
1752         if (offload_desc->tx &
1753             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
1754                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
1755         if (offload_desc->tx &
1756             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1757                 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
1758
1759         /* Tx IPv6 checksum offloads */
1760         if (offload_desc->tx &
1761             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
1762                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
1763         if (offload_desc->tx &
1764              ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
1765                 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
1766
1767         /* Rx IPv4 checksum offloads */
1768         if (offload_desc->rx_supported &
1769             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
1770                 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
1771         if (offload_desc->rx_supported &
1772             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1773                 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
1774
1775         /* Rx IPv6 checksum offloads */
1776         if (offload_desc->rx_supported &
1777             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
1778                 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
1779
1780         if (offload_desc->rx_supported &
1781             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
1782                 offloads->rx_offloads |= ENA_RX_RSS_HASH;
1783 }
1784
1785 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1786 {
1787         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1788         struct rte_pci_device *pci_dev;
1789         struct rte_intr_handle *intr_handle;
1790         struct ena_adapter *adapter = eth_dev->data->dev_private;
1791         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1792         struct ena_com_dev_get_features_ctx get_feat_ctx;
1793         struct ena_llq_configurations llq_config;
1794         const char *queue_type_str;
1795         uint32_t max_num_io_queues;
1796         int rc;
1797         static int adapters_found;
1798         bool disable_meta_caching;
1799
1800         eth_dev->dev_ops = &ena_dev_ops;
1801         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1802         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1803         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1804
1805         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1806                 return 0;
1807
1808         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1809
1810         memset(adapter, 0, sizeof(struct ena_adapter));
1811         ena_dev = &adapter->ena_dev;
1812
1813         adapter->edev_data = eth_dev->data;
1814
1815         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1816
1817         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1818                      pci_dev->addr.domain,
1819                      pci_dev->addr.bus,
1820                      pci_dev->addr.devid,
1821                      pci_dev->addr.function);
1822
1823         intr_handle = pci_dev->intr_handle;
1824
1825         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1826         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1827
1828         if (!adapter->regs) {
1829                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1830                              ENA_REGS_BAR);
1831                 return -ENXIO;
1832         }
1833
1834         ena_dev->reg_bar = adapter->regs;
1835         /* This is a dummy pointer for ena_com functions. */
1836         ena_dev->dmadev = adapter;
1837
1838         adapter->id_number = adapters_found;
1839
1840         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1841                  adapter->id_number);
1842
1843         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1844         if (rc != 0) {
1845                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1846                 goto err;
1847         }
1848
1849         /* device specific initialization routine */
1850         rc = ena_device_init(adapter, pci_dev, &get_feat_ctx);
1851         if (rc) {
1852                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1853                 goto err;
1854         }
1855
1856         /* Check if device supports LSC */
1857         if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE)))
1858                 adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1859
1860         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1861                 adapter->use_large_llq_hdr);
1862         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1863                                              &get_feat_ctx.llq, &llq_config);
1864         if (unlikely(rc)) {
1865                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1866                 return rc;
1867         }
1868
1869         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1870                 queue_type_str = "Regular";
1871         else
1872                 queue_type_str = "Low latency";
1873         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1874
1875         calc_queue_ctx.ena_dev = ena_dev;
1876         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1877
1878         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1879         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1880                 adapter->use_large_llq_hdr);
1881         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1882                 rc = -EFAULT;
1883                 goto err_device_destroy;
1884         }
1885
1886         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1887         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1888         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1889         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1890         adapter->max_num_io_queues = max_num_io_queues;
1891
1892         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1893                 disable_meta_caching =
1894                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1895                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1896         } else {
1897                 disable_meta_caching = false;
1898         }
1899
1900         /* prepare ring structures */
1901         ena_init_rings(adapter, disable_meta_caching);
1902
1903         ena_config_debug_area(adapter);
1904
1905         /* Set max MTU for this device */
1906         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1907
1908         ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
1909
1910         /* Copy MAC address and point DPDK to it */
1911         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1912         rte_ether_addr_copy((struct rte_ether_addr *)
1913                         get_feat_ctx.dev_attr.mac_addr,
1914                         (struct rte_ether_addr *)adapter->mac_addr);
1915
1916         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1917         if (unlikely(rc != 0)) {
1918                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1919                 goto err_delete_debug_area;
1920         }
1921
1922         adapter->drv_stats = rte_zmalloc("adapter stats",
1923                                          sizeof(*adapter->drv_stats),
1924                                          RTE_CACHE_LINE_SIZE);
1925         if (!adapter->drv_stats) {
1926                 PMD_DRV_LOG(ERR,
1927                         "Failed to allocate memory for adapter statistics\n");
1928                 rc = -ENOMEM;
1929                 goto err_rss_destroy;
1930         }
1931
1932         rte_spinlock_init(&adapter->admin_lock);
1933
1934         rte_intr_callback_register(intr_handle,
1935                                    ena_interrupt_handler_rte,
1936                                    eth_dev);
1937         rte_intr_enable(intr_handle);
1938         ena_com_set_admin_polling_mode(ena_dev, false);
1939         ena_com_admin_aenq_enable(ena_dev);
1940
1941         if (adapters_found == 0)
1942                 rte_timer_subsystem_init();
1943         rte_timer_init(&adapter->timer_wd);
1944
1945         adapters_found++;
1946         adapter->state = ENA_ADAPTER_STATE_INIT;
1947
1948         return 0;
1949
1950 err_rss_destroy:
1951         ena_com_rss_destroy(ena_dev);
1952 err_delete_debug_area:
1953         ena_com_delete_debug_area(ena_dev);
1954
1955 err_device_destroy:
1956         ena_com_delete_host_info(ena_dev);
1957         ena_com_admin_destroy(ena_dev);
1958
1959 err:
1960         return rc;
1961 }
1962
1963 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1964 {
1965         struct ena_adapter *adapter = eth_dev->data->dev_private;
1966         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1967
1968         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1969                 return;
1970
1971         ena_com_set_admin_running_state(ena_dev, false);
1972
1973         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1974                 ena_close(eth_dev);
1975
1976         ena_com_rss_destroy(ena_dev);
1977
1978         ena_com_delete_debug_area(ena_dev);
1979         ena_com_delete_host_info(ena_dev);
1980
1981         ena_com_abort_admin_commands(ena_dev);
1982         ena_com_wait_for_abort_completion(ena_dev);
1983         ena_com_admin_destroy(ena_dev);
1984         ena_com_mmio_reg_read_request_destroy(ena_dev);
1985
1986         adapter->state = ENA_ADAPTER_STATE_FREE;
1987 }
1988
1989 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1990 {
1991         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1992                 return 0;
1993
1994         ena_destroy_device(eth_dev);
1995
1996         return 0;
1997 }
1998
1999 static int ena_dev_configure(struct rte_eth_dev *dev)
2000 {
2001         struct ena_adapter *adapter = dev->data->dev_private;
2002         int rc;
2003
2004         adapter->state = ENA_ADAPTER_STATE_CONFIG;
2005
2006         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2007                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2008         dev->data->dev_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2009
2010         /* Scattered Rx cannot be turned off in the HW, so this capability must
2011          * be forced.
2012          */
2013         dev->data->scattered_rx = 1;
2014
2015         adapter->last_tx_comp_qid = 0;
2016
2017         adapter->missing_tx_completion_budget =
2018                 RTE_MIN(ENA_MONITORED_TX_QUEUES, dev->data->nb_tx_queues);
2019
2020         adapter->missing_tx_completion_to = ENA_TX_TIMEOUT;
2021         /* To avoid detection of the spurious Tx completion timeout due to
2022          * application not calling the Tx cleanup function, set timeout for the
2023          * Tx queue which should be half of the missing completion timeout for a
2024          * safety. If there will be a lot of missing Tx completions in the
2025          * queue, they will be detected sooner or later.
2026          */
2027         adapter->tx_cleanup_stall_delay = adapter->missing_tx_completion_to / 2;
2028
2029         rc = ena_configure_aenq(adapter);
2030
2031         return rc;
2032 }
2033
2034 static void ena_init_rings(struct ena_adapter *adapter,
2035                            bool disable_meta_caching)
2036 {
2037         size_t i;
2038
2039         for (i = 0; i < adapter->max_num_io_queues; i++) {
2040                 struct ena_ring *ring = &adapter->tx_ring[i];
2041
2042                 ring->configured = 0;
2043                 ring->type = ENA_RING_TYPE_TX;
2044                 ring->adapter = adapter;
2045                 ring->id = i;
2046                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
2047                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
2048                 ring->sgl_size = adapter->max_tx_sgl_size;
2049                 ring->disable_meta_caching = disable_meta_caching;
2050         }
2051
2052         for (i = 0; i < adapter->max_num_io_queues; i++) {
2053                 struct ena_ring *ring = &adapter->rx_ring[i];
2054
2055                 ring->configured = 0;
2056                 ring->type = ENA_RING_TYPE_RX;
2057                 ring->adapter = adapter;
2058                 ring->id = i;
2059                 ring->sgl_size = adapter->max_rx_sgl_size;
2060         }
2061 }
2062
2063 static uint64_t ena_get_rx_port_offloads(struct ena_adapter *adapter)
2064 {
2065         uint64_t port_offloads = 0;
2066
2067         if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
2068                 port_offloads |= RTE_ETH_RX_OFFLOAD_IPV4_CKSUM;
2069
2070         if (adapter->offloads.rx_offloads &
2071             (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
2072                 port_offloads |=
2073                         RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM;
2074
2075         if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
2076                 port_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2077
2078         port_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;
2079
2080         return port_offloads;
2081 }
2082
2083 static uint64_t ena_get_tx_port_offloads(struct ena_adapter *adapter)
2084 {
2085         uint64_t port_offloads = 0;
2086
2087         if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
2088                 port_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO;
2089
2090         if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
2091                 port_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM;
2092         if (adapter->offloads.tx_offloads &
2093             (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
2094              ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
2095                 port_offloads |=
2096                         RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
2097
2098         port_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
2099
2100         return port_offloads;
2101 }
2102
2103 static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter)
2104 {
2105         RTE_SET_USED(adapter);
2106
2107         return 0;
2108 }
2109
2110 static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter)
2111 {
2112         RTE_SET_USED(adapter);
2113
2114         return 0;
2115 }
2116
2117 static int ena_infos_get(struct rte_eth_dev *dev,
2118                           struct rte_eth_dev_info *dev_info)
2119 {
2120         struct ena_adapter *adapter;
2121         struct ena_com_dev *ena_dev;
2122
2123         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2124         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2125         adapter = dev->data->dev_private;
2126
2127         ena_dev = &adapter->ena_dev;
2128         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2129
2130         dev_info->speed_capa =
2131                         RTE_ETH_LINK_SPEED_1G   |
2132                         RTE_ETH_LINK_SPEED_2_5G |
2133                         RTE_ETH_LINK_SPEED_5G   |
2134                         RTE_ETH_LINK_SPEED_10G  |
2135                         RTE_ETH_LINK_SPEED_25G  |
2136                         RTE_ETH_LINK_SPEED_40G  |
2137                         RTE_ETH_LINK_SPEED_50G  |
2138                         RTE_ETH_LINK_SPEED_100G;
2139
2140         /* Inform framework about available features */
2141         dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter);
2142         dev_info->tx_offload_capa = ena_get_tx_port_offloads(adapter);
2143         dev_info->rx_queue_offload_capa = ena_get_rx_queue_offloads(adapter);
2144         dev_info->tx_queue_offload_capa = ena_get_tx_queue_offloads(adapter);
2145
2146         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2147         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2148
2149         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2150         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2151                 RTE_ETHER_CRC_LEN;
2152         dev_info->min_mtu = ENA_MIN_MTU;
2153         dev_info->max_mtu = adapter->max_mtu;
2154         dev_info->max_mac_addrs = 1;
2155
2156         dev_info->max_rx_queues = adapter->max_num_io_queues;
2157         dev_info->max_tx_queues = adapter->max_num_io_queues;
2158         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2159
2160         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2161         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2162         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2163                                         adapter->max_rx_sgl_size);
2164         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2165                                         adapter->max_rx_sgl_size);
2166
2167         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2168         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2169         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2170                                         adapter->max_tx_sgl_size);
2171         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2172                                         adapter->max_tx_sgl_size);
2173
2174         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2175         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2176
2177         return 0;
2178 }
2179
2180 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2181 {
2182         mbuf->data_len = len;
2183         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2184         mbuf->refcnt = 1;
2185         mbuf->next = NULL;
2186 }
2187
2188 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2189                                     struct ena_com_rx_buf_info *ena_bufs,
2190                                     uint32_t descs,
2191                                     uint16_t *next_to_clean,
2192                                     uint8_t offset)
2193 {
2194         struct rte_mbuf *mbuf;
2195         struct rte_mbuf *mbuf_head;
2196         struct ena_rx_buffer *rx_info;
2197         int rc;
2198         uint16_t ntc, len, req_id, buf = 0;
2199
2200         if (unlikely(descs == 0))
2201                 return NULL;
2202
2203         ntc = *next_to_clean;
2204
2205         len = ena_bufs[buf].len;
2206         req_id = ena_bufs[buf].req_id;
2207
2208         rx_info = &rx_ring->rx_buffer_info[req_id];
2209
2210         mbuf = rx_info->mbuf;
2211         RTE_ASSERT(mbuf != NULL);
2212
2213         ena_init_rx_mbuf(mbuf, len);
2214
2215         /* Fill the mbuf head with the data specific for 1st segment. */
2216         mbuf_head = mbuf;
2217         mbuf_head->nb_segs = descs;
2218         mbuf_head->port = rx_ring->port_id;
2219         mbuf_head->pkt_len = len;
2220         mbuf_head->data_off += offset;
2221
2222         rx_info->mbuf = NULL;
2223         rx_ring->empty_rx_reqs[ntc] = req_id;
2224         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2225
2226         while (--descs) {
2227                 ++buf;
2228                 len = ena_bufs[buf].len;
2229                 req_id = ena_bufs[buf].req_id;
2230
2231                 rx_info = &rx_ring->rx_buffer_info[req_id];
2232                 RTE_ASSERT(rx_info->mbuf != NULL);
2233
2234                 if (unlikely(len == 0)) {
2235                         /*
2236                          * Some devices can pass descriptor with the length 0.
2237                          * To avoid confusion, the PMD is simply putting the
2238                          * descriptor back, as it was never used. We'll avoid
2239                          * mbuf allocation that way.
2240                          */
2241                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2242                                 rx_info->mbuf, req_id);
2243                         if (unlikely(rc != 0)) {
2244                                 /* Free the mbuf in case of an error. */
2245                                 rte_mbuf_raw_free(rx_info->mbuf);
2246                         } else {
2247                                 /*
2248                                  * If there was no error, just exit the loop as
2249                                  * 0 length descriptor is always the last one.
2250                                  */
2251                                 break;
2252                         }
2253                 } else {
2254                         /* Create an mbuf chain. */
2255                         mbuf->next = rx_info->mbuf;
2256                         mbuf = mbuf->next;
2257
2258                         ena_init_rx_mbuf(mbuf, len);
2259                         mbuf_head->pkt_len += len;
2260                 }
2261
2262                 /*
2263                  * Mark the descriptor as depleted and perform necessary
2264                  * cleanup.
2265                  * This code will execute in two cases:
2266                  *  1. Descriptor len was greater than 0 - normal situation.
2267                  *  2. Descriptor len was 0 and we failed to add the descriptor
2268                  *     to the device. In that situation, we should try to add
2269                  *     the mbuf again in the populate routine and mark the
2270                  *     descriptor as used up by the device.
2271                  */
2272                 rx_info->mbuf = NULL;
2273                 rx_ring->empty_rx_reqs[ntc] = req_id;
2274                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2275         }
2276
2277         *next_to_clean = ntc;
2278
2279         return mbuf_head;
2280 }
2281
2282 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2283                                   uint16_t nb_pkts)
2284 {
2285         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2286         unsigned int free_queue_entries;
2287         uint16_t next_to_clean = rx_ring->next_to_clean;
2288         uint16_t descs_in_use;
2289         struct rte_mbuf *mbuf;
2290         uint16_t completed;
2291         struct ena_com_rx_ctx ena_rx_ctx;
2292         int i, rc = 0;
2293         bool fill_hash;
2294
2295 #ifdef RTE_ETHDEV_DEBUG_RX
2296         /* Check adapter state */
2297         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2298                 PMD_RX_LOG(ALERT,
2299                         "Trying to receive pkts while device is NOT running\n");
2300                 return 0;
2301         }
2302 #endif
2303
2304         fill_hash = rx_ring->offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH;
2305
2306         descs_in_use = rx_ring->ring_size -
2307                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2308         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2309
2310         for (completed = 0; completed < nb_pkts; completed++) {
2311                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2312                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2313                 ena_rx_ctx.descs = 0;
2314                 ena_rx_ctx.pkt_offset = 0;
2315                 /* receive packet context */
2316                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2317                                     rx_ring->ena_com_io_sq,
2318                                     &ena_rx_ctx);
2319                 if (unlikely(rc)) {
2320                         PMD_RX_LOG(ERR,
2321                                 "Failed to get the packet from the device, rc: %d\n",
2322                                 rc);
2323                         if (rc == ENA_COM_NO_SPACE) {
2324                                 ++rx_ring->rx_stats.bad_desc_num;
2325                                 rx_ring->adapter->reset_reason =
2326                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2327                         } else {
2328                                 ++rx_ring->rx_stats.bad_req_id;
2329                                 rx_ring->adapter->reset_reason =
2330                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2331                         }
2332                         rx_ring->adapter->trigger_reset = true;
2333                         return 0;
2334                 }
2335
2336                 mbuf = ena_rx_mbuf(rx_ring,
2337                         ena_rx_ctx.ena_bufs,
2338                         ena_rx_ctx.descs,
2339                         &next_to_clean,
2340                         ena_rx_ctx.pkt_offset);
2341                 if (unlikely(mbuf == NULL)) {
2342                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2343                                 rx_ring->empty_rx_reqs[next_to_clean] =
2344                                         rx_ring->ena_bufs[i].req_id;
2345                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2346                                         next_to_clean, rx_ring->size_mask);
2347                         }
2348                         break;
2349                 }
2350
2351                 /* fill mbuf attributes if any */
2352                 ena_rx_mbuf_prepare(rx_ring, mbuf, &ena_rx_ctx, fill_hash);
2353
2354                 if (unlikely(mbuf->ol_flags &
2355                                 (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD)))
2356                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2357
2358                 rx_pkts[completed] = mbuf;
2359                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2360         }
2361
2362         rx_ring->rx_stats.cnt += completed;
2363         rx_ring->next_to_clean = next_to_clean;
2364
2365         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2366
2367         /* Burst refill to save doorbells, memory barriers, const interval */
2368         if (free_queue_entries >= rx_ring->rx_free_thresh) {
2369                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2370                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2371         }
2372
2373         return completed;
2374 }
2375
2376 static uint16_t
2377 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2378                 uint16_t nb_pkts)
2379 {
2380         int32_t ret;
2381         uint32_t i;
2382         struct rte_mbuf *m;
2383         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2384         struct ena_adapter *adapter = tx_ring->adapter;
2385         struct rte_ipv4_hdr *ip_hdr;
2386         uint64_t ol_flags;
2387         uint64_t l4_csum_flag;
2388         uint64_t dev_offload_capa;
2389         uint16_t frag_field;
2390         bool need_pseudo_csum;
2391
2392         dev_offload_capa = adapter->offloads.tx_offloads;
2393         for (i = 0; i != nb_pkts; i++) {
2394                 m = tx_pkts[i];
2395                 ol_flags = m->ol_flags;
2396
2397                 /* Check if any offload flag was set */
2398                 if (ol_flags == 0)
2399                         continue;
2400
2401                 l4_csum_flag = ol_flags & RTE_MBUF_F_TX_L4_MASK;
2402                 /* SCTP checksum offload is not supported by the ENA. */
2403                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2404                     l4_csum_flag == RTE_MBUF_F_TX_SCTP_CKSUM) {
2405                         PMD_TX_LOG(DEBUG,
2406                                 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2407                                 i, ol_flags);
2408                         rte_errno = ENOTSUP;
2409                         return i;
2410                 }
2411
2412                 if (unlikely(m->nb_segs >= tx_ring->sgl_size &&
2413                     !(tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2414                       m->nb_segs == tx_ring->sgl_size &&
2415                       m->data_len < tx_ring->tx_max_header_size))) {
2416                         PMD_TX_LOG(DEBUG,
2417                                 "mbuf[%" PRIu32 "] has too many segments: %" PRIu16 "\n",
2418                                 i, m->nb_segs);
2419                         rte_errno = EINVAL;
2420                         return i;
2421                 }
2422
2423 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2424                 /* Check if requested offload is also enabled for the queue */
2425                 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2426                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)) ||
2427                     (l4_csum_flag == RTE_MBUF_F_TX_TCP_CKSUM &&
2428                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM)) ||
2429                     (l4_csum_flag == RTE_MBUF_F_TX_UDP_CKSUM &&
2430                      !(tx_ring->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM))) {
2431                         PMD_TX_LOG(DEBUG,
2432                                 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2433                                 i, m->nb_segs, tx_ring->id);
2434                         rte_errno = EINVAL;
2435                         return i;
2436                 }
2437
2438                 /* The caller is obligated to set l2 and l3 len if any cksum
2439                  * offload is enabled.
2440                  */
2441                 if (unlikely(ol_flags & (RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_L4_MASK) &&
2442                     (m->l2_len == 0 || m->l3_len == 0))) {
2443                         PMD_TX_LOG(DEBUG,
2444                                 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2445                                 i);
2446                         rte_errno = EINVAL;
2447                         return i;
2448                 }
2449                 ret = rte_validate_tx_offload(m);
2450                 if (ret != 0) {
2451                         rte_errno = -ret;
2452                         return i;
2453                 }
2454 #endif
2455
2456                 /* Verify HW support for requested offloads and determine if
2457                  * pseudo header checksum is needed.
2458                  */
2459                 need_pseudo_csum = false;
2460                 if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2461                         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM &&
2462                             !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2463                                 rte_errno = ENOTSUP;
2464                                 return i;
2465                         }
2466
2467                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
2468                             !(dev_offload_capa & ENA_IPV4_TSO)) {
2469                                 rte_errno = ENOTSUP;
2470                                 return i;
2471                         }
2472
2473                         /* Check HW capabilities and if pseudo csum is needed
2474                          * for L4 offloads.
2475                          */
2476                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2477                             !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2478                                 if (dev_offload_capa &
2479                                     ENA_L4_IPV4_CSUM_PARTIAL) {
2480                                         need_pseudo_csum = true;
2481                                 } else {
2482                                         rte_errno = ENOTSUP;
2483                                         return i;
2484                                 }
2485                         }
2486
2487                         /* Parse the DF flag */
2488                         ip_hdr = rte_pktmbuf_mtod_offset(m,
2489                                 struct rte_ipv4_hdr *, m->l2_len);
2490                         frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2491                         if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2492                                 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2493                         } else if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2494                                 /* In case we are supposed to TSO and have DF
2495                                  * not set (DF=0) hardware must be provided with
2496                                  * partial checksum.
2497                                  */
2498                                 need_pseudo_csum = true;
2499                         }
2500                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2501                         /* There is no support for IPv6 TSO as for now. */
2502                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2503                                 rte_errno = ENOTSUP;
2504                                 return i;
2505                         }
2506
2507                         /* Check HW capabilities and if pseudo csum is needed */
2508                         if (l4_csum_flag != RTE_MBUF_F_TX_L4_NO_CKSUM &&
2509                             !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2510                                 if (dev_offload_capa &
2511                                     ENA_L4_IPV6_CSUM_PARTIAL) {
2512                                         need_pseudo_csum = true;
2513                                 } else {
2514                                         rte_errno = ENOTSUP;
2515                                         return i;
2516                                 }
2517                         }
2518                 }
2519
2520                 if (need_pseudo_csum) {
2521                         ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2522                         if (ret != 0) {
2523                                 rte_errno = -ret;
2524                                 return i;
2525                         }
2526                 }
2527         }
2528
2529         return i;
2530 }
2531
2532 static void ena_update_hints(struct ena_adapter *adapter,
2533                              struct ena_admin_ena_hw_hints *hints)
2534 {
2535         if (hints->admin_completion_tx_timeout)
2536                 adapter->ena_dev.admin_queue.completion_timeout =
2537                         hints->admin_completion_tx_timeout * 1000;
2538
2539         if (hints->mmio_read_timeout)
2540                 /* convert to usec */
2541                 adapter->ena_dev.mmio_read.reg_read_to =
2542                         hints->mmio_read_timeout * 1000;
2543
2544         if (hints->missing_tx_completion_timeout) {
2545                 if (hints->missing_tx_completion_timeout ==
2546                     ENA_HW_HINTS_NO_TIMEOUT) {
2547                         adapter->missing_tx_completion_to =
2548                                 ENA_HW_HINTS_NO_TIMEOUT;
2549                 } else {
2550                         /* Convert from msecs to ticks */
2551                         adapter->missing_tx_completion_to = rte_get_timer_hz() *
2552                                 hints->missing_tx_completion_timeout / 1000;
2553                         adapter->tx_cleanup_stall_delay =
2554                                 adapter->missing_tx_completion_to / 2;
2555                 }
2556         }
2557
2558         if (hints->driver_watchdog_timeout) {
2559                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2560                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2561                 else
2562                         // Convert msecs to ticks
2563                         adapter->keep_alive_timeout =
2564                                 (hints->driver_watchdog_timeout *
2565                                 rte_get_timer_hz()) / 1000;
2566         }
2567 }
2568
2569 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2570         struct ena_tx_buffer *tx_info,
2571         struct rte_mbuf *mbuf,
2572         void **push_header,
2573         uint16_t *header_len)
2574 {
2575         struct ena_com_buf *ena_buf;
2576         uint16_t delta, seg_len, push_len;
2577
2578         delta = 0;
2579         seg_len = mbuf->data_len;
2580
2581         tx_info->mbuf = mbuf;
2582         ena_buf = tx_info->bufs;
2583
2584         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2585                 /*
2586                  * Tx header might be (and will be in most cases) smaller than
2587                  * tx_max_header_size. But it's not an issue to send more data
2588                  * to the device, than actually needed if the mbuf size is
2589                  * greater than tx_max_header_size.
2590                  */
2591                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2592                 *header_len = push_len;
2593
2594                 if (likely(push_len <= seg_len)) {
2595                         /* If the push header is in the single segment, then
2596                          * just point it to the 1st mbuf data.
2597                          */
2598                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2599                 } else {
2600                         /* If the push header lays in the several segments, copy
2601                          * it to the intermediate buffer.
2602                          */
2603                         rte_pktmbuf_read(mbuf, 0, push_len,
2604                                 tx_ring->push_buf_intermediate_buf);
2605                         *push_header = tx_ring->push_buf_intermediate_buf;
2606                         delta = push_len - seg_len;
2607                 }
2608         } else {
2609                 *push_header = NULL;
2610                 *header_len = 0;
2611                 push_len = 0;
2612         }
2613
2614         /* Process first segment taking into consideration pushed header */
2615         if (seg_len > push_len) {
2616                 ena_buf->paddr = mbuf->buf_iova +
2617                                 mbuf->data_off +
2618                                 push_len;
2619                 ena_buf->len = seg_len - push_len;
2620                 ena_buf++;
2621                 tx_info->num_of_bufs++;
2622         }
2623
2624         while ((mbuf = mbuf->next) != NULL) {
2625                 seg_len = mbuf->data_len;
2626
2627                 /* Skip mbufs if whole data is pushed as a header */
2628                 if (unlikely(delta > seg_len)) {
2629                         delta -= seg_len;
2630                         continue;
2631                 }
2632
2633                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2634                 ena_buf->len = seg_len - delta;
2635                 ena_buf++;
2636                 tx_info->num_of_bufs++;
2637
2638                 delta = 0;
2639         }
2640 }
2641
2642 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2643 {
2644         struct ena_tx_buffer *tx_info;
2645         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2646         uint16_t next_to_use;
2647         uint16_t header_len;
2648         uint16_t req_id;
2649         void *push_header;
2650         int nb_hw_desc;
2651         int rc;
2652
2653         /* Checking for space for 2 additional metadata descriptors due to
2654          * possible header split and metadata descriptor
2655          */
2656         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2657                                           mbuf->nb_segs + 2)) {
2658                 PMD_DRV_LOG(DEBUG, "Not enough space in the tx queue\n");
2659                 return ENA_COM_NO_MEM;
2660         }
2661
2662         next_to_use = tx_ring->next_to_use;
2663
2664         req_id = tx_ring->empty_tx_reqs[next_to_use];
2665         tx_info = &tx_ring->tx_buffer_info[req_id];
2666         tx_info->num_of_bufs = 0;
2667         RTE_ASSERT(tx_info->mbuf == NULL);
2668
2669         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2670
2671         ena_tx_ctx.ena_bufs = tx_info->bufs;
2672         ena_tx_ctx.push_header = push_header;
2673         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2674         ena_tx_ctx.req_id = req_id;
2675         ena_tx_ctx.header_len = header_len;
2676
2677         /* Set Tx offloads flags, if applicable */
2678         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2679                 tx_ring->disable_meta_caching);
2680
2681         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2682                         &ena_tx_ctx))) {
2683                 PMD_TX_LOG(DEBUG,
2684                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2685                         tx_ring->id);
2686                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2687                 tx_ring->tx_stats.doorbells++;
2688                 tx_ring->pkts_without_db = false;
2689         }
2690
2691         /* prepare the packet's descriptors to dma engine */
2692         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2693                 &nb_hw_desc);
2694         if (unlikely(rc)) {
2695                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2696                 ++tx_ring->tx_stats.prepare_ctx_err;
2697                 tx_ring->adapter->reset_reason =
2698                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2699                 tx_ring->adapter->trigger_reset = true;
2700                 return rc;
2701         }
2702
2703         tx_info->tx_descs = nb_hw_desc;
2704         tx_info->timestamp = rte_get_timer_cycles();
2705
2706         tx_ring->tx_stats.cnt++;
2707         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2708
2709         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2710                 tx_ring->size_mask);
2711
2712         return 0;
2713 }
2714
2715 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2716 {
2717         unsigned int total_tx_descs = 0;
2718         uint16_t cleanup_budget;
2719         uint16_t next_to_clean = tx_ring->next_to_clean;
2720
2721         /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
2722         cleanup_budget = tx_ring->size_mask;
2723
2724         while (likely(total_tx_descs < cleanup_budget)) {
2725                 struct rte_mbuf *mbuf;
2726                 struct ena_tx_buffer *tx_info;
2727                 uint16_t req_id;
2728
2729                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2730                         break;
2731
2732                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2733                         break;
2734
2735                 /* Get Tx info & store how many descs were processed  */
2736                 tx_info = &tx_ring->tx_buffer_info[req_id];
2737                 tx_info->timestamp = 0;
2738
2739                 mbuf = tx_info->mbuf;
2740                 rte_pktmbuf_free(mbuf);
2741
2742                 tx_info->mbuf = NULL;
2743                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2744
2745                 total_tx_descs += tx_info->tx_descs;
2746
2747                 /* Put back descriptor to the ring for reuse */
2748                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2749                         tx_ring->size_mask);
2750         }
2751
2752         if (likely(total_tx_descs > 0)) {
2753                 /* acknowledge completion of sent packets */
2754                 tx_ring->next_to_clean = next_to_clean;
2755                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2756                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2757         }
2758
2759         /* Notify completion handler that the cleanup was just called */
2760         tx_ring->last_cleanup_ticks = rte_get_timer_cycles();
2761 }
2762
2763 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2764                                   uint16_t nb_pkts)
2765 {
2766         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2767         int available_desc;
2768         uint16_t sent_idx = 0;
2769
2770 #ifdef RTE_ETHDEV_DEBUG_TX
2771         /* Check adapter state */
2772         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2773                 PMD_TX_LOG(ALERT,
2774                         "Trying to xmit pkts while device is NOT running\n");
2775                 return 0;
2776         }
2777 #endif
2778
2779         available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2780         if (available_desc < tx_ring->tx_free_thresh)
2781                 ena_tx_cleanup(tx_ring);
2782
2783         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2784                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2785                         break;
2786                 tx_ring->pkts_without_db = true;
2787                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2788                         tx_ring->size_mask)]);
2789         }
2790
2791         /* If there are ready packets to be xmitted... */
2792         if (likely(tx_ring->pkts_without_db)) {
2793                 /* ...let HW do its best :-) */
2794                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2795                 tx_ring->tx_stats.doorbells++;
2796                 tx_ring->pkts_without_db = false;
2797         }
2798
2799         tx_ring->tx_stats.available_desc =
2800                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2801         tx_ring->tx_stats.tx_poll++;
2802
2803         return sent_idx;
2804 }
2805
2806 int ena_copy_eni_stats(struct ena_adapter *adapter)
2807 {
2808         struct ena_admin_eni_stats admin_eni_stats;
2809         int rc;
2810
2811         rte_spinlock_lock(&adapter->admin_lock);
2812         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2813         rte_spinlock_unlock(&adapter->admin_lock);
2814         if (rc != 0) {
2815                 if (rc == ENA_COM_UNSUPPORTED) {
2816                         PMD_DRV_LOG(DEBUG,
2817                                 "Retrieving ENI metrics is not supported\n");
2818                 } else {
2819                         PMD_DRV_LOG(WARNING,
2820                                 "Failed to get ENI metrics, rc: %d\n", rc);
2821                 }
2822                 return rc;
2823         }
2824
2825         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2826                 sizeof(struct ena_stats_eni));
2827
2828         return 0;
2829 }
2830
2831 /**
2832  * DPDK callback to retrieve names of extended device statistics
2833  *
2834  * @param dev
2835  *   Pointer to Ethernet device structure.
2836  * @param[out] xstats_names
2837  *   Buffer to insert names into.
2838  * @param n
2839  *   Number of names.
2840  *
2841  * @return
2842  *   Number of xstats names.
2843  */
2844 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2845                                 struct rte_eth_xstat_name *xstats_names,
2846                                 unsigned int n)
2847 {
2848         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2849         unsigned int stat, i, count = 0;
2850
2851         if (n < xstats_count || !xstats_names)
2852                 return xstats_count;
2853
2854         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2855                 strcpy(xstats_names[count].name,
2856                         ena_stats_global_strings[stat].name);
2857
2858         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2859                 strcpy(xstats_names[count].name,
2860                         ena_stats_eni_strings[stat].name);
2861
2862         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2863                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2864                         snprintf(xstats_names[count].name,
2865                                 sizeof(xstats_names[count].name),
2866                                 "rx_q%d_%s", i,
2867                                 ena_stats_rx_strings[stat].name);
2868
2869         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2870                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2871                         snprintf(xstats_names[count].name,
2872                                 sizeof(xstats_names[count].name),
2873                                 "tx_q%d_%s", i,
2874                                 ena_stats_tx_strings[stat].name);
2875
2876         return xstats_count;
2877 }
2878
2879 /**
2880  * DPDK callback to get extended device statistics.
2881  *
2882  * @param dev
2883  *   Pointer to Ethernet device structure.
2884  * @param[out] stats
2885  *   Stats table output buffer.
2886  * @param n
2887  *   The size of the stats table.
2888  *
2889  * @return
2890  *   Number of xstats on success, negative on failure.
2891  */
2892 static int ena_xstats_get(struct rte_eth_dev *dev,
2893                           struct rte_eth_xstat *xstats,
2894                           unsigned int n)
2895 {
2896         struct ena_adapter *adapter = dev->data->dev_private;
2897         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2898         unsigned int stat, i, count = 0;
2899         int stat_offset;
2900         void *stats_begin;
2901
2902         if (n < xstats_count)
2903                 return xstats_count;
2904
2905         if (!xstats)
2906                 return 0;
2907
2908         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2909                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2910                 stats_begin = &adapter->dev_stats;
2911
2912                 xstats[count].id = count;
2913                 xstats[count].value = *((uint64_t *)
2914                         ((char *)stats_begin + stat_offset));
2915         }
2916
2917         /* Even if the function below fails, we should copy previous (or initial
2918          * values) to keep structure of rte_eth_xstat consistent.
2919          */
2920         ena_copy_eni_stats(adapter);
2921         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2922                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2923                 stats_begin = &adapter->eni_stats;
2924
2925                 xstats[count].id = count;
2926                 xstats[count].value = *((uint64_t *)
2927                     ((char *)stats_begin + stat_offset));
2928         }
2929
2930         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2931                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2932                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2933                         stats_begin = &adapter->rx_ring[i].rx_stats;
2934
2935                         xstats[count].id = count;
2936                         xstats[count].value = *((uint64_t *)
2937                                 ((char *)stats_begin + stat_offset));
2938                 }
2939         }
2940
2941         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2942                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2943                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2944                         stats_begin = &adapter->tx_ring[i].rx_stats;
2945
2946                         xstats[count].id = count;
2947                         xstats[count].value = *((uint64_t *)
2948                                 ((char *)stats_begin + stat_offset));
2949                 }
2950         }
2951
2952         return count;
2953 }
2954
2955 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2956                                 const uint64_t *ids,
2957                                 uint64_t *values,
2958                                 unsigned int n)
2959 {
2960         struct ena_adapter *adapter = dev->data->dev_private;
2961         uint64_t id;
2962         uint64_t rx_entries, tx_entries;
2963         unsigned int i;
2964         int qid;
2965         int valid = 0;
2966         bool was_eni_copied = false;
2967
2968         for (i = 0; i < n; ++i) {
2969                 id = ids[i];
2970                 /* Check if id belongs to global statistics */
2971                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2972                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2973                         ++valid;
2974                         continue;
2975                 }
2976
2977                 /* Check if id belongs to ENI statistics */
2978                 id -= ENA_STATS_ARRAY_GLOBAL;
2979                 if (id < ENA_STATS_ARRAY_ENI) {
2980                         /* Avoid reading ENI stats multiple times in a single
2981                          * function call, as it requires communication with the
2982                          * admin queue.
2983                          */
2984                         if (!was_eni_copied) {
2985                                 was_eni_copied = true;
2986                                 ena_copy_eni_stats(adapter);
2987                         }
2988                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2989                         ++valid;
2990                         continue;
2991                 }
2992
2993                 /* Check if id belongs to rx queue statistics */
2994                 id -= ENA_STATS_ARRAY_ENI;
2995                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2996                 if (id < rx_entries) {
2997                         qid = id % dev->data->nb_rx_queues;
2998                         id /= dev->data->nb_rx_queues;
2999                         values[i] = *((uint64_t *)
3000                                 &adapter->rx_ring[qid].rx_stats + id);
3001                         ++valid;
3002                         continue;
3003                 }
3004                                 /* Check if id belongs to rx queue statistics */
3005                 id -= rx_entries;
3006                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
3007                 if (id < tx_entries) {
3008                         qid = id % dev->data->nb_tx_queues;
3009                         id /= dev->data->nb_tx_queues;
3010                         values[i] = *((uint64_t *)
3011                                 &adapter->tx_ring[qid].tx_stats + id);
3012                         ++valid;
3013                         continue;
3014                 }
3015         }
3016
3017         return valid;
3018 }
3019
3020 static int ena_process_bool_devarg(const char *key,
3021                                    const char *value,
3022                                    void *opaque)
3023 {
3024         struct ena_adapter *adapter = opaque;
3025         bool bool_value;
3026
3027         /* Parse the value. */
3028         if (strcmp(value, "1") == 0) {
3029                 bool_value = true;
3030         } else if (strcmp(value, "0") == 0) {
3031                 bool_value = false;
3032         } else {
3033                 PMD_INIT_LOG(ERR,
3034                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
3035                         value, key);
3036                 return -EINVAL;
3037         }
3038
3039         /* Now, assign it to the proper adapter field. */
3040         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
3041                 adapter->use_large_llq_hdr = bool_value;
3042
3043         return 0;
3044 }
3045
3046 static int ena_parse_devargs(struct ena_adapter *adapter,
3047                              struct rte_devargs *devargs)
3048 {
3049         static const char * const allowed_args[] = {
3050                 ENA_DEVARG_LARGE_LLQ_HDR,
3051                 NULL,
3052         };
3053         struct rte_kvargs *kvlist;
3054         int rc;
3055
3056         if (devargs == NULL)
3057                 return 0;
3058
3059         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
3060         if (kvlist == NULL) {
3061                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
3062                         devargs->args);
3063                 return -EINVAL;
3064         }
3065
3066         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
3067                 ena_process_bool_devarg, adapter);
3068
3069         rte_kvargs_free(kvlist);
3070
3071         return rc;
3072 }
3073
3074 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
3075 {
3076         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3077         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3078         int rc;
3079         uint16_t vectors_nb, i;
3080         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
3081
3082         if (!rx_intr_requested)
3083                 return 0;
3084
3085         if (!rte_intr_cap_multiple(intr_handle)) {
3086                 PMD_DRV_LOG(ERR,
3087                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
3088                 return -ENOTSUP;
3089         }
3090
3091         /* Disable interrupt mapping before the configuration starts. */
3092         rte_intr_disable(intr_handle);
3093
3094         /* Verify if there are enough vectors available. */
3095         vectors_nb = dev->data->nb_rx_queues;
3096         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
3097                 PMD_DRV_LOG(ERR,
3098                         "Too many Rx interrupts requested, maximum number: %d\n",
3099                         RTE_MAX_RXTX_INTR_VEC_ID);
3100                 rc = -ENOTSUP;
3101                 goto enable_intr;
3102         }
3103
3104         /* Allocate the vector list */
3105         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
3106                                            dev->data->nb_rx_queues)) {
3107                 PMD_DRV_LOG(ERR,
3108                         "Failed to allocate interrupt vector for %d queues\n",
3109                         dev->data->nb_rx_queues);
3110                 rc = -ENOMEM;
3111                 goto enable_intr;
3112         }
3113
3114         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
3115         if (rc != 0)
3116                 goto free_intr_vec;
3117
3118         if (!rte_intr_allow_others(intr_handle)) {
3119                 PMD_DRV_LOG(ERR,
3120                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
3121                 goto disable_intr_efd;
3122         }
3123
3124         for (i = 0; i < vectors_nb; ++i)
3125                 if (rte_intr_vec_list_index_set(intr_handle, i,
3126                                            RTE_INTR_VEC_RXTX_OFFSET + i))
3127                         goto disable_intr_efd;
3128
3129         rte_intr_enable(intr_handle);
3130         return 0;
3131
3132 disable_intr_efd:
3133         rte_intr_efd_disable(intr_handle);
3134 free_intr_vec:
3135         rte_intr_vec_list_free(intr_handle);
3136 enable_intr:
3137         rte_intr_enable(intr_handle);
3138         return rc;
3139 }
3140
3141 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3142                                  uint16_t queue_id,
3143                                  bool unmask)
3144 {
3145         struct ena_adapter *adapter = dev->data->dev_private;
3146         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3147         struct ena_eth_io_intr_reg intr_reg;
3148
3149         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3150         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3151 }
3152
3153 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3154                                     uint16_t queue_id)
3155 {
3156         ena_rx_queue_intr_set(dev, queue_id, true);
3157
3158         return 0;
3159 }
3160
3161 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3162                                      uint16_t queue_id)
3163 {
3164         ena_rx_queue_intr_set(dev, queue_id, false);
3165
3166         return 0;
3167 }
3168
3169 static int ena_configure_aenq(struct ena_adapter *adapter)
3170 {
3171         uint32_t aenq_groups = adapter->all_aenq_groups;
3172         int rc;
3173
3174         /* All_aenq_groups holds all AENQ functions supported by the device and
3175          * the HW, so at first we need to be sure the LSC request is valid.
3176          */
3177         if (adapter->edev_data->dev_conf.intr_conf.lsc != 0) {
3178                 if (!(aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) {
3179                         PMD_DRV_LOG(ERR,
3180                                 "LSC requested, but it's not supported by the AENQ\n");
3181                         return -EINVAL;
3182                 }
3183         } else {
3184                 /* If LSC wasn't enabled by the app, let's enable all supported
3185                  * AENQ procedures except the LSC.
3186                  */
3187                 aenq_groups &= ~BIT(ENA_ADMIN_LINK_CHANGE);
3188         }
3189
3190         rc = ena_com_set_aenq_config(&adapter->ena_dev, aenq_groups);
3191         if (rc != 0) {
3192                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc=%d\n", rc);
3193                 return rc;
3194         }
3195
3196         adapter->active_aenq_groups = aenq_groups;
3197
3198         return 0;
3199 }
3200
3201 /*********************************************************************
3202  *  PMD configuration
3203  *********************************************************************/
3204 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3205         struct rte_pci_device *pci_dev)
3206 {
3207         return rte_eth_dev_pci_generic_probe(pci_dev,
3208                 sizeof(struct ena_adapter), eth_ena_dev_init);
3209 }
3210
3211 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3212 {
3213         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3214 }
3215
3216 static struct rte_pci_driver rte_ena_pmd = {
3217         .id_table = pci_id_ena_map,
3218         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3219                      RTE_PCI_DRV_WC_ACTIVATE,
3220         .probe = eth_ena_pci_probe,
3221         .remove = eth_ena_pci_remove,
3222 };
3223
3224 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3225 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3226 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3227 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3228 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3229 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3230 #ifdef RTE_ETHDEV_DEBUG_RX
3231 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3232 #endif
3233 #ifdef RTE_ETHDEV_DEBUG_TX
3234 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3235 #endif
3236 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3237
3238 /******************************************************************************
3239  ******************************** AENQ Handlers *******************************
3240  *****************************************************************************/
3241 static void ena_update_on_link_change(void *adapter_data,
3242                                       struct ena_admin_aenq_entry *aenq_e)
3243 {
3244         struct rte_eth_dev *eth_dev = adapter_data;
3245         struct ena_adapter *adapter = eth_dev->data->dev_private;
3246         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3247         uint32_t status;
3248
3249         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3250
3251         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3252         adapter->link_status = status;
3253
3254         ena_link_update(eth_dev, 0);
3255         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3256 }
3257
3258 static void ena_notification(void *adapter_data,
3259                              struct ena_admin_aenq_entry *aenq_e)
3260 {
3261         struct rte_eth_dev *eth_dev = adapter_data;
3262         struct ena_adapter *adapter = eth_dev->data->dev_private;
3263         struct ena_admin_ena_hw_hints *hints;
3264
3265         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3266                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3267                         aenq_e->aenq_common_desc.group,
3268                         ENA_ADMIN_NOTIFICATION);
3269
3270         switch (aenq_e->aenq_common_desc.syndrome) {
3271         case ENA_ADMIN_UPDATE_HINTS:
3272                 hints = (struct ena_admin_ena_hw_hints *)
3273                         (&aenq_e->inline_data_w4);
3274                 ena_update_hints(adapter, hints);
3275                 break;
3276         default:
3277                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3278                         aenq_e->aenq_common_desc.syndrome);
3279         }
3280 }
3281
3282 static void ena_keep_alive(void *adapter_data,
3283                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
3284 {
3285         struct rte_eth_dev *eth_dev = adapter_data;
3286         struct ena_adapter *adapter = eth_dev->data->dev_private;
3287         struct ena_admin_aenq_keep_alive_desc *desc;
3288         uint64_t rx_drops;
3289         uint64_t tx_drops;
3290
3291         adapter->timestamp_wd = rte_get_timer_cycles();
3292
3293         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3294         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3295         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3296
3297         adapter->drv_stats->rx_drops = rx_drops;
3298         adapter->dev_stats.tx_drops = tx_drops;
3299 }
3300
3301 /**
3302  * This handler will called for unknown event group or unimplemented handlers
3303  **/
3304 static void unimplemented_aenq_handler(__rte_unused void *data,
3305                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3306 {
3307         PMD_DRV_LOG(ERR,
3308                 "Unknown event was received or event with unimplemented handler\n");
3309 }
3310
3311 static struct ena_aenq_handlers aenq_handlers = {
3312         .handlers = {
3313                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3314                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3315                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3316         },
3317         .unimplemented_handler = unimplemented_aenq_handler
3318 };