1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_ethdev_pci.h>
11 #include <rte_atomic.h>
13 #include <rte_errno.h>
14 #include <rte_version.h>
17 #include "ena_ethdev.h"
19 #include "ena_platform.h"
21 #include "ena_eth_com.h"
23 #include <ena_common_defs.h>
24 #include <ena_regs_defs.h>
25 #include <ena_admin_defs.h>
26 #include <ena_eth_io_defs.h>
28 #define DRV_MODULE_VER_MAJOR 2
29 #define DRV_MODULE_VER_MINOR 0
30 #define DRV_MODULE_VER_SUBMINOR 3
32 #define ENA_IO_TXQ_IDX(q) (2 * (q))
33 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
34 /*reverse version of ENA_IO_RXQ_IDX*/
35 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
37 /* While processing submitted and completed descriptors (rx and tx path
38 * respectively) in a loop it is desired to:
39 * - perform batch submissions while populating sumbissmion queue
40 * - avoid blocking transmission of other packets during cleanup phase
41 * Hence the utilization ratio of 1/8 of a queue size.
43 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
45 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
46 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
48 #define GET_L4_HDR_LEN(mbuf) \
49 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
50 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
52 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
53 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
54 #define ENA_HASH_KEY_SIZE 40
55 #define ETH_GSTRING_LEN 32
57 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
59 #define ENA_MIN_RING_DESC 128
61 enum ethtool_stringset {
67 char name[ETH_GSTRING_LEN];
71 #define ENA_STAT_ENTRY(stat, stat_type) { \
73 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
76 #define ENA_STAT_RX_ENTRY(stat) \
77 ENA_STAT_ENTRY(stat, rx)
79 #define ENA_STAT_TX_ENTRY(stat) \
80 ENA_STAT_ENTRY(stat, tx)
82 #define ENA_STAT_GLOBAL_ENTRY(stat) \
83 ENA_STAT_ENTRY(stat, dev)
85 #define ENA_MAX_RING_SIZE_RX 8192
86 #define ENA_MAX_RING_SIZE_TX 1024
89 * Each rte_memzone should have unique name.
90 * To satisfy it, count number of allocation and add it to name.
92 rte_atomic32_t ena_alloc_cnt;
94 static const struct ena_stats ena_stats_global_strings[] = {
95 ENA_STAT_GLOBAL_ENTRY(wd_expired),
96 ENA_STAT_GLOBAL_ENTRY(dev_start),
97 ENA_STAT_GLOBAL_ENTRY(dev_stop),
100 static const struct ena_stats ena_stats_tx_strings[] = {
101 ENA_STAT_TX_ENTRY(cnt),
102 ENA_STAT_TX_ENTRY(bytes),
103 ENA_STAT_TX_ENTRY(prepare_ctx_err),
104 ENA_STAT_TX_ENTRY(linearize),
105 ENA_STAT_TX_ENTRY(linearize_failed),
106 ENA_STAT_TX_ENTRY(tx_poll),
107 ENA_STAT_TX_ENTRY(doorbells),
108 ENA_STAT_TX_ENTRY(bad_req_id),
109 ENA_STAT_TX_ENTRY(available_desc),
112 static const struct ena_stats ena_stats_rx_strings[] = {
113 ENA_STAT_RX_ENTRY(cnt),
114 ENA_STAT_RX_ENTRY(bytes),
115 ENA_STAT_RX_ENTRY(refill_partial),
116 ENA_STAT_RX_ENTRY(bad_csum),
117 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
118 ENA_STAT_RX_ENTRY(bad_desc_num),
119 ENA_STAT_RX_ENTRY(bad_req_id),
122 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
123 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
124 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
126 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
127 DEV_TX_OFFLOAD_UDP_CKSUM |\
128 DEV_TX_OFFLOAD_IPV4_CKSUM |\
129 DEV_TX_OFFLOAD_TCP_TSO)
130 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
134 /** Vendor ID used by Amazon devices */
135 #define PCI_VENDOR_ID_AMAZON 0x1D0F
136 /** Amazon devices */
137 #define PCI_DEVICE_ID_ENA_VF 0xEC20
138 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
140 #define ENA_TX_OFFLOAD_MASK (\
147 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
148 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
150 int ena_logtype_init;
151 int ena_logtype_driver;
153 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
156 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
159 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
160 int ena_logtype_tx_free;
162 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
166 static const struct rte_pci_id pci_id_ena_map[] = {
167 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
168 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
172 static struct ena_aenq_handlers aenq_handlers;
174 static int ena_device_init(struct ena_com_dev *ena_dev,
175 struct ena_com_dev_get_features_ctx *get_feat_ctx,
177 static int ena_dev_configure(struct rte_eth_dev *dev);
178 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
180 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_txconf *tx_conf);
185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
186 uint16_t nb_desc, unsigned int socket_id,
187 const struct rte_eth_rxconf *rx_conf,
188 struct rte_mempool *mp);
189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
190 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
192 static void ena_init_rings(struct ena_adapter *adapter);
193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
194 static int ena_start(struct rte_eth_dev *dev);
195 static void ena_stop(struct rte_eth_dev *dev);
196 static void ena_close(struct rte_eth_dev *dev);
197 static int ena_dev_reset(struct rte_eth_dev *dev);
198 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
199 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
200 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
201 static void ena_rx_queue_release(void *queue);
202 static void ena_tx_queue_release(void *queue);
203 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
204 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
205 static int ena_link_update(struct rte_eth_dev *dev,
206 int wait_to_complete);
207 static int ena_create_io_queue(struct ena_ring *ring);
208 static void ena_queue_stop(struct ena_ring *ring);
209 static void ena_queue_stop_all(struct rte_eth_dev *dev,
210 enum ena_ring_type ring_type);
211 static int ena_queue_start(struct ena_ring *ring);
212 static int ena_queue_start_all(struct rte_eth_dev *dev,
213 enum ena_ring_type ring_type);
214 static void ena_stats_restart(struct rte_eth_dev *dev);
215 static int ena_infos_get(struct rte_eth_dev *dev,
216 struct rte_eth_dev_info *dev_info);
217 static int ena_rss_reta_update(struct rte_eth_dev *dev,
218 struct rte_eth_rss_reta_entry64 *reta_conf,
220 static int ena_rss_reta_query(struct rte_eth_dev *dev,
221 struct rte_eth_rss_reta_entry64 *reta_conf,
223 static void ena_interrupt_handler_rte(void *cb_arg);
224 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
225 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
226 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
227 static int ena_xstats_get_names(struct rte_eth_dev *dev,
228 struct rte_eth_xstat_name *xstats_names,
230 static int ena_xstats_get(struct rte_eth_dev *dev,
231 struct rte_eth_xstat *stats,
233 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
238 static const struct eth_dev_ops ena_dev_ops = {
239 .dev_configure = ena_dev_configure,
240 .dev_infos_get = ena_infos_get,
241 .rx_queue_setup = ena_rx_queue_setup,
242 .tx_queue_setup = ena_tx_queue_setup,
243 .dev_start = ena_start,
244 .dev_stop = ena_stop,
245 .link_update = ena_link_update,
246 .stats_get = ena_stats_get,
247 .xstats_get_names = ena_xstats_get_names,
248 .xstats_get = ena_xstats_get,
249 .xstats_get_by_id = ena_xstats_get_by_id,
250 .mtu_set = ena_mtu_set,
251 .rx_queue_release = ena_rx_queue_release,
252 .tx_queue_release = ena_tx_queue_release,
253 .dev_close = ena_close,
254 .dev_reset = ena_dev_reset,
255 .reta_update = ena_rss_reta_update,
256 .reta_query = ena_rss_reta_query,
259 void ena_rss_key_fill(void *key, size_t size)
261 static bool key_generated;
262 static uint8_t default_key[ENA_HASH_KEY_SIZE];
265 RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
267 if (!key_generated) {
268 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
269 default_key[i] = rte_rand() & 0xff;
270 key_generated = true;
273 rte_memcpy(key, default_key, size);
276 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
277 struct ena_com_rx_ctx *ena_rx_ctx)
279 uint64_t ol_flags = 0;
280 uint32_t packet_type = 0;
282 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
283 packet_type |= RTE_PTYPE_L4_TCP;
284 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
285 packet_type |= RTE_PTYPE_L4_UDP;
287 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
288 packet_type |= RTE_PTYPE_L3_IPV4;
289 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
290 packet_type |= RTE_PTYPE_L3_IPV6;
292 if (!ena_rx_ctx->l4_csum_checked)
293 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
295 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
296 ol_flags |= PKT_RX_L4_CKSUM_BAD;
298 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
300 if (unlikely(ena_rx_ctx->l3_csum_err))
301 ol_flags |= PKT_RX_IP_CKSUM_BAD;
303 mbuf->ol_flags = ol_flags;
304 mbuf->packet_type = packet_type;
307 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
308 struct ena_com_tx_ctx *ena_tx_ctx,
309 uint64_t queue_offloads)
311 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
313 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
314 (queue_offloads & QUEUE_OFFLOADS)) {
315 /* check if TSO is required */
316 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
317 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
318 ena_tx_ctx->tso_enable = true;
320 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
323 /* check if L3 checksum is needed */
324 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
325 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
326 ena_tx_ctx->l3_csum_enable = true;
328 if (mbuf->ol_flags & PKT_TX_IPV6) {
329 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
331 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
333 /* set don't fragment (DF) flag */
334 if (mbuf->packet_type &
335 (RTE_PTYPE_L4_NONFRAG
336 | RTE_PTYPE_INNER_L4_NONFRAG))
337 ena_tx_ctx->df = true;
340 /* check if L4 checksum is needed */
341 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
342 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
343 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
344 ena_tx_ctx->l4_csum_enable = true;
345 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
347 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
348 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
349 ena_tx_ctx->l4_csum_enable = true;
351 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
352 ena_tx_ctx->l4_csum_enable = false;
355 ena_meta->mss = mbuf->tso_segsz;
356 ena_meta->l3_hdr_len = mbuf->l3_len;
357 ena_meta->l3_hdr_offset = mbuf->l2_len;
359 ena_tx_ctx->meta_valid = true;
361 ena_tx_ctx->meta_valid = false;
365 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
367 if (likely(req_id < rx_ring->ring_size))
370 PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
372 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
373 rx_ring->adapter->trigger_reset = true;
374 ++rx_ring->rx_stats.bad_req_id;
379 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
381 struct ena_tx_buffer *tx_info = NULL;
383 if (likely(req_id < tx_ring->ring_size)) {
384 tx_info = &tx_ring->tx_buffer_info[req_id];
385 if (likely(tx_info->mbuf))
390 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
392 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
394 /* Trigger device reset */
395 ++tx_ring->tx_stats.bad_req_id;
396 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
397 tx_ring->adapter->trigger_reset = true;
401 static void ena_config_host_info(struct ena_com_dev *ena_dev)
403 struct ena_admin_host_info *host_info;
406 /* Allocate only the host info */
407 rc = ena_com_allocate_host_info(ena_dev);
409 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
413 host_info = ena_dev->host_attr.host_info;
415 host_info->os_type = ENA_ADMIN_OS_DPDK;
416 host_info->kernel_ver = RTE_VERSION;
417 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
418 sizeof(host_info->kernel_ver_str));
419 host_info->os_dist = RTE_VERSION;
420 strlcpy((char *)host_info->os_dist_str, rte_version(),
421 sizeof(host_info->os_dist_str));
422 host_info->driver_version =
423 (DRV_MODULE_VER_MAJOR) |
424 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
425 (DRV_MODULE_VER_SUBMINOR <<
426 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
427 host_info->num_cpus = rte_lcore_count();
429 host_info->driver_supported_features =
430 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
432 rc = ena_com_set_host_attributes(ena_dev);
434 if (rc == -ENA_COM_UNSUPPORTED)
435 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
437 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
445 ena_com_delete_host_info(ena_dev);
448 /* This function calculates the number of xstats based on the current config */
449 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
451 return ENA_STATS_ARRAY_GLOBAL +
452 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
453 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
456 static void ena_config_debug_area(struct ena_adapter *adapter)
461 ss_count = ena_xstats_calc_num(adapter->rte_dev);
463 /* allocate 32 bytes for each string and 64bit for the value */
464 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
466 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
468 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
472 rc = ena_com_set_host_attributes(&adapter->ena_dev);
474 if (rc == -ENA_COM_UNSUPPORTED)
475 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
477 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
484 ena_com_delete_debug_area(&adapter->ena_dev);
487 static void ena_close(struct rte_eth_dev *dev)
489 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
490 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
491 struct ena_adapter *adapter = dev->data->dev_private;
493 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
495 adapter->state = ENA_ADAPTER_STATE_CLOSED;
497 ena_rx_queue_release_all(dev);
498 ena_tx_queue_release_all(dev);
500 rte_free(adapter->drv_stats);
501 adapter->drv_stats = NULL;
503 rte_intr_disable(intr_handle);
504 rte_intr_callback_unregister(intr_handle,
505 ena_interrupt_handler_rte,
509 * MAC is not allocated dynamically. Setting NULL should prevent from
510 * release of the resource in the rte_eth_dev_release_port().
512 dev->data->mac_addrs = NULL;
516 ena_dev_reset(struct rte_eth_dev *dev)
520 ena_destroy_device(dev);
521 rc = eth_ena_dev_init(dev);
523 PMD_INIT_LOG(CRIT, "Cannot initialize device");
528 static int ena_rss_reta_update(struct rte_eth_dev *dev,
529 struct rte_eth_rss_reta_entry64 *reta_conf,
532 struct ena_adapter *adapter = dev->data->dev_private;
533 struct ena_com_dev *ena_dev = &adapter->ena_dev;
539 if ((reta_size == 0) || (reta_conf == NULL))
542 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
544 "indirection table %d is bigger than supported (%d)\n",
545 reta_size, ENA_RX_RSS_TABLE_SIZE);
549 for (i = 0 ; i < reta_size ; i++) {
550 /* each reta_conf is for 64 entries.
551 * to support 128 we use 2 conf of 64
553 conf_idx = i / RTE_RETA_GROUP_SIZE;
554 idx = i % RTE_RETA_GROUP_SIZE;
555 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
557 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
559 rc = ena_com_indirect_table_fill_entry(ena_dev,
562 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
564 "Cannot fill indirect table\n");
570 rc = ena_com_indirect_table_set(ena_dev);
571 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
572 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
576 PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n",
577 __func__, reta_size, adapter->rte_dev->data->port_id);
582 /* Query redirection table. */
583 static int ena_rss_reta_query(struct rte_eth_dev *dev,
584 struct rte_eth_rss_reta_entry64 *reta_conf,
587 struct ena_adapter *adapter = dev->data->dev_private;
588 struct ena_com_dev *ena_dev = &adapter->ena_dev;
591 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
595 if (reta_size == 0 || reta_conf == NULL ||
596 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
599 rc = ena_com_indirect_table_get(ena_dev, indirect_table);
600 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
601 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
605 for (i = 0 ; i < reta_size ; i++) {
606 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
607 reta_idx = i % RTE_RETA_GROUP_SIZE;
608 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
609 reta_conf[reta_conf_idx].reta[reta_idx] =
610 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
616 static int ena_rss_init_default(struct ena_adapter *adapter)
618 struct ena_com_dev *ena_dev = &adapter->ena_dev;
619 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
623 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
625 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
629 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
630 val = i % nb_rx_queues;
631 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
632 ENA_IO_RXQ_IDX(val));
633 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
634 PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
639 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
640 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
641 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
642 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
646 rc = ena_com_set_default_hash_ctrl(ena_dev);
647 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
648 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
652 rc = ena_com_indirect_table_set(ena_dev);
653 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
654 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
657 PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
658 adapter->rte_dev->data->port_id);
663 ena_com_rss_destroy(ena_dev);
669 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
671 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
672 int nb_queues = dev->data->nb_rx_queues;
675 for (i = 0; i < nb_queues; i++)
676 ena_rx_queue_release(queues[i]);
679 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
681 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
682 int nb_queues = dev->data->nb_tx_queues;
685 for (i = 0; i < nb_queues; i++)
686 ena_tx_queue_release(queues[i]);
689 static void ena_rx_queue_release(void *queue)
691 struct ena_ring *ring = (struct ena_ring *)queue;
693 /* Free ring resources */
694 if (ring->rx_buffer_info)
695 rte_free(ring->rx_buffer_info);
696 ring->rx_buffer_info = NULL;
698 if (ring->rx_refill_buffer)
699 rte_free(ring->rx_refill_buffer);
700 ring->rx_refill_buffer = NULL;
702 if (ring->empty_rx_reqs)
703 rte_free(ring->empty_rx_reqs);
704 ring->empty_rx_reqs = NULL;
706 ring->configured = 0;
708 PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
709 ring->port_id, ring->id);
712 static void ena_tx_queue_release(void *queue)
714 struct ena_ring *ring = (struct ena_ring *)queue;
716 /* Free ring resources */
717 if (ring->push_buf_intermediate_buf)
718 rte_free(ring->push_buf_intermediate_buf);
720 if (ring->tx_buffer_info)
721 rte_free(ring->tx_buffer_info);
723 if (ring->empty_tx_reqs)
724 rte_free(ring->empty_tx_reqs);
726 ring->empty_tx_reqs = NULL;
727 ring->tx_buffer_info = NULL;
728 ring->push_buf_intermediate_buf = NULL;
730 ring->configured = 0;
732 PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
733 ring->port_id, ring->id);
736 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
740 for (i = 0; i < ring->ring_size; ++i)
741 if (ring->rx_buffer_info[i]) {
742 rte_mbuf_raw_free(ring->rx_buffer_info[i]);
743 ring->rx_buffer_info[i] = NULL;
747 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
751 for (i = 0; i < ring->ring_size; ++i) {
752 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
755 rte_pktmbuf_free(tx_buf->mbuf);
759 static int ena_link_update(struct rte_eth_dev *dev,
760 __rte_unused int wait_to_complete)
762 struct rte_eth_link *link = &dev->data->dev_link;
763 struct ena_adapter *adapter = dev->data->dev_private;
765 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
766 link->link_speed = ETH_SPEED_NUM_NONE;
767 link->link_duplex = ETH_LINK_FULL_DUPLEX;
772 static int ena_queue_start_all(struct rte_eth_dev *dev,
773 enum ena_ring_type ring_type)
775 struct ena_adapter *adapter = dev->data->dev_private;
776 struct ena_ring *queues = NULL;
781 if (ring_type == ENA_RING_TYPE_RX) {
782 queues = adapter->rx_ring;
783 nb_queues = dev->data->nb_rx_queues;
785 queues = adapter->tx_ring;
786 nb_queues = dev->data->nb_tx_queues;
788 for (i = 0; i < nb_queues; i++) {
789 if (queues[i].configured) {
790 if (ring_type == ENA_RING_TYPE_RX) {
792 dev->data->rx_queues[i] == &queues[i],
793 "Inconsistent state of rx queues\n");
796 dev->data->tx_queues[i] == &queues[i],
797 "Inconsistent state of tx queues\n");
800 rc = ena_queue_start(&queues[i]);
804 "failed to start queue %d type(%d)",
815 if (queues[i].configured)
816 ena_queue_stop(&queues[i]);
821 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
823 uint32_t max_frame_len = adapter->max_mtu;
825 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
826 DEV_RX_OFFLOAD_JUMBO_FRAME)
828 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
830 return max_frame_len;
833 static int ena_check_valid_conf(struct ena_adapter *adapter)
835 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
837 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
838 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
839 "max mtu: %d, min mtu: %d",
840 max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
841 return ENA_COM_UNSUPPORTED;
848 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
850 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
851 struct ena_com_dev *ena_dev = ctx->ena_dev;
852 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
853 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
855 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
856 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
857 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
858 rx_queue_size = RTE_MIN(rx_queue_size,
859 max_queue_ext->max_rx_cq_depth);
860 rx_queue_size = RTE_MIN(rx_queue_size,
861 max_queue_ext->max_rx_sq_depth);
862 tx_queue_size = RTE_MIN(tx_queue_size,
863 max_queue_ext->max_tx_cq_depth);
865 if (ena_dev->tx_mem_queue_type ==
866 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
867 tx_queue_size = RTE_MIN(tx_queue_size,
870 tx_queue_size = RTE_MIN(tx_queue_size,
871 max_queue_ext->max_tx_sq_depth);
874 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
875 max_queue_ext->max_per_packet_rx_descs);
876 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
877 max_queue_ext->max_per_packet_tx_descs);
879 struct ena_admin_queue_feature_desc *max_queues =
880 &ctx->get_feat_ctx->max_queues;
881 rx_queue_size = RTE_MIN(rx_queue_size,
882 max_queues->max_cq_depth);
883 rx_queue_size = RTE_MIN(rx_queue_size,
884 max_queues->max_sq_depth);
885 tx_queue_size = RTE_MIN(tx_queue_size,
886 max_queues->max_cq_depth);
888 if (ena_dev->tx_mem_queue_type ==
889 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
890 tx_queue_size = RTE_MIN(tx_queue_size,
893 tx_queue_size = RTE_MIN(tx_queue_size,
894 max_queues->max_sq_depth);
897 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
898 max_queues->max_packet_tx_descs);
899 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
900 max_queues->max_packet_rx_descs);
903 /* Round down to the nearest power of 2 */
904 rx_queue_size = rte_align32prevpow2(rx_queue_size);
905 tx_queue_size = rte_align32prevpow2(tx_queue_size);
907 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
908 PMD_INIT_LOG(ERR, "Invalid queue size");
912 ctx->rx_queue_size = rx_queue_size;
913 ctx->tx_queue_size = tx_queue_size;
918 static void ena_stats_restart(struct rte_eth_dev *dev)
920 struct ena_adapter *adapter = dev->data->dev_private;
922 rte_atomic64_init(&adapter->drv_stats->ierrors);
923 rte_atomic64_init(&adapter->drv_stats->oerrors);
924 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
925 rte_atomic64_init(&adapter->drv_stats->rx_drops);
928 static int ena_stats_get(struct rte_eth_dev *dev,
929 struct rte_eth_stats *stats)
931 struct ena_admin_basic_stats ena_stats;
932 struct ena_adapter *adapter = dev->data->dev_private;
933 struct ena_com_dev *ena_dev = &adapter->ena_dev;
938 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
941 memset(&ena_stats, 0, sizeof(ena_stats));
942 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
944 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
948 /* Set of basic statistics from ENA */
949 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
950 ena_stats.rx_pkts_low);
951 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
952 ena_stats.tx_pkts_low);
953 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
954 ena_stats.rx_bytes_low);
955 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
956 ena_stats.tx_bytes_low);
958 /* Driver related stats */
959 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops);
960 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
961 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
962 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
964 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
965 RTE_ETHDEV_QUEUE_STAT_CNTRS);
966 for (i = 0; i < max_rings_stats; ++i) {
967 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
969 stats->q_ibytes[i] = rx_stats->bytes;
970 stats->q_ipackets[i] = rx_stats->cnt;
971 stats->q_errors[i] = rx_stats->bad_desc_num +
972 rx_stats->bad_req_id;
975 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
976 RTE_ETHDEV_QUEUE_STAT_CNTRS);
977 for (i = 0; i < max_rings_stats; ++i) {
978 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
980 stats->q_obytes[i] = tx_stats->bytes;
981 stats->q_opackets[i] = tx_stats->cnt;
987 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
989 struct ena_adapter *adapter;
990 struct ena_com_dev *ena_dev;
993 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
994 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
995 adapter = dev->data->dev_private;
997 ena_dev = &adapter->ena_dev;
998 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1000 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1002 "Invalid MTU setting. new_mtu: %d "
1003 "max mtu: %d min mtu: %d\n",
1004 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1008 rc = ena_com_set_dev_mtu(ena_dev, mtu);
1010 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1012 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1017 static int ena_start(struct rte_eth_dev *dev)
1019 struct ena_adapter *adapter = dev->data->dev_private;
1023 rc = ena_check_valid_conf(adapter);
1027 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1031 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1035 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1036 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1037 rc = ena_rss_init_default(adapter);
1042 ena_stats_restart(dev);
1044 adapter->timestamp_wd = rte_get_timer_cycles();
1045 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1047 ticks = rte_get_timer_hz();
1048 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1049 ena_timer_wd_callback, adapter);
1051 ++adapter->dev_stats.dev_start;
1052 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1057 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1059 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1063 static void ena_stop(struct rte_eth_dev *dev)
1065 struct ena_adapter *adapter = dev->data->dev_private;
1066 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1069 rte_timer_stop_sync(&adapter->timer_wd);
1070 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1071 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1073 if (adapter->trigger_reset) {
1074 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1076 PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1079 ++adapter->dev_stats.dev_stop;
1080 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1083 static int ena_create_io_queue(struct ena_ring *ring)
1085 struct ena_adapter *adapter;
1086 struct ena_com_dev *ena_dev;
1087 struct ena_com_create_io_ctx ctx =
1088 /* policy set to _HOST just to satisfy icc compiler */
1089 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1095 adapter = ring->adapter;
1096 ena_dev = &adapter->ena_dev;
1098 if (ring->type == ENA_RING_TYPE_TX) {
1099 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1100 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1101 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1102 ctx.queue_size = adapter->tx_ring_size;
1103 for (i = 0; i < ring->ring_size; i++)
1104 ring->empty_tx_reqs[i] = i;
1106 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1107 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1108 ctx.queue_size = adapter->rx_ring_size;
1109 for (i = 0; i < ring->ring_size; i++)
1110 ring->empty_rx_reqs[i] = i;
1113 ctx.msix_vector = -1; /* interrupts not used */
1114 ctx.numa_node = ring->numa_socket_id;
1116 rc = ena_com_create_io_queue(ena_dev, &ctx);
1119 "failed to create io queue #%d (qid:%d) rc: %d\n",
1120 ring->id, ena_qid, rc);
1124 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1125 &ring->ena_com_io_sq,
1126 &ring->ena_com_io_cq);
1129 "Failed to get io queue handlers. queue num %d rc: %d\n",
1131 ena_com_destroy_io_queue(ena_dev, ena_qid);
1135 if (ring->type == ENA_RING_TYPE_TX)
1136 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1141 static void ena_queue_stop(struct ena_ring *ring)
1143 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1145 if (ring->type == ENA_RING_TYPE_RX) {
1146 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1147 ena_rx_queue_release_bufs(ring);
1149 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1150 ena_tx_queue_release_bufs(ring);
1154 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1155 enum ena_ring_type ring_type)
1157 struct ena_adapter *adapter = dev->data->dev_private;
1158 struct ena_ring *queues = NULL;
1159 uint16_t nb_queues, i;
1161 if (ring_type == ENA_RING_TYPE_RX) {
1162 queues = adapter->rx_ring;
1163 nb_queues = dev->data->nb_rx_queues;
1165 queues = adapter->tx_ring;
1166 nb_queues = dev->data->nb_tx_queues;
1169 for (i = 0; i < nb_queues; ++i)
1170 if (queues[i].configured)
1171 ena_queue_stop(&queues[i]);
1174 static int ena_queue_start(struct ena_ring *ring)
1178 ena_assert_msg(ring->configured == 1,
1179 "Trying to start unconfigured queue\n");
1181 rc = ena_create_io_queue(ring);
1183 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1187 ring->next_to_clean = 0;
1188 ring->next_to_use = 0;
1190 if (ring->type == ENA_RING_TYPE_TX) {
1191 ring->tx_stats.available_desc =
1192 ena_com_free_q_entries(ring->ena_com_io_sq);
1196 bufs_num = ring->ring_size - 1;
1197 rc = ena_populate_rx_queue(ring, bufs_num);
1198 if (rc != bufs_num) {
1199 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1200 ENA_IO_RXQ_IDX(ring->id));
1201 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1202 return ENA_COM_FAULT;
1208 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1211 unsigned int socket_id,
1212 const struct rte_eth_txconf *tx_conf)
1214 struct ena_ring *txq = NULL;
1215 struct ena_adapter *adapter = dev->data->dev_private;
1218 txq = &adapter->tx_ring[queue_idx];
1220 if (txq->configured) {
1222 "API violation. Queue %d is already configured\n",
1224 return ENA_COM_FAULT;
1227 if (!rte_is_power_of_2(nb_desc)) {
1229 "Unsupported size of TX queue: %d is not a power of 2.\n",
1234 if (nb_desc > adapter->tx_ring_size) {
1236 "Unsupported size of TX queue (max size: %d)\n",
1237 adapter->tx_ring_size);
1241 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1242 nb_desc = adapter->tx_ring_size;
1244 txq->port_id = dev->data->port_id;
1245 txq->next_to_clean = 0;
1246 txq->next_to_use = 0;
1247 txq->ring_size = nb_desc;
1248 txq->numa_socket_id = socket_id;
1250 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1251 sizeof(struct ena_tx_buffer) *
1253 RTE_CACHE_LINE_SIZE);
1254 if (!txq->tx_buffer_info) {
1255 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1259 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1260 sizeof(u16) * txq->ring_size,
1261 RTE_CACHE_LINE_SIZE);
1262 if (!txq->empty_tx_reqs) {
1263 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1264 rte_free(txq->tx_buffer_info);
1268 txq->push_buf_intermediate_buf =
1269 rte_zmalloc("txq->push_buf_intermediate_buf",
1270 txq->tx_max_header_size,
1271 RTE_CACHE_LINE_SIZE);
1272 if (!txq->push_buf_intermediate_buf) {
1273 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1274 rte_free(txq->tx_buffer_info);
1275 rte_free(txq->empty_tx_reqs);
1279 for (i = 0; i < txq->ring_size; i++)
1280 txq->empty_tx_reqs[i] = i;
1282 if (tx_conf != NULL) {
1284 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1286 /* Store pointer to this queue in upper layer */
1287 txq->configured = 1;
1288 dev->data->tx_queues[queue_idx] = txq;
1293 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1296 unsigned int socket_id,
1297 __rte_unused const struct rte_eth_rxconf *rx_conf,
1298 struct rte_mempool *mp)
1300 struct ena_adapter *adapter = dev->data->dev_private;
1301 struct ena_ring *rxq = NULL;
1305 rxq = &adapter->rx_ring[queue_idx];
1306 if (rxq->configured) {
1308 "API violation. Queue %d is already configured\n",
1310 return ENA_COM_FAULT;
1313 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1314 nb_desc = adapter->rx_ring_size;
1316 if (!rte_is_power_of_2(nb_desc)) {
1318 "Unsupported size of RX queue: %d is not a power of 2.\n",
1323 if (nb_desc > adapter->rx_ring_size) {
1325 "Unsupported size of RX queue (max size: %d)\n",
1326 adapter->rx_ring_size);
1330 /* ENA isn't supporting buffers smaller than 1400 bytes */
1331 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1332 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1334 "Unsupported size of RX buffer: %zu (min size: %d)\n",
1335 buffer_size, ENA_RX_BUF_MIN_SIZE);
1339 rxq->port_id = dev->data->port_id;
1340 rxq->next_to_clean = 0;
1341 rxq->next_to_use = 0;
1342 rxq->ring_size = nb_desc;
1343 rxq->numa_socket_id = socket_id;
1346 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1347 sizeof(struct rte_mbuf *) * nb_desc,
1348 RTE_CACHE_LINE_SIZE);
1349 if (!rxq->rx_buffer_info) {
1350 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1354 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1355 sizeof(struct rte_mbuf *) * nb_desc,
1356 RTE_CACHE_LINE_SIZE);
1358 if (!rxq->rx_refill_buffer) {
1359 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1360 rte_free(rxq->rx_buffer_info);
1361 rxq->rx_buffer_info = NULL;
1365 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1366 sizeof(uint16_t) * nb_desc,
1367 RTE_CACHE_LINE_SIZE);
1368 if (!rxq->empty_rx_reqs) {
1369 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1370 rte_free(rxq->rx_buffer_info);
1371 rxq->rx_buffer_info = NULL;
1372 rte_free(rxq->rx_refill_buffer);
1373 rxq->rx_refill_buffer = NULL;
1377 for (i = 0; i < nb_desc; i++)
1378 rxq->empty_rx_reqs[i] = i;
1380 /* Store pointer to this queue in upper layer */
1381 rxq->configured = 1;
1382 dev->data->rx_queues[queue_idx] = rxq;
1387 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1391 uint16_t ring_size = rxq->ring_size;
1392 uint16_t ring_mask = ring_size - 1;
1393 uint16_t next_to_use = rxq->next_to_use;
1394 uint16_t in_use, req_id;
1395 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1397 if (unlikely(!count))
1400 in_use = rxq->next_to_use - rxq->next_to_clean;
1401 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1403 /* get resources for incoming packets */
1404 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1405 if (unlikely(rc < 0)) {
1406 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1407 ++rxq->rx_stats.mbuf_alloc_fail;
1408 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1412 for (i = 0; i < count; i++) {
1413 uint16_t next_to_use_masked = next_to_use & ring_mask;
1414 struct rte_mbuf *mbuf = mbufs[i];
1415 struct ena_com_buf ebuf;
1417 if (likely((i + 4) < count))
1418 rte_prefetch0(mbufs[i + 4]);
1420 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1421 rc = validate_rx_req_id(rxq, req_id);
1422 if (unlikely(rc < 0))
1424 rxq->rx_buffer_info[req_id] = mbuf;
1426 /* prepare physical address for DMA transaction */
1427 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1428 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1429 /* pass resource to device */
1430 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1433 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1434 rxq->rx_buffer_info[req_id] = NULL;
1440 if (unlikely(i < count)) {
1441 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1442 "buffers (from %d)\n", rxq->id, i, count);
1443 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1445 ++rxq->rx_stats.refill_partial;
1448 /* When we submitted free recources to device... */
1449 if (likely(i > 0)) {
1450 /* ...let HW know that it can fill buffers with data
1452 * Add memory barrier to make sure the desc were written before
1456 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1458 rxq->next_to_use = next_to_use;
1464 static int ena_device_init(struct ena_com_dev *ena_dev,
1465 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1468 uint32_t aenq_groups;
1470 bool readless_supported;
1472 /* Initialize mmio registers */
1473 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1475 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1479 /* The PCIe configuration space revision id indicate if mmio reg
1482 readless_supported =
1483 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1484 & ENA_MMIO_DISABLE_REG_READ);
1485 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1488 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1490 PMD_DRV_LOG(ERR, "cannot reset device\n");
1491 goto err_mmio_read_less;
1494 /* check FW version */
1495 rc = ena_com_validate_version(ena_dev);
1497 PMD_DRV_LOG(ERR, "device version is too low\n");
1498 goto err_mmio_read_less;
1501 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1503 /* ENA device administration layer init */
1504 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1507 "cannot initialize ena admin queue with device\n");
1508 goto err_mmio_read_less;
1511 /* To enable the msix interrupts the driver needs to know the number
1512 * of queues. So the driver uses polling mode to retrieve this
1515 ena_com_set_admin_polling_mode(ena_dev, true);
1517 ena_config_host_info(ena_dev);
1519 /* Get Device Attributes and features */
1520 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1523 "cannot get attribute for ena device rc= %d\n", rc);
1524 goto err_admin_init;
1527 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1528 BIT(ENA_ADMIN_NOTIFICATION) |
1529 BIT(ENA_ADMIN_KEEP_ALIVE) |
1530 BIT(ENA_ADMIN_FATAL_ERROR) |
1531 BIT(ENA_ADMIN_WARNING);
1533 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1534 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1536 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1537 goto err_admin_init;
1540 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1545 ena_com_admin_destroy(ena_dev);
1548 ena_com_mmio_reg_read_request_destroy(ena_dev);
1553 static void ena_interrupt_handler_rte(void *cb_arg)
1555 struct ena_adapter *adapter = cb_arg;
1556 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1558 ena_com_admin_q_comp_intr_handler(ena_dev);
1559 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1560 ena_com_aenq_intr_handler(ena_dev, adapter);
1563 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1565 if (!adapter->wd_state)
1568 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1571 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1572 adapter->keep_alive_timeout)) {
1573 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1574 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1575 adapter->trigger_reset = true;
1576 ++adapter->dev_stats.wd_expired;
1580 /* Check if admin queue is enabled */
1581 static void check_for_admin_com_state(struct ena_adapter *adapter)
1583 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1584 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1585 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1586 adapter->trigger_reset = true;
1590 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1593 struct ena_adapter *adapter = arg;
1594 struct rte_eth_dev *dev = adapter->rte_dev;
1596 check_for_missing_keep_alive(adapter);
1597 check_for_admin_com_state(adapter);
1599 if (unlikely(adapter->trigger_reset)) {
1600 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1601 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1607 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1609 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1610 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1611 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1612 llq_config->llq_num_decs_before_header =
1613 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1614 llq_config->llq_ring_entry_size_value = 128;
1618 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1619 struct ena_com_dev *ena_dev,
1620 struct ena_admin_feature_llq_desc *llq,
1621 struct ena_llq_configurations *llq_default_configurations)
1624 u32 llq_feature_mask;
1626 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1627 if (!(ena_dev->supported_features & llq_feature_mask)) {
1629 "LLQ is not supported. Fallback to host mode policy.\n");
1630 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1634 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1636 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1637 "Fallback to host mode policy.");
1638 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1642 /* Nothing to config, exit */
1643 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1646 if (!adapter->dev_mem_base) {
1647 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1648 "Fallback to host mode policy.\n.");
1649 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1653 ena_dev->mem_bar = adapter->dev_mem_base;
1658 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1659 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1661 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1663 /* Regular queues capabilities */
1664 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1665 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1666 &get_feat_ctx->max_queue_ext.max_queue_ext;
1667 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1668 max_queue_ext->max_rx_cq_num);
1669 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1670 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1672 struct ena_admin_queue_feature_desc *max_queues =
1673 &get_feat_ctx->max_queues;
1674 io_tx_sq_num = max_queues->max_sq_num;
1675 io_tx_cq_num = max_queues->max_cq_num;
1676 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1679 /* In case of LLQ use the llq number in the get feature cmd */
1680 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1681 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1683 io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1684 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1685 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1687 if (unlikely(io_queue_num == 0)) {
1688 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1692 return io_queue_num;
1695 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1697 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1698 struct rte_pci_device *pci_dev;
1699 struct rte_intr_handle *intr_handle;
1700 struct ena_adapter *adapter = eth_dev->data->dev_private;
1701 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1702 struct ena_com_dev_get_features_ctx get_feat_ctx;
1703 struct ena_llq_configurations llq_config;
1704 const char *queue_type_str;
1707 static int adapters_found;
1710 eth_dev->dev_ops = &ena_dev_ops;
1711 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1712 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1713 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1715 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1718 memset(adapter, 0, sizeof(struct ena_adapter));
1719 ena_dev = &adapter->ena_dev;
1721 adapter->rte_eth_dev_data = eth_dev->data;
1722 adapter->rte_dev = eth_dev;
1724 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1725 adapter->pdev = pci_dev;
1727 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1728 pci_dev->addr.domain,
1730 pci_dev->addr.devid,
1731 pci_dev->addr.function);
1733 intr_handle = &pci_dev->intr_handle;
1735 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1736 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1738 if (!adapter->regs) {
1739 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1744 ena_dev->reg_bar = adapter->regs;
1745 ena_dev->dmadev = adapter->pdev;
1747 adapter->id_number = adapters_found;
1749 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1750 adapter->id_number);
1752 /* device specific initialization routine */
1753 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1755 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1758 adapter->wd_state = wd_state;
1760 set_default_llq_configurations(&llq_config);
1761 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1762 &get_feat_ctx.llq, &llq_config);
1764 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1768 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1769 queue_type_str = "Regular";
1771 queue_type_str = "Low latency";
1772 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1774 calc_queue_ctx.ena_dev = ena_dev;
1775 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1776 adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1779 rc = ena_calc_queue_size(&calc_queue_ctx);
1780 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1782 goto err_device_destroy;
1785 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1786 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1788 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1789 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1791 /* prepare ring structures */
1792 ena_init_rings(adapter);
1794 ena_config_debug_area(adapter);
1796 /* Set max MTU for this device */
1797 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1799 /* set device support for offloads */
1800 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1801 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1802 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1803 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1804 adapter->offloads.rx_csum_supported =
1805 (get_feat_ctx.offload.rx_supported &
1806 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1808 /* Copy MAC address and point DPDK to it */
1809 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1810 rte_ether_addr_copy((struct rte_ether_addr *)
1811 get_feat_ctx.dev_attr.mac_addr,
1812 (struct rte_ether_addr *)adapter->mac_addr);
1815 * Pass the information to the rte_eth_dev_close() that it should also
1816 * release the private port resources.
1818 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1820 adapter->drv_stats = rte_zmalloc("adapter stats",
1821 sizeof(*adapter->drv_stats),
1822 RTE_CACHE_LINE_SIZE);
1823 if (!adapter->drv_stats) {
1824 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1826 goto err_delete_debug_area;
1829 rte_intr_callback_register(intr_handle,
1830 ena_interrupt_handler_rte,
1832 rte_intr_enable(intr_handle);
1833 ena_com_set_admin_polling_mode(ena_dev, false);
1834 ena_com_admin_aenq_enable(ena_dev);
1836 if (adapters_found == 0)
1837 rte_timer_subsystem_init();
1838 rte_timer_init(&adapter->timer_wd);
1841 adapter->state = ENA_ADAPTER_STATE_INIT;
1845 err_delete_debug_area:
1846 ena_com_delete_debug_area(ena_dev);
1849 ena_com_delete_host_info(ena_dev);
1850 ena_com_admin_destroy(ena_dev);
1856 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1858 struct ena_adapter *adapter = eth_dev->data->dev_private;
1859 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1861 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1864 ena_com_set_admin_running_state(ena_dev, false);
1866 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1869 ena_com_delete_debug_area(ena_dev);
1870 ena_com_delete_host_info(ena_dev);
1872 ena_com_abort_admin_commands(ena_dev);
1873 ena_com_wait_for_abort_completion(ena_dev);
1874 ena_com_admin_destroy(ena_dev);
1875 ena_com_mmio_reg_read_request_destroy(ena_dev);
1877 adapter->state = ENA_ADAPTER_STATE_FREE;
1880 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1882 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1885 ena_destroy_device(eth_dev);
1887 eth_dev->dev_ops = NULL;
1888 eth_dev->rx_pkt_burst = NULL;
1889 eth_dev->tx_pkt_burst = NULL;
1890 eth_dev->tx_pkt_prepare = NULL;
1895 static int ena_dev_configure(struct rte_eth_dev *dev)
1897 struct ena_adapter *adapter = dev->data->dev_private;
1899 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1901 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1902 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1906 static void ena_init_rings(struct ena_adapter *adapter)
1910 for (i = 0; i < adapter->num_queues; i++) {
1911 struct ena_ring *ring = &adapter->tx_ring[i];
1913 ring->configured = 0;
1914 ring->type = ENA_RING_TYPE_TX;
1915 ring->adapter = adapter;
1917 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1918 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1919 ring->sgl_size = adapter->max_tx_sgl_size;
1922 for (i = 0; i < adapter->num_queues; i++) {
1923 struct ena_ring *ring = &adapter->rx_ring[i];
1925 ring->configured = 0;
1926 ring->type = ENA_RING_TYPE_RX;
1927 ring->adapter = adapter;
1929 ring->sgl_size = adapter->max_rx_sgl_size;
1933 static int ena_infos_get(struct rte_eth_dev *dev,
1934 struct rte_eth_dev_info *dev_info)
1936 struct ena_adapter *adapter;
1937 struct ena_com_dev *ena_dev;
1938 uint64_t rx_feat = 0, tx_feat = 0;
1940 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1941 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1942 adapter = dev->data->dev_private;
1944 ena_dev = &adapter->ena_dev;
1945 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1947 dev_info->speed_capa =
1949 ETH_LINK_SPEED_2_5G |
1951 ETH_LINK_SPEED_10G |
1952 ETH_LINK_SPEED_25G |
1953 ETH_LINK_SPEED_40G |
1954 ETH_LINK_SPEED_50G |
1955 ETH_LINK_SPEED_100G;
1957 /* Set Tx & Rx features available for device */
1958 if (adapter->offloads.tso4_supported)
1959 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1961 if (adapter->offloads.tx_csum_supported)
1962 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1963 DEV_TX_OFFLOAD_UDP_CKSUM |
1964 DEV_TX_OFFLOAD_TCP_CKSUM;
1966 if (adapter->offloads.rx_csum_supported)
1967 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1968 DEV_RX_OFFLOAD_UDP_CKSUM |
1969 DEV_RX_OFFLOAD_TCP_CKSUM;
1971 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1973 /* Inform framework about available features */
1974 dev_info->rx_offload_capa = rx_feat;
1975 dev_info->rx_queue_offload_capa = rx_feat;
1976 dev_info->tx_offload_capa = tx_feat;
1977 dev_info->tx_queue_offload_capa = tx_feat;
1979 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1982 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1983 dev_info->max_rx_pktlen = adapter->max_mtu;
1984 dev_info->max_mac_addrs = 1;
1986 dev_info->max_rx_queues = adapter->num_queues;
1987 dev_info->max_tx_queues = adapter->num_queues;
1988 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1990 adapter->tx_supported_offloads = tx_feat;
1991 adapter->rx_supported_offloads = rx_feat;
1993 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1994 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1995 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1996 adapter->max_rx_sgl_size);
1997 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1998 adapter->max_rx_sgl_size);
2000 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2001 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2002 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2003 adapter->max_tx_sgl_size);
2004 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2005 adapter->max_tx_sgl_size);
2010 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2013 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2014 unsigned int ring_size = rx_ring->ring_size;
2015 unsigned int ring_mask = ring_size - 1;
2016 uint16_t next_to_clean = rx_ring->next_to_clean;
2017 uint16_t desc_in_use = 0;
2019 unsigned int recv_idx = 0;
2020 struct rte_mbuf *mbuf = NULL;
2021 struct rte_mbuf *mbuf_head = NULL;
2022 struct rte_mbuf *mbuf_prev = NULL;
2023 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2024 unsigned int completed;
2026 struct ena_com_rx_ctx ena_rx_ctx;
2029 /* Check adapter state */
2030 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2032 "Trying to receive pkts while device is NOT running\n");
2036 desc_in_use = rx_ring->next_to_use - next_to_clean;
2037 if (unlikely(nb_pkts > desc_in_use))
2038 nb_pkts = desc_in_use;
2040 for (completed = 0; completed < nb_pkts; completed++) {
2043 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2044 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2045 ena_rx_ctx.descs = 0;
2046 ena_rx_ctx.pkt_offset = 0;
2047 /* receive packet context */
2048 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2049 rx_ring->ena_com_io_sq,
2052 PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2053 rx_ring->adapter->reset_reason =
2054 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2055 rx_ring->adapter->trigger_reset = true;
2056 ++rx_ring->rx_stats.bad_desc_num;
2060 if (unlikely(ena_rx_ctx.descs == 0))
2063 while (segments < ena_rx_ctx.descs) {
2064 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2065 rc = validate_rx_req_id(rx_ring, req_id);
2068 rte_mbuf_raw_free(mbuf_head);
2072 mbuf = rx_buff_info[req_id];
2073 rx_buff_info[req_id] = NULL;
2074 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2075 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2078 if (unlikely(segments == 0)) {
2079 mbuf->nb_segs = ena_rx_ctx.descs;
2080 mbuf->port = rx_ring->port_id;
2082 mbuf->data_off += ena_rx_ctx.pkt_offset;
2085 /* for multi-segment pkts create mbuf chain */
2086 mbuf_prev->next = mbuf;
2088 mbuf_head->pkt_len += mbuf->data_len;
2091 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2099 /* fill mbuf attributes if any */
2100 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2102 if (unlikely(mbuf_head->ol_flags &
2103 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2104 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2105 ++rx_ring->rx_stats.bad_csum;
2108 mbuf_head->hash.rss = ena_rx_ctx.hash;
2110 /* pass to DPDK application head mbuf */
2111 rx_pkts[recv_idx] = mbuf_head;
2113 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2116 rx_ring->rx_stats.cnt += recv_idx;
2117 rx_ring->next_to_clean = next_to_clean;
2119 desc_in_use = desc_in_use - completed + 1;
2120 /* Burst refill to save doorbells, memory barriers, const interval */
2121 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) {
2122 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2123 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2130 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2136 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2137 struct rte_ipv4_hdr *ip_hdr;
2139 uint16_t frag_field;
2141 for (i = 0; i != nb_pkts; i++) {
2143 ol_flags = m->ol_flags;
2145 if (!(ol_flags & PKT_TX_IPV4))
2148 /* If there was not L2 header length specified, assume it is
2149 * length of the ethernet header.
2151 if (unlikely(m->l2_len == 0))
2152 m->l2_len = sizeof(struct rte_ether_hdr);
2154 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2156 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2158 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2159 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2161 /* If IPv4 header has DF flag enabled and TSO support is
2162 * disabled, partial chcecksum should not be calculated.
2164 if (!tx_ring->adapter->offloads.tso4_supported)
2168 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2169 (ol_flags & PKT_TX_L4_MASK) ==
2170 PKT_TX_SCTP_CKSUM) {
2171 rte_errno = ENOTSUP;
2175 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2176 ret = rte_validate_tx_offload(m);
2183 /* In case we are supposed to TSO and have DF not set (DF=0)
2184 * hardware must be provided with partial checksum, otherwise
2185 * it will take care of necessary calculations.
2188 ret = rte_net_intel_cksum_flags_prepare(m,
2189 ol_flags & ~PKT_TX_TCP_SEG);
2199 static void ena_update_hints(struct ena_adapter *adapter,
2200 struct ena_admin_ena_hw_hints *hints)
2202 if (hints->admin_completion_tx_timeout)
2203 adapter->ena_dev.admin_queue.completion_timeout =
2204 hints->admin_completion_tx_timeout * 1000;
2206 if (hints->mmio_read_timeout)
2207 /* convert to usec */
2208 adapter->ena_dev.mmio_read.reg_read_to =
2209 hints->mmio_read_timeout * 1000;
2211 if (hints->driver_watchdog_timeout) {
2212 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2213 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2215 // Convert msecs to ticks
2216 adapter->keep_alive_timeout =
2217 (hints->driver_watchdog_timeout *
2218 rte_get_timer_hz()) / 1000;
2222 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2223 struct rte_mbuf *mbuf)
2225 struct ena_com_dev *ena_dev;
2226 int num_segments, header_len, rc;
2228 ena_dev = &tx_ring->adapter->ena_dev;
2229 num_segments = mbuf->nb_segs;
2230 header_len = mbuf->data_len;
2232 if (likely(num_segments < tx_ring->sgl_size))
2235 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2236 (num_segments == tx_ring->sgl_size) &&
2237 (header_len < tx_ring->tx_max_header_size))
2240 ++tx_ring->tx_stats.linearize;
2241 rc = rte_pktmbuf_linearize(mbuf);
2243 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2244 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2245 ++tx_ring->tx_stats.linearize_failed;
2252 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2255 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2256 uint16_t next_to_use = tx_ring->next_to_use;
2257 uint16_t next_to_clean = tx_ring->next_to_clean;
2258 struct rte_mbuf *mbuf;
2260 unsigned int ring_size = tx_ring->ring_size;
2261 unsigned int ring_mask = ring_size - 1;
2262 struct ena_com_tx_ctx ena_tx_ctx;
2263 struct ena_tx_buffer *tx_info;
2264 struct ena_com_buf *ebuf;
2265 uint16_t rc, req_id, total_tx_descs = 0;
2266 uint16_t sent_idx = 0, empty_tx_reqs;
2267 uint16_t push_len = 0;
2270 uint32_t total_length;
2272 /* Check adapter state */
2273 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2275 "Trying to xmit pkts while device is NOT running\n");
2279 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2280 if (nb_pkts > empty_tx_reqs)
2281 nb_pkts = empty_tx_reqs;
2283 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2284 mbuf = tx_pkts[sent_idx];
2287 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2291 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2292 tx_info = &tx_ring->tx_buffer_info[req_id];
2293 tx_info->mbuf = mbuf;
2294 tx_info->num_of_bufs = 0;
2295 ebuf = tx_info->bufs;
2297 /* Prepare TX context */
2298 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2299 memset(&ena_tx_ctx.ena_meta, 0x0,
2300 sizeof(struct ena_com_tx_meta));
2301 ena_tx_ctx.ena_bufs = ebuf;
2302 ena_tx_ctx.req_id = req_id;
2305 seg_len = mbuf->data_len;
2307 if (tx_ring->tx_mem_queue_type ==
2308 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2309 push_len = RTE_MIN(mbuf->pkt_len,
2310 tx_ring->tx_max_header_size);
2311 ena_tx_ctx.header_len = push_len;
2313 if (likely(push_len <= seg_len)) {
2314 /* If the push header is in the single segment,
2315 * then just point it to the 1st mbuf data.
2317 ena_tx_ctx.push_header =
2318 rte_pktmbuf_mtod(mbuf, uint8_t *);
2320 /* If the push header lays in the several
2321 * segments, copy it to the intermediate buffer.
2323 rte_pktmbuf_read(mbuf, 0, push_len,
2324 tx_ring->push_buf_intermediate_buf);
2325 ena_tx_ctx.push_header =
2326 tx_ring->push_buf_intermediate_buf;
2327 delta = push_len - seg_len;
2329 } /* there's no else as we take advantage of memset zeroing */
2331 /* Set TX offloads flags, if applicable */
2332 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2334 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2336 /* Process first segment taking into
2337 * consideration pushed header
2339 if (seg_len > push_len) {
2340 ebuf->paddr = mbuf->buf_iova +
2343 ebuf->len = seg_len - push_len;
2345 tx_info->num_of_bufs++;
2347 total_length += mbuf->data_len;
2349 while ((mbuf = mbuf->next) != NULL) {
2350 seg_len = mbuf->data_len;
2352 /* Skip mbufs if whole data is pushed as a header */
2353 if (unlikely(delta > seg_len)) {
2358 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2359 ebuf->len = seg_len - delta;
2360 total_length += ebuf->len;
2362 tx_info->num_of_bufs++;
2367 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2369 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2371 PMD_DRV_LOG(DEBUG, "llq tx max burst size of queue %d"
2372 " achieved, writing doorbell to send burst\n",
2375 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2378 /* prepare the packet's descriptors to dma engine */
2379 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2380 &ena_tx_ctx, &nb_hw_desc);
2382 ++tx_ring->tx_stats.prepare_ctx_err;
2385 tx_info->tx_descs = nb_hw_desc;
2388 tx_ring->tx_stats.cnt++;
2389 tx_ring->tx_stats.bytes += total_length;
2391 tx_ring->tx_stats.available_desc =
2392 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2394 /* If there are ready packets to be xmitted... */
2396 /* ...let HW do its best :-) */
2398 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2399 tx_ring->tx_stats.doorbells++;
2400 tx_ring->next_to_use = next_to_use;
2403 /* Clear complete packets */
2404 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2405 rc = validate_tx_req_id(tx_ring, req_id);
2409 /* Get Tx info & store how many descs were processed */
2410 tx_info = &tx_ring->tx_buffer_info[req_id];
2411 total_tx_descs += tx_info->tx_descs;
2413 /* Free whole mbuf chain */
2414 mbuf = tx_info->mbuf;
2415 rte_pktmbuf_free(mbuf);
2416 tx_info->mbuf = NULL;
2418 /* Put back descriptor to the ring for reuse */
2419 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2422 /* If too many descs to clean, leave it for another run */
2423 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2426 tx_ring->tx_stats.available_desc =
2427 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2429 if (total_tx_descs > 0) {
2430 /* acknowledge completion of sent packets */
2431 tx_ring->next_to_clean = next_to_clean;
2432 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2433 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2436 tx_ring->tx_stats.tx_poll++;
2442 * DPDK callback to retrieve names of extended device statistics
2445 * Pointer to Ethernet device structure.
2446 * @param[out] xstats_names
2447 * Buffer to insert names into.
2452 * Number of xstats names.
2454 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2455 struct rte_eth_xstat_name *xstats_names,
2458 unsigned int xstats_count = ena_xstats_calc_num(dev);
2459 unsigned int stat, i, count = 0;
2461 if (n < xstats_count || !xstats_names)
2462 return xstats_count;
2464 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2465 strcpy(xstats_names[count].name,
2466 ena_stats_global_strings[stat].name);
2468 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2469 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2470 snprintf(xstats_names[count].name,
2471 sizeof(xstats_names[count].name),
2473 ena_stats_rx_strings[stat].name);
2475 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2476 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2477 snprintf(xstats_names[count].name,
2478 sizeof(xstats_names[count].name),
2480 ena_stats_tx_strings[stat].name);
2482 return xstats_count;
2486 * DPDK callback to get extended device statistics.
2489 * Pointer to Ethernet device structure.
2491 * Stats table output buffer.
2493 * The size of the stats table.
2496 * Number of xstats on success, negative on failure.
2498 static int ena_xstats_get(struct rte_eth_dev *dev,
2499 struct rte_eth_xstat *xstats,
2502 struct ena_adapter *adapter = dev->data->dev_private;
2503 unsigned int xstats_count = ena_xstats_calc_num(dev);
2504 unsigned int stat, i, count = 0;
2508 if (n < xstats_count)
2509 return xstats_count;
2514 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2515 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2516 stats_begin = &adapter->dev_stats;
2518 xstats[count].id = count;
2519 xstats[count].value = *((uint64_t *)
2520 ((char *)stats_begin + stat_offset));
2523 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2524 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2525 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2526 stats_begin = &adapter->rx_ring[i].rx_stats;
2528 xstats[count].id = count;
2529 xstats[count].value = *((uint64_t *)
2530 ((char *)stats_begin + stat_offset));
2534 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2535 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2536 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2537 stats_begin = &adapter->tx_ring[i].rx_stats;
2539 xstats[count].id = count;
2540 xstats[count].value = *((uint64_t *)
2541 ((char *)stats_begin + stat_offset));
2548 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2549 const uint64_t *ids,
2553 struct ena_adapter *adapter = dev->data->dev_private;
2555 uint64_t rx_entries, tx_entries;
2559 for (i = 0; i < n; ++i) {
2561 /* Check if id belongs to global statistics */
2562 if (id < ENA_STATS_ARRAY_GLOBAL) {
2563 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2568 /* Check if id belongs to rx queue statistics */
2569 id -= ENA_STATS_ARRAY_GLOBAL;
2570 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2571 if (id < rx_entries) {
2572 qid = id % dev->data->nb_rx_queues;
2573 id /= dev->data->nb_rx_queues;
2574 values[i] = *((uint64_t *)
2575 &adapter->rx_ring[qid].rx_stats + id);
2579 /* Check if id belongs to rx queue statistics */
2581 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2582 if (id < tx_entries) {
2583 qid = id % dev->data->nb_tx_queues;
2584 id /= dev->data->nb_tx_queues;
2585 values[i] = *((uint64_t *)
2586 &adapter->tx_ring[qid].tx_stats + id);
2595 /*********************************************************************
2597 *********************************************************************/
2598 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2599 struct rte_pci_device *pci_dev)
2601 return rte_eth_dev_pci_generic_probe(pci_dev,
2602 sizeof(struct ena_adapter), eth_ena_dev_init);
2605 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2607 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2610 static struct rte_pci_driver rte_ena_pmd = {
2611 .id_table = pci_id_ena_map,
2612 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2613 RTE_PCI_DRV_WC_ACTIVATE,
2614 .probe = eth_ena_pci_probe,
2615 .remove = eth_ena_pci_remove,
2618 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2619 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2620 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2622 RTE_INIT(ena_init_log)
2624 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2625 if (ena_logtype_init >= 0)
2626 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2627 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2628 if (ena_logtype_driver >= 0)
2629 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2631 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2632 ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2633 if (ena_logtype_rx >= 0)
2634 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2637 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2638 ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2639 if (ena_logtype_tx >= 0)
2640 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2643 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2644 ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2645 if (ena_logtype_tx_free >= 0)
2646 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2649 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2650 ena_logtype_com = rte_log_register("pmd.net.ena.com");
2651 if (ena_logtype_com >= 0)
2652 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2656 /******************************************************************************
2657 ******************************** AENQ Handlers *******************************
2658 *****************************************************************************/
2659 static void ena_update_on_link_change(void *adapter_data,
2660 struct ena_admin_aenq_entry *aenq_e)
2662 struct rte_eth_dev *eth_dev;
2663 struct ena_adapter *adapter;
2664 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2667 adapter = adapter_data;
2668 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2669 eth_dev = adapter->rte_dev;
2671 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2672 adapter->link_status = status;
2674 ena_link_update(eth_dev, 0);
2675 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2678 static void ena_notification(void *data,
2679 struct ena_admin_aenq_entry *aenq_e)
2681 struct ena_adapter *adapter = data;
2682 struct ena_admin_ena_hw_hints *hints;
2684 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2685 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2686 aenq_e->aenq_common_desc.group,
2687 ENA_ADMIN_NOTIFICATION);
2689 switch (aenq_e->aenq_common_desc.syndrom) {
2690 case ENA_ADMIN_UPDATE_HINTS:
2691 hints = (struct ena_admin_ena_hw_hints *)
2692 (&aenq_e->inline_data_w4);
2693 ena_update_hints(adapter, hints);
2696 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2697 aenq_e->aenq_common_desc.syndrom);
2701 static void ena_keep_alive(void *adapter_data,
2702 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2704 struct ena_adapter *adapter = adapter_data;
2705 struct ena_admin_aenq_keep_alive_desc *desc;
2708 adapter->timestamp_wd = rte_get_timer_cycles();
2710 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2711 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2712 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops);
2716 * This handler will called for unknown event group or unimplemented handlers
2718 static void unimplemented_aenq_handler(__rte_unused void *data,
2719 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2721 PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2722 "unimplemented handler\n");
2725 static struct ena_aenq_handlers aenq_handlers = {
2727 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2728 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2729 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2731 .unimplemented_handler = unimplemented_aenq_handler